1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #define MAX_NOPID ((u32)~0)
41 * Interrupts that are always left unmasked.
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
47 #define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
67 /* For display hotplug interrupt */
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
91 if ((dev_priv->pipestat[pipe] & mask) != mask) {
92 u32 reg = PIPESTAT(pipe);
94 dev_priv->pipestat[pipe] |= mask;
95 /* Enable the interrupt, clear any pending status */
96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
105 u32 reg = PIPESTAT(pipe);
107 dev_priv->pipestat[pipe] &= ~mask;
108 I915_WRITE(reg, dev_priv->pipestat[pipe]);
114 * intel_enable_asle - enable ASLE interrupt for OpRegion
116 void intel_enable_asle(struct drm_device *dev)
118 drm_i915_private_t *dev_priv = dev->dev_private;
119 unsigned long irqflags;
121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
123 if (HAS_PCH_SPLIT(dev))
124 ironlake_enable_display_irq(dev_priv, DE_GSE);
126 i915_enable_pipestat(dev_priv, 1,
127 PIPE_LEGACY_BLC_EVENT_ENABLE);
128 if (INTEL_INFO(dev)->gen >= 4)
129 i915_enable_pipestat(dev_priv, 0,
130 PIPE_LEGACY_BLC_EVENT_ENABLE);
133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
137 * i915_pipe_enabled - check if a pipe is enabled
139 * @pipe: pipe to check
141 * Reading certain registers when the pipe is disabled can hang the chip.
142 * Use this routine to make sure the PLL is running and the pipe is active
143 * before reading such registers if unsure.
146 i915_pipe_enabled(struct drm_device *dev, int pipe)
148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
152 /* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index
155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame;
159 unsigned long low_frame;
160 u32 high1, high2, low;
162 if (!i915_pipe_enabled(dev, pipe)) {
163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
164 "pipe %c\n", pipe_name(pipe));
168 high_frame = PIPEFRAME(pipe);
169 low_frame = PIPEFRAMEPIXEL(pipe);
172 * High & low register fields aren't synchronized, so make sure
173 * we get a low value that's stable across two reads of the high
177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
180 } while (high1 != high2);
182 high1 >>= PIPE_FRAME_HIGH_SHIFT;
183 low >>= PIPE_FRAME_LOW_SHIFT;
184 return (high1 << 8) | low;
187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
190 int reg = PIPE_FRMCOUNT_GM45(pipe);
192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
194 "pipe %c\n", pipe_name(pipe));
198 return I915_READ(reg);
201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
202 int *vpos, int *hpos)
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205 u32 vbl = 0, position = 0;
206 int vbl_start, vbl_end, htotal, vtotal;
210 if (!i915_pipe_enabled(dev, pipe)) {
211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
212 "pipe %c\n", pipe_name(pipe));
217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
219 if (INTEL_INFO(dev)->gen >= 4) {
220 /* No obvious pixelcount register. Only query vertical
221 * scanout position from Display scan line register.
223 position = I915_READ(PIPEDSL(pipe));
225 /* Decode into vertical scanout position. Don't have
226 * horizontal scanout position.
228 *vpos = position & 0x1fff;
231 /* Have access to pixelcount since start of frame.
232 * We can split this into vertical and horizontal
235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
238 *vpos = position / htotal;
239 *hpos = position - (*vpos * htotal);
242 /* Query vblank area. */
243 vbl = I915_READ(VBLANK(pipe));
245 /* Test position against vblank region. */
246 vbl_start = vbl & 0x1fff;
247 vbl_end = (vbl >> 16) & 0x1fff;
249 if ((*vpos < vbl_start) || (*vpos > vbl_end))
252 /* Inside "upper part" of vblank area? Apply corrective offset: */
253 if (in_vbl && (*vpos >= vbl_start))
254 *vpos = *vpos - vtotal;
256 /* Readouts valid? */
258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
262 ret |= DRM_SCANOUTPOS_INVBL;
267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
269 struct timeval *vblank_time,
272 struct drm_i915_private *dev_priv = dev->dev_private;
273 struct drm_crtc *crtc;
275 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
276 DRM_ERROR("Invalid crtc %d\n", pipe);
280 /* Get drm_crtc to timestamp: */
281 crtc = intel_get_crtc_for_pipe(dev, pipe);
283 DRM_ERROR("Invalid crtc %d\n", pipe);
287 if (!crtc->enabled) {
288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
292 /* Helper routine in DRM core does all the work: */
293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
299 * Handle hotplug events outside the interrupt handler proper.
301 static void i915_hotplug_work_func(struct work_struct *work)
303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
305 struct drm_device *dev = dev_priv->dev;
306 struct drm_mode_config *mode_config = &dev->mode_config;
307 struct intel_encoder *encoder;
309 mutex_lock(&mode_config->mutex);
310 DRM_DEBUG_KMS("running encoder hotplug functions\n");
312 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
313 if (encoder->hot_plug)
314 encoder->hot_plug(encoder);
316 mutex_unlock(&mode_config->mutex);
318 /* Just fire off a uevent and let userspace tell us what to do */
319 drm_helper_hpd_irq_event(dev);
322 static void i915_handle_rps_change(struct drm_device *dev)
324 drm_i915_private_t *dev_priv = dev->dev_private;
325 u32 busy_up, busy_down, max_avg, min_avg;
326 u8 new_delay = dev_priv->cur_delay;
328 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
329 busy_up = I915_READ(RCPREVBSYTUPAVG);
330 busy_down = I915_READ(RCPREVBSYTDNAVG);
331 max_avg = I915_READ(RCBMAXAVG);
332 min_avg = I915_READ(RCBMINAVG);
334 /* Handle RCS change request from hw */
335 if (busy_up > max_avg) {
336 if (dev_priv->cur_delay != dev_priv->max_delay)
337 new_delay = dev_priv->cur_delay - 1;
338 if (new_delay < dev_priv->max_delay)
339 new_delay = dev_priv->max_delay;
340 } else if (busy_down < min_avg) {
341 if (dev_priv->cur_delay != dev_priv->min_delay)
342 new_delay = dev_priv->cur_delay + 1;
343 if (new_delay > dev_priv->min_delay)
344 new_delay = dev_priv->min_delay;
347 if (ironlake_set_drps(dev, new_delay))
348 dev_priv->cur_delay = new_delay;
353 static void notify_ring(struct drm_device *dev,
354 struct intel_ring_buffer *ring)
356 struct drm_i915_private *dev_priv = dev->dev_private;
359 if (ring->obj == NULL)
362 seqno = ring->get_seqno(ring);
363 trace_i915_gem_request_complete(ring, seqno);
365 ring->irq_seqno = seqno;
366 wake_up_all(&ring->irq_queue);
367 if (i915_enable_hangcheck) {
368 dev_priv->hangcheck_count = 0;
369 mod_timer(&dev_priv->hangcheck_timer,
371 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
375 static void gen6_pm_rps_work(struct work_struct *work)
377 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
379 u8 new_delay = dev_priv->cur_delay;
382 spin_lock_irq(&dev_priv->rps_lock);
383 pm_iir = dev_priv->pm_iir;
384 dev_priv->pm_iir = 0;
385 pm_imr = I915_READ(GEN6_PMIMR);
386 I915_WRITE(GEN6_PMIMR, 0);
387 spin_unlock_irq(&dev_priv->rps_lock);
392 mutex_lock(&dev_priv->dev->struct_mutex);
393 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
394 if (dev_priv->cur_delay != dev_priv->max_delay)
395 new_delay = dev_priv->cur_delay + 1;
396 if (new_delay > dev_priv->max_delay)
397 new_delay = dev_priv->max_delay;
398 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
399 gen6_gt_force_wake_get(dev_priv);
400 if (dev_priv->cur_delay != dev_priv->min_delay)
401 new_delay = dev_priv->cur_delay - 1;
402 if (new_delay < dev_priv->min_delay) {
403 new_delay = dev_priv->min_delay;
404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
406 ((new_delay << 16) & 0x3f0000));
408 /* Make sure we continue to get down interrupts
409 * until we hit the minimum frequency */
410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
413 gen6_gt_force_wake_put(dev_priv);
416 gen6_set_rps(dev_priv->dev, new_delay);
417 dev_priv->cur_delay = new_delay;
420 * rps_lock not held here because clearing is non-destructive. There is
421 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
422 * by holding struct_mutex for the duration of the write.
424 mutex_unlock(&dev_priv->dev->struct_mutex);
427 static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
429 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
432 if (pch_iir & SDE_AUDIO_POWER_MASK)
433 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
434 (pch_iir & SDE_AUDIO_POWER_MASK) >>
435 SDE_AUDIO_POWER_SHIFT);
437 if (pch_iir & SDE_GMBUS)
438 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
440 if (pch_iir & SDE_AUDIO_HDCP_MASK)
441 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
443 if (pch_iir & SDE_AUDIO_TRANS_MASK)
444 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
446 if (pch_iir & SDE_POISON)
447 DRM_ERROR("PCH poison interrupt\n");
449 if (pch_iir & SDE_FDI_MASK)
451 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
453 I915_READ(FDI_RX_IIR(pipe)));
455 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
456 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
458 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
459 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
461 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
462 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
463 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
464 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
467 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
469 struct drm_device *dev = (struct drm_device *) arg;
470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
472 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
473 struct drm_i915_master_private *master_priv;
475 atomic_inc(&dev_priv->irq_received);
477 /* disable master interrupt before clearing iir */
478 de_ier = I915_READ(DEIER);
479 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
482 de_iir = I915_READ(DEIIR);
483 gt_iir = I915_READ(GTIIR);
484 pch_iir = I915_READ(SDEIIR);
485 pm_iir = I915_READ(GEN6_PMIIR);
487 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
492 if (dev->primary->master) {
493 master_priv = dev->primary->master->driver_priv;
494 if (master_priv->sarea_priv)
495 master_priv->sarea_priv->last_dispatch =
496 READ_BREADCRUMB(dev_priv);
499 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
500 notify_ring(dev, &dev_priv->ring[RCS]);
501 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
502 notify_ring(dev, &dev_priv->ring[VCS]);
503 if (gt_iir & GT_BLT_USER_INTERRUPT)
504 notify_ring(dev, &dev_priv->ring[BCS]);
506 if (de_iir & DE_GSE_IVB)
507 intel_opregion_gse_intr(dev);
509 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
510 intel_prepare_page_flip(dev, 0);
511 intel_finish_page_flip_plane(dev, 0);
514 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
515 intel_prepare_page_flip(dev, 1);
516 intel_finish_page_flip_plane(dev, 1);
519 if (de_iir & DE_PIPEA_VBLANK_IVB)
520 drm_handle_vblank(dev, 0);
522 if (de_iir & DE_PIPEB_VBLANK_IVB)
523 drm_handle_vblank(dev, 1);
525 /* check event from PCH */
526 if (de_iir & DE_PCH_EVENT_IVB) {
527 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
528 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
529 pch_irq_handler(dev, pch_iir);
532 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
534 spin_lock_irqsave(&dev_priv->rps_lock, flags);
535 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
536 dev_priv->pm_iir |= pm_iir;
537 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
538 POSTING_READ(GEN6_PMIMR);
539 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
540 queue_work(dev_priv->wq, &dev_priv->rps_work);
543 /* should clear PCH hotplug event before clear CPU irq */
544 I915_WRITE(SDEIIR, pch_iir);
545 I915_WRITE(GTIIR, gt_iir);
546 I915_WRITE(DEIIR, de_iir);
547 I915_WRITE(GEN6_PMIIR, pm_iir);
550 I915_WRITE(DEIER, de_ier);
556 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
558 struct drm_device *dev = (struct drm_device *) arg;
559 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
561 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
563 struct drm_i915_master_private *master_priv;
564 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
566 atomic_inc(&dev_priv->irq_received);
569 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
571 /* disable master interrupt before clearing iir */
572 de_ier = I915_READ(DEIER);
573 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
576 de_iir = I915_READ(DEIIR);
577 gt_iir = I915_READ(GTIIR);
578 pch_iir = I915_READ(SDEIIR);
579 pm_iir = I915_READ(GEN6_PMIIR);
581 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
582 (!IS_GEN6(dev) || pm_iir == 0))
585 if (HAS_PCH_CPT(dev))
586 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
588 hotplug_mask = SDE_HOTPLUG_MASK;
592 if (dev->primary->master) {
593 master_priv = dev->primary->master->driver_priv;
594 if (master_priv->sarea_priv)
595 master_priv->sarea_priv->last_dispatch =
596 READ_BREADCRUMB(dev_priv);
599 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
600 notify_ring(dev, &dev_priv->ring[RCS]);
601 if (gt_iir & bsd_usr_interrupt)
602 notify_ring(dev, &dev_priv->ring[VCS]);
603 if (gt_iir & GT_BLT_USER_INTERRUPT)
604 notify_ring(dev, &dev_priv->ring[BCS]);
607 intel_opregion_gse_intr(dev);
609 if (de_iir & DE_PLANEA_FLIP_DONE) {
610 intel_prepare_page_flip(dev, 0);
611 intel_finish_page_flip_plane(dev, 0);
614 if (de_iir & DE_PLANEB_FLIP_DONE) {
615 intel_prepare_page_flip(dev, 1);
616 intel_finish_page_flip_plane(dev, 1);
619 if (de_iir & DE_PIPEA_VBLANK)
620 drm_handle_vblank(dev, 0);
622 if (de_iir & DE_PIPEB_VBLANK)
623 drm_handle_vblank(dev, 1);
625 /* check event from PCH */
626 if (de_iir & DE_PCH_EVENT) {
627 if (pch_iir & hotplug_mask)
628 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
629 pch_irq_handler(dev, pch_iir);
632 if (de_iir & DE_PCU_EVENT) {
633 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
634 i915_handle_rps_change(dev);
637 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
639 * IIR bits should never already be set because IMR should
640 * prevent an interrupt from being shown in IIR. The warning
641 * displays a case where we've unsafely cleared
642 * dev_priv->pm_iir. Although missing an interrupt of the same
643 * type is not a problem, it displays a problem in the logic.
645 * The mask bit in IMR is cleared by rps_work.
648 spin_lock_irqsave(&dev_priv->rps_lock, flags);
649 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
650 dev_priv->pm_iir |= pm_iir;
651 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
652 POSTING_READ(GEN6_PMIMR);
653 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
654 queue_work(dev_priv->wq, &dev_priv->rps_work);
657 /* should clear PCH hotplug event before clear CPU irq */
658 I915_WRITE(SDEIIR, pch_iir);
659 I915_WRITE(GTIIR, gt_iir);
660 I915_WRITE(DEIIR, de_iir);
661 I915_WRITE(GEN6_PMIIR, pm_iir);
664 I915_WRITE(DEIER, de_ier);
671 * i915_error_work_func - do process context error handling work
674 * Fire an error uevent so userspace can see that a hang or error
677 static void i915_error_work_func(struct work_struct *work)
679 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
681 struct drm_device *dev = dev_priv->dev;
682 char *error_event[] = { "ERROR=1", NULL };
683 char *reset_event[] = { "RESET=1", NULL };
684 char *reset_done_event[] = { "ERROR=0", NULL };
686 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
688 if (atomic_read(&dev_priv->mm.wedged)) {
689 DRM_DEBUG_DRIVER("resetting chip\n");
690 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
691 if (!i915_reset(dev, GRDOM_RENDER)) {
692 atomic_set(&dev_priv->mm.wedged, 0);
693 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
695 complete_all(&dev_priv->error_completion);
699 #ifdef CONFIG_DEBUG_FS
700 static struct drm_i915_error_object *
701 i915_error_object_create(struct drm_i915_private *dev_priv,
702 struct drm_i915_gem_object *src)
704 struct drm_i915_error_object *dst;
705 int page, page_count;
708 if (src == NULL || src->pages == NULL)
711 page_count = src->base.size / PAGE_SIZE;
713 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
717 reloc_offset = src->gtt_offset;
718 for (page = 0; page < page_count; page++) {
723 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
727 local_irq_save(flags);
728 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
730 memcpy_fromio(d, s, PAGE_SIZE);
731 io_mapping_unmap_atomic(s);
732 local_irq_restore(flags);
734 dst->pages[page] = d;
736 reloc_offset += PAGE_SIZE;
738 dst->page_count = page_count;
739 dst->gtt_offset = src->gtt_offset;
745 kfree(dst->pages[page]);
751 i915_error_object_free(struct drm_i915_error_object *obj)
758 for (page = 0; page < obj->page_count; page++)
759 kfree(obj->pages[page]);
765 i915_error_state_free(struct drm_device *dev,
766 struct drm_i915_error_state *error)
770 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
771 i915_error_object_free(error->batchbuffer[i]);
773 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
774 i915_error_object_free(error->ringbuffer[i]);
776 kfree(error->active_bo);
777 kfree(error->overlay);
781 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
783 struct list_head *head)
785 struct drm_i915_gem_object *obj;
788 list_for_each_entry(obj, head, mm_list) {
789 err->size = obj->base.size;
790 err->name = obj->base.name;
791 err->seqno = obj->last_rendering_seqno;
792 err->gtt_offset = obj->gtt_offset;
793 err->read_domains = obj->base.read_domains;
794 err->write_domain = obj->base.write_domain;
795 err->fence_reg = obj->fence_reg;
797 if (obj->pin_count > 0)
799 if (obj->user_pin_count > 0)
801 err->tiling = obj->tiling_mode;
802 err->dirty = obj->dirty;
803 err->purgeable = obj->madv != I915_MADV_WILLNEED;
804 err->ring = obj->ring ? obj->ring->id : 0;
805 err->cache_level = obj->cache_level;
816 static void i915_gem_record_fences(struct drm_device *dev,
817 struct drm_i915_error_state *error)
819 struct drm_i915_private *dev_priv = dev->dev_private;
823 switch (INTEL_INFO(dev)->gen) {
826 for (i = 0; i < 16; i++)
827 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
831 for (i = 0; i < 16; i++)
832 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
835 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
836 for (i = 0; i < 8; i++)
837 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
839 for (i = 0; i < 8; i++)
840 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
846 static struct drm_i915_error_object *
847 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
848 struct intel_ring_buffer *ring)
850 struct drm_i915_gem_object *obj;
853 if (!ring->get_seqno)
856 seqno = ring->get_seqno(ring);
857 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
858 if (obj->ring != ring)
861 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
864 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
867 /* We need to copy these to an anonymous buffer as the simplest
868 * method to avoid being overwritten by userspace.
870 return i915_error_object_create(dev_priv, obj);
877 * i915_capture_error_state - capture an error record for later analysis
880 * Should be called when an error is detected (either a hang or an error
881 * interrupt) to capture error state from the time of the error. Fills
882 * out a structure which becomes available in debugfs for user level tools
885 static void i915_capture_error_state(struct drm_device *dev)
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 struct drm_i915_gem_object *obj;
889 struct drm_i915_error_state *error;
893 spin_lock_irqsave(&dev_priv->error_lock, flags);
894 error = dev_priv->first_error;
895 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
899 /* Account for pipe specific data like PIPE*STAT */
900 error = kmalloc(sizeof(*error), GFP_ATOMIC);
902 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
906 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
907 dev->primary->index);
909 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
910 error->eir = I915_READ(EIR);
911 error->pgtbl_er = I915_READ(PGTBL_ER);
913 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
914 error->instpm = I915_READ(INSTPM);
916 if (INTEL_INFO(dev)->gen >= 6) {
917 error->error = I915_READ(ERROR_GEN6);
919 error->bcs_acthd = I915_READ(BCS_ACTHD);
920 error->bcs_ipehr = I915_READ(BCS_IPEHR);
921 error->bcs_ipeir = I915_READ(BCS_IPEIR);
922 error->bcs_instdone = I915_READ(BCS_INSTDONE);
923 error->bcs_seqno = 0;
924 if (dev_priv->ring[BCS].get_seqno)
925 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
927 error->vcs_acthd = I915_READ(VCS_ACTHD);
928 error->vcs_ipehr = I915_READ(VCS_IPEHR);
929 error->vcs_ipeir = I915_READ(VCS_IPEIR);
930 error->vcs_instdone = I915_READ(VCS_INSTDONE);
931 error->vcs_seqno = 0;
932 if (dev_priv->ring[VCS].get_seqno)
933 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
935 if (INTEL_INFO(dev)->gen >= 4) {
936 error->ipeir = I915_READ(IPEIR_I965);
937 error->ipehr = I915_READ(IPEHR_I965);
938 error->instdone = I915_READ(INSTDONE_I965);
939 error->instps = I915_READ(INSTPS);
940 error->instdone1 = I915_READ(INSTDONE1);
941 error->acthd = I915_READ(ACTHD_I965);
942 error->bbaddr = I915_READ64(BB_ADDR);
944 error->ipeir = I915_READ(IPEIR);
945 error->ipehr = I915_READ(IPEHR);
946 error->instdone = I915_READ(INSTDONE);
947 error->acthd = I915_READ(ACTHD);
950 i915_gem_record_fences(dev, error);
952 /* Record the active batch and ring buffers */
953 for (i = 0; i < I915_NUM_RINGS; i++) {
954 error->batchbuffer[i] =
955 i915_error_first_batchbuffer(dev_priv,
958 error->ringbuffer[i] =
959 i915_error_object_create(dev_priv,
960 dev_priv->ring[i].obj);
963 /* Record buffers on the active and pinned lists. */
964 error->active_bo = NULL;
965 error->pinned_bo = NULL;
968 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
970 error->active_bo_count = i;
971 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
973 error->pinned_bo_count = i - error->active_bo_count;
975 error->active_bo = NULL;
976 error->pinned_bo = NULL;
978 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
980 if (error->active_bo)
982 error->active_bo + error->active_bo_count;
985 if (error->active_bo)
986 error->active_bo_count =
987 capture_bo_list(error->active_bo,
988 error->active_bo_count,
989 &dev_priv->mm.active_list);
991 if (error->pinned_bo)
992 error->pinned_bo_count =
993 capture_bo_list(error->pinned_bo,
994 error->pinned_bo_count,
995 &dev_priv->mm.pinned_list);
997 do_gettimeofday(&error->time);
999 error->overlay = intel_overlay_capture_error_state(dev);
1000 error->display = intel_display_capture_error_state(dev);
1002 spin_lock_irqsave(&dev_priv->error_lock, flags);
1003 if (dev_priv->first_error == NULL) {
1004 dev_priv->first_error = error;
1007 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1010 i915_error_state_free(dev, error);
1013 void i915_destroy_error_state(struct drm_device *dev)
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 struct drm_i915_error_state *error;
1018 spin_lock(&dev_priv->error_lock);
1019 error = dev_priv->first_error;
1020 dev_priv->first_error = NULL;
1021 spin_unlock(&dev_priv->error_lock);
1024 i915_error_state_free(dev, error);
1027 #define i915_capture_error_state(x)
1030 static void i915_report_and_clear_eir(struct drm_device *dev)
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 u32 eir = I915_READ(EIR);
1039 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1043 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1044 u32 ipeir = I915_READ(IPEIR_I965);
1046 printk(KERN_ERR " IPEIR: 0x%08x\n",
1047 I915_READ(IPEIR_I965));
1048 printk(KERN_ERR " IPEHR: 0x%08x\n",
1049 I915_READ(IPEHR_I965));
1050 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1051 I915_READ(INSTDONE_I965));
1052 printk(KERN_ERR " INSTPS: 0x%08x\n",
1054 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1055 I915_READ(INSTDONE1));
1056 printk(KERN_ERR " ACTHD: 0x%08x\n",
1057 I915_READ(ACTHD_I965));
1058 I915_WRITE(IPEIR_I965, ipeir);
1059 POSTING_READ(IPEIR_I965);
1061 if (eir & GM45_ERROR_PAGE_TABLE) {
1062 u32 pgtbl_err = I915_READ(PGTBL_ER);
1063 printk(KERN_ERR "page table error\n");
1064 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
1066 I915_WRITE(PGTBL_ER, pgtbl_err);
1067 POSTING_READ(PGTBL_ER);
1071 if (!IS_GEN2(dev)) {
1072 if (eir & I915_ERROR_PAGE_TABLE) {
1073 u32 pgtbl_err = I915_READ(PGTBL_ER);
1074 printk(KERN_ERR "page table error\n");
1075 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
1077 I915_WRITE(PGTBL_ER, pgtbl_err);
1078 POSTING_READ(PGTBL_ER);
1082 if (eir & I915_ERROR_MEMORY_REFRESH) {
1083 printk(KERN_ERR "memory refresh error:\n");
1085 printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1086 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1087 /* pipestat has already been acked */
1089 if (eir & I915_ERROR_INSTRUCTION) {
1090 printk(KERN_ERR "instruction error\n");
1091 printk(KERN_ERR " INSTPM: 0x%08x\n",
1093 if (INTEL_INFO(dev)->gen < 4) {
1094 u32 ipeir = I915_READ(IPEIR);
1096 printk(KERN_ERR " IPEIR: 0x%08x\n",
1098 printk(KERN_ERR " IPEHR: 0x%08x\n",
1100 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1101 I915_READ(INSTDONE));
1102 printk(KERN_ERR " ACTHD: 0x%08x\n",
1104 I915_WRITE(IPEIR, ipeir);
1105 POSTING_READ(IPEIR);
1107 u32 ipeir = I915_READ(IPEIR_I965);
1109 printk(KERN_ERR " IPEIR: 0x%08x\n",
1110 I915_READ(IPEIR_I965));
1111 printk(KERN_ERR " IPEHR: 0x%08x\n",
1112 I915_READ(IPEHR_I965));
1113 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1114 I915_READ(INSTDONE_I965));
1115 printk(KERN_ERR " INSTPS: 0x%08x\n",
1117 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1118 I915_READ(INSTDONE1));
1119 printk(KERN_ERR " ACTHD: 0x%08x\n",
1120 I915_READ(ACTHD_I965));
1121 I915_WRITE(IPEIR_I965, ipeir);
1122 POSTING_READ(IPEIR_I965);
1126 I915_WRITE(EIR, eir);
1128 eir = I915_READ(EIR);
1131 * some errors might have become stuck,
1134 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1135 I915_WRITE(EMR, I915_READ(EMR) | eir);
1136 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1141 * i915_handle_error - handle an error interrupt
1144 * Do some basic checking of regsiter state at error interrupt time and
1145 * dump it to the syslog. Also call i915_capture_error_state() to make
1146 * sure we get a record and make it available in debugfs. Fire a uevent
1147 * so userspace knows something bad happened (should trigger collection
1148 * of a ring dump etc.).
1150 void i915_handle_error(struct drm_device *dev, bool wedged)
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1154 i915_capture_error_state(dev);
1155 i915_report_and_clear_eir(dev);
1158 INIT_COMPLETION(dev_priv->error_completion);
1159 atomic_set(&dev_priv->mm.wedged, 1);
1162 * Wakeup waiting processes so they don't hang
1164 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1166 wake_up_all(&dev_priv->ring[VCS].irq_queue);
1168 wake_up_all(&dev_priv->ring[BCS].irq_queue);
1171 queue_work(dev_priv->wq, &dev_priv->error_work);
1174 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1176 drm_i915_private_t *dev_priv = dev->dev_private;
1177 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1179 struct drm_i915_gem_object *obj;
1180 struct intel_unpin_work *work;
1181 unsigned long flags;
1182 bool stall_detected;
1184 /* Ignore early vblank irqs */
1185 if (intel_crtc == NULL)
1188 spin_lock_irqsave(&dev->event_lock, flags);
1189 work = intel_crtc->unpin_work;
1191 if (work == NULL || work->pending || !work->enable_stall_check) {
1192 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1193 spin_unlock_irqrestore(&dev->event_lock, flags);
1197 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1198 obj = work->pending_flip_obj;
1199 if (INTEL_INFO(dev)->gen >= 4) {
1200 int dspsurf = DSPSURF(intel_crtc->plane);
1201 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1203 int dspaddr = DSPADDR(intel_crtc->plane);
1204 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1205 crtc->y * crtc->fb->pitch +
1206 crtc->x * crtc->fb->bits_per_pixel/8);
1209 spin_unlock_irqrestore(&dev->event_lock, flags);
1211 if (stall_detected) {
1212 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1213 intel_prepare_page_flip(dev, intel_crtc->plane);
1217 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1219 struct drm_device *dev = (struct drm_device *) arg;
1220 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1221 struct drm_i915_master_private *master_priv;
1223 u32 pipe_stats[I915_MAX_PIPES];
1226 unsigned long irqflags;
1228 int ret = IRQ_NONE, pipe;
1229 bool blc_event = false;
1231 atomic_inc(&dev_priv->irq_received);
1233 iir = I915_READ(IIR);
1235 if (INTEL_INFO(dev)->gen >= 4)
1236 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1238 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1241 irq_received = iir != 0;
1243 /* Can't rely on pipestat interrupt bit in iir as it might
1244 * have been cleared after the pipestat interrupt was received.
1245 * It doesn't set the bit in iir again, but it still produces
1246 * interrupts (for non-MSI).
1248 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1249 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1250 i915_handle_error(dev, false);
1252 for_each_pipe(pipe) {
1253 int reg = PIPESTAT(pipe);
1254 pipe_stats[pipe] = I915_READ(reg);
1257 * Clear the PIPE*STAT regs before the IIR
1259 if (pipe_stats[pipe] & 0x8000ffff) {
1260 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1261 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1263 I915_WRITE(reg, pipe_stats[pipe]);
1267 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1274 /* Consume port. Then clear IIR or we'll miss events */
1275 if ((I915_HAS_HOTPLUG(dev)) &&
1276 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1277 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1279 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1281 if (hotplug_status & dev_priv->hotplug_supported_mask)
1282 queue_work(dev_priv->wq,
1283 &dev_priv->hotplug_work);
1285 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1286 I915_READ(PORT_HOTPLUG_STAT);
1289 I915_WRITE(IIR, iir);
1290 new_iir = I915_READ(IIR); /* Flush posted writes */
1292 if (dev->primary->master) {
1293 master_priv = dev->primary->master->driver_priv;
1294 if (master_priv->sarea_priv)
1295 master_priv->sarea_priv->last_dispatch =
1296 READ_BREADCRUMB(dev_priv);
1299 if (iir & I915_USER_INTERRUPT)
1300 notify_ring(dev, &dev_priv->ring[RCS]);
1301 if (iir & I915_BSD_USER_INTERRUPT)
1302 notify_ring(dev, &dev_priv->ring[VCS]);
1304 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1305 intel_prepare_page_flip(dev, 0);
1306 if (dev_priv->flip_pending_is_done)
1307 intel_finish_page_flip_plane(dev, 0);
1310 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1311 intel_prepare_page_flip(dev, 1);
1312 if (dev_priv->flip_pending_is_done)
1313 intel_finish_page_flip_plane(dev, 1);
1316 for_each_pipe(pipe) {
1317 if (pipe_stats[pipe] & vblank_status &&
1318 drm_handle_vblank(dev, pipe)) {
1320 if (!dev_priv->flip_pending_is_done) {
1321 i915_pageflip_stall_check(dev, pipe);
1322 intel_finish_page_flip(dev, pipe);
1326 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1331 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1332 intel_opregion_asle_intr(dev);
1334 /* With MSI, interrupts are only generated when iir
1335 * transitions from zero to nonzero. If another bit got
1336 * set while we were handling the existing iir bits, then
1337 * we would never get another interrupt.
1339 * This is fine on non-MSI as well, as if we hit this path
1340 * we avoid exiting the interrupt handler only to generate
1343 * Note that for MSI this could cause a stray interrupt report
1344 * if an interrupt landed in the time between writing IIR and
1345 * the posting read. This should be rare enough to never
1346 * trigger the 99% of 100,000 interrupts test for disabling
1355 static int i915_emit_irq(struct drm_device * dev)
1357 drm_i915_private_t *dev_priv = dev->dev_private;
1358 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1360 i915_kernel_lost_context(dev);
1362 DRM_DEBUG_DRIVER("\n");
1364 dev_priv->counter++;
1365 if (dev_priv->counter > 0x7FFFFFFFUL)
1366 dev_priv->counter = 1;
1367 if (master_priv->sarea_priv)
1368 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1370 if (BEGIN_LP_RING(4) == 0) {
1371 OUT_RING(MI_STORE_DWORD_INDEX);
1372 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1373 OUT_RING(dev_priv->counter);
1374 OUT_RING(MI_USER_INTERRUPT);
1378 return dev_priv->counter;
1381 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1383 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1384 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1386 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1388 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1389 READ_BREADCRUMB(dev_priv));
1391 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1392 if (master_priv->sarea_priv)
1393 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1397 if (master_priv->sarea_priv)
1398 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1400 if (ring->irq_get(ring)) {
1401 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1402 READ_BREADCRUMB(dev_priv) >= irq_nr);
1403 ring->irq_put(ring);
1404 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1407 if (ret == -EBUSY) {
1408 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1409 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1415 /* Needs the lock as it touches the ring.
1417 int i915_irq_emit(struct drm_device *dev, void *data,
1418 struct drm_file *file_priv)
1420 drm_i915_private_t *dev_priv = dev->dev_private;
1421 drm_i915_irq_emit_t *emit = data;
1424 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1425 DRM_ERROR("called with no initialization\n");
1429 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1431 mutex_lock(&dev->struct_mutex);
1432 result = i915_emit_irq(dev);
1433 mutex_unlock(&dev->struct_mutex);
1435 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1436 DRM_ERROR("copy_to_user\n");
1443 /* Doesn't need the hardware lock.
1445 int i915_irq_wait(struct drm_device *dev, void *data,
1446 struct drm_file *file_priv)
1448 drm_i915_private_t *dev_priv = dev->dev_private;
1449 drm_i915_irq_wait_t *irqwait = data;
1452 DRM_ERROR("called with no initialization\n");
1456 return i915_wait_irq(dev, irqwait->irq_seq);
1459 /* Called from drm generic code, passed 'crtc' which
1460 * we use as a pipe index
1462 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1464 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1465 unsigned long irqflags;
1467 if (!i915_pipe_enabled(dev, pipe))
1470 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1471 if (INTEL_INFO(dev)->gen >= 4)
1472 i915_enable_pipestat(dev_priv, pipe,
1473 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1475 i915_enable_pipestat(dev_priv, pipe,
1476 PIPE_VBLANK_INTERRUPT_ENABLE);
1478 /* maintain vblank delivery even in deep C-states */
1479 if (dev_priv->info->gen == 3)
1480 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1481 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1486 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1488 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1489 unsigned long irqflags;
1491 if (!i915_pipe_enabled(dev, pipe))
1494 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1495 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1496 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1497 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1502 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1505 unsigned long irqflags;
1507 if (!i915_pipe_enabled(dev, pipe))
1510 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1511 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1512 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1513 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1518 /* Called from drm generic code, passed 'crtc' which
1519 * we use as a pipe index
1521 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1524 unsigned long irqflags;
1526 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1527 if (dev_priv->info->gen == 3)
1529 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1531 i915_disable_pipestat(dev_priv, pipe,
1532 PIPE_VBLANK_INTERRUPT_ENABLE |
1533 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1534 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1537 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1539 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1540 unsigned long irqflags;
1542 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1543 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1544 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1545 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1548 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1550 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1551 unsigned long irqflags;
1553 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1554 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1555 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1556 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1559 /* Set the vblank monitor pipe
1561 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1562 struct drm_file *file_priv)
1564 drm_i915_private_t *dev_priv = dev->dev_private;
1567 DRM_ERROR("called with no initialization\n");
1574 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1575 struct drm_file *file_priv)
1577 drm_i915_private_t *dev_priv = dev->dev_private;
1578 drm_i915_vblank_pipe_t *pipe = data;
1581 DRM_ERROR("called with no initialization\n");
1585 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1591 * Schedule buffer swap at given vertical blank.
1593 int i915_vblank_swap(struct drm_device *dev, void *data,
1594 struct drm_file *file_priv)
1596 /* The delayed swap mechanism was fundamentally racy, and has been
1597 * removed. The model was that the client requested a delayed flip/swap
1598 * from the kernel, then waited for vblank before continuing to perform
1599 * rendering. The problem was that the kernel might wake the client
1600 * up before it dispatched the vblank swap (since the lock has to be
1601 * held while touching the ringbuffer), in which case the client would
1602 * clear and start the next frame before the swap occurred, and
1603 * flicker would occur in addition to likely missing the vblank.
1605 * In the absence of this ioctl, userland falls back to a correct path
1606 * of waiting for a vblank, then dispatching the swap on its own.
1607 * Context switching to userland and back is plenty fast enough for
1608 * meeting the requirements of vblank swapping.
1614 ring_last_seqno(struct intel_ring_buffer *ring)
1616 return list_entry(ring->request_list.prev,
1617 struct drm_i915_gem_request, list)->seqno;
1620 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1622 if (list_empty(&ring->request_list) ||
1623 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1624 /* Issue a wake-up to catch stuck h/w. */
1625 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1626 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1628 ring->waiting_seqno,
1629 ring->get_seqno(ring));
1630 wake_up_all(&ring->irq_queue);
1638 static bool kick_ring(struct intel_ring_buffer *ring)
1640 struct drm_device *dev = ring->dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 tmp = I915_READ_CTL(ring);
1643 if (tmp & RING_WAIT) {
1644 DRM_ERROR("Kicking stuck wait on %s\n",
1646 I915_WRITE_CTL(ring, tmp);
1650 (tmp & RING_WAIT_SEMAPHORE)) {
1651 DRM_ERROR("Kicking stuck semaphore on %s\n",
1653 I915_WRITE_CTL(ring, tmp);
1660 * This is called when the chip hasn't reported back with completed
1661 * batchbuffers in a long time. The first time this is called we simply record
1662 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1663 * again, we assume the chip is wedged and try to fix it.
1665 void i915_hangcheck_elapsed(unsigned long data)
1667 struct drm_device *dev = (struct drm_device *)data;
1668 drm_i915_private_t *dev_priv = dev->dev_private;
1669 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1672 if (!i915_enable_hangcheck)
1675 /* If all work is done then ACTHD clearly hasn't advanced. */
1676 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1677 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1678 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1679 dev_priv->hangcheck_count = 0;
1685 if (INTEL_INFO(dev)->gen < 4) {
1686 instdone = I915_READ(INSTDONE);
1689 instdone = I915_READ(INSTDONE_I965);
1690 instdone1 = I915_READ(INSTDONE1);
1692 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1693 acthd_bsd = HAS_BSD(dev) ?
1694 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1695 acthd_blt = HAS_BLT(dev) ?
1696 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1698 if (dev_priv->last_acthd == acthd &&
1699 dev_priv->last_acthd_bsd == acthd_bsd &&
1700 dev_priv->last_acthd_blt == acthd_blt &&
1701 dev_priv->last_instdone == instdone &&
1702 dev_priv->last_instdone1 == instdone1) {
1703 if (dev_priv->hangcheck_count++ > 1) {
1704 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1706 if (!IS_GEN2(dev)) {
1707 /* Is the chip hanging on a WAIT_FOR_EVENT?
1708 * If so we can simply poke the RB_WAIT bit
1709 * and break the hang. This should work on
1710 * all but the second generation chipsets.
1713 if (kick_ring(&dev_priv->ring[RCS]))
1717 kick_ring(&dev_priv->ring[VCS]))
1721 kick_ring(&dev_priv->ring[BCS]))
1725 i915_handle_error(dev, true);
1729 dev_priv->hangcheck_count = 0;
1731 dev_priv->last_acthd = acthd;
1732 dev_priv->last_acthd_bsd = acthd_bsd;
1733 dev_priv->last_acthd_blt = acthd_blt;
1734 dev_priv->last_instdone = instdone;
1735 dev_priv->last_instdone1 = instdone1;
1739 /* Reset timer case chip hangs without another request being added */
1740 mod_timer(&dev_priv->hangcheck_timer,
1741 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1746 static void ironlake_irq_preinstall(struct drm_device *dev)
1748 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1750 atomic_set(&dev_priv->irq_received, 0);
1752 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1753 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1754 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1755 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1757 I915_WRITE(HWSTAM, 0xeffe);
1758 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1759 /* Workaround stalls observed on Sandy Bridge GPUs by
1760 * making the blitter command streamer generate a
1761 * write to the Hardware Status Page for
1762 * MI_USER_INTERRUPT. This appears to serialize the
1763 * previous seqno write out before the interrupt
1766 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1767 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1770 /* XXX hotplug from PCH */
1772 I915_WRITE(DEIMR, 0xffffffff);
1773 I915_WRITE(DEIER, 0x0);
1774 POSTING_READ(DEIER);
1777 I915_WRITE(GTIMR, 0xffffffff);
1778 I915_WRITE(GTIER, 0x0);
1779 POSTING_READ(GTIER);
1781 /* south display irq */
1782 I915_WRITE(SDEIMR, 0xffffffff);
1783 I915_WRITE(SDEIER, 0x0);
1784 POSTING_READ(SDEIER);
1788 * Enable digital hotplug on the PCH, and configure the DP short pulse
1789 * duration to 2ms (which is the minimum in the Display Port spec)
1791 * This register is the same on all known PCH chips.
1794 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1796 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1799 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1800 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1801 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1802 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1803 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1804 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1807 static int ironlake_irq_postinstall(struct drm_device *dev)
1809 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1810 /* enable kind of interrupts always enabled */
1811 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1812 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1816 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1818 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1820 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1822 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1823 dev_priv->irq_mask = ~display_mask;
1825 /* should always can generate irq */
1826 I915_WRITE(DEIIR, I915_READ(DEIIR));
1827 I915_WRITE(DEIMR, dev_priv->irq_mask);
1828 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1829 POSTING_READ(DEIER);
1831 dev_priv->gt_irq_mask = ~0;
1833 I915_WRITE(GTIIR, I915_READ(GTIIR));
1834 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1839 GT_GEN6_BSD_USER_INTERRUPT |
1840 GT_BLT_USER_INTERRUPT;
1845 GT_BSD_USER_INTERRUPT;
1846 I915_WRITE(GTIER, render_irqs);
1847 POSTING_READ(GTIER);
1849 if (HAS_PCH_CPT(dev)) {
1850 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1851 SDE_PORTB_HOTPLUG_CPT |
1852 SDE_PORTC_HOTPLUG_CPT |
1853 SDE_PORTD_HOTPLUG_CPT);
1855 hotplug_mask = (SDE_CRT_HOTPLUG |
1862 dev_priv->pch_irq_mask = ~hotplug_mask;
1864 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1865 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1866 I915_WRITE(SDEIER, hotplug_mask);
1867 POSTING_READ(SDEIER);
1869 ironlake_enable_pch_hotplug(dev);
1871 if (IS_IRONLAKE_M(dev)) {
1872 /* Clear & enable PCU event interrupts */
1873 I915_WRITE(DEIIR, DE_PCU_EVENT);
1874 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1875 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1881 static int ivybridge_irq_postinstall(struct drm_device *dev)
1883 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1884 /* enable kind of interrupts always enabled */
1885 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1886 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1887 DE_PLANEB_FLIP_DONE_IVB;
1891 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1893 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1895 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1897 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1898 dev_priv->irq_mask = ~display_mask;
1900 /* should always can generate irq */
1901 I915_WRITE(DEIIR, I915_READ(DEIIR));
1902 I915_WRITE(DEIMR, dev_priv->irq_mask);
1903 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1904 DE_PIPEB_VBLANK_IVB);
1905 POSTING_READ(DEIER);
1907 dev_priv->gt_irq_mask = ~0;
1909 I915_WRITE(GTIIR, I915_READ(GTIIR));
1910 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1912 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1913 GT_BLT_USER_INTERRUPT;
1914 I915_WRITE(GTIER, render_irqs);
1915 POSTING_READ(GTIER);
1917 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1918 SDE_PORTB_HOTPLUG_CPT |
1919 SDE_PORTC_HOTPLUG_CPT |
1920 SDE_PORTD_HOTPLUG_CPT);
1921 dev_priv->pch_irq_mask = ~hotplug_mask;
1923 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1924 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1925 I915_WRITE(SDEIER, hotplug_mask);
1926 POSTING_READ(SDEIER);
1928 ironlake_enable_pch_hotplug(dev);
1933 static void i915_driver_irq_preinstall(struct drm_device * dev)
1935 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1938 atomic_set(&dev_priv->irq_received, 0);
1940 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1941 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1943 if (I915_HAS_HOTPLUG(dev)) {
1944 I915_WRITE(PORT_HOTPLUG_EN, 0);
1945 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1948 I915_WRITE(HWSTAM, 0xeffe);
1950 I915_WRITE(PIPESTAT(pipe), 0);
1951 I915_WRITE(IMR, 0xffffffff);
1952 I915_WRITE(IER, 0x0);
1957 * Must be called after intel_modeset_init or hotplug interrupts won't be
1958 * enabled correctly.
1960 static int i915_driver_irq_postinstall(struct drm_device *dev)
1962 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1963 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1966 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1968 /* Unmask the interrupts that we always want on. */
1969 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1971 dev_priv->pipestat[0] = 0;
1972 dev_priv->pipestat[1] = 0;
1974 if (I915_HAS_HOTPLUG(dev)) {
1975 /* Enable in IER... */
1976 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1977 /* and unmask in IMR */
1978 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1982 * Enable some error detection, note the instruction error mask
1983 * bit is reserved, so we leave it masked.
1986 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1987 GM45_ERROR_MEM_PRIV |
1988 GM45_ERROR_CP_PRIV |
1989 I915_ERROR_MEMORY_REFRESH);
1991 error_mask = ~(I915_ERROR_PAGE_TABLE |
1992 I915_ERROR_MEMORY_REFRESH);
1994 I915_WRITE(EMR, error_mask);
1996 I915_WRITE(IMR, dev_priv->irq_mask);
1997 I915_WRITE(IER, enable_mask);
2000 if (I915_HAS_HOTPLUG(dev)) {
2001 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2003 /* Note HDMI and DP share bits */
2004 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2005 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2006 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2007 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2008 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2009 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2010 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2011 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2012 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2013 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2014 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2015 hotplug_en |= CRT_HOTPLUG_INT_EN;
2017 /* Programming the CRT detection parameters tends
2018 to generate a spurious hotplug event about three
2019 seconds later. So just do it once.
2022 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2023 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2026 /* Ignore TV since it's buggy */
2028 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2031 intel_opregion_enable_asle(dev);
2036 static void ironlake_irq_uninstall(struct drm_device *dev)
2038 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2043 dev_priv->vblank_pipe = 0;
2045 I915_WRITE(HWSTAM, 0xffffffff);
2047 I915_WRITE(DEIMR, 0xffffffff);
2048 I915_WRITE(DEIER, 0x0);
2049 I915_WRITE(DEIIR, I915_READ(DEIIR));
2051 I915_WRITE(GTIMR, 0xffffffff);
2052 I915_WRITE(GTIER, 0x0);
2053 I915_WRITE(GTIIR, I915_READ(GTIIR));
2055 I915_WRITE(SDEIMR, 0xffffffff);
2056 I915_WRITE(SDEIER, 0x0);
2057 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2060 static void i915_driver_irq_uninstall(struct drm_device * dev)
2062 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2068 dev_priv->vblank_pipe = 0;
2070 if (I915_HAS_HOTPLUG(dev)) {
2071 I915_WRITE(PORT_HOTPLUG_EN, 0);
2072 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2075 I915_WRITE(HWSTAM, 0xffffffff);
2077 I915_WRITE(PIPESTAT(pipe), 0);
2078 I915_WRITE(IMR, 0xffffffff);
2079 I915_WRITE(IER, 0x0);
2082 I915_WRITE(PIPESTAT(pipe),
2083 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2084 I915_WRITE(IIR, I915_READ(IIR));
2087 void intel_irq_init(struct drm_device *dev)
2089 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2090 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2091 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2092 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2093 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2096 if (drm_core_check_feature(dev, DRIVER_MODESET))
2097 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2099 dev->driver->get_vblank_timestamp = NULL;
2100 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2102 if (IS_IVYBRIDGE(dev)) {
2103 /* Share pre & uninstall handlers with ILK/SNB */
2104 dev->driver->irq_handler = ivybridge_irq_handler;
2105 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2106 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2107 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2108 dev->driver->enable_vblank = ivybridge_enable_vblank;
2109 dev->driver->disable_vblank = ivybridge_disable_vblank;
2110 } else if (HAS_PCH_SPLIT(dev)) {
2111 dev->driver->irq_handler = ironlake_irq_handler;
2112 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2113 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2114 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2115 dev->driver->enable_vblank = ironlake_enable_vblank;
2116 dev->driver->disable_vblank = ironlake_disable_vblank;
2118 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2119 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2120 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2121 dev->driver->irq_handler = i915_driver_irq_handler;
2122 dev->driver->enable_vblank = i915_enable_vblank;
2123 dev->driver->disable_vblank = i915_disable_vblank;