drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 static inline u32
  89 i915_pipestat(int pipe)
  90 {
  91         if (pipe == 0)
  92                 return PIPEASTAT;
  93         if (pipe == 1)
  94                 return PIPEBSTAT;
  95         BUG();
  96 }
  97
  98 void
  99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 100 {
 101         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 102                 u32 reg = i915_pipestat(pipe);
 103
 104                 dev_priv->pipestat[pipe] |= mask;
 105                 /* Enable the interrupt, clear any pending status */
 106                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 107                 POSTING_READ(reg);
 108         }
 109 }
 110
 111 void
 112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 113 {
 114         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 115                 u32 reg = i915_pipestat(pipe);
 116
 117                 dev_priv->pipestat[pipe] &= ~mask;
 118                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 119                 POSTING_READ(reg);
 120         }
 121 }
 122
 123 /**
 124  * intel_enable_asle - enable ASLE interrupt for OpRegion
 125  */
 126 void intel_enable_asle(struct drm_device *dev)
 127 {
 128         drm_i915_private_t *dev_priv = dev->dev_private;
 129         unsigned long irqflags;
 130
 131         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 132
 133         if (HAS_PCH_SPLIT(dev))
 134                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 135         else {
 136                 i915_enable_pipestat(dev_priv, 1,
 137                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 138                 if (INTEL_INFO(dev)->gen >= 4)
 139                         i915_enable_pipestat(dev_priv, 0,
 140                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 141         }
 142
 143         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 144 }
 145
 146 /**
 147  * i915_pipe_enabled - check if a pipe is enabled
 148  * @dev: DRM device
 149  * @pipe: pipe to check
 150  *
 151  * Reading certain registers when the pipe is disabled can hang the chip.
 152  * Use this routine to make sure the PLL is running and the pipe is active
 153  * before reading such registers if unsure.
 154  */
 155 static int
 156 i915_pipe_enabled(struct drm_device *dev, int pipe)
 157 {
 158         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 159         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 160 }
 161
 162 /* Called from drm generic code, passed a 'crtc', which
 163  * we use as a pipe index
 164  */
 165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168         unsigned long high_frame;
 169         unsigned long low_frame;
 170         u32 high1, high2, low;
 171
 172         if (!i915_pipe_enabled(dev, pipe)) {
 173                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 174                                 "pipe %d\n", pipe);
 175                 return 0;
 176         }
 177
 178         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 179         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 180
 181         /*
 182          * High & low register fields aren't synchronized, so make sure
 183          * we get a low value that's stable across two reads of the high
 184          * register.
 185          */
 186         do {
 187                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 188                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 189                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 190         } while (high1 != high2);
 191
 192         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 193         low >>= PIPE_FRAME_LOW_SHIFT;
 194         return (high1 << 8) | low;
 195 }
 196
 197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 198 {
 199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 200         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 201
 202         if (!i915_pipe_enabled(dev, pipe)) {
 203                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 204                                         "pipe %d\n", pipe);
 205                 return 0;
 206         }
 207
 208         return I915_READ(reg);
 209 }
 210
 211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 212                              int *vpos, int *hpos)
 213 {
 214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 215         u32 vbl = 0, position = 0;
 216         int vbl_start, vbl_end, htotal, vtotal;
 217         bool in_vbl = true;
 218         int ret = 0;
 219
 220         if (!i915_pipe_enabled(dev, pipe)) {
 221                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 222                                         "pipe %d\n", pipe);
 223                 return 0;
 224         }
 225
 226         /* Get vtotal. */
 227         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 228
 229         if (INTEL_INFO(dev)->gen >= 4) {
 230                 /* No obvious pixelcount register. Only query vertical
 231                  * scanout position from Display scan line register.
 232                  */
 233                 position = I915_READ(PIPEDSL(pipe));
 234
 235                 /* Decode into vertical scanout position. Don't have
 236                  * horizontal scanout position.
 237                  */
 238                 *vpos = position & 0x1fff;
 239                 *hpos = 0;
 240         } else {
 241                 /* Have access to pixelcount since start of frame.
 242                  * We can split this into vertical and horizontal
 243                  * scanout position.
 244                  */
 245                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 246
 247                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 248                 *vpos = position / htotal;
 249                 *hpos = position - (*vpos * htotal);
 250         }
 251
 252         /* Query vblank area. */
 253         vbl = I915_READ(VBLANK(pipe));
 254
 255         /* Test position against vblank region. */
 256         vbl_start = vbl & 0x1fff;
 257         vbl_end = (vbl >> 16) & 0x1fff;
 258
 259         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 260                 in_vbl = false;
 261
 262         /* Inside "upper part" of vblank area? Apply corrective offset: */
 263         if (in_vbl && (*vpos >= vbl_start))
 264                 *vpos = *vpos - vtotal;
 265
 266         /* Readouts valid? */
 267         if (vbl > 0)
 268                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 269
 270         /* In vblank? */
 271         if (in_vbl)
 272                 ret |= DRM_SCANOUTPOS_INVBL;
 273
 274         return ret;
 275 }
 276
 277 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
 278                               int *max_error,
 279                               struct timeval *vblank_time,
 280                               unsigned flags)
 281 {
 282         struct drm_crtc *drmcrtc;
 283
 284         if (crtc < 0 || crtc >= dev->num_crtcs) {
 285                 DRM_ERROR("Invalid crtc %d\n", crtc);
 286                 return -EINVAL;
 287         }
 288
 289         /* Get drm_crtc to timestamp: */
 290         drmcrtc = intel_get_crtc_for_pipe(dev, crtc);
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 294                                                      vblank_time, flags, drmcrtc);
 295 }
 296
 297 /*
 298  * Handle hotplug events outside the interrupt handler proper.
 299  */
 300 static void i915_hotplug_work_func(struct work_struct *work)
 301 {
 302         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 303                                                     hotplug_work);
 304         struct drm_device *dev = dev_priv->dev;
 305         struct drm_mode_config *mode_config = &dev->mode_config;
 306         struct intel_encoder *encoder;
 307
 308         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 309                 if (encoder->hot_plug)
 310                         encoder->hot_plug(encoder);
 311
 312         /* Just fire off a uevent and let userspace tell us what to do */
 313         drm_helper_hpd_irq_event(dev);
 314 }
 315
 316 static void i915_handle_rps_change(struct drm_device *dev)
 317 {
 318         drm_i915_private_t *dev_priv = dev->dev_private;
 319         u32 busy_up, busy_down, max_avg, min_avg;
 320         u8 new_delay = dev_priv->cur_delay;
 321
 322         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 323         busy_up = I915_READ(RCPREVBSYTUPAVG);
 324         busy_down = I915_READ(RCPREVBSYTDNAVG);
 325         max_avg = I915_READ(RCBMAXAVG);
 326         min_avg = I915_READ(RCBMINAVG);
 327
 328         /* Handle RCS change request from hw */
 329         if (busy_up > max_avg) {
 330                 if (dev_priv->cur_delay != dev_priv->max_delay)
 331                         new_delay = dev_priv->cur_delay - 1;
 332                 if (new_delay < dev_priv->max_delay)
 333                         new_delay = dev_priv->max_delay;
 334         } else if (busy_down < min_avg) {
 335                 if (dev_priv->cur_delay != dev_priv->min_delay)
 336                         new_delay = dev_priv->cur_delay + 1;
 337                 if (new_delay > dev_priv->min_delay)
 338                         new_delay = dev_priv->min_delay;
 339         }
 340
 341         if (ironlake_set_drps(dev, new_delay))
 342                 dev_priv->cur_delay = new_delay;
 343
 344         return;
 345 }
 346
 347 static void notify_ring(struct drm_device *dev,
 348                         struct intel_ring_buffer *ring)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         u32 seqno = ring->get_seqno(ring);
 352
 353         trace_i915_gem_request_complete(dev, seqno);
 354
 355         ring->irq_seqno = seqno;
 356         wake_up_all(&ring->irq_queue);
 357
 358         dev_priv->hangcheck_count = 0;
 359         mod_timer(&dev_priv->hangcheck_timer,
 360                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 361 }
 362
 363 static void gen6_pm_irq_handler(struct drm_device *dev)
 364 {
 365         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 366         u8 new_delay = dev_priv->cur_delay;
 367         u32 pm_iir;
 368
 369         pm_iir = I915_READ(GEN6_PMIIR);
 370         if (!pm_iir)
 371                 return;
 372
 373         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 374                 if (dev_priv->cur_delay != dev_priv->max_delay)
 375                         new_delay = dev_priv->cur_delay + 1;
 376                 if (new_delay > dev_priv->max_delay)
 377                         new_delay = dev_priv->max_delay;
 378         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 379                 if (dev_priv->cur_delay != dev_priv->min_delay)
 380                         new_delay = dev_priv->cur_delay - 1;
 381                 if (new_delay < dev_priv->min_delay) {
 382                         new_delay = dev_priv->min_delay;
 383                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 384                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 385                                    ((new_delay << 16) & 0x3f0000));
 386                 } else {
 387                         /* Make sure we continue to get down interrupts
 388                          * until we hit the minimum frequency */
 389                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 390                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 391                 }
 392
 393         }
 394
 395         gen6_set_rps(dev, new_delay);
 396         dev_priv->cur_delay = new_delay;
 397
 398         I915_WRITE(GEN6_PMIIR, pm_iir);
 399 }
 400
 401 static void pch_irq_handler(struct drm_device *dev)
 402 {
 403         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 404         u32 pch_iir;
 405
 406         pch_iir = I915_READ(SDEIIR);
 407
 408         if (pch_iir & SDE_AUDIO_POWER_MASK)
 409                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 410                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 411                                  SDE_AUDIO_POWER_SHIFT);
 412
 413         if (pch_iir & SDE_GMBUS)
 414                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 415
 416         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 417                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 418
 419         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 420                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 421
 422         if (pch_iir & SDE_POISON)
 423                 DRM_ERROR("PCH poison interrupt\n");
 424
 425         if (pch_iir & SDE_FDI_MASK) {
 426                 u32 fdia, fdib;
 427
 428                 fdia = I915_READ(FDI_RXA_IIR);
 429                 fdib = I915_READ(FDI_RXB_IIR);
 430                 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
 431         }
 432
 433         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 434                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 435
 436         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 437                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 438
 439         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 440                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 441         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 442                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 443 }
 444
 445 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 446 {
 447         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 448         int ret = IRQ_NONE;
 449         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 450         u32 hotplug_mask;
 451         struct drm_i915_master_private *master_priv;
 452         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 453
 454         if (IS_GEN6(dev))
 455                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 456
 457         /* disable master interrupt before clearing iir  */
 458         de_ier = I915_READ(DEIER);
 459         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 460         POSTING_READ(DEIER);
 461
 462         de_iir = I915_READ(DEIIR);
 463         gt_iir = I915_READ(GTIIR);
 464         pch_iir = I915_READ(SDEIIR);
 465         pm_iir = I915_READ(GEN6_PMIIR);
 466
 467         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 468             (!IS_GEN6(dev) || pm_iir == 0))
 469                 goto done;
 470
 471         if (HAS_PCH_CPT(dev))
 472                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 473         else
 474                 hotplug_mask = SDE_HOTPLUG_MASK;
 475
 476         ret = IRQ_HANDLED;
 477
 478         if (dev->primary->master) {
 479                 master_priv = dev->primary->master->driver_priv;
 480                 if (master_priv->sarea_priv)
 481                         master_priv->sarea_priv->last_dispatch =
 482                                 READ_BREADCRUMB(dev_priv);
 483         }
 484
 485         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 486                 notify_ring(dev, &dev_priv->ring[RCS]);
 487         if (gt_iir & bsd_usr_interrupt)
 488                 notify_ring(dev, &dev_priv->ring[VCS]);
 489         if (gt_iir & GT_BLT_USER_INTERRUPT)
 490                 notify_ring(dev, &dev_priv->ring[BCS]);
 491
 492         if (de_iir & DE_GSE)
 493                 intel_opregion_gse_intr(dev);
 494
 495         if (de_iir & DE_PLANEA_FLIP_DONE) {
 496                 intel_prepare_page_flip(dev, 0);
 497                 intel_finish_page_flip_plane(dev, 0);
 498         }
 499
 500         if (de_iir & DE_PLANEB_FLIP_DONE) {
 501                 intel_prepare_page_flip(dev, 1);
 502                 intel_finish_page_flip_plane(dev, 1);
 503         }
 504
 505         if (de_iir & DE_PIPEA_VBLANK)
 506                 drm_handle_vblank(dev, 0);
 507
 508         if (de_iir & DE_PIPEB_VBLANK)
 509                 drm_handle_vblank(dev, 1);
 510
 511         /* check event from PCH */
 512         if (de_iir & DE_PCH_EVENT) {
 513                 if (pch_iir & hotplug_mask)
 514                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 515                 pch_irq_handler(dev);
 516         }
 517
 518         if (de_iir & DE_PCU_EVENT) {
 519                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 520                 i915_handle_rps_change(dev);
 521         }
 522
 523         if (IS_GEN6(dev))
 524                 gen6_pm_irq_handler(dev);
 525
 526         /* should clear PCH hotplug event before clear CPU irq */
 527         I915_WRITE(SDEIIR, pch_iir);
 528         I915_WRITE(GTIIR, gt_iir);
 529         I915_WRITE(DEIIR, de_iir);
 530
 531 done:
 532         I915_WRITE(DEIER, de_ier);
 533         POSTING_READ(DEIER);
 534
 535         return ret;
 536 }
 537
 538 /**
 539  * i915_error_work_func - do process context error handling work
 540  * @work: work struct
 541  *
 542  * Fire an error uevent so userspace can see that a hang or error
 543  * was detected.
 544  */
 545 static void i915_error_work_func(struct work_struct *work)
 546 {
 547         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 548                                                     error_work);
 549         struct drm_device *dev = dev_priv->dev;
 550         char *error_event[] = { "ERROR=1", NULL };
 551         char *reset_event[] = { "RESET=1", NULL };
 552         char *reset_done_event[] = { "ERROR=0", NULL };
 553
 554         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 555
 556         if (atomic_read(&dev_priv->mm.wedged)) {
 557                 DRM_DEBUG_DRIVER("resetting chip\n");
 558                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 559                 if (!i915_reset(dev, GRDOM_RENDER)) {
 560                         atomic_set(&dev_priv->mm.wedged, 0);
 561                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 562                 }
 563                 complete_all(&dev_priv->error_completion);
 564         }
 565 }
 566
 567 #ifdef CONFIG_DEBUG_FS
 568 static struct drm_i915_error_object *
 569 i915_error_object_create(struct drm_i915_private *dev_priv,
 570                          struct drm_i915_gem_object *src)
 571 {
 572         struct drm_i915_error_object *dst;
 573         int page, page_count;
 574         u32 reloc_offset;
 575
 576         if (src == NULL || src->pages == NULL)
 577                 return NULL;
 578
 579         page_count = src->base.size / PAGE_SIZE;
 580
 581         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 582         if (dst == NULL)
 583                 return NULL;
 584
 585         reloc_offset = src->gtt_offset;
 586         for (page = 0; page < page_count; page++) {
 587                 unsigned long flags;
 588                 void __iomem *s;
 589                 void *d;
 590
 591                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 592                 if (d == NULL)
 593                         goto unwind;
 594
 595                 local_irq_save(flags);
 596                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 597                                              reloc_offset);
 598                 memcpy_fromio(d, s, PAGE_SIZE);
 599                 io_mapping_unmap_atomic(s);
 600                 local_irq_restore(flags);
 601
 602                 dst->pages[page] = d;
 603
 604                 reloc_offset += PAGE_SIZE;
 605         }
 606         dst->page_count = page_count;
 607         dst->gtt_offset = src->gtt_offset;
 608
 609         return dst;
 610
 611 unwind:
 612         while (page--)
 613                 kfree(dst->pages[page]);
 614         kfree(dst);
 615         return NULL;
 616 }
 617
 618 static void
 619 i915_error_object_free(struct drm_i915_error_object *obj)
 620 {
 621         int page;
 622
 623         if (obj == NULL)
 624                 return;
 625
 626         for (page = 0; page < obj->page_count; page++)
 627                 kfree(obj->pages[page]);
 628
 629         kfree(obj);
 630 }
 631
 632 static void
 633 i915_error_state_free(struct drm_device *dev,
 634                       struct drm_i915_error_state *error)
 635 {
 636         i915_error_object_free(error->batchbuffer[0]);
 637         i915_error_object_free(error->batchbuffer[1]);
 638         i915_error_object_free(error->ringbuffer);
 639         kfree(error->active_bo);
 640         kfree(error->overlay);
 641         kfree(error);
 642 }
 643
 644 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 645                            int count,
 646                            struct list_head *head)
 647 {
 648         struct drm_i915_gem_object *obj;
 649         int i = 0;
 650
 651         list_for_each_entry(obj, head, mm_list) {
 652                 err->size = obj->base.size;
 653                 err->name = obj->base.name;
 654                 err->seqno = obj->last_rendering_seqno;
 655                 err->gtt_offset = obj->gtt_offset;
 656                 err->read_domains = obj->base.read_domains;
 657                 err->write_domain = obj->base.write_domain;
 658                 err->fence_reg = obj->fence_reg;
 659                 err->pinned = 0;
 660                 if (obj->pin_count > 0)
 661                         err->pinned = 1;
 662                 if (obj->user_pin_count > 0)
 663                         err->pinned = -1;
 664                 err->tiling = obj->tiling_mode;
 665                 err->dirty = obj->dirty;
 666                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 667                 err->ring = obj->ring ? obj->ring->id : 0;
 668                 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
 669
 670                 if (++i == count)
 671                         break;
 672
 673                 err++;
 674         }
 675
 676         return i;
 677 }
 678
 679 static void i915_gem_record_fences(struct drm_device *dev,
 680                                    struct drm_i915_error_state *error)
 681 {
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         int i;
 684
 685         /* Fences */
 686         switch (INTEL_INFO(dev)->gen) {
 687         case 6:
 688                 for (i = 0; i < 16; i++)
 689                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 690                 break;
 691         case 5:
 692         case 4:
 693                 for (i = 0; i < 16; i++)
 694                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 695                 break;
 696         case 3:
 697                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 698                         for (i = 0; i < 8; i++)
 699                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 700         case 2:
 701                 for (i = 0; i < 8; i++)
 702                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 703                 break;
 704
 705         }
 706 }
 707
 708 static struct drm_i915_error_object *
 709 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 710                              struct intel_ring_buffer *ring)
 711 {
 712         struct drm_i915_gem_object *obj;
 713         u32 seqno;
 714
 715         if (!ring->get_seqno)
 716                 return NULL;
 717
 718         seqno = ring->get_seqno(ring);
 719         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 720                 if (obj->ring != ring)
 721                         continue;
 722
 723                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 724                         continue;
 725
 726                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 727                         continue;
 728
 729                 /* We need to copy these to an anonymous buffer as the simplest
 730                  * method to avoid being overwritten by userspace.
 731                  */
 732                 return i915_error_object_create(dev_priv, obj);
 733         }
 734
 735         return NULL;
 736 }
 737
 738 /**
 739  * i915_capture_error_state - capture an error record for later analysis
 740  * @dev: drm device
 741  *
 742  * Should be called when an error is detected (either a hang or an error
 743  * interrupt) to capture error state from the time of the error.  Fills
 744  * out a structure which becomes available in debugfs for user level tools
 745  * to pick up.
 746  */
 747 static void i915_capture_error_state(struct drm_device *dev)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750         struct drm_i915_gem_object *obj;
 751         struct drm_i915_error_state *error;
 752         unsigned long flags;
 753         int i;
 754
 755         spin_lock_irqsave(&dev_priv->error_lock, flags);
 756         error = dev_priv->first_error;
 757         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 758         if (error)
 759                 return;
 760
 761         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 762         if (!error) {
 763                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 764                 return;
 765         }
 766
 767         DRM_DEBUG_DRIVER("generating error event\n");
 768
 769         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
 770         error->eir = I915_READ(EIR);
 771         error->pgtbl_er = I915_READ(PGTBL_ER);
 772         error->pipeastat = I915_READ(PIPEASTAT);
 773         error->pipebstat = I915_READ(PIPEBSTAT);
 774         error->instpm = I915_READ(INSTPM);
 775         error->error = 0;
 776         if (INTEL_INFO(dev)->gen >= 6) {
 777                 error->error = I915_READ(ERROR_GEN6);
 778
 779                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 780                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 781                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 782                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 783                 error->bcs_seqno = 0;
 784                 if (dev_priv->ring[BCS].get_seqno)
 785                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
 786
 787                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 788                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 789                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 790                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 791                 error->vcs_seqno = 0;
 792                 if (dev_priv->ring[VCS].get_seqno)
 793                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
 794         }
 795         if (INTEL_INFO(dev)->gen >= 4) {
 796                 error->ipeir = I915_READ(IPEIR_I965);
 797                 error->ipehr = I915_READ(IPEHR_I965);
 798                 error->instdone = I915_READ(INSTDONE_I965);
 799                 error->instps = I915_READ(INSTPS);
 800                 error->instdone1 = I915_READ(INSTDONE1);
 801                 error->acthd = I915_READ(ACTHD_I965);
 802                 error->bbaddr = I915_READ64(BB_ADDR);
 803         } else {
 804                 error->ipeir = I915_READ(IPEIR);
 805                 error->ipehr = I915_READ(IPEHR);
 806                 error->instdone = I915_READ(INSTDONE);
 807                 error->acthd = I915_READ(ACTHD);
 808                 error->bbaddr = 0;
 809         }
 810         i915_gem_record_fences(dev, error);
 811
 812         /* Record the active batchbuffers */
 813         for (i = 0; i < I915_NUM_RINGS; i++)
 814                 error->batchbuffer[i] =
 815                         i915_error_first_batchbuffer(dev_priv,
 816                                                      &dev_priv->ring[i]);
 817
 818         /* Record the ringbuffer */
 819         error->ringbuffer = i915_error_object_create(dev_priv,
 820                                                      dev_priv->ring[RCS].obj);
 821
 822         /* Record buffers on the active and pinned lists. */
 823         error->active_bo = NULL;
 824         error->pinned_bo = NULL;
 825
 826         i = 0;
 827         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 828                 i++;
 829         error->active_bo_count = i;
 830         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 831                 i++;
 832         error->pinned_bo_count = i - error->active_bo_count;
 833
 834         if (i) {
 835                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 836                                            GFP_ATOMIC);
 837                 if (error->active_bo)
 838                         error->pinned_bo =
 839                                 error->active_bo + error->active_bo_count;
 840         }
 841
 842         if (error->active_bo)
 843                 error->active_bo_count =
 844                         capture_bo_list(error->active_bo,
 845                                         error->active_bo_count,
 846                                         &dev_priv->mm.active_list);
 847
 848         if (error->pinned_bo)
 849                 error->pinned_bo_count =
 850                         capture_bo_list(error->pinned_bo,
 851                                         error->pinned_bo_count,
 852                                         &dev_priv->mm.pinned_list);
 853
 854         do_gettimeofday(&error->time);
 855
 856         error->overlay = intel_overlay_capture_error_state(dev);
 857         error->display = intel_display_capture_error_state(dev);
 858
 859         spin_lock_irqsave(&dev_priv->error_lock, flags);
 860         if (dev_priv->first_error == NULL) {
 861                 dev_priv->first_error = error;
 862                 error = NULL;
 863         }
 864         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 865
 866         if (error)
 867                 i915_error_state_free(dev, error);
 868 }
 869
 870 void i915_destroy_error_state(struct drm_device *dev)
 871 {
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873         struct drm_i915_error_state *error;
 874
 875         spin_lock(&dev_priv->error_lock);
 876         error = dev_priv->first_error;
 877         dev_priv->first_error = NULL;
 878         spin_unlock(&dev_priv->error_lock);
 879
 880         if (error)
 881                 i915_error_state_free(dev, error);
 882 }
 883 #else
 884 #define i915_capture_error_state(x)
 885 #endif
 886
 887 static void i915_report_and_clear_eir(struct drm_device *dev)
 888 {
 889         struct drm_i915_private *dev_priv = dev->dev_private;
 890         u32 eir = I915_READ(EIR);
 891
 892         if (!eir)
 893                 return;
 894
 895         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 896                eir);
 897
 898         if (IS_G4X(dev)) {
 899                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 900                         u32 ipeir = I915_READ(IPEIR_I965);
 901
 902                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 903                                I915_READ(IPEIR_I965));
 904                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 905                                I915_READ(IPEHR_I965));
 906                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 907                                I915_READ(INSTDONE_I965));
 908                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 909                                I915_READ(INSTPS));
 910                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 911                                I915_READ(INSTDONE1));
 912                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 913                                I915_READ(ACTHD_I965));
 914                         I915_WRITE(IPEIR_I965, ipeir);
 915                         POSTING_READ(IPEIR_I965);
 916                 }
 917                 if (eir & GM45_ERROR_PAGE_TABLE) {
 918                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 919                         printk(KERN_ERR "page table error\n");
 920                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 921                                pgtbl_err);
 922                         I915_WRITE(PGTBL_ER, pgtbl_err);
 923                         POSTING_READ(PGTBL_ER);
 924                 }
 925         }
 926
 927         if (!IS_GEN2(dev)) {
 928                 if (eir & I915_ERROR_PAGE_TABLE) {
 929                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 930                         printk(KERN_ERR "page table error\n");
 931                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 932                                pgtbl_err);
 933                         I915_WRITE(PGTBL_ER, pgtbl_err);
 934                         POSTING_READ(PGTBL_ER);
 935                 }
 936         }
 937
 938         if (eir & I915_ERROR_MEMORY_REFRESH) {
 939                 u32 pipea_stats = I915_READ(PIPEASTAT);
 940                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 941
 942                 printk(KERN_ERR "memory refresh error\n");
 943                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 944                        pipea_stats);
 945                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 946                        pipeb_stats);
 947                 /* pipestat has already been acked */
 948         }
 949         if (eir & I915_ERROR_INSTRUCTION) {
 950                 printk(KERN_ERR "instruction error\n");
 951                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 952                        I915_READ(INSTPM));
 953                 if (INTEL_INFO(dev)->gen < 4) {
 954                         u32 ipeir = I915_READ(IPEIR);
 955
 956                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 957                                I915_READ(IPEIR));
 958                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 959                                I915_READ(IPEHR));
 960                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 961                                I915_READ(INSTDONE));
 962                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 963                                I915_READ(ACTHD));
 964                         I915_WRITE(IPEIR, ipeir);
 965                         POSTING_READ(IPEIR);
 966                 } else {
 967                         u32 ipeir = I915_READ(IPEIR_I965);
 968
 969                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 970                                I915_READ(IPEIR_I965));
 971                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 972                                I915_READ(IPEHR_I965));
 973                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 974                                I915_READ(INSTDONE_I965));
 975                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 976                                I915_READ(INSTPS));
 977                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 978                                I915_READ(INSTDONE1));
 979                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 980                                I915_READ(ACTHD_I965));
 981                         I915_WRITE(IPEIR_I965, ipeir);
 982                         POSTING_READ(IPEIR_I965);
 983                 }
 984         }
 985
 986         I915_WRITE(EIR, eir);
 987         POSTING_READ(EIR);
 988         eir = I915_READ(EIR);
 989         if (eir) {
 990                 /*
 991                  * some errors might have become stuck,
 992                  * mask them.
 993                  */
 994                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 995                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 996                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 997         }
 998 }
 999
1000 /**
1001  * i915_handle_error - handle an error interrupt
1002  * @dev: drm device
1003  *
1004  * Do some basic checking of regsiter state at error interrupt time and
1005  * dump it to the syslog.  Also call i915_capture_error_state() to make
1006  * sure we get a record and make it available in debugfs.  Fire a uevent
1007  * so userspace knows something bad happened (should trigger collection
1008  * of a ring dump etc.).
1009  */
1010 void i915_handle_error(struct drm_device *dev, bool wedged)
1011 {
1012         struct drm_i915_private *dev_priv = dev->dev_private;
1013
1014         i915_capture_error_state(dev);
1015         i915_report_and_clear_eir(dev);
1016
1017         if (wedged) {
1018                 INIT_COMPLETION(dev_priv->error_completion);
1019                 atomic_set(&dev_priv->mm.wedged, 1);
1020
1021                 /*
1022                  * Wakeup waiting processes so they don't hang
1023                  */
1024                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1025                 if (HAS_BSD(dev))
1026                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1027                 if (HAS_BLT(dev))
1028                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1029         }
1030
1031         queue_work(dev_priv->wq, &dev_priv->error_work);
1032 }
1033
1034 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1035 {
1036         drm_i915_private_t *dev_priv = dev->dev_private;
1037         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039         struct drm_i915_gem_object *obj;
1040         struct intel_unpin_work *work;
1041         unsigned long flags;
1042         bool stall_detected;
1043
1044         /* Ignore early vblank irqs */
1045         if (intel_crtc == NULL)
1046                 return;
1047
1048         spin_lock_irqsave(&dev->event_lock, flags);
1049         work = intel_crtc->unpin_work;
1050
1051         if (work == NULL || work->pending || !work->enable_stall_check) {
1052                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1053                 spin_unlock_irqrestore(&dev->event_lock, flags);
1054                 return;
1055         }
1056
1057         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1058         obj = work->pending_flip_obj;
1059         if (INTEL_INFO(dev)->gen >= 4) {
1060                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1061                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1062         } else {
1063                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1064                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1065                                                         crtc->y * crtc->fb->pitch +
1066                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1067         }
1068
1069         spin_unlock_irqrestore(&dev->event_lock, flags);
1070
1071         if (stall_detected) {
1072                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1073                 intel_prepare_page_flip(dev, intel_crtc->plane);
1074         }
1075 }
1076
1077 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1078 {
1079         struct drm_device *dev = (struct drm_device *) arg;
1080         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1081         struct drm_i915_master_private *master_priv;
1082         u32 iir, new_iir;
1083         u32 pipea_stats, pipeb_stats;
1084         u32 vblank_status;
1085         int vblank = 0;
1086         unsigned long irqflags;
1087         int irq_received;
1088         int ret = IRQ_NONE;
1089
1090         atomic_inc(&dev_priv->irq_received);
1091
1092         if (HAS_PCH_SPLIT(dev))
1093                 return ironlake_irq_handler(dev);
1094
1095         iir = I915_READ(IIR);
1096
1097         if (INTEL_INFO(dev)->gen >= 4)
1098                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1099         else
1100                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1101
1102         for (;;) {
1103                 irq_received = iir != 0;
1104
1105                 /* Can't rely on pipestat interrupt bit in iir as it might
1106                  * have been cleared after the pipestat interrupt was received.
1107                  * It doesn't set the bit in iir again, but it still produces
1108                  * interrupts (for non-MSI).
1109                  */
1110                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1111                 pipea_stats = I915_READ(PIPEASTAT);
1112                 pipeb_stats = I915_READ(PIPEBSTAT);
1113
1114                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1115                         i915_handle_error(dev, false);
1116
1117                 /*
1118                  * Clear the PIPE(A|B)STAT regs before the IIR
1119                  */
1120                 if (pipea_stats & 0x8000ffff) {
1121                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1122                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1123                         I915_WRITE(PIPEASTAT, pipea_stats);
1124                         irq_received = 1;
1125                 }
1126
1127                 if (pipeb_stats & 0x8000ffff) {
1128                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1129                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1130                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1131                         irq_received = 1;
1132                 }
1133                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1134
1135                 if (!irq_received)
1136                         break;
1137
1138                 ret = IRQ_HANDLED;
1139
1140                 /* Consume port.  Then clear IIR or we'll miss events */
1141                 if ((I915_HAS_HOTPLUG(dev)) &&
1142                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1143                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1144
1145                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1146                                   hotplug_status);
1147                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1148                                 queue_work(dev_priv->wq,
1149                                            &dev_priv->hotplug_work);
1150
1151                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1152                         I915_READ(PORT_HOTPLUG_STAT);
1153                 }
1154
1155                 I915_WRITE(IIR, iir);
1156                 new_iir = I915_READ(IIR); /* Flush posted writes */
1157
1158                 if (dev->primary->master) {
1159                         master_priv = dev->primary->master->driver_priv;
1160                         if (master_priv->sarea_priv)
1161                                 master_priv->sarea_priv->last_dispatch =
1162                                         READ_BREADCRUMB(dev_priv);
1163                 }
1164
1165                 if (iir & I915_USER_INTERRUPT)
1166                         notify_ring(dev, &dev_priv->ring[RCS]);
1167                 if (iir & I915_BSD_USER_INTERRUPT)
1168                         notify_ring(dev, &dev_priv->ring[VCS]);
1169
1170                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1171                         intel_prepare_page_flip(dev, 0);
1172                         if (dev_priv->flip_pending_is_done)
1173                                 intel_finish_page_flip_plane(dev, 0);
1174                 }
1175
1176                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1177                         intel_prepare_page_flip(dev, 1);
1178                         if (dev_priv->flip_pending_is_done)
1179                                 intel_finish_page_flip_plane(dev, 1);
1180                 }
1181
1182                 if (pipea_stats & vblank_status) {
1183                         vblank++;
1184                         drm_handle_vblank(dev, 0);
1185                         if (!dev_priv->flip_pending_is_done) {
1186                                 i915_pageflip_stall_check(dev, 0);
1187                                 intel_finish_page_flip(dev, 0);
1188                         }
1189                 }
1190
1191                 if (pipeb_stats & vblank_status) {
1192                         vblank++;
1193                         drm_handle_vblank(dev, 1);
1194                         if (!dev_priv->flip_pending_is_done) {
1195                                 i915_pageflip_stall_check(dev, 1);
1196                                 intel_finish_page_flip(dev, 1);
1197                         }
1198                 }
1199
1200                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1201                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1202                     (iir & I915_ASLE_INTERRUPT))
1203                         intel_opregion_asle_intr(dev);
1204
1205                 /* With MSI, interrupts are only generated when iir
1206                  * transitions from zero to nonzero.  If another bit got
1207                  * set while we were handling the existing iir bits, then
1208                  * we would never get another interrupt.
1209                  *
1210                  * This is fine on non-MSI as well, as if we hit this path
1211                  * we avoid exiting the interrupt handler only to generate
1212                  * another one.
1213                  *
1214                  * Note that for MSI this could cause a stray interrupt report
1215                  * if an interrupt landed in the time between writing IIR and
1216                  * the posting read.  This should be rare enough to never
1217                  * trigger the 99% of 100,000 interrupts test for disabling
1218                  * stray interrupts.
1219                  */
1220                 iir = new_iir;
1221         }
1222
1223         return ret;
1224 }
1225
1226 static int i915_emit_irq(struct drm_device * dev)
1227 {
1228         drm_i915_private_t *dev_priv = dev->dev_private;
1229         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1230
1231         i915_kernel_lost_context(dev);
1232
1233         DRM_DEBUG_DRIVER("\n");
1234
1235         dev_priv->counter++;
1236         if (dev_priv->counter > 0x7FFFFFFFUL)
1237                 dev_priv->counter = 1;
1238         if (master_priv->sarea_priv)
1239                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1240
1241         if (BEGIN_LP_RING(4) == 0) {
1242                 OUT_RING(MI_STORE_DWORD_INDEX);
1243                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1244                 OUT_RING(dev_priv->counter);
1245                 OUT_RING(MI_USER_INTERRUPT);
1246                 ADVANCE_LP_RING();
1247         }
1248
1249         return dev_priv->counter;
1250 }
1251
1252 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1253 {
1254         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1255         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1256
1257         if (dev_priv->trace_irq_seqno == 0 &&
1258             ring->irq_get(ring))
1259                 dev_priv->trace_irq_seqno = seqno;
1260 }
1261
1262 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1263 {
1264         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1265         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1266         int ret = 0;
1267         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1268
1269         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1270                   READ_BREADCRUMB(dev_priv));
1271
1272         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1273                 if (master_priv->sarea_priv)
1274                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1275                 return 0;
1276         }
1277
1278         if (master_priv->sarea_priv)
1279                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1280
1281         ret = -ENODEV;
1282         if (ring->irq_get(ring)) {
1283                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1284                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1285                 ring->irq_put(ring);
1286         }
1287
1288         if (ret == -EBUSY) {
1289                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1290                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1291         }
1292
1293         return ret;
1294 }
1295
1296 /* Needs the lock as it touches the ring.
1297  */
1298 int i915_irq_emit(struct drm_device *dev, void *data,
1299                          struct drm_file *file_priv)
1300 {
1301         drm_i915_private_t *dev_priv = dev->dev_private;
1302         drm_i915_irq_emit_t *emit = data;
1303         int result;
1304
1305         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1306                 DRM_ERROR("called with no initialization\n");
1307                 return -EINVAL;
1308         }
1309
1310         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1311
1312         mutex_lock(&dev->struct_mutex);
1313         result = i915_emit_irq(dev);
1314         mutex_unlock(&dev->struct_mutex);
1315
1316         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1317                 DRM_ERROR("copy_to_user\n");
1318                 return -EFAULT;
1319         }
1320
1321         return 0;
1322 }
1323
1324 /* Doesn't need the hardware lock.
1325  */
1326 int i915_irq_wait(struct drm_device *dev, void *data,
1327                          struct drm_file *file_priv)
1328 {
1329         drm_i915_private_t *dev_priv = dev->dev_private;
1330         drm_i915_irq_wait_t *irqwait = data;
1331
1332         if (!dev_priv) {
1333                 DRM_ERROR("called with no initialization\n");
1334                 return -EINVAL;
1335         }
1336
1337         return i915_wait_irq(dev, irqwait->irq_seq);
1338 }
1339
1340 /* Called from drm generic code, passed 'crtc' which
1341  * we use as a pipe index
1342  */
1343 int i915_enable_vblank(struct drm_device *dev, int pipe)
1344 {
1345         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1346         unsigned long irqflags;
1347
1348         if (!i915_pipe_enabled(dev, pipe))
1349                 return -EINVAL;
1350
1351         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1352         if (HAS_PCH_SPLIT(dev))
1353                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1354                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1355         else if (INTEL_INFO(dev)->gen >= 4)
1356                 i915_enable_pipestat(dev_priv, pipe,
1357                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1358         else
1359                 i915_enable_pipestat(dev_priv, pipe,
1360                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1361         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1362         return 0;
1363 }
1364
1365 /* Called from drm generic code, passed 'crtc' which
1366  * we use as a pipe index
1367  */
1368 void i915_disable_vblank(struct drm_device *dev, int pipe)
1369 {
1370         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1371         unsigned long irqflags;
1372
1373         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1374         if (HAS_PCH_SPLIT(dev))
1375                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1376                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1377         else
1378                 i915_disable_pipestat(dev_priv, pipe,
1379                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1380                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1381         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1382 }
1383
1384 void i915_enable_interrupt (struct drm_device *dev)
1385 {
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387
1388         if (!HAS_PCH_SPLIT(dev))
1389                 intel_opregion_enable_asle(dev);
1390         dev_priv->irq_enabled = 1;
1391 }
1392
1393
1394 /* Set the vblank monitor pipe
1395  */
1396 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1397                          struct drm_file *file_priv)
1398 {
1399         drm_i915_private_t *dev_priv = dev->dev_private;
1400
1401         if (!dev_priv) {
1402                 DRM_ERROR("called with no initialization\n");
1403                 return -EINVAL;
1404         }
1405
1406         return 0;
1407 }
1408
1409 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1410                          struct drm_file *file_priv)
1411 {
1412         drm_i915_private_t *dev_priv = dev->dev_private;
1413         drm_i915_vblank_pipe_t *pipe = data;
1414
1415         if (!dev_priv) {
1416                 DRM_ERROR("called with no initialization\n");
1417                 return -EINVAL;
1418         }
1419
1420         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1421
1422         return 0;
1423 }
1424
1425 /**
1426  * Schedule buffer swap at given vertical blank.
1427  */
1428 int i915_vblank_swap(struct drm_device *dev, void *data,
1429                      struct drm_file *file_priv)
1430 {
1431         /* The delayed swap mechanism was fundamentally racy, and has been
1432          * removed.  The model was that the client requested a delayed flip/swap
1433          * from the kernel, then waited for vblank before continuing to perform
1434          * rendering.  The problem was that the kernel might wake the client
1435          * up before it dispatched the vblank swap (since the lock has to be
1436          * held while touching the ringbuffer), in which case the client would
1437          * clear and start the next frame before the swap occurred, and
1438          * flicker would occur in addition to likely missing the vblank.
1439          *
1440          * In the absence of this ioctl, userland falls back to a correct path
1441          * of waiting for a vblank, then dispatching the swap on its own.
1442          * Context switching to userland and back is plenty fast enough for
1443          * meeting the requirements of vblank swapping.
1444          */
1445         return -EINVAL;
1446 }
1447
1448 static u32
1449 ring_last_seqno(struct intel_ring_buffer *ring)
1450 {
1451         return list_entry(ring->request_list.prev,
1452                           struct drm_i915_gem_request, list)->seqno;
1453 }
1454
1455 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1456 {
1457         if (list_empty(&ring->request_list) ||
1458             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1459                 /* Issue a wake-up to catch stuck h/w. */
1460                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1461                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1462                                   ring->name,
1463                                   ring->waiting_seqno,
1464                                   ring->get_seqno(ring));
1465                         wake_up_all(&ring->irq_queue);
1466                         *err = true;
1467                 }
1468                 return true;
1469         }
1470         return false;
1471 }
1472
1473 static bool kick_ring(struct intel_ring_buffer *ring)
1474 {
1475         struct drm_device *dev = ring->dev;
1476         struct drm_i915_private *dev_priv = dev->dev_private;
1477         u32 tmp = I915_READ_CTL(ring);
1478         if (tmp & RING_WAIT) {
1479                 DRM_ERROR("Kicking stuck wait on %s\n",
1480                           ring->name);
1481                 I915_WRITE_CTL(ring, tmp);
1482                 return true;
1483         }
1484         if (IS_GEN6(dev) &&
1485             (tmp & RING_WAIT_SEMAPHORE)) {
1486                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1487                           ring->name);
1488                 I915_WRITE_CTL(ring, tmp);
1489                 return true;
1490         }
1491         return false;
1492 }
1493
1494 /**
1495  * This is called when the chip hasn't reported back with completed
1496  * batchbuffers in a long time. The first time this is called we simply record
1497  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1498  * again, we assume the chip is wedged and try to fix it.
1499  */
1500 void i915_hangcheck_elapsed(unsigned long data)
1501 {
1502         struct drm_device *dev = (struct drm_device *)data;
1503         drm_i915_private_t *dev_priv = dev->dev_private;
1504         uint32_t acthd, instdone, instdone1;
1505         bool err = false;
1506
1507         /* If all work is done then ACTHD clearly hasn't advanced. */
1508         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1509             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1510             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1511                 dev_priv->hangcheck_count = 0;
1512                 if (err)
1513                         goto repeat;
1514                 return;
1515         }
1516
1517         if (INTEL_INFO(dev)->gen < 4) {
1518                 acthd = I915_READ(ACTHD);
1519                 instdone = I915_READ(INSTDONE);
1520                 instdone1 = 0;
1521         } else {
1522                 acthd = I915_READ(ACTHD_I965);
1523                 instdone = I915_READ(INSTDONE_I965);
1524                 instdone1 = I915_READ(INSTDONE1);
1525         }
1526
1527         if (dev_priv->last_acthd == acthd &&
1528             dev_priv->last_instdone == instdone &&
1529             dev_priv->last_instdone1 == instdone1) {
1530                 if (dev_priv->hangcheck_count++ > 1) {
1531                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1532
1533                         if (!IS_GEN2(dev)) {
1534                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1535                                  * If so we can simply poke the RB_WAIT bit
1536                                  * and break the hang. This should work on
1537                                  * all but the second generation chipsets.
1538                                  */
1539
1540                                 if (kick_ring(&dev_priv->ring[RCS]))
1541                                         goto repeat;
1542
1543                                 if (HAS_BSD(dev) &&
1544                                     kick_ring(&dev_priv->ring[VCS]))
1545                                         goto repeat;
1546
1547                                 if (HAS_BLT(dev) &&
1548                                     kick_ring(&dev_priv->ring[BCS]))
1549                                         goto repeat;
1550                         }
1551
1552                         i915_handle_error(dev, true);
1553                         return;
1554                 }
1555         } else {
1556                 dev_priv->hangcheck_count = 0;
1557
1558                 dev_priv->last_acthd = acthd;
1559                 dev_priv->last_instdone = instdone;
1560                 dev_priv->last_instdone1 = instdone1;
1561         }
1562
1563 repeat:
1564         /* Reset timer case chip hangs without another request being added */
1565         mod_timer(&dev_priv->hangcheck_timer,
1566                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1567 }
1568
1569 /* drm_dma.h hooks
1570 */
1571 static void ironlake_irq_preinstall(struct drm_device *dev)
1572 {
1573         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1574
1575         I915_WRITE(HWSTAM, 0xeffe);
1576
1577         /* XXX hotplug from PCH */
1578
1579         I915_WRITE(DEIMR, 0xffffffff);
1580         I915_WRITE(DEIER, 0x0);
1581         POSTING_READ(DEIER);
1582
1583         /* and GT */
1584         I915_WRITE(GTIMR, 0xffffffff);
1585         I915_WRITE(GTIER, 0x0);
1586         POSTING_READ(GTIER);
1587
1588         /* south display irq */
1589         I915_WRITE(SDEIMR, 0xffffffff);
1590         I915_WRITE(SDEIER, 0x0);
1591         POSTING_READ(SDEIER);
1592 }
1593
1594 static int ironlake_irq_postinstall(struct drm_device *dev)
1595 {
1596         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1597         /* enable kind of interrupts always enabled */
1598         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1599                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1600         u32 render_irqs;
1601         u32 hotplug_mask;
1602
1603         dev_priv->irq_mask = ~display_mask;
1604
1605         /* should always can generate irq */
1606         I915_WRITE(DEIIR, I915_READ(DEIIR));
1607         I915_WRITE(DEIMR, dev_priv->irq_mask);
1608         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1609         POSTING_READ(DEIER);
1610
1611         dev_priv->gt_irq_mask = ~0;
1612
1613         I915_WRITE(GTIIR, I915_READ(GTIIR));
1614         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1615
1616         if (IS_GEN6(dev))
1617                 render_irqs =
1618                         GT_USER_INTERRUPT |
1619                         GT_GEN6_BSD_USER_INTERRUPT |
1620                         GT_BLT_USER_INTERRUPT;
1621         else
1622                 render_irqs =
1623                         GT_USER_INTERRUPT |
1624                         GT_PIPE_NOTIFY |
1625                         GT_BSD_USER_INTERRUPT;
1626         I915_WRITE(GTIER, render_irqs);
1627         POSTING_READ(GTIER);
1628
1629         if (HAS_PCH_CPT(dev)) {
1630                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1631                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1632         } else {
1633                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1634                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1635                 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
1636                 I915_WRITE(FDI_RXA_IMR, 0);
1637                 I915_WRITE(FDI_RXB_IMR, 0);
1638         }
1639
1640         dev_priv->pch_irq_mask = ~hotplug_mask;
1641
1642         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1643         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1644         I915_WRITE(SDEIER, hotplug_mask);
1645         POSTING_READ(SDEIER);
1646
1647         if (IS_IRONLAKE_M(dev)) {
1648                 /* Clear & enable PCU event interrupts */
1649                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1650                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1651                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1652         }
1653
1654         return 0;
1655 }
1656
1657 void i915_driver_irq_preinstall(struct drm_device * dev)
1658 {
1659         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1660
1661         atomic_set(&dev_priv->irq_received, 0);
1662
1663         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1664         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1665
1666         if (HAS_PCH_SPLIT(dev)) {
1667                 ironlake_irq_preinstall(dev);
1668                 return;
1669         }
1670
1671         if (I915_HAS_HOTPLUG(dev)) {
1672                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1673                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1674         }
1675
1676         I915_WRITE(HWSTAM, 0xeffe);
1677         I915_WRITE(PIPEASTAT, 0);
1678         I915_WRITE(PIPEBSTAT, 0);
1679         I915_WRITE(IMR, 0xffffffff);
1680         I915_WRITE(IER, 0x0);
1681         POSTING_READ(IER);
1682 }
1683
1684 /*
1685  * Must be called after intel_modeset_init or hotplug interrupts won't be
1686  * enabled correctly.
1687  */
1688 int i915_driver_irq_postinstall(struct drm_device *dev)
1689 {
1690         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1691         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1692         u32 error_mask;
1693
1694         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1695         if (HAS_BSD(dev))
1696                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1697         if (HAS_BLT(dev))
1698                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1699
1700         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1701
1702         if (HAS_PCH_SPLIT(dev))
1703                 return ironlake_irq_postinstall(dev);
1704
1705         /* Unmask the interrupts that we always want on. */
1706         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1707
1708         dev_priv->pipestat[0] = 0;
1709         dev_priv->pipestat[1] = 0;
1710
1711         if (I915_HAS_HOTPLUG(dev)) {
1712                 /* Enable in IER... */
1713                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1714                 /* and unmask in IMR */
1715                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1716         }
1717
1718         /*
1719          * Enable some error detection, note the instruction error mask
1720          * bit is reserved, so we leave it masked.
1721          */
1722         if (IS_G4X(dev)) {
1723                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1724                                GM45_ERROR_MEM_PRIV |
1725                                GM45_ERROR_CP_PRIV |
1726                                I915_ERROR_MEMORY_REFRESH);
1727         } else {
1728                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1729                                I915_ERROR_MEMORY_REFRESH);
1730         }
1731         I915_WRITE(EMR, error_mask);
1732
1733         I915_WRITE(IMR, dev_priv->irq_mask);
1734         I915_WRITE(IER, enable_mask);
1735         POSTING_READ(IER);
1736
1737         if (I915_HAS_HOTPLUG(dev)) {
1738                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1739
1740                 /* Note HDMI and DP share bits */
1741                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1742                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1743                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1744                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1745                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1746                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1747                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1748                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1749                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1750                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1751                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1752                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1753
1754                         /* Programming the CRT detection parameters tends
1755                            to generate a spurious hotplug event about three
1756                            seconds later.  So just do it once.
1757                         */
1758                         if (IS_G4X(dev))
1759                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1760                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1761                 }
1762
1763                 /* Ignore TV since it's buggy */
1764
1765                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1766         }
1767
1768         intel_opregion_enable_asle(dev);
1769
1770         return 0;
1771 }
1772
1773 static void ironlake_irq_uninstall(struct drm_device *dev)
1774 {
1775         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1776         I915_WRITE(HWSTAM, 0xffffffff);
1777
1778         I915_WRITE(DEIMR, 0xffffffff);
1779         I915_WRITE(DEIER, 0x0);
1780         I915_WRITE(DEIIR, I915_READ(DEIIR));
1781
1782         I915_WRITE(GTIMR, 0xffffffff);
1783         I915_WRITE(GTIER, 0x0);
1784         I915_WRITE(GTIIR, I915_READ(GTIIR));
1785 }
1786
1787 void i915_driver_irq_uninstall(struct drm_device * dev)
1788 {
1789         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1790
1791         if (!dev_priv)
1792                 return;
1793
1794         dev_priv->vblank_pipe = 0;
1795
1796         if (HAS_PCH_SPLIT(dev)) {
1797                 ironlake_irq_uninstall(dev);
1798                 return;
1799         }
1800
1801         if (I915_HAS_HOTPLUG(dev)) {
1802                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1803                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1804         }
1805
1806         I915_WRITE(HWSTAM, 0xffffffff);
1807         I915_WRITE(PIPEASTAT, 0);
1808         I915_WRITE(PIPEBSTAT, 0);
1809         I915_WRITE(IMR, 0xffffffff);
1810         I915_WRITE(IER, 0x0);
1811
1812         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1813         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1814         I915_WRITE(IIR, I915_READ(IIR));
1815 }