drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119         unsigned long irqflags;
 120
 121         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194                                  "pipe %c\n", pipe_name(pipe));
 195                 return 0;
 196         }
 197
 198         return I915_READ(reg);
 199 }
 200
 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202                              int *vpos, int *hpos)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205         u32 vbl = 0, position = 0;
 206         int vbl_start, vbl_end, htotal, vtotal;
 207         bool in_vbl = true;
 208         int ret = 0;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212                                  "pipe %c\n", pipe_name(pipe));
 213                 return 0;
 214         }
 215
 216         /* Get vtotal. */
 217         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 218
 219         if (INTEL_INFO(dev)->gen >= 4) {
 220                 /* No obvious pixelcount register. Only query vertical
 221                  * scanout position from Display scan line register.
 222                  */
 223                 position = I915_READ(PIPEDSL(pipe));
 224
 225                 /* Decode into vertical scanout position. Don't have
 226                  * horizontal scanout position.
 227                  */
 228                 *vpos = position & 0x1fff;
 229                 *hpos = 0;
 230         } else {
 231                 /* Have access to pixelcount since start of frame.
 232                  * We can split this into vertical and horizontal
 233                  * scanout position.
 234                  */
 235                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238                 *vpos = position / htotal;
 239                 *hpos = position - (*vpos * htotal);
 240         }
 241
 242         /* Query vblank area. */
 243         vbl = I915_READ(VBLANK(pipe));
 244
 245         /* Test position against vblank region. */
 246         vbl_start = vbl & 0x1fff;
 247         vbl_end = (vbl >> 16) & 0x1fff;
 248
 249         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250                 in_vbl = false;
 251
 252         /* Inside "upper part" of vblank area? Apply corrective offset: */
 253         if (in_vbl && (*vpos >= vbl_start))
 254                 *vpos = *vpos - vtotal;
 255
 256         /* Readouts valid? */
 257         if (vbl > 0)
 258                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 259
 260         /* In vblank? */
 261         if (in_vbl)
 262                 ret |= DRM_SCANOUTPOS_INVBL;
 263
 264         return ret;
 265 }
 266
 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 268                               int *max_error,
 269                               struct timeval *vblank_time,
 270                               unsigned flags)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         struct drm_crtc *crtc;
 274
 275         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276                 DRM_ERROR("Invalid crtc %d\n", pipe);
 277                 return -EINVAL;
 278         }
 279
 280         /* Get drm_crtc to timestamp: */
 281         crtc = intel_get_crtc_for_pipe(dev, pipe);
 282         if (crtc == NULL) {
 283                 DRM_ERROR("Invalid crtc %d\n", pipe);
 284                 return -EINVAL;
 285         }
 286
 287         if (!crtc->enabled) {
 288                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289                 return -EBUSY;
 290         }
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294                                                      vblank_time, flags,
 295                                                      crtc);
 296 }
 297
 298 /*
 299  * Handle hotplug events outside the interrupt handler proper.
 300  */
 301 static void i915_hotplug_work_func(struct work_struct *work)
 302 {
 303         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304                                                     hotplug_work);
 305         struct drm_device *dev = dev_priv->dev;
 306         struct drm_mode_config *mode_config = &dev->mode_config;
 307         struct intel_encoder *encoder;
 308
 309         mutex_lock(&mode_config->mutex);
 310         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 311
 312         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 313                 if (encoder->hot_plug)
 314                         encoder->hot_plug(encoder);
 315
 316         mutex_unlock(&mode_config->mutex);
 317
 318         /* Just fire off a uevent and let userspace tell us what to do */
 319         drm_helper_hpd_irq_event(dev);
 320 }
 321
 322 static void i915_handle_rps_change(struct drm_device *dev)
 323 {
 324         drm_i915_private_t *dev_priv = dev->dev_private;
 325         u32 busy_up, busy_down, max_avg, min_avg;
 326         u8 new_delay = dev_priv->cur_delay;
 327
 328         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 329         busy_up = I915_READ(RCPREVBSYTUPAVG);
 330         busy_down = I915_READ(RCPREVBSYTDNAVG);
 331         max_avg = I915_READ(RCBMAXAVG);
 332         min_avg = I915_READ(RCBMINAVG);
 333
 334         /* Handle RCS change request from hw */
 335         if (busy_up > max_avg) {
 336                 if (dev_priv->cur_delay != dev_priv->max_delay)
 337                         new_delay = dev_priv->cur_delay - 1;
 338                 if (new_delay < dev_priv->max_delay)
 339                         new_delay = dev_priv->max_delay;
 340         } else if (busy_down < min_avg) {
 341                 if (dev_priv->cur_delay != dev_priv->min_delay)
 342                         new_delay = dev_priv->cur_delay + 1;
 343                 if (new_delay > dev_priv->min_delay)
 344                         new_delay = dev_priv->min_delay;
 345         }
 346
 347         if (ironlake_set_drps(dev, new_delay))
 348                 dev_priv->cur_delay = new_delay;
 349
 350         return;
 351 }
 352
 353 static void notify_ring(struct drm_device *dev,
 354                         struct intel_ring_buffer *ring)
 355 {
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         u32 seqno;
 358
 359         if (ring->obj == NULL)
 360                 return;
 361
 362         seqno = ring->get_seqno(ring);
 363         trace_i915_gem_request_complete(ring, seqno);
 364
 365         ring->irq_seqno = seqno;
 366         wake_up_all(&ring->irq_queue);
 367         if (i915_enable_hangcheck) {
 368                 dev_priv->hangcheck_count = 0;
 369                 mod_timer(&dev_priv->hangcheck_timer,
 370                           jiffies +
 371                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 372         }
 373 }
 374
 375 static void gen6_pm_rps_work(struct work_struct *work)
 376 {
 377         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 378                                                     rps_work);
 379         u8 new_delay = dev_priv->cur_delay;
 380         u32 pm_iir, pm_imr;
 381
 382         spin_lock_irq(&dev_priv->rps_lock);
 383         pm_iir = dev_priv->pm_iir;
 384         dev_priv->pm_iir = 0;
 385         pm_imr = I915_READ(GEN6_PMIMR);
 386         I915_WRITE(GEN6_PMIMR, 0);
 387         spin_unlock_irq(&dev_priv->rps_lock);
 388
 389         if (!pm_iir)
 390                 return;
 391
 392         mutex_lock(&dev_priv->dev->struct_mutex);
 393         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 394                 if (dev_priv->cur_delay != dev_priv->max_delay)
 395                         new_delay = dev_priv->cur_delay + 1;
 396                 if (new_delay > dev_priv->max_delay)
 397                         new_delay = dev_priv->max_delay;
 398         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 399                 gen6_gt_force_wake_get(dev_priv);
 400                 if (dev_priv->cur_delay != dev_priv->min_delay)
 401                         new_delay = dev_priv->cur_delay - 1;
 402                 if (new_delay < dev_priv->min_delay) {
 403                         new_delay = dev_priv->min_delay;
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 406                                    ((new_delay << 16) & 0x3f0000));
 407                 } else {
 408                         /* Make sure we continue to get down interrupts
 409                          * until we hit the minimum frequency */
 410                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 411                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 412                 }
 413                 gen6_gt_force_wake_put(dev_priv);
 414         }
 415
 416         gen6_set_rps(dev_priv->dev, new_delay);
 417         dev_priv->cur_delay = new_delay;
 418
 419         /*
 420          * rps_lock not held here because clearing is non-destructive. There is
 421          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 422          * by holding struct_mutex for the duration of the write.
 423          */
 424         mutex_unlock(&dev_priv->dev->struct_mutex);
 425 }
 426
 427 static void pch_irq_handler(struct drm_device *dev)
 428 {
 429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 430         u32 pch_iir;
 431         int pipe;
 432
 433         pch_iir = I915_READ(SDEIIR);
 434
 435         if (pch_iir & SDE_AUDIO_POWER_MASK)
 436                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 437                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 438                                  SDE_AUDIO_POWER_SHIFT);
 439
 440         if (pch_iir & SDE_GMBUS)
 441                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 442
 443         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 444                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 445
 446         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 447                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 448
 449         if (pch_iir & SDE_POISON)
 450                 DRM_ERROR("PCH poison interrupt\n");
 451
 452         if (pch_iir & SDE_FDI_MASK)
 453                 for_each_pipe(pipe)
 454                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 455                                          pipe_name(pipe),
 456                                          I915_READ(FDI_RX_IIR(pipe)));
 457
 458         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 459                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 460
 461         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 462                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 463
 464         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 465                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 466         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 467                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 468 }
 469
 470 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 471 {
 472         struct drm_device *dev = (struct drm_device *) arg;
 473         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 474         int ret = IRQ_NONE;
 475         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 476         struct drm_i915_master_private *master_priv;
 477
 478         atomic_inc(&dev_priv->irq_received);
 479
 480         /* disable master interrupt before clearing iir  */
 481         de_ier = I915_READ(DEIER);
 482         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 483         POSTING_READ(DEIER);
 484
 485         de_iir = I915_READ(DEIIR);
 486         gt_iir = I915_READ(GTIIR);
 487         pch_iir = I915_READ(SDEIIR);
 488         pm_iir = I915_READ(GEN6_PMIIR);
 489
 490         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 491                 goto done;
 492
 493         ret = IRQ_HANDLED;
 494
 495         if (dev->primary->master) {
 496                 master_priv = dev->primary->master->driver_priv;
 497                 if (master_priv->sarea_priv)
 498                         master_priv->sarea_priv->last_dispatch =
 499                                 READ_BREADCRUMB(dev_priv);
 500         }
 501
 502         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 503                 notify_ring(dev, &dev_priv->ring[RCS]);
 504         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 505                 notify_ring(dev, &dev_priv->ring[VCS]);
 506         if (gt_iir & GT_BLT_USER_INTERRUPT)
 507                 notify_ring(dev, &dev_priv->ring[BCS]);
 508
 509         if (de_iir & DE_GSE_IVB)
 510                 intel_opregion_gse_intr(dev);
 511
 512         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 513                 intel_prepare_page_flip(dev, 0);
 514                 intel_finish_page_flip_plane(dev, 0);
 515         }
 516
 517         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 518                 intel_prepare_page_flip(dev, 1);
 519                 intel_finish_page_flip_plane(dev, 1);
 520         }
 521
 522         if (de_iir & DE_PIPEA_VBLANK_IVB)
 523                 drm_handle_vblank(dev, 0);
 524
 525         if (de_iir & DE_PIPEB_VBLANK_IVB)
 526                 drm_handle_vblank(dev, 1);
 527
 528         /* check event from PCH */
 529         if (de_iir & DE_PCH_EVENT_IVB) {
 530                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 531                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 532                 pch_irq_handler(dev);
 533         }
 534
 535         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 536                 unsigned long flags;
 537                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 538                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 539                 dev_priv->pm_iir |= pm_iir;
 540                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 541                 POSTING_READ(GEN6_PMIMR);
 542                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 543                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 544         }
 545
 546         /* should clear PCH hotplug event before clear CPU irq */
 547         I915_WRITE(SDEIIR, pch_iir);
 548         I915_WRITE(GTIIR, gt_iir);
 549         I915_WRITE(DEIIR, de_iir);
 550         I915_WRITE(GEN6_PMIIR, pm_iir);
 551
 552 done:
 553         I915_WRITE(DEIER, de_ier);
 554         POSTING_READ(DEIER);
 555
 556         return ret;
 557 }
 558
 559 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 560 {
 561         struct drm_device *dev = (struct drm_device *) arg;
 562         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 563         int ret = IRQ_NONE;
 564         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 565         u32 hotplug_mask;
 566         struct drm_i915_master_private *master_priv;
 567         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 568
 569         atomic_inc(&dev_priv->irq_received);
 570
 571         if (IS_GEN6(dev))
 572                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 573
 574         /* disable master interrupt before clearing iir  */
 575         de_ier = I915_READ(DEIER);
 576         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 577         POSTING_READ(DEIER);
 578
 579         de_iir = I915_READ(DEIIR);
 580         gt_iir = I915_READ(GTIIR);
 581         pch_iir = I915_READ(SDEIIR);
 582         pm_iir = I915_READ(GEN6_PMIIR);
 583
 584         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 585             (!IS_GEN6(dev) || pm_iir == 0))
 586                 goto done;
 587
 588         if (HAS_PCH_CPT(dev))
 589                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 590         else
 591                 hotplug_mask = SDE_HOTPLUG_MASK;
 592
 593         ret = IRQ_HANDLED;
 594
 595         if (dev->primary->master) {
 596                 master_priv = dev->primary->master->driver_priv;
 597                 if (master_priv->sarea_priv)
 598                         master_priv->sarea_priv->last_dispatch =
 599                                 READ_BREADCRUMB(dev_priv);
 600         }
 601
 602         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 603                 notify_ring(dev, &dev_priv->ring[RCS]);
 604         if (gt_iir & bsd_usr_interrupt)
 605                 notify_ring(dev, &dev_priv->ring[VCS]);
 606         if (gt_iir & GT_BLT_USER_INTERRUPT)
 607                 notify_ring(dev, &dev_priv->ring[BCS]);
 608
 609         if (de_iir & DE_GSE)
 610                 intel_opregion_gse_intr(dev);
 611
 612         if (de_iir & DE_PLANEA_FLIP_DONE) {
 613                 intel_prepare_page_flip(dev, 0);
 614                 intel_finish_page_flip_plane(dev, 0);
 615         }
 616
 617         if (de_iir & DE_PLANEB_FLIP_DONE) {
 618                 intel_prepare_page_flip(dev, 1);
 619                 intel_finish_page_flip_plane(dev, 1);
 620         }
 621
 622         if (de_iir & DE_PIPEA_VBLANK)
 623                 drm_handle_vblank(dev, 0);
 624
 625         if (de_iir & DE_PIPEB_VBLANK)
 626                 drm_handle_vblank(dev, 1);
 627
 628         /* check event from PCH */
 629         if (de_iir & DE_PCH_EVENT) {
 630                 if (pch_iir & hotplug_mask)
 631                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 632                 pch_irq_handler(dev);
 633         }
 634
 635         if (de_iir & DE_PCU_EVENT) {
 636                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 637                 i915_handle_rps_change(dev);
 638         }
 639
 640         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 641                 /*
 642                  * IIR bits should never already be set because IMR should
 643                  * prevent an interrupt from being shown in IIR. The warning
 644                  * displays a case where we've unsafely cleared
 645                  * dev_priv->pm_iir. Although missing an interrupt of the same
 646                  * type is not a problem, it displays a problem in the logic.
 647                  *
 648                  * The mask bit in IMR is cleared by rps_work.
 649                  */
 650                 unsigned long flags;
 651                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 652                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 653                 dev_priv->pm_iir |= pm_iir;
 654                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 655                 POSTING_READ(GEN6_PMIMR);
 656                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 657                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 658         }
 659
 660         /* should clear PCH hotplug event before clear CPU irq */
 661         I915_WRITE(SDEIIR, pch_iir);
 662         I915_WRITE(GTIIR, gt_iir);
 663         I915_WRITE(DEIIR, de_iir);
 664         I915_WRITE(GEN6_PMIIR, pm_iir);
 665
 666 done:
 667         I915_WRITE(DEIER, de_ier);
 668         POSTING_READ(DEIER);
 669
 670         return ret;
 671 }
 672
 673 /**
 674  * i915_error_work_func - do process context error handling work
 675  * @work: work struct
 676  *
 677  * Fire an error uevent so userspace can see that a hang or error
 678  * was detected.
 679  */
 680 static void i915_error_work_func(struct work_struct *work)
 681 {
 682         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 683                                                     error_work);
 684         struct drm_device *dev = dev_priv->dev;
 685         char *error_event[] = { "ERROR=1", NULL };
 686         char *reset_event[] = { "RESET=1", NULL };
 687         char *reset_done_event[] = { "ERROR=0", NULL };
 688
 689         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 690
 691         if (atomic_read(&dev_priv->mm.wedged)) {
 692                 DRM_DEBUG_DRIVER("resetting chip\n");
 693                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 694                 if (!i915_reset(dev, GRDOM_RENDER)) {
 695                         atomic_set(&dev_priv->mm.wedged, 0);
 696                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 697                 }
 698                 complete_all(&dev_priv->error_completion);
 699         }
 700 }
 701
 702 #ifdef CONFIG_DEBUG_FS
 703 static struct drm_i915_error_object *
 704 i915_error_object_create(struct drm_i915_private *dev_priv,
 705                          struct drm_i915_gem_object *src)
 706 {
 707         struct drm_i915_error_object *dst;
 708         int page, page_count;
 709         u32 reloc_offset;
 710
 711         if (src == NULL || src->pages == NULL)
 712                 return NULL;
 713
 714         page_count = src->base.size / PAGE_SIZE;
 715
 716         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 717         if (dst == NULL)
 718                 return NULL;
 719
 720         reloc_offset = src->gtt_offset;
 721         for (page = 0; page < page_count; page++) {
 722                 unsigned long flags;
 723                 void __iomem *s;
 724                 void *d;
 725
 726                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 727                 if (d == NULL)
 728                         goto unwind;
 729
 730                 local_irq_save(flags);
 731                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 732                                              reloc_offset);
 733                 memcpy_fromio(d, s, PAGE_SIZE);
 734                 io_mapping_unmap_atomic(s);
 735                 local_irq_restore(flags);
 736
 737                 dst->pages[page] = d;
 738
 739                 reloc_offset += PAGE_SIZE;
 740         }
 741         dst->page_count = page_count;
 742         dst->gtt_offset = src->gtt_offset;
 743
 744         return dst;
 745
 746 unwind:
 747         while (page--)
 748                 kfree(dst->pages[page]);
 749         kfree(dst);
 750         return NULL;
 751 }
 752
 753 static void
 754 i915_error_object_free(struct drm_i915_error_object *obj)
 755 {
 756         int page;
 757
 758         if (obj == NULL)
 759                 return;
 760
 761         for (page = 0; page < obj->page_count; page++)
 762                 kfree(obj->pages[page]);
 763
 764         kfree(obj);
 765 }
 766
 767 static void
 768 i915_error_state_free(struct drm_device *dev,
 769                       struct drm_i915_error_state *error)
 770 {
 771         int i;
 772
 773         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 774                 i915_error_object_free(error->batchbuffer[i]);
 775
 776         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 777                 i915_error_object_free(error->ringbuffer[i]);
 778
 779         kfree(error->active_bo);
 780         kfree(error->overlay);
 781         kfree(error);
 782 }
 783
 784 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 785                            int count,
 786                            struct list_head *head)
 787 {
 788         struct drm_i915_gem_object *obj;
 789         int i = 0;
 790
 791         list_for_each_entry(obj, head, mm_list) {
 792                 err->size = obj->base.size;
 793                 err->name = obj->base.name;
 794                 err->seqno = obj->last_rendering_seqno;
 795                 err->gtt_offset = obj->gtt_offset;
 796                 err->read_domains = obj->base.read_domains;
 797                 err->write_domain = obj->base.write_domain;
 798                 err->fence_reg = obj->fence_reg;
 799                 err->pinned = 0;
 800                 if (obj->pin_count > 0)
 801                         err->pinned = 1;
 802                 if (obj->user_pin_count > 0)
 803                         err->pinned = -1;
 804                 err->tiling = obj->tiling_mode;
 805                 err->dirty = obj->dirty;
 806                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 807                 err->ring = obj->ring ? obj->ring->id : 0;
 808                 err->cache_level = obj->cache_level;
 809
 810                 if (++i == count)
 811                         break;
 812
 813                 err++;
 814         }
 815
 816         return i;
 817 }
 818
 819 static void i915_gem_record_fences(struct drm_device *dev,
 820                                    struct drm_i915_error_state *error)
 821 {
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         int i;
 824
 825         /* Fences */
 826         switch (INTEL_INFO(dev)->gen) {
 827         case 6:
 828                 for (i = 0; i < 16; i++)
 829                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 830                 break;
 831         case 5:
 832         case 4:
 833                 for (i = 0; i < 16; i++)
 834                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 835                 break;
 836         case 3:
 837                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 838                         for (i = 0; i < 8; i++)
 839                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 840         case 2:
 841                 for (i = 0; i < 8; i++)
 842                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 843                 break;
 844
 845         }
 846 }
 847
 848 static struct drm_i915_error_object *
 849 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 850                              struct intel_ring_buffer *ring)
 851 {
 852         struct drm_i915_gem_object *obj;
 853         u32 seqno;
 854
 855         if (!ring->get_seqno)
 856                 return NULL;
 857
 858         seqno = ring->get_seqno(ring);
 859         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 860                 if (obj->ring != ring)
 861                         continue;
 862
 863                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 864                         continue;
 865
 866                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 867                         continue;
 868
 869                 /* We need to copy these to an anonymous buffer as the simplest
 870                  * method to avoid being overwritten by userspace.
 871                  */
 872                 return i915_error_object_create(dev_priv, obj);
 873         }
 874
 875         return NULL;
 876 }
 877
 878 /**
 879  * i915_capture_error_state - capture an error record for later analysis
 880  * @dev: drm device
 881  *
 882  * Should be called when an error is detected (either a hang or an error
 883  * interrupt) to capture error state from the time of the error.  Fills
 884  * out a structure which becomes available in debugfs for user level tools
 885  * to pick up.
 886  */
 887 static void i915_capture_error_state(struct drm_device *dev)
 888 {
 889         struct drm_i915_private *dev_priv = dev->dev_private;
 890         struct drm_i915_gem_object *obj;
 891         struct drm_i915_error_state *error;
 892         unsigned long flags;
 893         int i, pipe;
 894
 895         spin_lock_irqsave(&dev_priv->error_lock, flags);
 896         error = dev_priv->first_error;
 897         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 898         if (error)
 899                 return;
 900
 901         /* Account for pipe specific data like PIPE*STAT */
 902         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 903         if (!error) {
 904                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 905                 return;
 906         }
 907
 908         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 909                  dev->primary->index);
 910
 911         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
 912         error->eir = I915_READ(EIR);
 913         error->pgtbl_er = I915_READ(PGTBL_ER);
 914         for_each_pipe(pipe)
 915                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 916         error->instpm = I915_READ(INSTPM);
 917         error->error = 0;
 918         if (INTEL_INFO(dev)->gen >= 6) {
 919                 error->error = I915_READ(ERROR_GEN6);
 920
 921                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 922                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 923                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 924                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 925                 error->bcs_seqno = 0;
 926                 if (dev_priv->ring[BCS].get_seqno)
 927                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
 928
 929                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 930                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 931                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 932                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 933                 error->vcs_seqno = 0;
 934                 if (dev_priv->ring[VCS].get_seqno)
 935                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
 936         }
 937         if (INTEL_INFO(dev)->gen >= 4) {
 938                 error->ipeir = I915_READ(IPEIR_I965);
 939                 error->ipehr = I915_READ(IPEHR_I965);
 940                 error->instdone = I915_READ(INSTDONE_I965);
 941                 error->instps = I915_READ(INSTPS);
 942                 error->instdone1 = I915_READ(INSTDONE1);
 943                 error->acthd = I915_READ(ACTHD_I965);
 944                 error->bbaddr = I915_READ64(BB_ADDR);
 945         } else {
 946                 error->ipeir = I915_READ(IPEIR);
 947                 error->ipehr = I915_READ(IPEHR);
 948                 error->instdone = I915_READ(INSTDONE);
 949                 error->acthd = I915_READ(ACTHD);
 950                 error->bbaddr = 0;
 951         }
 952         i915_gem_record_fences(dev, error);
 953
 954         /* Record the active batch and ring buffers */
 955         for (i = 0; i < I915_NUM_RINGS; i++) {
 956                 error->batchbuffer[i] =
 957                         i915_error_first_batchbuffer(dev_priv,
 958                                                      &dev_priv->ring[i]);
 959
 960                 error->ringbuffer[i] =
 961                         i915_error_object_create(dev_priv,
 962                                                  dev_priv->ring[i].obj);
 963         }
 964
 965         /* Record buffers on the active and pinned lists. */
 966         error->active_bo = NULL;
 967         error->pinned_bo = NULL;
 968
 969         i = 0;
 970         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 971                 i++;
 972         error->active_bo_count = i;
 973         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 974                 i++;
 975         error->pinned_bo_count = i - error->active_bo_count;
 976
 977         error->active_bo = NULL;
 978         error->pinned_bo = NULL;
 979         if (i) {
 980                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 981                                            GFP_ATOMIC);
 982                 if (error->active_bo)
 983                         error->pinned_bo =
 984                                 error->active_bo + error->active_bo_count;
 985         }
 986
 987         if (error->active_bo)
 988                 error->active_bo_count =
 989                         capture_bo_list(error->active_bo,
 990                                         error->active_bo_count,
 991                                         &dev_priv->mm.active_list);
 992
 993         if (error->pinned_bo)
 994                 error->pinned_bo_count =
 995                         capture_bo_list(error->pinned_bo,
 996                                         error->pinned_bo_count,
 997                                         &dev_priv->mm.pinned_list);
 998
 999         do_gettimeofday(&error->time);
1000
1001         error->overlay = intel_overlay_capture_error_state(dev);
1002         error->display = intel_display_capture_error_state(dev);
1003
1004         spin_lock_irqsave(&dev_priv->error_lock, flags);
1005         if (dev_priv->first_error == NULL) {
1006                 dev_priv->first_error = error;
1007                 error = NULL;
1008         }
1009         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1010
1011         if (error)
1012                 i915_error_state_free(dev, error);
1013 }
1014
1015 void i915_destroy_error_state(struct drm_device *dev)
1016 {
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         struct drm_i915_error_state *error;
1019
1020         spin_lock(&dev_priv->error_lock);
1021         error = dev_priv->first_error;
1022         dev_priv->first_error = NULL;
1023         spin_unlock(&dev_priv->error_lock);
1024
1025         if (error)
1026                 i915_error_state_free(dev, error);
1027 }
1028 #else
1029 #define i915_capture_error_state(x)
1030 #endif
1031
1032 static void i915_report_and_clear_eir(struct drm_device *dev)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         u32 eir = I915_READ(EIR);
1036         int pipe;
1037
1038         if (!eir)
1039                 return;
1040
1041         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1042                eir);
1043
1044         if (IS_G4X(dev)) {
1045                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1046                         u32 ipeir = I915_READ(IPEIR_I965);
1047
1048                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1049                                I915_READ(IPEIR_I965));
1050                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1051                                I915_READ(IPEHR_I965));
1052                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1053                                I915_READ(INSTDONE_I965));
1054                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1055                                I915_READ(INSTPS));
1056                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1057                                I915_READ(INSTDONE1));
1058                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1059                                I915_READ(ACTHD_I965));
1060                         I915_WRITE(IPEIR_I965, ipeir);
1061                         POSTING_READ(IPEIR_I965);
1062                 }
1063                 if (eir & GM45_ERROR_PAGE_TABLE) {
1064                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1065                         printk(KERN_ERR "page table error\n");
1066                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1067                                pgtbl_err);
1068                         I915_WRITE(PGTBL_ER, pgtbl_err);
1069                         POSTING_READ(PGTBL_ER);
1070                 }
1071         }
1072
1073         if (!IS_GEN2(dev)) {
1074                 if (eir & I915_ERROR_PAGE_TABLE) {
1075                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1076                         printk(KERN_ERR "page table error\n");
1077                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1078                                pgtbl_err);
1079                         I915_WRITE(PGTBL_ER, pgtbl_err);
1080                         POSTING_READ(PGTBL_ER);
1081                 }
1082         }
1083
1084         if (eir & I915_ERROR_MEMORY_REFRESH) {
1085                 printk(KERN_ERR "memory refresh error:\n");
1086                 for_each_pipe(pipe)
1087                         printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1088                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1089                 /* pipestat has already been acked */
1090         }
1091         if (eir & I915_ERROR_INSTRUCTION) {
1092                 printk(KERN_ERR "instruction error\n");
1093                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
1094                        I915_READ(INSTPM));
1095                 if (INTEL_INFO(dev)->gen < 4) {
1096                         u32 ipeir = I915_READ(IPEIR);
1097
1098                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1099                                I915_READ(IPEIR));
1100                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1101                                I915_READ(IPEHR));
1102                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1103                                I915_READ(INSTDONE));
1104                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1105                                I915_READ(ACTHD));
1106                         I915_WRITE(IPEIR, ipeir);
1107                         POSTING_READ(IPEIR);
1108                 } else {
1109                         u32 ipeir = I915_READ(IPEIR_I965);
1110
1111                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1112                                I915_READ(IPEIR_I965));
1113                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1114                                I915_READ(IPEHR_I965));
1115                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1116                                I915_READ(INSTDONE_I965));
1117                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1118                                I915_READ(INSTPS));
1119                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1120                                I915_READ(INSTDONE1));
1121                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1122                                I915_READ(ACTHD_I965));
1123                         I915_WRITE(IPEIR_I965, ipeir);
1124                         POSTING_READ(IPEIR_I965);
1125                 }
1126         }
1127
1128         I915_WRITE(EIR, eir);
1129         POSTING_READ(EIR);
1130         eir = I915_READ(EIR);
1131         if (eir) {
1132                 /*
1133                  * some errors might have become stuck,
1134                  * mask them.
1135                  */
1136                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1137                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1138                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1139         }
1140 }
1141
1142 /**
1143  * i915_handle_error - handle an error interrupt
1144  * @dev: drm device
1145  *
1146  * Do some basic checking of regsiter state at error interrupt time and
1147  * dump it to the syslog.  Also call i915_capture_error_state() to make
1148  * sure we get a record and make it available in debugfs.  Fire a uevent
1149  * so userspace knows something bad happened (should trigger collection
1150  * of a ring dump etc.).
1151  */
1152 void i915_handle_error(struct drm_device *dev, bool wedged)
1153 {
1154         struct drm_i915_private *dev_priv = dev->dev_private;
1155
1156         i915_capture_error_state(dev);
1157         i915_report_and_clear_eir(dev);
1158
1159         if (wedged) {
1160                 INIT_COMPLETION(dev_priv->error_completion);
1161                 atomic_set(&dev_priv->mm.wedged, 1);
1162
1163                 /*
1164                  * Wakeup waiting processes so they don't hang
1165                  */
1166                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1167                 if (HAS_BSD(dev))
1168                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1169                 if (HAS_BLT(dev))
1170                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1171         }
1172
1173         queue_work(dev_priv->wq, &dev_priv->error_work);
1174 }
1175
1176 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1177 {
1178         drm_i915_private_t *dev_priv = dev->dev_private;
1179         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1181         struct drm_i915_gem_object *obj;
1182         struct intel_unpin_work *work;
1183         unsigned long flags;
1184         bool stall_detected;
1185
1186         /* Ignore early vblank irqs */
1187         if (intel_crtc == NULL)
1188                 return;
1189
1190         spin_lock_irqsave(&dev->event_lock, flags);
1191         work = intel_crtc->unpin_work;
1192
1193         if (work == NULL || work->pending || !work->enable_stall_check) {
1194                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1195                 spin_unlock_irqrestore(&dev->event_lock, flags);
1196                 return;
1197         }
1198
1199         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1200         obj = work->pending_flip_obj;
1201         if (INTEL_INFO(dev)->gen >= 4) {
1202                 int dspsurf = DSPSURF(intel_crtc->plane);
1203                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1204         } else {
1205                 int dspaddr = DSPADDR(intel_crtc->plane);
1206                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1207                                                         crtc->y * crtc->fb->pitch +
1208                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1209         }
1210
1211         spin_unlock_irqrestore(&dev->event_lock, flags);
1212
1213         if (stall_detected) {
1214                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1215                 intel_prepare_page_flip(dev, intel_crtc->plane);
1216         }
1217 }
1218
1219 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1220 {
1221         struct drm_device *dev = (struct drm_device *) arg;
1222         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1223         struct drm_i915_master_private *master_priv;
1224         u32 iir, new_iir;
1225         u32 pipe_stats[I915_MAX_PIPES];
1226         u32 vblank_status;
1227         int vblank = 0;
1228         unsigned long irqflags;
1229         int irq_received;
1230         int ret = IRQ_NONE, pipe;
1231         bool blc_event = false;
1232
1233         atomic_inc(&dev_priv->irq_received);
1234
1235         iir = I915_READ(IIR);
1236
1237         if (INTEL_INFO(dev)->gen >= 4)
1238                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1239         else
1240                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1241
1242         for (;;) {
1243                 irq_received = iir != 0;
1244
1245                 /* Can't rely on pipestat interrupt bit in iir as it might
1246                  * have been cleared after the pipestat interrupt was received.
1247                  * It doesn't set the bit in iir again, but it still produces
1248                  * interrupts (for non-MSI).
1249                  */
1250                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1251                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1252                         i915_handle_error(dev, false);
1253
1254                 for_each_pipe(pipe) {
1255                         int reg = PIPESTAT(pipe);
1256                         pipe_stats[pipe] = I915_READ(reg);
1257
1258                         /*
1259                          * Clear the PIPE*STAT regs before the IIR
1260                          */
1261                         if (pipe_stats[pipe] & 0x8000ffff) {
1262                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1263                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1264                                                          pipe_name(pipe));
1265                                 I915_WRITE(reg, pipe_stats[pipe]);
1266                                 irq_received = 1;
1267                         }
1268                 }
1269                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1270
1271                 if (!irq_received)
1272                         break;
1273
1274                 ret = IRQ_HANDLED;
1275
1276                 /* Consume port.  Then clear IIR or we'll miss events */
1277                 if ((I915_HAS_HOTPLUG(dev)) &&
1278                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1279                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1280
1281                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1282                                   hotplug_status);
1283                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1284                                 queue_work(dev_priv->wq,
1285                                            &dev_priv->hotplug_work);
1286
1287                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1288                         I915_READ(PORT_HOTPLUG_STAT);
1289                 }
1290
1291                 I915_WRITE(IIR, iir);
1292                 new_iir = I915_READ(IIR); /* Flush posted writes */
1293
1294                 if (dev->primary->master) {
1295                         master_priv = dev->primary->master->driver_priv;
1296                         if (master_priv->sarea_priv)
1297                                 master_priv->sarea_priv->last_dispatch =
1298                                         READ_BREADCRUMB(dev_priv);
1299                 }
1300
1301                 if (iir & I915_USER_INTERRUPT)
1302                         notify_ring(dev, &dev_priv->ring[RCS]);
1303                 if (iir & I915_BSD_USER_INTERRUPT)
1304                         notify_ring(dev, &dev_priv->ring[VCS]);
1305
1306                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1307                         intel_prepare_page_flip(dev, 0);
1308                         if (dev_priv->flip_pending_is_done)
1309                                 intel_finish_page_flip_plane(dev, 0);
1310                 }
1311
1312                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1313                         intel_prepare_page_flip(dev, 1);
1314                         if (dev_priv->flip_pending_is_done)
1315                                 intel_finish_page_flip_plane(dev, 1);
1316                 }
1317
1318                 for_each_pipe(pipe) {
1319                         if (pipe_stats[pipe] & vblank_status &&
1320                             drm_handle_vblank(dev, pipe)) {
1321                                 vblank++;
1322                                 if (!dev_priv->flip_pending_is_done) {
1323                                         i915_pageflip_stall_check(dev, pipe);
1324                                         intel_finish_page_flip(dev, pipe);
1325                                 }
1326                         }
1327
1328                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1329                                 blc_event = true;
1330                 }
1331
1332
1333                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1334                         intel_opregion_asle_intr(dev);
1335
1336                 /* With MSI, interrupts are only generated when iir
1337                  * transitions from zero to nonzero.  If another bit got
1338                  * set while we were handling the existing iir bits, then
1339                  * we would never get another interrupt.
1340                  *
1341                  * This is fine on non-MSI as well, as if we hit this path
1342                  * we avoid exiting the interrupt handler only to generate
1343                  * another one.
1344                  *
1345                  * Note that for MSI this could cause a stray interrupt report
1346                  * if an interrupt landed in the time between writing IIR and
1347                  * the posting read.  This should be rare enough to never
1348                  * trigger the 99% of 100,000 interrupts test for disabling
1349                  * stray interrupts.
1350                  */
1351                 iir = new_iir;
1352         }
1353
1354         return ret;
1355 }
1356
1357 static int i915_emit_irq(struct drm_device * dev)
1358 {
1359         drm_i915_private_t *dev_priv = dev->dev_private;
1360         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1361
1362         i915_kernel_lost_context(dev);
1363
1364         DRM_DEBUG_DRIVER("\n");
1365
1366         dev_priv->counter++;
1367         if (dev_priv->counter > 0x7FFFFFFFUL)
1368                 dev_priv->counter = 1;
1369         if (master_priv->sarea_priv)
1370                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1371
1372         if (BEGIN_LP_RING(4) == 0) {
1373                 OUT_RING(MI_STORE_DWORD_INDEX);
1374                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1375                 OUT_RING(dev_priv->counter);
1376                 OUT_RING(MI_USER_INTERRUPT);
1377                 ADVANCE_LP_RING();
1378         }
1379
1380         return dev_priv->counter;
1381 }
1382
1383 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1384 {
1385         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1386         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1387         int ret = 0;
1388         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1389
1390         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1391                   READ_BREADCRUMB(dev_priv));
1392
1393         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1394                 if (master_priv->sarea_priv)
1395                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1396                 return 0;
1397         }
1398
1399         if (master_priv->sarea_priv)
1400                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1401
1402         if (ring->irq_get(ring)) {
1403                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1404                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1405                 ring->irq_put(ring);
1406         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1407                 ret = -EBUSY;
1408
1409         if (ret == -EBUSY) {
1410                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1411                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1412         }
1413
1414         return ret;
1415 }
1416
1417 /* Needs the lock as it touches the ring.
1418  */
1419 int i915_irq_emit(struct drm_device *dev, void *data,
1420                          struct drm_file *file_priv)
1421 {
1422         drm_i915_private_t *dev_priv = dev->dev_private;
1423         drm_i915_irq_emit_t *emit = data;
1424         int result;
1425
1426         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1427                 DRM_ERROR("called with no initialization\n");
1428                 return -EINVAL;
1429         }
1430
1431         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1432
1433         mutex_lock(&dev->struct_mutex);
1434         result = i915_emit_irq(dev);
1435         mutex_unlock(&dev->struct_mutex);
1436
1437         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1438                 DRM_ERROR("copy_to_user\n");
1439                 return -EFAULT;
1440         }
1441
1442         return 0;
1443 }
1444
1445 /* Doesn't need the hardware lock.
1446  */
1447 int i915_irq_wait(struct drm_device *dev, void *data,
1448                          struct drm_file *file_priv)
1449 {
1450         drm_i915_private_t *dev_priv = dev->dev_private;
1451         drm_i915_irq_wait_t *irqwait = data;
1452
1453         if (!dev_priv) {
1454                 DRM_ERROR("called with no initialization\n");
1455                 return -EINVAL;
1456         }
1457
1458         return i915_wait_irq(dev, irqwait->irq_seq);
1459 }
1460
1461 /* Called from drm generic code, passed 'crtc' which
1462  * we use as a pipe index
1463  */
1464 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1465 {
1466         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1467         unsigned long irqflags;
1468
1469         if (!i915_pipe_enabled(dev, pipe))
1470                 return -EINVAL;
1471
1472         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1473         if (INTEL_INFO(dev)->gen >= 4)
1474                 i915_enable_pipestat(dev_priv, pipe,
1475                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1476         else
1477                 i915_enable_pipestat(dev_priv, pipe,
1478                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1479
1480         /* maintain vblank delivery even in deep C-states */
1481         if (dev_priv->info->gen == 3)
1482                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1483         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1484
1485         return 0;
1486 }
1487
1488 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1489 {
1490         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1491         unsigned long irqflags;
1492
1493         if (!i915_pipe_enabled(dev, pipe))
1494                 return -EINVAL;
1495
1496         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1497         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1498                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1499         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1500
1501         return 0;
1502 }
1503
1504 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1505 {
1506         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1507         unsigned long irqflags;
1508
1509         if (!i915_pipe_enabled(dev, pipe))
1510                 return -EINVAL;
1511
1512         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1513         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1514                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1515         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1516
1517         return 0;
1518 }
1519
1520 /* Called from drm generic code, passed 'crtc' which
1521  * we use as a pipe index
1522  */
1523 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1524 {
1525         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1526         unsigned long irqflags;
1527
1528         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1529         if (dev_priv->info->gen == 3)
1530                 I915_WRITE(INSTPM,
1531                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1532
1533         i915_disable_pipestat(dev_priv, pipe,
1534                               PIPE_VBLANK_INTERRUPT_ENABLE |
1535                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1536         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1537 }
1538
1539 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1540 {
1541         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1542         unsigned long irqflags;
1543
1544         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1545         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1546                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1547         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1548 }
1549
1550 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1551 {
1552         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1553         unsigned long irqflags;
1554
1555         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1556         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1557                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1558         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1559 }
1560
1561 /* Set the vblank monitor pipe
1562  */
1563 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1564                          struct drm_file *file_priv)
1565 {
1566         drm_i915_private_t *dev_priv = dev->dev_private;
1567
1568         if (!dev_priv) {
1569                 DRM_ERROR("called with no initialization\n");
1570                 return -EINVAL;
1571         }
1572
1573         return 0;
1574 }
1575
1576 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1577                          struct drm_file *file_priv)
1578 {
1579         drm_i915_private_t *dev_priv = dev->dev_private;
1580         drm_i915_vblank_pipe_t *pipe = data;
1581
1582         if (!dev_priv) {
1583                 DRM_ERROR("called with no initialization\n");
1584                 return -EINVAL;
1585         }
1586
1587         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1588
1589         return 0;
1590 }
1591
1592 /**
1593  * Schedule buffer swap at given vertical blank.
1594  */
1595 int i915_vblank_swap(struct drm_device *dev, void *data,
1596                      struct drm_file *file_priv)
1597 {
1598         /* The delayed swap mechanism was fundamentally racy, and has been
1599          * removed.  The model was that the client requested a delayed flip/swap
1600          * from the kernel, then waited for vblank before continuing to perform
1601          * rendering.  The problem was that the kernel might wake the client
1602          * up before it dispatched the vblank swap (since the lock has to be
1603          * held while touching the ringbuffer), in which case the client would
1604          * clear and start the next frame before the swap occurred, and
1605          * flicker would occur in addition to likely missing the vblank.
1606          *
1607          * In the absence of this ioctl, userland falls back to a correct path
1608          * of waiting for a vblank, then dispatching the swap on its own.
1609          * Context switching to userland and back is plenty fast enough for
1610          * meeting the requirements of vblank swapping.
1611          */
1612         return -EINVAL;
1613 }
1614
1615 static u32
1616 ring_last_seqno(struct intel_ring_buffer *ring)
1617 {
1618         return list_entry(ring->request_list.prev,
1619                           struct drm_i915_gem_request, list)->seqno;
1620 }
1621
1622 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1623 {
1624         if (list_empty(&ring->request_list) ||
1625             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1626                 /* Issue a wake-up to catch stuck h/w. */
1627                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1628                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1629                                   ring->name,
1630                                   ring->waiting_seqno,
1631                                   ring->get_seqno(ring));
1632                         wake_up_all(&ring->irq_queue);
1633                         *err = true;
1634                 }
1635                 return true;
1636         }
1637         return false;
1638 }
1639
1640 static bool kick_ring(struct intel_ring_buffer *ring)
1641 {
1642         struct drm_device *dev = ring->dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         u32 tmp = I915_READ_CTL(ring);
1645         if (tmp & RING_WAIT) {
1646                 DRM_ERROR("Kicking stuck wait on %s\n",
1647                           ring->name);
1648                 I915_WRITE_CTL(ring, tmp);
1649                 return true;
1650         }
1651         if (IS_GEN6(dev) &&
1652             (tmp & RING_WAIT_SEMAPHORE)) {
1653                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1654                           ring->name);
1655                 I915_WRITE_CTL(ring, tmp);
1656                 return true;
1657         }
1658         return false;
1659 }
1660
1661 /**
1662  * This is called when the chip hasn't reported back with completed
1663  * batchbuffers in a long time. The first time this is called we simply record
1664  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1665  * again, we assume the chip is wedged and try to fix it.
1666  */
1667 void i915_hangcheck_elapsed(unsigned long data)
1668 {
1669         struct drm_device *dev = (struct drm_device *)data;
1670         drm_i915_private_t *dev_priv = dev->dev_private;
1671         uint32_t acthd, instdone, instdone1;
1672         bool err = false;
1673
1674         if (!i915_enable_hangcheck)
1675                 return;
1676
1677         /* If all work is done then ACTHD clearly hasn't advanced. */
1678         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1679             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1680             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1681                 dev_priv->hangcheck_count = 0;
1682                 if (err)
1683                         goto repeat;
1684                 return;
1685         }
1686
1687         if (INTEL_INFO(dev)->gen < 4) {
1688                 acthd = I915_READ(ACTHD);
1689                 instdone = I915_READ(INSTDONE);
1690                 instdone1 = 0;
1691         } else {
1692                 acthd = I915_READ(ACTHD_I965);
1693                 instdone = I915_READ(INSTDONE_I965);
1694                 instdone1 = I915_READ(INSTDONE1);
1695         }
1696
1697         if (dev_priv->last_acthd == acthd &&
1698             dev_priv->last_instdone == instdone &&
1699             dev_priv->last_instdone1 == instdone1) {
1700                 if (dev_priv->hangcheck_count++ > 1) {
1701                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1702
1703                         if (!IS_GEN2(dev)) {
1704                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1705                                  * If so we can simply poke the RB_WAIT bit
1706                                  * and break the hang. This should work on
1707                                  * all but the second generation chipsets.
1708                                  */
1709
1710                                 if (kick_ring(&dev_priv->ring[RCS]))
1711                                         goto repeat;
1712
1713                                 if (HAS_BSD(dev) &&
1714                                     kick_ring(&dev_priv->ring[VCS]))
1715                                         goto repeat;
1716
1717                                 if (HAS_BLT(dev) &&
1718                                     kick_ring(&dev_priv->ring[BCS]))
1719                                         goto repeat;
1720                         }
1721
1722                         i915_handle_error(dev, true);
1723                         return;
1724                 }
1725         } else {
1726                 dev_priv->hangcheck_count = 0;
1727
1728                 dev_priv->last_acthd = acthd;
1729                 dev_priv->last_instdone = instdone;
1730                 dev_priv->last_instdone1 = instdone1;
1731         }
1732
1733 repeat:
1734         /* Reset timer case chip hangs without another request being added */
1735         mod_timer(&dev_priv->hangcheck_timer,
1736                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1737 }
1738
1739 /* drm_dma.h hooks
1740 */
1741 static void ironlake_irq_preinstall(struct drm_device *dev)
1742 {
1743         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1744
1745         atomic_set(&dev_priv->irq_received, 0);
1746
1747         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1748         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1749         if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1750                 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1751
1752         I915_WRITE(HWSTAM, 0xeffe);
1753         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1754                 /* Workaround stalls observed on Sandy Bridge GPUs by
1755                  * making the blitter command streamer generate a
1756                  * write to the Hardware Status Page for
1757                  * MI_USER_INTERRUPT.  This appears to serialize the
1758                  * previous seqno write out before the interrupt
1759                  * happens.
1760                  */
1761                 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1762                 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1763         }
1764
1765         /* XXX hotplug from PCH */
1766
1767         I915_WRITE(DEIMR, 0xffffffff);
1768         I915_WRITE(DEIER, 0x0);
1769         POSTING_READ(DEIER);
1770
1771         /* and GT */
1772         I915_WRITE(GTIMR, 0xffffffff);
1773         I915_WRITE(GTIER, 0x0);
1774         POSTING_READ(GTIER);
1775
1776         /* south display irq */
1777         I915_WRITE(SDEIMR, 0xffffffff);
1778         I915_WRITE(SDEIER, 0x0);
1779         POSTING_READ(SDEIER);
1780 }
1781
1782 /*
1783  * Enable digital hotplug on the PCH, and configure the DP short pulse
1784  * duration to 2ms (which is the minimum in the Display Port spec)
1785  *
1786  * This register is the same on all known PCH chips.
1787  */
1788
1789 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1790 {
1791         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1792         u32     hotplug;
1793
1794         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1795         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1796         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1797         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1798         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1799         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1800 }
1801
1802 static int ironlake_irq_postinstall(struct drm_device *dev)
1803 {
1804         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1805         /* enable kind of interrupts always enabled */
1806         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1807                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1808         u32 render_irqs;
1809         u32 hotplug_mask;
1810
1811         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1812         if (HAS_BSD(dev))
1813                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1814         if (HAS_BLT(dev))
1815                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1816
1817         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1818         dev_priv->irq_mask = ~display_mask;
1819
1820         /* should always can generate irq */
1821         I915_WRITE(DEIIR, I915_READ(DEIIR));
1822         I915_WRITE(DEIMR, dev_priv->irq_mask);
1823         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1824         POSTING_READ(DEIER);
1825
1826         dev_priv->gt_irq_mask = ~0;
1827
1828         I915_WRITE(GTIIR, I915_READ(GTIIR));
1829         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1830
1831         if (IS_GEN6(dev))
1832                 render_irqs =
1833                         GT_USER_INTERRUPT |
1834                         GT_GEN6_BSD_USER_INTERRUPT |
1835                         GT_BLT_USER_INTERRUPT;
1836         else
1837                 render_irqs =
1838                         GT_USER_INTERRUPT |
1839                         GT_PIPE_NOTIFY |
1840                         GT_BSD_USER_INTERRUPT;
1841         I915_WRITE(GTIER, render_irqs);
1842         POSTING_READ(GTIER);
1843
1844         if (HAS_PCH_CPT(dev)) {
1845                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1846                                 SDE_PORTB_HOTPLUG_CPT |
1847                                 SDE_PORTC_HOTPLUG_CPT |
1848                                 SDE_PORTD_HOTPLUG_CPT);
1849         } else {
1850                 hotplug_mask = (SDE_CRT_HOTPLUG |
1851                                 SDE_PORTB_HOTPLUG |
1852                                 SDE_PORTC_HOTPLUG |
1853                                 SDE_PORTD_HOTPLUG |
1854                                 SDE_AUX_MASK);
1855         }
1856
1857         dev_priv->pch_irq_mask = ~hotplug_mask;
1858
1859         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1860         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1861         I915_WRITE(SDEIER, hotplug_mask);
1862         POSTING_READ(SDEIER);
1863
1864         ironlake_enable_pch_hotplug(dev);
1865
1866         if (IS_IRONLAKE_M(dev)) {
1867                 /* Clear & enable PCU event interrupts */
1868                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1869                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1870                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1871         }
1872
1873         return 0;
1874 }
1875
1876 static int ivybridge_irq_postinstall(struct drm_device *dev)
1877 {
1878         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1879         /* enable kind of interrupts always enabled */
1880         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1881                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1882                 DE_PLANEB_FLIP_DONE_IVB;
1883         u32 render_irqs;
1884         u32 hotplug_mask;
1885
1886         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1887         if (HAS_BSD(dev))
1888                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1889         if (HAS_BLT(dev))
1890                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1891
1892         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1893         dev_priv->irq_mask = ~display_mask;
1894
1895         /* should always can generate irq */
1896         I915_WRITE(DEIIR, I915_READ(DEIIR));
1897         I915_WRITE(DEIMR, dev_priv->irq_mask);
1898         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1899                    DE_PIPEB_VBLANK_IVB);
1900         POSTING_READ(DEIER);
1901
1902         dev_priv->gt_irq_mask = ~0;
1903
1904         I915_WRITE(GTIIR, I915_READ(GTIIR));
1905         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1906
1907         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1908                 GT_BLT_USER_INTERRUPT;
1909         I915_WRITE(GTIER, render_irqs);
1910         POSTING_READ(GTIER);
1911
1912         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1913                         SDE_PORTB_HOTPLUG_CPT |
1914                         SDE_PORTC_HOTPLUG_CPT |
1915                         SDE_PORTD_HOTPLUG_CPT);
1916         dev_priv->pch_irq_mask = ~hotplug_mask;
1917
1918         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1919         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1920         I915_WRITE(SDEIER, hotplug_mask);
1921         POSTING_READ(SDEIER);
1922
1923         ironlake_enable_pch_hotplug(dev);
1924
1925         return 0;
1926 }
1927
1928 static void i915_driver_irq_preinstall(struct drm_device * dev)
1929 {
1930         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1931         int pipe;
1932
1933         atomic_set(&dev_priv->irq_received, 0);
1934
1935         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1936         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1937
1938         if (I915_HAS_HOTPLUG(dev)) {
1939                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1940                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1941         }
1942
1943         I915_WRITE(HWSTAM, 0xeffe);
1944         for_each_pipe(pipe)
1945                 I915_WRITE(PIPESTAT(pipe), 0);
1946         I915_WRITE(IMR, 0xffffffff);
1947         I915_WRITE(IER, 0x0);
1948         POSTING_READ(IER);
1949 }
1950
1951 /*
1952  * Must be called after intel_modeset_init or hotplug interrupts won't be
1953  * enabled correctly.
1954  */
1955 static int i915_driver_irq_postinstall(struct drm_device *dev)
1956 {
1957         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1958         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1959         u32 error_mask;
1960
1961         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1962
1963         /* Unmask the interrupts that we always want on. */
1964         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1965
1966         dev_priv->pipestat[0] = 0;
1967         dev_priv->pipestat[1] = 0;
1968
1969         if (I915_HAS_HOTPLUG(dev)) {
1970                 /* Enable in IER... */
1971                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1972                 /* and unmask in IMR */
1973                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1974         }
1975
1976         /*
1977          * Enable some error detection, note the instruction error mask
1978          * bit is reserved, so we leave it masked.
1979          */
1980         if (IS_G4X(dev)) {
1981                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1982                                GM45_ERROR_MEM_PRIV |
1983                                GM45_ERROR_CP_PRIV |
1984                                I915_ERROR_MEMORY_REFRESH);
1985         } else {
1986                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1987                                I915_ERROR_MEMORY_REFRESH);
1988         }
1989         I915_WRITE(EMR, error_mask);
1990
1991         I915_WRITE(IMR, dev_priv->irq_mask);
1992         I915_WRITE(IER, enable_mask);
1993         POSTING_READ(IER);
1994
1995         if (I915_HAS_HOTPLUG(dev)) {
1996                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1997
1998                 /* Note HDMI and DP share bits */
1999                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2000                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2001                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2002                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2003                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2004                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2005                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2006                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2007                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2008                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2009                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2010                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2011
2012                         /* Programming the CRT detection parameters tends
2013                            to generate a spurious hotplug event about three
2014                            seconds later.  So just do it once.
2015                         */
2016                         if (IS_G4X(dev))
2017                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2018                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2019                 }
2020
2021                 /* Ignore TV since it's buggy */
2022
2023                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2024         }
2025
2026         intel_opregion_enable_asle(dev);
2027
2028         return 0;
2029 }
2030
2031 static void ironlake_irq_uninstall(struct drm_device *dev)
2032 {
2033         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2034
2035         if (!dev_priv)
2036                 return;
2037
2038         dev_priv->vblank_pipe = 0;
2039
2040         I915_WRITE(HWSTAM, 0xffffffff);
2041
2042         I915_WRITE(DEIMR, 0xffffffff);
2043         I915_WRITE(DEIER, 0x0);
2044         I915_WRITE(DEIIR, I915_READ(DEIIR));
2045
2046         I915_WRITE(GTIMR, 0xffffffff);
2047         I915_WRITE(GTIER, 0x0);
2048         I915_WRITE(GTIIR, I915_READ(GTIIR));
2049
2050         I915_WRITE(SDEIMR, 0xffffffff);
2051         I915_WRITE(SDEIER, 0x0);
2052         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2053 }
2054
2055 static void i915_driver_irq_uninstall(struct drm_device * dev)
2056 {
2057         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2058         int pipe;
2059
2060         if (!dev_priv)
2061                 return;
2062
2063         dev_priv->vblank_pipe = 0;
2064
2065         if (I915_HAS_HOTPLUG(dev)) {
2066                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2067                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2068         }
2069
2070         I915_WRITE(HWSTAM, 0xffffffff);
2071         for_each_pipe(pipe)
2072                 I915_WRITE(PIPESTAT(pipe), 0);
2073         I915_WRITE(IMR, 0xffffffff);
2074         I915_WRITE(IER, 0x0);
2075
2076         for_each_pipe(pipe)
2077                 I915_WRITE(PIPESTAT(pipe),
2078                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2079         I915_WRITE(IIR, I915_READ(IIR));
2080 }
2081
2082 void intel_irq_init(struct drm_device *dev)
2083 {
2084         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2085         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2086         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2087                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2088                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2089         }
2090
2091         if (drm_core_check_feature(dev, DRIVER_MODESET))
2092                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2093         else
2094                 dev->driver->get_vblank_timestamp = NULL;
2095         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2096
2097         if (IS_IVYBRIDGE(dev)) {
2098                 /* Share pre & uninstall handlers with ILK/SNB */
2099                 dev->driver->irq_handler = ivybridge_irq_handler;
2100                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2101                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2102                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2103                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2104                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2105         } else if (HAS_PCH_SPLIT(dev)) {
2106                 dev->driver->irq_handler = ironlake_irq_handler;
2107                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2108                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2109                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2110                 dev->driver->enable_vblank = ironlake_enable_vblank;
2111                 dev->driver->disable_vblank = ironlake_disable_vblank;
2112         } else {
2113                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2114                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2115                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2116                 dev->driver->irq_handler = i915_driver_irq_handler;
2117                 dev->driver->enable_vblank = i915_enable_vblank;
2118                 dev->driver->disable_vblank = i915_disable_vblank;
2119         }
2120 }