drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119         unsigned long irqflags;
 120
 121         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194                                  "pipe %c\n", pipe_name(pipe));
 195                 return 0;
 196         }
 197
 198         return I915_READ(reg);
 199 }
 200
 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202                              int *vpos, int *hpos)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205         u32 vbl = 0, position = 0;
 206         int vbl_start, vbl_end, htotal, vtotal;
 207         bool in_vbl = true;
 208         int ret = 0;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212                                  "pipe %c\n", pipe_name(pipe));
 213                 return 0;
 214         }
 215
 216         /* Get vtotal. */
 217         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 218
 219         if (INTEL_INFO(dev)->gen >= 4) {
 220                 /* No obvious pixelcount register. Only query vertical
 221                  * scanout position from Display scan line register.
 222                  */
 223                 position = I915_READ(PIPEDSL(pipe));
 224
 225                 /* Decode into vertical scanout position. Don't have
 226                  * horizontal scanout position.
 227                  */
 228                 *vpos = position & 0x1fff;
 229                 *hpos = 0;
 230         } else {
 231                 /* Have access to pixelcount since start of frame.
 232                  * We can split this into vertical and horizontal
 233                  * scanout position.
 234                  */
 235                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238                 *vpos = position / htotal;
 239                 *hpos = position - (*vpos * htotal);
 240         }
 241
 242         /* Query vblank area. */
 243         vbl = I915_READ(VBLANK(pipe));
 244
 245         /* Test position against vblank region. */
 246         vbl_start = vbl & 0x1fff;
 247         vbl_end = (vbl >> 16) & 0x1fff;
 248
 249         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250                 in_vbl = false;
 251
 252         /* Inside "upper part" of vblank area? Apply corrective offset: */
 253         if (in_vbl && (*vpos >= vbl_start))
 254                 *vpos = *vpos - vtotal;
 255
 256         /* Readouts valid? */
 257         if (vbl > 0)
 258                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 259
 260         /* In vblank? */
 261         if (in_vbl)
 262                 ret |= DRM_SCANOUTPOS_INVBL;
 263
 264         return ret;
 265 }
 266
 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 268                               int *max_error,
 269                               struct timeval *vblank_time,
 270                               unsigned flags)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         struct drm_crtc *crtc;
 274
 275         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276                 DRM_ERROR("Invalid crtc %d\n", pipe);
 277                 return -EINVAL;
 278         }
 279
 280         /* Get drm_crtc to timestamp: */
 281         crtc = intel_get_crtc_for_pipe(dev, pipe);
 282         if (crtc == NULL) {
 283                 DRM_ERROR("Invalid crtc %d\n", pipe);
 284                 return -EINVAL;
 285         }
 286
 287         if (!crtc->enabled) {
 288                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289                 return -EBUSY;
 290         }
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294                                                      vblank_time, flags,
 295                                                      crtc);
 296 }
 297
 298 /*
 299  * Handle hotplug events outside the interrupt handler proper.
 300  */
 301 static void i915_hotplug_work_func(struct work_struct *work)
 302 {
 303         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304                                                     hotplug_work);
 305         struct drm_device *dev = dev_priv->dev;
 306         struct drm_mode_config *mode_config = &dev->mode_config;
 307         struct intel_encoder *encoder;
 308
 309         mutex_lock(&mode_config->mutex);
 310         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 311
 312         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 313                 if (encoder->hot_plug)
 314                         encoder->hot_plug(encoder);
 315
 316         mutex_unlock(&mode_config->mutex);
 317
 318         /* Just fire off a uevent and let userspace tell us what to do */
 319         drm_helper_hpd_irq_event(dev);
 320 }
 321
 322 static void i915_handle_rps_change(struct drm_device *dev)
 323 {
 324         drm_i915_private_t *dev_priv = dev->dev_private;
 325         u32 busy_up, busy_down, max_avg, min_avg;
 326         u8 new_delay = dev_priv->cur_delay;
 327
 328         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 329         busy_up = I915_READ(RCPREVBSYTUPAVG);
 330         busy_down = I915_READ(RCPREVBSYTDNAVG);
 331         max_avg = I915_READ(RCBMAXAVG);
 332         min_avg = I915_READ(RCBMINAVG);
 333
 334         /* Handle RCS change request from hw */
 335         if (busy_up > max_avg) {
 336                 if (dev_priv->cur_delay != dev_priv->max_delay)
 337                         new_delay = dev_priv->cur_delay - 1;
 338                 if (new_delay < dev_priv->max_delay)
 339                         new_delay = dev_priv->max_delay;
 340         } else if (busy_down < min_avg) {
 341                 if (dev_priv->cur_delay != dev_priv->min_delay)
 342                         new_delay = dev_priv->cur_delay + 1;
 343                 if (new_delay > dev_priv->min_delay)
 344                         new_delay = dev_priv->min_delay;
 345         }
 346
 347         if (ironlake_set_drps(dev, new_delay))
 348                 dev_priv->cur_delay = new_delay;
 349
 350         return;
 351 }
 352
 353 static void notify_ring(struct drm_device *dev,
 354                         struct intel_ring_buffer *ring)
 355 {
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         u32 seqno;
 358
 359         if (ring->obj == NULL)
 360                 return;
 361
 362         seqno = ring->get_seqno(ring);
 363         trace_i915_gem_request_complete(ring, seqno);
 364
 365         ring->irq_seqno = seqno;
 366         wake_up_all(&ring->irq_queue);
 367         if (i915_enable_hangcheck) {
 368                 dev_priv->hangcheck_count = 0;
 369                 mod_timer(&dev_priv->hangcheck_timer,
 370                           jiffies +
 371                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 372         }
 373 }
 374
 375 static void gen6_pm_rps_work(struct work_struct *work)
 376 {
 377         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 378                                                     rps_work);
 379         u8 new_delay = dev_priv->cur_delay;
 380         u32 pm_iir, pm_imr;
 381
 382         spin_lock_irq(&dev_priv->rps_lock);
 383         pm_iir = dev_priv->pm_iir;
 384         dev_priv->pm_iir = 0;
 385         pm_imr = I915_READ(GEN6_PMIMR);
 386         I915_WRITE(GEN6_PMIMR, 0);
 387         spin_unlock_irq(&dev_priv->rps_lock);
 388
 389         if (!pm_iir)
 390                 return;
 391
 392         mutex_lock(&dev_priv->dev->struct_mutex);
 393         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 394                 if (dev_priv->cur_delay != dev_priv->max_delay)
 395                         new_delay = dev_priv->cur_delay + 1;
 396                 if (new_delay > dev_priv->max_delay)
 397                         new_delay = dev_priv->max_delay;
 398         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 399                 gen6_gt_force_wake_get(dev_priv);
 400                 if (dev_priv->cur_delay != dev_priv->min_delay)
 401                         new_delay = dev_priv->cur_delay - 1;
 402                 if (new_delay < dev_priv->min_delay) {
 403                         new_delay = dev_priv->min_delay;
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 406                                    ((new_delay << 16) & 0x3f0000));
 407                 } else {
 408                         /* Make sure we continue to get down interrupts
 409                          * until we hit the minimum frequency */
 410                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 411                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 412                 }
 413                 gen6_gt_force_wake_put(dev_priv);
 414         }
 415
 416         gen6_set_rps(dev_priv->dev, new_delay);
 417         dev_priv->cur_delay = new_delay;
 418
 419         /*
 420          * rps_lock not held here because clearing is non-destructive. There is
 421          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 422          * by holding struct_mutex for the duration of the write.
 423          */
 424         mutex_unlock(&dev_priv->dev->struct_mutex);
 425 }
 426
 427 static void pch_irq_handler(struct drm_device *dev)
 428 {
 429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 430         u32 pch_iir;
 431         int pipe;
 432
 433         pch_iir = I915_READ(SDEIIR);
 434
 435         if (pch_iir & SDE_AUDIO_POWER_MASK)
 436                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 437                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 438                                  SDE_AUDIO_POWER_SHIFT);
 439
 440         if (pch_iir & SDE_GMBUS)
 441                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 442
 443         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 444                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 445
 446         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 447                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 448
 449         if (pch_iir & SDE_POISON)
 450                 DRM_ERROR("PCH poison interrupt\n");
 451
 452         if (pch_iir & SDE_FDI_MASK)
 453                 for_each_pipe(pipe)
 454                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 455                                          pipe_name(pipe),
 456                                          I915_READ(FDI_RX_IIR(pipe)));
 457
 458         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 459                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 460
 461         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 462                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 463
 464         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 465                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 466         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 467                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 468 }
 469
 470 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 471 {
 472         struct drm_device *dev = (struct drm_device *) arg;
 473         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 474         int ret = IRQ_NONE;
 475         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 476         struct drm_i915_master_private *master_priv;
 477
 478         atomic_inc(&dev_priv->irq_received);
 479
 480         /* disable master interrupt before clearing iir  */
 481         de_ier = I915_READ(DEIER);
 482         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 483         POSTING_READ(DEIER);
 484
 485         de_iir = I915_READ(DEIIR);
 486         gt_iir = I915_READ(GTIIR);
 487         pch_iir = I915_READ(SDEIIR);
 488         pm_iir = I915_READ(GEN6_PMIIR);
 489
 490         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 491                 goto done;
 492
 493         ret = IRQ_HANDLED;
 494
 495         if (dev->primary->master) {
 496                 master_priv = dev->primary->master->driver_priv;
 497                 if (master_priv->sarea_priv)
 498                         master_priv->sarea_priv->last_dispatch =
 499                                 READ_BREADCRUMB(dev_priv);
 500         }
 501
 502         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 503                 notify_ring(dev, &dev_priv->ring[RCS]);
 504         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 505                 notify_ring(dev, &dev_priv->ring[VCS]);
 506         if (gt_iir & GT_BLT_USER_INTERRUPT)
 507                 notify_ring(dev, &dev_priv->ring[BCS]);
 508
 509         if (de_iir & DE_GSE_IVB)
 510                 intel_opregion_gse_intr(dev);
 511
 512         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 513                 intel_prepare_page_flip(dev, 0);
 514                 intel_finish_page_flip_plane(dev, 0);
 515         }
 516
 517         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 518                 intel_prepare_page_flip(dev, 1);
 519                 intel_finish_page_flip_plane(dev, 1);
 520         }
 521
 522         if (de_iir & DE_PIPEA_VBLANK_IVB)
 523                 drm_handle_vblank(dev, 0);
 524
 525         if (de_iir & DE_PIPEB_VBLANK_IVB)
 526                 drm_handle_vblank(dev, 1);
 527
 528         /* check event from PCH */
 529         if (de_iir & DE_PCH_EVENT_IVB) {
 530                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 531                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 532                 pch_irq_handler(dev);
 533         }
 534
 535         if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 536                 unsigned long flags;
 537                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 538                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 539                 dev_priv->pm_iir |= pm_iir;
 540                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 541                 POSTING_READ(GEN6_PMIMR);
 542                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 543                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 544         }
 545
 546         /* should clear PCH hotplug event before clear CPU irq */
 547         I915_WRITE(SDEIIR, pch_iir);
 548         I915_WRITE(GTIIR, gt_iir);
 549         I915_WRITE(DEIIR, de_iir);
 550         I915_WRITE(GEN6_PMIIR, pm_iir);
 551
 552 done:
 553         I915_WRITE(DEIER, de_ier);
 554         POSTING_READ(DEIER);
 555
 556         return ret;
 557 }
 558
 559 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 560 {
 561         struct drm_device *dev = (struct drm_device *) arg;
 562         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 563         int ret = IRQ_NONE;
 564         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 565         u32 hotplug_mask;
 566         struct drm_i915_master_private *master_priv;
 567         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 568
 569         atomic_inc(&dev_priv->irq_received);
 570
 571         if (IS_GEN6(dev))
 572                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 573
 574         /* disable master interrupt before clearing iir  */
 575         de_ier = I915_READ(DEIER);
 576         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 577         POSTING_READ(DEIER);
 578
 579         de_iir = I915_READ(DEIIR);
 580         gt_iir = I915_READ(GTIIR);
 581         pch_iir = I915_READ(SDEIIR);
 582         pm_iir = I915_READ(GEN6_PMIIR);
 583
 584         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 585             (!IS_GEN6(dev) || pm_iir == 0))
 586                 goto done;
 587
 588         if (HAS_PCH_CPT(dev))
 589                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 590         else
 591                 hotplug_mask = SDE_HOTPLUG_MASK;
 592
 593         ret = IRQ_HANDLED;
 594
 595         if (dev->primary->master) {
 596                 master_priv = dev->primary->master->driver_priv;
 597                 if (master_priv->sarea_priv)
 598                         master_priv->sarea_priv->last_dispatch =
 599                                 READ_BREADCRUMB(dev_priv);
 600         }
 601
 602         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 603                 notify_ring(dev, &dev_priv->ring[RCS]);
 604         if (gt_iir & bsd_usr_interrupt)
 605                 notify_ring(dev, &dev_priv->ring[VCS]);
 606         if (gt_iir & GT_BLT_USER_INTERRUPT)
 607                 notify_ring(dev, &dev_priv->ring[BCS]);
 608
 609         if (de_iir & DE_GSE)
 610                 intel_opregion_gse_intr(dev);
 611
 612         if (de_iir & DE_PLANEA_FLIP_DONE) {
 613                 intel_prepare_page_flip(dev, 0);
 614                 intel_finish_page_flip_plane(dev, 0);
 615         }
 616
 617         if (de_iir & DE_PLANEB_FLIP_DONE) {
 618                 intel_prepare_page_flip(dev, 1);
 619                 intel_finish_page_flip_plane(dev, 1);
 620         }
 621
 622         if (de_iir & DE_PIPEA_VBLANK)
 623                 drm_handle_vblank(dev, 0);
 624
 625         if (de_iir & DE_PIPEB_VBLANK)
 626                 drm_handle_vblank(dev, 1);
 627
 628         /* check event from PCH */
 629         if (de_iir & DE_PCH_EVENT) {
 630                 if (pch_iir & hotplug_mask)
 631                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 632                 pch_irq_handler(dev);
 633         }
 634
 635         if (de_iir & DE_PCU_EVENT) {
 636                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 637                 i915_handle_rps_change(dev);
 638         }
 639
 640         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 641                 /*
 642                  * IIR bits should never already be set because IMR should
 643                  * prevent an interrupt from being shown in IIR. The warning
 644                  * displays a case where we've unsafely cleared
 645                  * dev_priv->pm_iir. Although missing an interrupt of the same
 646                  * type is not a problem, it displays a problem in the logic.
 647                  *
 648                  * The mask bit in IMR is cleared by rps_work.
 649                  */
 650                 unsigned long flags;
 651                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 652                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 653                 dev_priv->pm_iir |= pm_iir;
 654                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 655                 POSTING_READ(GEN6_PMIMR);
 656                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 657                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 658         }
 659
 660         /* should clear PCH hotplug event before clear CPU irq */
 661         I915_WRITE(SDEIIR, pch_iir);
 662         I915_WRITE(GTIIR, gt_iir);
 663         I915_WRITE(DEIIR, de_iir);
 664         I915_WRITE(GEN6_PMIIR, pm_iir);
 665
 666 done:
 667         I915_WRITE(DEIER, de_ier);
 668         POSTING_READ(DEIER);
 669
 670         return ret;
 671 }
 672
 673 /**
 674  * i915_error_work_func - do process context error handling work
 675  * @work: work struct
 676  *
 677  * Fire an error uevent so userspace can see that a hang or error
 678  * was detected.
 679  */
 680 static void i915_error_work_func(struct work_struct *work)
 681 {
 682         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 683                                                     error_work);
 684         struct drm_device *dev = dev_priv->dev;
 685         char *error_event[] = { "ERROR=1", NULL };
 686         char *reset_event[] = { "RESET=1", NULL };
 687         char *reset_done_event[] = { "ERROR=0", NULL };
 688
 689         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 690
 691         if (atomic_read(&dev_priv->mm.wedged)) {
 692                 DRM_DEBUG_DRIVER("resetting chip\n");
 693                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 694                 if (!i915_reset(dev, GRDOM_RENDER)) {
 695                         atomic_set(&dev_priv->mm.wedged, 0);
 696                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 697                 }
 698                 complete_all(&dev_priv->error_completion);
 699         }
 700 }
 701
 702 #ifdef CONFIG_DEBUG_FS
 703 static struct drm_i915_error_object *
 704 i915_error_object_create(struct drm_i915_private *dev_priv,
 705                          struct drm_i915_gem_object *src)
 706 {
 707         struct drm_i915_error_object *dst;
 708         int page, page_count;
 709         u32 reloc_offset;
 710
 711         if (src == NULL || src->pages == NULL)
 712                 return NULL;
 713
 714         page_count = src->base.size / PAGE_SIZE;
 715
 716         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 717         if (dst == NULL)
 718                 return NULL;
 719
 720         reloc_offset = src->gtt_offset;
 721         for (page = 0; page < page_count; page++) {
 722                 unsigned long flags;
 723                 void *d;
 724
 725                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 726                 if (d == NULL)
 727                         goto unwind;
 728
 729                 local_irq_save(flags);
 730                 if (reloc_offset < dev_priv->mm.gtt_mappable_end) {
 731                         void __iomem *s;
 732
 733                         /* Simply ignore tiling or any overlapping fence.
 734                          * It's part of the error state, and this hopefully
 735                          * captures what the GPU read.
 736                          */
 737
 738                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 739                                                      reloc_offset);
 740                         memcpy_fromio(d, s, PAGE_SIZE);
 741                         io_mapping_unmap_atomic(s);
 742                 } else {
 743                         void *s;
 744
 745                         drm_clflush_pages(&src->pages[page], 1);
 746
 747                         s = kmap_atomic(src->pages[page]);
 748                         memcpy(d, s, PAGE_SIZE);
 749                         kunmap_atomic(s);
 750
 751                         drm_clflush_pages(&src->pages[page], 1);
 752                 }
 753                 local_irq_restore(flags);
 754
 755                 dst->pages[page] = d;
 756
 757                 reloc_offset += PAGE_SIZE;
 758         }
 759         dst->page_count = page_count;
 760         dst->gtt_offset = src->gtt_offset;
 761
 762         return dst;
 763
 764 unwind:
 765         while (page--)
 766                 kfree(dst->pages[page]);
 767         kfree(dst);
 768         return NULL;
 769 }
 770
 771 static void
 772 i915_error_object_free(struct drm_i915_error_object *obj)
 773 {
 774         int page;
 775
 776         if (obj == NULL)
 777                 return;
 778
 779         for (page = 0; page < obj->page_count; page++)
 780                 kfree(obj->pages[page]);
 781
 782         kfree(obj);
 783 }
 784
 785 static void
 786 i915_error_state_free(struct drm_device *dev,
 787                       struct drm_i915_error_state *error)
 788 {
 789         int i;
 790
 791         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 792                 i915_error_object_free(error->batchbuffer[i]);
 793
 794         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 795                 i915_error_object_free(error->ringbuffer[i]);
 796
 797         kfree(error->active_bo);
 798         kfree(error->overlay);
 799         kfree(error);
 800 }
 801
 802 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 803                            int count,
 804                            struct list_head *head)
 805 {
 806         struct drm_i915_gem_object *obj;
 807         int i = 0;
 808
 809         list_for_each_entry(obj, head, mm_list) {
 810                 err->size = obj->base.size;
 811                 err->name = obj->base.name;
 812                 err->seqno = obj->last_rendering_seqno;
 813                 err->gtt_offset = obj->gtt_offset;
 814                 err->read_domains = obj->base.read_domains;
 815                 err->write_domain = obj->base.write_domain;
 816                 err->fence_reg = obj->fence_reg;
 817                 err->pinned = 0;
 818                 if (obj->pin_count > 0)
 819                         err->pinned = 1;
 820                 if (obj->user_pin_count > 0)
 821                         err->pinned = -1;
 822                 err->tiling = obj->tiling_mode;
 823                 err->dirty = obj->dirty;
 824                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 825                 err->ring = obj->ring ? obj->ring->id : -1;
 826                 err->cache_level = obj->cache_level;
 827
 828                 if (++i == count)
 829                         break;
 830
 831                 err++;
 832         }
 833
 834         return i;
 835 }
 836
 837 static void i915_gem_record_fences(struct drm_device *dev,
 838                                    struct drm_i915_error_state *error)
 839 {
 840         struct drm_i915_private *dev_priv = dev->dev_private;
 841         int i;
 842
 843         /* Fences */
 844         switch (INTEL_INFO(dev)->gen) {
 845         case 7:
 846         case 6:
 847                 for (i = 0; i < 16; i++)
 848                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 849                 break;
 850         case 5:
 851         case 4:
 852                 for (i = 0; i < 16; i++)
 853                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 854                 break;
 855         case 3:
 856                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 857                         for (i = 0; i < 8; i++)
 858                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 859         case 2:
 860                 for (i = 0; i < 8; i++)
 861                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 862                 break;
 863
 864         }
 865 }
 866
 867 static struct drm_i915_error_object *
 868 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 869                              struct intel_ring_buffer *ring)
 870 {
 871         struct drm_i915_gem_object *obj;
 872         u32 seqno;
 873
 874         if (!ring->get_seqno)
 875                 return NULL;
 876
 877         seqno = ring->get_seqno(ring);
 878         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 879                 if (obj->ring != ring)
 880                         continue;
 881
 882                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 883                         continue;
 884
 885                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 886                         continue;
 887
 888                 /* We need to copy these to an anonymous buffer as the simplest
 889                  * method to avoid being overwritten by userspace.
 890                  */
 891                 return i915_error_object_create(dev_priv, obj);
 892         }
 893
 894         return NULL;
 895 }
 896
 897 static void i915_record_ring_state(struct drm_device *dev,
 898                                    struct drm_i915_error_state *error,
 899                                    struct intel_ring_buffer *ring)
 900 {
 901         struct drm_i915_private *dev_priv = dev->dev_private;
 902
 903         if (INTEL_INFO(dev)->gen >= 6) {
 904                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
 905                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
 906         }
 907
 908         if (INTEL_INFO(dev)->gen >= 4) {
 909                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
 910                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
 911                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
 912                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
 913                 if (ring->id == RCS) {
 914                         error->instdone1 = I915_READ(INSTDONE1);
 915                         error->bbaddr = I915_READ64(BB_ADDR);
 916                 }
 917         } else {
 918                 error->ipeir[ring->id] = I915_READ(IPEIR);
 919                 error->ipehr[ring->id] = I915_READ(IPEHR);
 920                 error->instdone[ring->id] = I915_READ(INSTDONE);
 921         }
 922
 923         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
 924         error->seqno[ring->id] = ring->get_seqno(ring);
 925         error->acthd[ring->id] = intel_ring_get_active_head(ring);
 926         error->head[ring->id] = I915_READ_HEAD(ring);
 927         error->tail[ring->id] = I915_READ_TAIL(ring);
 928 }
 929
 930 /**
 931  * i915_capture_error_state - capture an error record for later analysis
 932  * @dev: drm device
 933  *
 934  * Should be called when an error is detected (either a hang or an error
 935  * interrupt) to capture error state from the time of the error.  Fills
 936  * out a structure which becomes available in debugfs for user level tools
 937  * to pick up.
 938  */
 939 static void i915_capture_error_state(struct drm_device *dev)
 940 {
 941         struct drm_i915_private *dev_priv = dev->dev_private;
 942         struct drm_i915_gem_object *obj;
 943         struct drm_i915_error_state *error;
 944         unsigned long flags;
 945         int i, pipe;
 946
 947         spin_lock_irqsave(&dev_priv->error_lock, flags);
 948         error = dev_priv->first_error;
 949         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 950         if (error)
 951                 return;
 952
 953         /* Account for pipe specific data like PIPE*STAT */
 954         error = kzalloc(sizeof(*error), GFP_ATOMIC);
 955         if (!error) {
 956                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 957                 return;
 958         }
 959
 960         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 961                  dev->primary->index);
 962
 963         error->eir = I915_READ(EIR);
 964         error->pgtbl_er = I915_READ(PGTBL_ER);
 965         for_each_pipe(pipe)
 966                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 967
 968         if (INTEL_INFO(dev)->gen >= 6) {
 969                 error->error = I915_READ(ERROR_GEN6);
 970                 error->done_reg = I915_READ(DONE_REG);
 971         }
 972
 973         i915_record_ring_state(dev, error, &dev_priv->ring[RCS]);
 974         if (HAS_BLT(dev))
 975                 i915_record_ring_state(dev, error, &dev_priv->ring[BCS]);
 976         if (HAS_BSD(dev))
 977                 i915_record_ring_state(dev, error, &dev_priv->ring[VCS]);
 978
 979         i915_gem_record_fences(dev, error);
 980
 981         /* Record the active batch and ring buffers */
 982         for (i = 0; i < I915_NUM_RINGS; i++) {
 983                 error->batchbuffer[i] =
 984                         i915_error_first_batchbuffer(dev_priv,
 985                                                      &dev_priv->ring[i]);
 986
 987                 error->ringbuffer[i] =
 988                         i915_error_object_create(dev_priv,
 989                                                  dev_priv->ring[i].obj);
 990         }
 991
 992         /* Record buffers on the active and pinned lists. */
 993         error->active_bo = NULL;
 994         error->pinned_bo = NULL;
 995
 996         i = 0;
 997         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 998                 i++;
 999         error->active_bo_count = i;
1000         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
1001                 i++;
1002         error->pinned_bo_count = i - error->active_bo_count;
1003
1004         error->active_bo = NULL;
1005         error->pinned_bo = NULL;
1006         if (i) {
1007                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1008                                            GFP_ATOMIC);
1009                 if (error->active_bo)
1010                         error->pinned_bo =
1011                                 error->active_bo + error->active_bo_count;
1012         }
1013
1014         if (error->active_bo)
1015                 error->active_bo_count =
1016                         capture_bo_list(error->active_bo,
1017                                         error->active_bo_count,
1018                                         &dev_priv->mm.active_list);
1019
1020         if (error->pinned_bo)
1021                 error->pinned_bo_count =
1022                         capture_bo_list(error->pinned_bo,
1023                                         error->pinned_bo_count,
1024                                         &dev_priv->mm.pinned_list);
1025
1026         do_gettimeofday(&error->time);
1027
1028         error->overlay = intel_overlay_capture_error_state(dev);
1029         error->display = intel_display_capture_error_state(dev);
1030
1031         spin_lock_irqsave(&dev_priv->error_lock, flags);
1032         if (dev_priv->first_error == NULL) {
1033                 dev_priv->first_error = error;
1034                 error = NULL;
1035         }
1036         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1037
1038         if (error)
1039                 i915_error_state_free(dev, error);
1040 }
1041
1042 void i915_destroy_error_state(struct drm_device *dev)
1043 {
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045         struct drm_i915_error_state *error;
1046         unsigned long flags;
1047
1048         spin_lock_irqsave(&dev_priv->error_lock, flags);
1049         error = dev_priv->first_error;
1050         dev_priv->first_error = NULL;
1051         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1052
1053         if (error)
1054                 i915_error_state_free(dev, error);
1055 }
1056 #else
1057 #define i915_capture_error_state(x)
1058 #endif
1059
1060 static void i915_report_and_clear_eir(struct drm_device *dev)
1061 {
1062         struct drm_i915_private *dev_priv = dev->dev_private;
1063         u32 eir = I915_READ(EIR);
1064         int pipe;
1065
1066         if (!eir)
1067                 return;
1068
1069         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1070                eir);
1071
1072         if (IS_G4X(dev)) {
1073                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1074                         u32 ipeir = I915_READ(IPEIR_I965);
1075
1076                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1077                                I915_READ(IPEIR_I965));
1078                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1079                                I915_READ(IPEHR_I965));
1080                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1081                                I915_READ(INSTDONE_I965));
1082                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1083                                I915_READ(INSTPS));
1084                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1085                                I915_READ(INSTDONE1));
1086                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1087                                I915_READ(ACTHD_I965));
1088                         I915_WRITE(IPEIR_I965, ipeir);
1089                         POSTING_READ(IPEIR_I965);
1090                 }
1091                 if (eir & GM45_ERROR_PAGE_TABLE) {
1092                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1093                         printk(KERN_ERR "page table error\n");
1094                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1095                                pgtbl_err);
1096                         I915_WRITE(PGTBL_ER, pgtbl_err);
1097                         POSTING_READ(PGTBL_ER);
1098                 }
1099         }
1100
1101         if (!IS_GEN2(dev)) {
1102                 if (eir & I915_ERROR_PAGE_TABLE) {
1103                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1104                         printk(KERN_ERR "page table error\n");
1105                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1106                                pgtbl_err);
1107                         I915_WRITE(PGTBL_ER, pgtbl_err);
1108                         POSTING_READ(PGTBL_ER);
1109                 }
1110         }
1111
1112         if (eir & I915_ERROR_MEMORY_REFRESH) {
1113                 printk(KERN_ERR "memory refresh error:\n");
1114                 for_each_pipe(pipe)
1115                         printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1116                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1117                 /* pipestat has already been acked */
1118         }
1119         if (eir & I915_ERROR_INSTRUCTION) {
1120                 printk(KERN_ERR "instruction error\n");
1121                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
1122                        I915_READ(INSTPM));
1123                 if (INTEL_INFO(dev)->gen < 4) {
1124                         u32 ipeir = I915_READ(IPEIR);
1125
1126                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1127                                I915_READ(IPEIR));
1128                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1129                                I915_READ(IPEHR));
1130                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1131                                I915_READ(INSTDONE));
1132                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1133                                I915_READ(ACTHD));
1134                         I915_WRITE(IPEIR, ipeir);
1135                         POSTING_READ(IPEIR);
1136                 } else {
1137                         u32 ipeir = I915_READ(IPEIR_I965);
1138
1139                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1140                                I915_READ(IPEIR_I965));
1141                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1142                                I915_READ(IPEHR_I965));
1143                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1144                                I915_READ(INSTDONE_I965));
1145                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1146                                I915_READ(INSTPS));
1147                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1148                                I915_READ(INSTDONE1));
1149                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1150                                I915_READ(ACTHD_I965));
1151                         I915_WRITE(IPEIR_I965, ipeir);
1152                         POSTING_READ(IPEIR_I965);
1153                 }
1154         }
1155
1156         I915_WRITE(EIR, eir);
1157         POSTING_READ(EIR);
1158         eir = I915_READ(EIR);
1159         if (eir) {
1160                 /*
1161                  * some errors might have become stuck,
1162                  * mask them.
1163                  */
1164                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1165                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1166                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1167         }
1168 }
1169
1170 /**
1171  * i915_handle_error - handle an error interrupt
1172  * @dev: drm device
1173  *
1174  * Do some basic checking of regsiter state at error interrupt time and
1175  * dump it to the syslog.  Also call i915_capture_error_state() to make
1176  * sure we get a record and make it available in debugfs.  Fire a uevent
1177  * so userspace knows something bad happened (should trigger collection
1178  * of a ring dump etc.).
1179  */
1180 void i915_handle_error(struct drm_device *dev, bool wedged)
1181 {
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183
1184         i915_capture_error_state(dev);
1185         i915_report_and_clear_eir(dev);
1186
1187         if (wedged) {
1188                 INIT_COMPLETION(dev_priv->error_completion);
1189                 atomic_set(&dev_priv->mm.wedged, 1);
1190
1191                 /*
1192                  * Wakeup waiting processes so they don't hang
1193                  */
1194                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1195                 if (HAS_BSD(dev))
1196                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1197                 if (HAS_BLT(dev))
1198                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1199         }
1200
1201         queue_work(dev_priv->wq, &dev_priv->error_work);
1202 }
1203
1204 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1205 {
1206         drm_i915_private_t *dev_priv = dev->dev_private;
1207         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1209         struct drm_i915_gem_object *obj;
1210         struct intel_unpin_work *work;
1211         unsigned long flags;
1212         bool stall_detected;
1213
1214         /* Ignore early vblank irqs */
1215         if (intel_crtc == NULL)
1216                 return;
1217
1218         spin_lock_irqsave(&dev->event_lock, flags);
1219         work = intel_crtc->unpin_work;
1220
1221         if (work == NULL || work->pending || !work->enable_stall_check) {
1222                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1223                 spin_unlock_irqrestore(&dev->event_lock, flags);
1224                 return;
1225         }
1226
1227         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1228         obj = work->pending_flip_obj;
1229         if (INTEL_INFO(dev)->gen >= 4) {
1230                 int dspsurf = DSPSURF(intel_crtc->plane);
1231                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1232         } else {
1233                 int dspaddr = DSPADDR(intel_crtc->plane);
1234                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1235                                                         crtc->y * crtc->fb->pitches[0] +
1236                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1237         }
1238
1239         spin_unlock_irqrestore(&dev->event_lock, flags);
1240
1241         if (stall_detected) {
1242                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1243                 intel_prepare_page_flip(dev, intel_crtc->plane);
1244         }
1245 }
1246
1247 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1248 {
1249         struct drm_device *dev = (struct drm_device *) arg;
1250         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1251         struct drm_i915_master_private *master_priv;
1252         u32 iir, new_iir;
1253         u32 pipe_stats[I915_MAX_PIPES];
1254         u32 vblank_status;
1255         int vblank = 0;
1256         unsigned long irqflags;
1257         int irq_received;
1258         int ret = IRQ_NONE, pipe;
1259         bool blc_event = false;
1260
1261         atomic_inc(&dev_priv->irq_received);
1262
1263         iir = I915_READ(IIR);
1264
1265         if (INTEL_INFO(dev)->gen >= 4)
1266                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1267         else
1268                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1269
1270         for (;;) {
1271                 irq_received = iir != 0;
1272
1273                 /* Can't rely on pipestat interrupt bit in iir as it might
1274                  * have been cleared after the pipestat interrupt was received.
1275                  * It doesn't set the bit in iir again, but it still produces
1276                  * interrupts (for non-MSI).
1277                  */
1278                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1279                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1280                         i915_handle_error(dev, false);
1281
1282                 for_each_pipe(pipe) {
1283                         int reg = PIPESTAT(pipe);
1284                         pipe_stats[pipe] = I915_READ(reg);
1285
1286                         /*
1287                          * Clear the PIPE*STAT regs before the IIR
1288                          */
1289                         if (pipe_stats[pipe] & 0x8000ffff) {
1290                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1291                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1292                                                          pipe_name(pipe));
1293                                 I915_WRITE(reg, pipe_stats[pipe]);
1294                                 irq_received = 1;
1295                         }
1296                 }
1297                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1298
1299                 if (!irq_received)
1300                         break;
1301
1302                 ret = IRQ_HANDLED;
1303
1304                 /* Consume port.  Then clear IIR or we'll miss events */
1305                 if ((I915_HAS_HOTPLUG(dev)) &&
1306                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1307                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1308
1309                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1310                                   hotplug_status);
1311                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1312                                 queue_work(dev_priv->wq,
1313                                            &dev_priv->hotplug_work);
1314
1315                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1316                         I915_READ(PORT_HOTPLUG_STAT);
1317                 }
1318
1319                 I915_WRITE(IIR, iir);
1320                 new_iir = I915_READ(IIR); /* Flush posted writes */
1321
1322                 if (dev->primary->master) {
1323                         master_priv = dev->primary->master->driver_priv;
1324                         if (master_priv->sarea_priv)
1325                                 master_priv->sarea_priv->last_dispatch =
1326                                         READ_BREADCRUMB(dev_priv);
1327                 }
1328
1329                 if (iir & I915_USER_INTERRUPT)
1330                         notify_ring(dev, &dev_priv->ring[RCS]);
1331                 if (iir & I915_BSD_USER_INTERRUPT)
1332                         notify_ring(dev, &dev_priv->ring[VCS]);
1333
1334                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1335                         intel_prepare_page_flip(dev, 0);
1336                         if (dev_priv->flip_pending_is_done)
1337                                 intel_finish_page_flip_plane(dev, 0);
1338                 }
1339
1340                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1341                         intel_prepare_page_flip(dev, 1);
1342                         if (dev_priv->flip_pending_is_done)
1343                                 intel_finish_page_flip_plane(dev, 1);
1344                 }
1345
1346                 for_each_pipe(pipe) {
1347                         if (pipe_stats[pipe] & vblank_status &&
1348                             drm_handle_vblank(dev, pipe)) {
1349                                 vblank++;
1350                                 if (!dev_priv->flip_pending_is_done) {
1351                                         i915_pageflip_stall_check(dev, pipe);
1352                                         intel_finish_page_flip(dev, pipe);
1353                                 }
1354                         }
1355
1356                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1357                                 blc_event = true;
1358                 }
1359
1360
1361                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1362                         intel_opregion_asle_intr(dev);
1363
1364                 /* With MSI, interrupts are only generated when iir
1365                  * transitions from zero to nonzero.  If another bit got
1366                  * set while we were handling the existing iir bits, then
1367                  * we would never get another interrupt.
1368                  *
1369                  * This is fine on non-MSI as well, as if we hit this path
1370                  * we avoid exiting the interrupt handler only to generate
1371                  * another one.
1372                  *
1373                  * Note that for MSI this could cause a stray interrupt report
1374                  * if an interrupt landed in the time between writing IIR and
1375                  * the posting read.  This should be rare enough to never
1376                  * trigger the 99% of 100,000 interrupts test for disabling
1377                  * stray interrupts.
1378                  */
1379                 iir = new_iir;
1380         }
1381
1382         return ret;
1383 }
1384
1385 static int i915_emit_irq(struct drm_device * dev)
1386 {
1387         drm_i915_private_t *dev_priv = dev->dev_private;
1388         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1389
1390         i915_kernel_lost_context(dev);
1391
1392         DRM_DEBUG_DRIVER("\n");
1393
1394         dev_priv->counter++;
1395         if (dev_priv->counter > 0x7FFFFFFFUL)
1396                 dev_priv->counter = 1;
1397         if (master_priv->sarea_priv)
1398                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1399
1400         if (BEGIN_LP_RING(4) == 0) {
1401                 OUT_RING(MI_STORE_DWORD_INDEX);
1402                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1403                 OUT_RING(dev_priv->counter);
1404                 OUT_RING(MI_USER_INTERRUPT);
1405                 ADVANCE_LP_RING();
1406         }
1407
1408         return dev_priv->counter;
1409 }
1410
1411 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1412 {
1413         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1414         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1415         int ret = 0;
1416         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1417
1418         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1419                   READ_BREADCRUMB(dev_priv));
1420
1421         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1422                 if (master_priv->sarea_priv)
1423                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1424                 return 0;
1425         }
1426
1427         if (master_priv->sarea_priv)
1428                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1429
1430         if (ring->irq_get(ring)) {
1431                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1432                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1433                 ring->irq_put(ring);
1434         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1435                 ret = -EBUSY;
1436
1437         if (ret == -EBUSY) {
1438                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1439                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1440         }
1441
1442         return ret;
1443 }
1444
1445 /* Needs the lock as it touches the ring.
1446  */
1447 int i915_irq_emit(struct drm_device *dev, void *data,
1448                          struct drm_file *file_priv)
1449 {
1450         drm_i915_private_t *dev_priv = dev->dev_private;
1451         drm_i915_irq_emit_t *emit = data;
1452         int result;
1453
1454         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1455                 DRM_ERROR("called with no initialization\n");
1456                 return -EINVAL;
1457         }
1458
1459         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1460
1461         mutex_lock(&dev->struct_mutex);
1462         result = i915_emit_irq(dev);
1463         mutex_unlock(&dev->struct_mutex);
1464
1465         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1466                 DRM_ERROR("copy_to_user\n");
1467                 return -EFAULT;
1468         }
1469
1470         return 0;
1471 }
1472
1473 /* Doesn't need the hardware lock.
1474  */
1475 int i915_irq_wait(struct drm_device *dev, void *data,
1476                          struct drm_file *file_priv)
1477 {
1478         drm_i915_private_t *dev_priv = dev->dev_private;
1479         drm_i915_irq_wait_t *irqwait = data;
1480
1481         if (!dev_priv) {
1482                 DRM_ERROR("called with no initialization\n");
1483                 return -EINVAL;
1484         }
1485
1486         return i915_wait_irq(dev, irqwait->irq_seq);
1487 }
1488
1489 /* Called from drm generic code, passed 'crtc' which
1490  * we use as a pipe index
1491  */
1492 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1493 {
1494         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1495         unsigned long irqflags;
1496
1497         if (!i915_pipe_enabled(dev, pipe))
1498                 return -EINVAL;
1499
1500         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1501         if (INTEL_INFO(dev)->gen >= 4)
1502                 i915_enable_pipestat(dev_priv, pipe,
1503                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1504         else
1505                 i915_enable_pipestat(dev_priv, pipe,
1506                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1507
1508         /* maintain vblank delivery even in deep C-states */
1509         if (dev_priv->info->gen == 3)
1510                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1511         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1512
1513         return 0;
1514 }
1515
1516 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1517 {
1518         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1519         unsigned long irqflags;
1520
1521         if (!i915_pipe_enabled(dev, pipe))
1522                 return -EINVAL;
1523
1524         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1525         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1526                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1527         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1528
1529         return 0;
1530 }
1531
1532 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1533 {
1534         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535         unsigned long irqflags;
1536
1537         if (!i915_pipe_enabled(dev, pipe))
1538                 return -EINVAL;
1539
1540         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1541         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1542                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1543         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1544
1545         return 0;
1546 }
1547
1548 /* Called from drm generic code, passed 'crtc' which
1549  * we use as a pipe index
1550  */
1551 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1552 {
1553         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1554         unsigned long irqflags;
1555
1556         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1557         if (dev_priv->info->gen == 3)
1558                 I915_WRITE(INSTPM,
1559                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1560
1561         i915_disable_pipestat(dev_priv, pipe,
1562                               PIPE_VBLANK_INTERRUPT_ENABLE |
1563                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1564         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1565 }
1566
1567 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1568 {
1569         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1570         unsigned long irqflags;
1571
1572         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1573         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1574                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1575         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1576 }
1577
1578 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1579 {
1580         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1581         unsigned long irqflags;
1582
1583         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1584         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1585                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1586         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1587 }
1588
1589 /* Set the vblank monitor pipe
1590  */
1591 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1592                          struct drm_file *file_priv)
1593 {
1594         drm_i915_private_t *dev_priv = dev->dev_private;
1595
1596         if (!dev_priv) {
1597                 DRM_ERROR("called with no initialization\n");
1598                 return -EINVAL;
1599         }
1600
1601         return 0;
1602 }
1603
1604 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1605                          struct drm_file *file_priv)
1606 {
1607         drm_i915_private_t *dev_priv = dev->dev_private;
1608         drm_i915_vblank_pipe_t *pipe = data;
1609
1610         if (!dev_priv) {
1611                 DRM_ERROR("called with no initialization\n");
1612                 return -EINVAL;
1613         }
1614
1615         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1616
1617         return 0;
1618 }
1619
1620 /**
1621  * Schedule buffer swap at given vertical blank.
1622  */
1623 int i915_vblank_swap(struct drm_device *dev, void *data,
1624                      struct drm_file *file_priv)
1625 {
1626         /* The delayed swap mechanism was fundamentally racy, and has been
1627          * removed.  The model was that the client requested a delayed flip/swap
1628          * from the kernel, then waited for vblank before continuing to perform
1629          * rendering.  The problem was that the kernel might wake the client
1630          * up before it dispatched the vblank swap (since the lock has to be
1631          * held while touching the ringbuffer), in which case the client would
1632          * clear and start the next frame before the swap occurred, and
1633          * flicker would occur in addition to likely missing the vblank.
1634          *
1635          * In the absence of this ioctl, userland falls back to a correct path
1636          * of waiting for a vblank, then dispatching the swap on its own.
1637          * Context switching to userland and back is plenty fast enough for
1638          * meeting the requirements of vblank swapping.
1639          */
1640         return -EINVAL;
1641 }
1642
1643 static u32
1644 ring_last_seqno(struct intel_ring_buffer *ring)
1645 {
1646         return list_entry(ring->request_list.prev,
1647                           struct drm_i915_gem_request, list)->seqno;
1648 }
1649
1650 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1651 {
1652         if (list_empty(&ring->request_list) ||
1653             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1654                 /* Issue a wake-up to catch stuck h/w. */
1655                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1656                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1657                                   ring->name,
1658                                   ring->waiting_seqno,
1659                                   ring->get_seqno(ring));
1660                         wake_up_all(&ring->irq_queue);
1661                         *err = true;
1662                 }
1663                 return true;
1664         }
1665         return false;
1666 }
1667
1668 static bool kick_ring(struct intel_ring_buffer *ring)
1669 {
1670         struct drm_device *dev = ring->dev;
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         u32 tmp = I915_READ_CTL(ring);
1673         if (tmp & RING_WAIT) {
1674                 DRM_ERROR("Kicking stuck wait on %s\n",
1675                           ring->name);
1676                 I915_WRITE_CTL(ring, tmp);
1677                 return true;
1678         }
1679         return false;
1680 }
1681
1682 /**
1683  * This is called when the chip hasn't reported back with completed
1684  * batchbuffers in a long time. The first time this is called we simply record
1685  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1686  * again, we assume the chip is wedged and try to fix it.
1687  */
1688 void i915_hangcheck_elapsed(unsigned long data)
1689 {
1690         struct drm_device *dev = (struct drm_device *)data;
1691         drm_i915_private_t *dev_priv = dev->dev_private;
1692         uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1693         bool err = false;
1694
1695         if (!i915_enable_hangcheck)
1696                 return;
1697
1698         /* If all work is done then ACTHD clearly hasn't advanced. */
1699         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1700             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1701             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1702                 dev_priv->hangcheck_count = 0;
1703                 if (err)
1704                         goto repeat;
1705                 return;
1706         }
1707
1708         if (INTEL_INFO(dev)->gen < 4) {
1709                 instdone = I915_READ(INSTDONE);
1710                 instdone1 = 0;
1711         } else {
1712                 instdone = I915_READ(INSTDONE_I965);
1713                 instdone1 = I915_READ(INSTDONE1);
1714         }
1715         acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1716         acthd_bsd = HAS_BSD(dev) ?
1717                 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1718         acthd_blt = HAS_BLT(dev) ?
1719                 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1720
1721         if (dev_priv->last_acthd == acthd &&
1722             dev_priv->last_acthd_bsd == acthd_bsd &&
1723             dev_priv->last_acthd_blt == acthd_blt &&
1724             dev_priv->last_instdone == instdone &&
1725             dev_priv->last_instdone1 == instdone1) {
1726                 if (dev_priv->hangcheck_count++ > 1) {
1727                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1728                         i915_handle_error(dev, true);
1729
1730                         if (!IS_GEN2(dev)) {
1731                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1732                                  * If so we can simply poke the RB_WAIT bit
1733                                  * and break the hang. This should work on
1734                                  * all but the second generation chipsets.
1735                                  */
1736                                 if (kick_ring(&dev_priv->ring[RCS]))
1737                                         goto repeat;
1738
1739                                 if (HAS_BSD(dev) &&
1740                                     kick_ring(&dev_priv->ring[VCS]))
1741                                         goto repeat;
1742
1743                                 if (HAS_BLT(dev) &&
1744                                     kick_ring(&dev_priv->ring[BCS]))
1745                                         goto repeat;
1746                         }
1747
1748                         return;
1749                 }
1750         } else {
1751                 dev_priv->hangcheck_count = 0;
1752
1753                 dev_priv->last_acthd = acthd;
1754                 dev_priv->last_acthd_bsd = acthd_bsd;
1755                 dev_priv->last_acthd_blt = acthd_blt;
1756                 dev_priv->last_instdone = instdone;
1757                 dev_priv->last_instdone1 = instdone1;
1758         }
1759
1760 repeat:
1761         /* Reset timer case chip hangs without another request being added */
1762         mod_timer(&dev_priv->hangcheck_timer,
1763                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1764 }
1765
1766 /* drm_dma.h hooks
1767 */
1768 static void ironlake_irq_preinstall(struct drm_device *dev)
1769 {
1770         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1771
1772         atomic_set(&dev_priv->irq_received, 0);
1773
1774         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1775         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1776         if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1777                 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1778
1779         I915_WRITE(HWSTAM, 0xeffe);
1780
1781         if (IS_GEN6(dev)) {
1782                 /* Workaround stalls observed on Sandy Bridge GPUs by
1783                  * making the blitter command streamer generate a
1784                  * write to the Hardware Status Page for
1785                  * MI_USER_INTERRUPT.  This appears to serialize the
1786                  * previous seqno write out before the interrupt
1787                  * happens.
1788                  */
1789                 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1790                 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1791         }
1792
1793         /* XXX hotplug from PCH */
1794
1795         I915_WRITE(DEIMR, 0xffffffff);
1796         I915_WRITE(DEIER, 0x0);
1797         POSTING_READ(DEIER);
1798
1799         /* and GT */
1800         I915_WRITE(GTIMR, 0xffffffff);
1801         I915_WRITE(GTIER, 0x0);
1802         POSTING_READ(GTIER);
1803
1804         /* south display irq */
1805         I915_WRITE(SDEIMR, 0xffffffff);
1806         I915_WRITE(SDEIER, 0x0);
1807         POSTING_READ(SDEIER);
1808 }
1809
1810 /*
1811  * Enable digital hotplug on the PCH, and configure the DP short pulse
1812  * duration to 2ms (which is the minimum in the Display Port spec)
1813  *
1814  * This register is the same on all known PCH chips.
1815  */
1816
1817 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1818 {
1819         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1820         u32     hotplug;
1821
1822         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1823         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1824         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1825         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1826         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1827         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1828 }
1829
1830 static int ironlake_irq_postinstall(struct drm_device *dev)
1831 {
1832         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1833         /* enable kind of interrupts always enabled */
1834         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1835                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1836         u32 render_irqs;
1837         u32 hotplug_mask;
1838
1839         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1840         if (HAS_BSD(dev))
1841                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1842         if (HAS_BLT(dev))
1843                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1844
1845         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1846         dev_priv->irq_mask = ~display_mask;
1847
1848         /* should always can generate irq */
1849         I915_WRITE(DEIIR, I915_READ(DEIIR));
1850         I915_WRITE(DEIMR, dev_priv->irq_mask);
1851         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1852         POSTING_READ(DEIER);
1853
1854         dev_priv->gt_irq_mask = ~0;
1855
1856         I915_WRITE(GTIIR, I915_READ(GTIIR));
1857         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1858
1859         if (IS_GEN6(dev))
1860                 render_irqs =
1861                         GT_USER_INTERRUPT |
1862                         GT_GEN6_BSD_USER_INTERRUPT |
1863                         GT_BLT_USER_INTERRUPT;
1864         else
1865                 render_irqs =
1866                         GT_USER_INTERRUPT |
1867                         GT_PIPE_NOTIFY |
1868                         GT_BSD_USER_INTERRUPT;
1869         I915_WRITE(GTIER, render_irqs);
1870         POSTING_READ(GTIER);
1871
1872         if (HAS_PCH_CPT(dev)) {
1873                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1874                                 SDE_PORTB_HOTPLUG_CPT |
1875                                 SDE_PORTC_HOTPLUG_CPT |
1876                                 SDE_PORTD_HOTPLUG_CPT);
1877         } else {
1878                 hotplug_mask = (SDE_CRT_HOTPLUG |
1879                                 SDE_PORTB_HOTPLUG |
1880                                 SDE_PORTC_HOTPLUG |
1881                                 SDE_PORTD_HOTPLUG |
1882                                 SDE_AUX_MASK);
1883         }
1884
1885         dev_priv->pch_irq_mask = ~hotplug_mask;
1886
1887         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1888         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1889         I915_WRITE(SDEIER, hotplug_mask);
1890         POSTING_READ(SDEIER);
1891
1892         ironlake_enable_pch_hotplug(dev);
1893
1894         if (IS_IRONLAKE_M(dev)) {
1895                 /* Clear & enable PCU event interrupts */
1896                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1897                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1898                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int ivybridge_irq_postinstall(struct drm_device *dev)
1905 {
1906         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1907         /* enable kind of interrupts always enabled */
1908         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1909                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1910                 DE_PLANEB_FLIP_DONE_IVB;
1911         u32 render_irqs;
1912         u32 hotplug_mask;
1913
1914         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1915         if (HAS_BSD(dev))
1916                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1917         if (HAS_BLT(dev))
1918                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1919
1920         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1921         dev_priv->irq_mask = ~display_mask;
1922
1923         /* should always can generate irq */
1924         I915_WRITE(DEIIR, I915_READ(DEIIR));
1925         I915_WRITE(DEIMR, dev_priv->irq_mask);
1926         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1927                    DE_PIPEB_VBLANK_IVB);
1928         POSTING_READ(DEIER);
1929
1930         dev_priv->gt_irq_mask = ~0;
1931
1932         I915_WRITE(GTIIR, I915_READ(GTIIR));
1933         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1934
1935         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1936                 GT_BLT_USER_INTERRUPT;
1937         I915_WRITE(GTIER, render_irqs);
1938         POSTING_READ(GTIER);
1939
1940         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1941                         SDE_PORTB_HOTPLUG_CPT |
1942                         SDE_PORTC_HOTPLUG_CPT |
1943                         SDE_PORTD_HOTPLUG_CPT);
1944         dev_priv->pch_irq_mask = ~hotplug_mask;
1945
1946         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1947         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1948         I915_WRITE(SDEIER, hotplug_mask);
1949         POSTING_READ(SDEIER);
1950
1951         ironlake_enable_pch_hotplug(dev);
1952
1953         return 0;
1954 }
1955
1956 static void i915_driver_irq_preinstall(struct drm_device * dev)
1957 {
1958         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1959         int pipe;
1960
1961         atomic_set(&dev_priv->irq_received, 0);
1962
1963         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1964         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1965
1966         if (I915_HAS_HOTPLUG(dev)) {
1967                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1968                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1969         }
1970
1971         I915_WRITE(HWSTAM, 0xeffe);
1972         for_each_pipe(pipe)
1973                 I915_WRITE(PIPESTAT(pipe), 0);
1974         I915_WRITE(IMR, 0xffffffff);
1975         I915_WRITE(IER, 0x0);
1976         POSTING_READ(IER);
1977 }
1978
1979 /*
1980  * Must be called after intel_modeset_init or hotplug interrupts won't be
1981  * enabled correctly.
1982  */
1983 static int i915_driver_irq_postinstall(struct drm_device *dev)
1984 {
1985         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1986         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1987         u32 error_mask;
1988
1989         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1990
1991         /* Unmask the interrupts that we always want on. */
1992         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1993
1994         dev_priv->pipestat[0] = 0;
1995         dev_priv->pipestat[1] = 0;
1996
1997         if (I915_HAS_HOTPLUG(dev)) {
1998                 /* Enable in IER... */
1999                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2000                 /* and unmask in IMR */
2001                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2002         }
2003
2004         /*
2005          * Enable some error detection, note the instruction error mask
2006          * bit is reserved, so we leave it masked.
2007          */
2008         if (IS_G4X(dev)) {
2009                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2010                                GM45_ERROR_MEM_PRIV |
2011                                GM45_ERROR_CP_PRIV |
2012                                I915_ERROR_MEMORY_REFRESH);
2013         } else {
2014                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2015                                I915_ERROR_MEMORY_REFRESH);
2016         }
2017         I915_WRITE(EMR, error_mask);
2018
2019         I915_WRITE(IMR, dev_priv->irq_mask);
2020         I915_WRITE(IER, enable_mask);
2021         POSTING_READ(IER);
2022
2023         if (I915_HAS_HOTPLUG(dev)) {
2024                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2025
2026                 /* Note HDMI and DP share bits */
2027                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2028                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2029                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2030                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2031                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2032                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2033                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2034                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2035                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2036                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2037                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2038                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2039
2040                         /* Programming the CRT detection parameters tends
2041                            to generate a spurious hotplug event about three
2042                            seconds later.  So just do it once.
2043                         */
2044                         if (IS_G4X(dev))
2045                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2046                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2047                 }
2048
2049                 /* Ignore TV since it's buggy */
2050
2051                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2052         }
2053
2054         intel_opregion_enable_asle(dev);
2055
2056         return 0;
2057 }
2058
2059 static void ironlake_irq_uninstall(struct drm_device *dev)
2060 {
2061         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2062
2063         if (!dev_priv)
2064                 return;
2065
2066         dev_priv->vblank_pipe = 0;
2067
2068         I915_WRITE(HWSTAM, 0xffffffff);
2069
2070         I915_WRITE(DEIMR, 0xffffffff);
2071         I915_WRITE(DEIER, 0x0);
2072         I915_WRITE(DEIIR, I915_READ(DEIIR));
2073
2074         I915_WRITE(GTIMR, 0xffffffff);
2075         I915_WRITE(GTIER, 0x0);
2076         I915_WRITE(GTIIR, I915_READ(GTIIR));
2077
2078         I915_WRITE(SDEIMR, 0xffffffff);
2079         I915_WRITE(SDEIER, 0x0);
2080         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2081 }
2082
2083 static void i915_driver_irq_uninstall(struct drm_device * dev)
2084 {
2085         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2086         int pipe;
2087
2088         if (!dev_priv)
2089                 return;
2090
2091         dev_priv->vblank_pipe = 0;
2092
2093         if (I915_HAS_HOTPLUG(dev)) {
2094                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2095                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2096         }
2097
2098         I915_WRITE(HWSTAM, 0xffffffff);
2099         for_each_pipe(pipe)
2100                 I915_WRITE(PIPESTAT(pipe), 0);
2101         I915_WRITE(IMR, 0xffffffff);
2102         I915_WRITE(IER, 0x0);
2103
2104         for_each_pipe(pipe)
2105                 I915_WRITE(PIPESTAT(pipe),
2106                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2107         I915_WRITE(IIR, I915_READ(IIR));
2108 }
2109
2110 void intel_irq_init(struct drm_device *dev)
2111 {
2112         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2113         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2114         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2115                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2116                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2117         }
2118
2119         if (drm_core_check_feature(dev, DRIVER_MODESET))
2120                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2121         else
2122                 dev->driver->get_vblank_timestamp = NULL;
2123         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2124
2125         if (IS_IVYBRIDGE(dev)) {
2126                 /* Share pre & uninstall handlers with ILK/SNB */
2127                 dev->driver->irq_handler = ivybridge_irq_handler;
2128                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2129                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2130                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2131                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2132                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2133         } else if (HAS_PCH_SPLIT(dev)) {
2134                 dev->driver->irq_handler = ironlake_irq_handler;
2135                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2136                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2137                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2138                 dev->driver->enable_vblank = ironlake_enable_vblank;
2139                 dev->driver->disable_vblank = ironlake_disable_vblank;
2140         } else {
2141                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2142                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2143                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2144                 dev->driver->irq_handler = i915_driver_irq_handler;
2145                 dev->driver->enable_vblank = i915_enable_vblank;
2146                 dev->driver->disable_vblank = i915_disable_vblank;
2147         }
2148 }