drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static int
  62 i915_gem_object_get_pages(struct drm_gem_object *obj,
  63                           gfp_t gfpmask);
  64
  65 static void
  66 i915_gem_object_put_pages(struct drm_gem_object *obj);
  67
  68 static LIST_HEAD(shrink_list);
  69 static DEFINE_SPINLOCK(shrink_list_lock);
  70
  71 /* some bookkeeping */
  72 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  73                                   size_t size)
  74 {
  75         dev_priv->mm.object_count++;
  76         dev_priv->mm.object_memory += size;
  77 }
  78
  79 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  80                                      size_t size)
  81 {
  82         dev_priv->mm.object_count--;
  83         dev_priv->mm.object_memory -= size;
  84 }
  85
  86 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
  87                                   size_t size)
  88 {
  89         dev_priv->mm.gtt_count++;
  90         dev_priv->mm.gtt_memory += size;
  91 }
  92
  93 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
  94                                      size_t size)
  95 {
  96         dev_priv->mm.gtt_count--;
  97         dev_priv->mm.gtt_memory -= size;
  98 }
  99
 100 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
 101                                   size_t size)
 102 {
 103         dev_priv->mm.pin_count++;
 104         dev_priv->mm.pin_memory += size;
 105 }
 106
 107 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
 108                                      size_t size)
 109 {
 110         dev_priv->mm.pin_count--;
 111         dev_priv->mm.pin_memory -= size;
 112 }
 113
 114 int
 115 i915_gem_check_is_wedged(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct completion *x = &dev_priv->error_completion;
 119         unsigned long flags;
 120         int ret;
 121
 122         if (!atomic_read(&dev_priv->mm.wedged))
 123                 return 0;
 124
 125         ret = wait_for_completion_interruptible(x);
 126         if (ret)
 127                 return ret;
 128
 129         /* Success, we reset the GPU! */
 130         if (!atomic_read(&dev_priv->mm.wedged))
 131                 return 0;
 132
 133         /* GPU is hung, bump the completion count to account for
 134          * the token we just consumed so that we never hit zero and
 135          * end up waiting upon a subsequent completion event that
 136          * will never happen.
 137          */
 138         spin_lock_irqsave(&x->wait.lock, flags);
 139         x->done++;
 140         spin_unlock_irqrestore(&x->wait.lock, flags);
 141         return -EIO;
 142 }
 143
 144 static int i915_mutex_lock_interruptible(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         int ret;
 148
 149         ret = i915_gem_check_is_wedged(dev);
 150         if (ret)
 151                 return ret;
 152
 153         ret = mutex_lock_interruptible(&dev->struct_mutex);
 154         if (ret)
 155                 return ret;
 156
 157         if (atomic_read(&dev_priv->mm.wedged)) {
 158                 mutex_unlock(&dev->struct_mutex);
 159                 return -EAGAIN;
 160         }
 161
 162         WARN_ON(i915_verify_lists(dev));
 163         return 0;
 164 }
 165
 166 static inline bool
 167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
 168 {
 169         return obj_priv->gtt_space &&
 170                 !obj_priv->active &&
 171                 obj_priv->pin_count == 0;
 172 }
 173
 174 int i915_gem_do_init(struct drm_device *dev,
 175                      unsigned long start,
 176                      unsigned long end)
 177 {
 178         drm_i915_private_t *dev_priv = dev->dev_private;
 179
 180         if (start >= end ||
 181             (start & (PAGE_SIZE - 1)) != 0 ||
 182             (end & (PAGE_SIZE - 1)) != 0) {
 183                 return -EINVAL;
 184         }
 185
 186         drm_mm_init(&dev_priv->mm.gtt_space, start,
 187                     end - start);
 188
 189         dev_priv->mm.gtt_total = end - start;
 190
 191         return 0;
 192 }
 193
 194 int
 195 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 196                     struct drm_file *file_priv)
 197 {
 198         struct drm_i915_gem_init *args = data;
 199         int ret;
 200
 201         mutex_lock(&dev->struct_mutex);
 202         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 203         mutex_unlock(&dev->struct_mutex);
 204
 205         return ret;
 206 }
 207
 208 int
 209 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 210                             struct drm_file *file_priv)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct drm_i915_gem_get_aperture *args = data;
 214
 215         if (!(dev->driver->driver_features & DRIVER_GEM))
 216                 return -ENODEV;
 217
 218         mutex_lock(&dev->struct_mutex);
 219         args->aper_size = dev_priv->mm.gtt_total;
 220         args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
 221         mutex_unlock(&dev->struct_mutex);
 222
 223         return 0;
 224 }
 225
 226
 227 /**
 228  * Creates a new mm object and returns a handle to it.
 229  */
 230 int
 231 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 232                       struct drm_file *file_priv)
 233 {
 234         struct drm_i915_gem_create *args = data;
 235         struct drm_gem_object *obj;
 236         int ret;
 237         u32 handle;
 238
 239         args->size = roundup(args->size, PAGE_SIZE);
 240
 241         /* Allocate the new object */
 242         obj = i915_gem_alloc_object(dev, args->size);
 243         if (obj == NULL)
 244                 return -ENOMEM;
 245
 246         ret = drm_gem_handle_create(file_priv, obj, &handle);
 247         if (ret) {
 248                 drm_gem_object_release(obj);
 249                 i915_gem_info_remove_obj(dev->dev_private, obj->size);
 250                 kfree(obj);
 251                 return ret;
 252         }
 253
 254         /* drop reference from allocate - handle holds it now */
 255         drm_gem_object_unreference(obj);
 256         trace_i915_gem_object_create(obj);
 257
 258         args->handle = handle;
 259         return 0;
 260 }
 261
 262 static inline int
 263 fast_shmem_read(struct page **pages,
 264                 loff_t page_base, int page_offset,
 265                 char __user *data,
 266                 int length)
 267 {
 268         char *vaddr;
 269         int ret;
 270
 271         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 272         ret = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 273         kunmap_atomic(vaddr, KM_USER0);
 274
 275         return ret;
 276 }
 277
 278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 279 {
 280         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 281         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 282
 283         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 284                 obj_priv->tiling_mode != I915_TILING_NONE;
 285 }
 286
 287 static inline void
 288 slow_shmem_copy(struct page *dst_page,
 289                 int dst_offset,
 290                 struct page *src_page,
 291                 int src_offset,
 292                 int length)
 293 {
 294         char *dst_vaddr, *src_vaddr;
 295
 296         dst_vaddr = kmap(dst_page);
 297         src_vaddr = kmap(src_page);
 298
 299         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 300
 301         kunmap(src_page);
 302         kunmap(dst_page);
 303 }
 304
 305 static inline void
 306 slow_shmem_bit17_copy(struct page *gpu_page,
 307                       int gpu_offset,
 308                       struct page *cpu_page,
 309                       int cpu_offset,
 310                       int length,
 311                       int is_read)
 312 {
 313         char *gpu_vaddr, *cpu_vaddr;
 314
 315         /* Use the unswizzled path if this page isn't affected. */
 316         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 317                 if (is_read)
 318                         return slow_shmem_copy(cpu_page, cpu_offset,
 319                                                gpu_page, gpu_offset, length);
 320                 else
 321                         return slow_shmem_copy(gpu_page, gpu_offset,
 322                                                cpu_page, cpu_offset, length);
 323         }
 324
 325         gpu_vaddr = kmap(gpu_page);
 326         cpu_vaddr = kmap(cpu_page);
 327
 328         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 329          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 330          */
 331         while (length > 0) {
 332                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 333                 int this_length = min(cacheline_end - gpu_offset, length);
 334                 int swizzled_gpu_offset = gpu_offset ^ 64;
 335
 336                 if (is_read) {
 337                         memcpy(cpu_vaddr + cpu_offset,
 338                                gpu_vaddr + swizzled_gpu_offset,
 339                                this_length);
 340                 } else {
 341                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 342                                cpu_vaddr + cpu_offset,
 343                                this_length);
 344                 }
 345                 cpu_offset += this_length;
 346                 gpu_offset += this_length;
 347                 length -= this_length;
 348         }
 349
 350         kunmap(cpu_page);
 351         kunmap(gpu_page);
 352 }
 353
 354 /**
 355  * This is the fast shmem pread path, which attempts to copy_from_user directly
 356  * from the backing pages of the object to the user's address space.  On a
 357  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 358  */
 359 static int
 360 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 361                           struct drm_i915_gem_pread *args,
 362                           struct drm_file *file_priv)
 363 {
 364         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 365         ssize_t remain;
 366         loff_t offset, page_base;
 367         char __user *user_data;
 368         int page_offset, page_length;
 369
 370         user_data = (char __user *) (uintptr_t) args->data_ptr;
 371         remain = args->size;
 372
 373         obj_priv = to_intel_bo(obj);
 374         offset = args->offset;
 375
 376         while (remain > 0) {
 377                 /* Operation in this page
 378                  *
 379                  * page_base = page offset within aperture
 380                  * page_offset = offset within page
 381                  * page_length = bytes to copy for this page
 382                  */
 383                 page_base = (offset & ~(PAGE_SIZE-1));
 384                 page_offset = offset & (PAGE_SIZE-1);
 385                 page_length = remain;
 386                 if ((page_offset + remain) > PAGE_SIZE)
 387                         page_length = PAGE_SIZE - page_offset;
 388
 389                 if (fast_shmem_read(obj_priv->pages,
 390                                     page_base, page_offset,
 391                                     user_data, page_length))
 392                         return -EFAULT;
 393
 394                 remain -= page_length;
 395                 user_data += page_length;
 396                 offset += page_length;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int
 403 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 404 {
 405         int ret;
 406
 407         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 408
 409         /* If we've insufficient memory to map in the pages, attempt
 410          * to make some space by throwing out some old buffers.
 411          */
 412         if (ret == -ENOMEM) {
 413                 struct drm_device *dev = obj->dev;
 414
 415                 ret = i915_gem_evict_something(dev, obj->size,
 416                                                i915_gem_get_gtt_alignment(obj));
 417                 if (ret)
 418                         return ret;
 419
 420                 ret = i915_gem_object_get_pages(obj, 0);
 421         }
 422
 423         return ret;
 424 }
 425
 426 /**
 427  * This is the fallback shmem pread path, which allocates temporary storage
 428  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 429  * can copy out of the object's backing pages while holding the struct mutex
 430  * and not take page faults.
 431  */
 432 static int
 433 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 434                           struct drm_i915_gem_pread *args,
 435                           struct drm_file *file_priv)
 436 {
 437         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 438         struct mm_struct *mm = current->mm;
 439         struct page **user_pages;
 440         ssize_t remain;
 441         loff_t offset, pinned_pages, i;
 442         loff_t first_data_page, last_data_page, num_pages;
 443         int shmem_page_index, shmem_page_offset;
 444         int data_page_index,  data_page_offset;
 445         int page_length;
 446         int ret;
 447         uint64_t data_ptr = args->data_ptr;
 448         int do_bit17_swizzling;
 449
 450         remain = args->size;
 451
 452         /* Pin the user pages containing the data.  We can't fault while
 453          * holding the struct mutex, yet we want to hold it while
 454          * dereferencing the user data.
 455          */
 456         first_data_page = data_ptr / PAGE_SIZE;
 457         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 458         num_pages = last_data_page - first_data_page + 1;
 459
 460         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 461         if (user_pages == NULL)
 462                 return -ENOMEM;
 463
 464         mutex_unlock(&dev->struct_mutex);
 465         down_read(&mm->mmap_sem);
 466         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 467                                       num_pages, 1, 0, user_pages, NULL);
 468         up_read(&mm->mmap_sem);
 469         mutex_lock(&dev->struct_mutex);
 470         if (pinned_pages < num_pages) {
 471                 ret = -EFAULT;
 472                 goto out;
 473         }
 474
 475         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 476                                                         args->offset,
 477                                                         args->size);
 478         if (ret)
 479                 goto out;
 480
 481         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 482
 483         obj_priv = to_intel_bo(obj);
 484         offset = args->offset;
 485
 486         while (remain > 0) {
 487                 /* Operation in this page
 488                  *
 489                  * shmem_page_index = page number within shmem file
 490                  * shmem_page_offset = offset within page in shmem file
 491                  * data_page_index = page number in get_user_pages return
 492                  * data_page_offset = offset with data_page_index page.
 493                  * page_length = bytes to copy for this page
 494                  */
 495                 shmem_page_index = offset / PAGE_SIZE;
 496                 shmem_page_offset = offset & ~PAGE_MASK;
 497                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 498                 data_page_offset = data_ptr & ~PAGE_MASK;
 499
 500                 page_length = remain;
 501                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 502                         page_length = PAGE_SIZE - shmem_page_offset;
 503                 if ((data_page_offset + page_length) > PAGE_SIZE)
 504                         page_length = PAGE_SIZE - data_page_offset;
 505
 506                 if (do_bit17_swizzling) {
 507                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 508                                               shmem_page_offset,
 509                                               user_pages[data_page_index],
 510                                               data_page_offset,
 511                                               page_length,
 512                                               1);
 513                 } else {
 514                         slow_shmem_copy(user_pages[data_page_index],
 515                                         data_page_offset,
 516                                         obj_priv->pages[shmem_page_index],
 517                                         shmem_page_offset,
 518                                         page_length);
 519                 }
 520
 521                 remain -= page_length;
 522                 data_ptr += page_length;
 523                 offset += page_length;
 524         }
 525
 526 out:
 527         for (i = 0; i < pinned_pages; i++) {
 528                 SetPageDirty(user_pages[i]);
 529                 page_cache_release(user_pages[i]);
 530         }
 531         drm_free_large(user_pages);
 532
 533         return ret;
 534 }
 535
 536 /**
 537  * Reads data from the object referenced by handle.
 538  *
 539  * On error, the contents of *data are undefined.
 540  */
 541 int
 542 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 543                      struct drm_file *file_priv)
 544 {
 545         struct drm_i915_gem_pread *args = data;
 546         struct drm_gem_object *obj;
 547         struct drm_i915_gem_object *obj_priv;
 548         int ret = 0;
 549
 550         ret = i915_mutex_lock_interruptible(dev);
 551         if (ret)
 552                 return ret;
 553
 554         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 555         if (obj == NULL) {
 556                 ret = -ENOENT;
 557                 goto unlock;
 558         }
 559         obj_priv = to_intel_bo(obj);
 560
 561         /* Bounds check source.  */
 562         if (args->offset > obj->size || args->size > obj->size - args->offset) {
 563                 ret = -EINVAL;
 564                 goto out;
 565         }
 566
 567         if (args->size == 0)
 568                 goto out;
 569
 570         if (!access_ok(VERIFY_WRITE,
 571                        (char __user *)(uintptr_t)args->data_ptr,
 572                        args->size)) {
 573                 ret = -EFAULT;
 574                 goto out;
 575         }
 576
 577         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 578                                        args->size);
 579         if (ret) {
 580                 ret = -EFAULT;
 581                 goto out;
 582         }
 583
 584         ret = i915_gem_object_get_pages_or_evict(obj);
 585         if (ret)
 586                 goto out;
 587
 588         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 589                                                         args->offset,
 590                                                         args->size);
 591         if (ret)
 592                 goto out_put;
 593
 594         ret = -EFAULT;
 595         if (!i915_gem_object_needs_bit17_swizzle(obj))
 596                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 597         if (ret == -EFAULT)
 598                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 599
 600 out_put:
 601         i915_gem_object_put_pages(obj);
 602 out:
 603         drm_gem_object_unreference(obj);
 604 unlock:
 605         mutex_unlock(&dev->struct_mutex);
 606         return ret;
 607 }
 608
 609 /* This is the fast write path which cannot handle
 610  * page faults in the source data
 611  */
 612
 613 static inline int
 614 fast_user_write(struct io_mapping *mapping,
 615                 loff_t page_base, int page_offset,
 616                 char __user *user_data,
 617                 int length)
 618 {
 619         char *vaddr_atomic;
 620         unsigned long unwritten;
 621
 622         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
 623         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 624                                                       user_data, length);
 625         io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
 626         return unwritten;
 627 }
 628
 629 /* Here's the write path which can sleep for
 630  * page faults
 631  */
 632
 633 static inline void
 634 slow_kernel_write(struct io_mapping *mapping,
 635                   loff_t gtt_base, int gtt_offset,
 636                   struct page *user_page, int user_offset,
 637                   int length)
 638 {
 639         char __iomem *dst_vaddr;
 640         char *src_vaddr;
 641
 642         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 643         src_vaddr = kmap(user_page);
 644
 645         memcpy_toio(dst_vaddr + gtt_offset,
 646                     src_vaddr + user_offset,
 647                     length);
 648
 649         kunmap(user_page);
 650         io_mapping_unmap(dst_vaddr);
 651 }
 652
 653 static inline int
 654 fast_shmem_write(struct page **pages,
 655                  loff_t page_base, int page_offset,
 656                  char __user *data,
 657                  int length)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 663         ret = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 664         kunmap_atomic(vaddr, KM_USER0);
 665
 666         return ret;
 667 }
 668
 669 /**
 670  * This is the fast pwrite path, where we copy the data directly from the
 671  * user into the GTT, uncached.
 672  */
 673 static int
 674 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 675                          struct drm_i915_gem_pwrite *args,
 676                          struct drm_file *file_priv)
 677 {
 678         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 679         drm_i915_private_t *dev_priv = dev->dev_private;
 680         ssize_t remain;
 681         loff_t offset, page_base;
 682         char __user *user_data;
 683         int page_offset, page_length;
 684
 685         user_data = (char __user *) (uintptr_t) args->data_ptr;
 686         remain = args->size;
 687
 688         obj_priv = to_intel_bo(obj);
 689         offset = obj_priv->gtt_offset + args->offset;
 690
 691         while (remain > 0) {
 692                 /* Operation in this page
 693                  *
 694                  * page_base = page offset within aperture
 695                  * page_offset = offset within page
 696                  * page_length = bytes to copy for this page
 697                  */
 698                 page_base = (offset & ~(PAGE_SIZE-1));
 699                 page_offset = offset & (PAGE_SIZE-1);
 700                 page_length = remain;
 701                 if ((page_offset + remain) > PAGE_SIZE)
 702                         page_length = PAGE_SIZE - page_offset;
 703
 704                 /* If we get a fault while copying data, then (presumably) our
 705                  * source page isn't available.  Return the error and we'll
 706                  * retry in the slow path.
 707                  */
 708                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 709                                     page_offset, user_data, page_length))
 710
 711                         return -EFAULT;
 712
 713                 remain -= page_length;
 714                 user_data += page_length;
 715                 offset += page_length;
 716         }
 717
 718         return 0;
 719 }
 720
 721 /**
 722  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 723  * the memory and maps it using kmap_atomic for copying.
 724  *
 725  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 726  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 727  */
 728 static int
 729 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 730                          struct drm_i915_gem_pwrite *args,
 731                          struct drm_file *file_priv)
 732 {
 733         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 734         drm_i915_private_t *dev_priv = dev->dev_private;
 735         ssize_t remain;
 736         loff_t gtt_page_base, offset;
 737         loff_t first_data_page, last_data_page, num_pages;
 738         loff_t pinned_pages, i;
 739         struct page **user_pages;
 740         struct mm_struct *mm = current->mm;
 741         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 742         int ret;
 743         uint64_t data_ptr = args->data_ptr;
 744
 745         remain = args->size;
 746
 747         /* Pin the user pages containing the data.  We can't fault while
 748          * holding the struct mutex, and all of the pwrite implementations
 749          * want to hold it while dereferencing the user data.
 750          */
 751         first_data_page = data_ptr / PAGE_SIZE;
 752         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 753         num_pages = last_data_page - first_data_page + 1;
 754
 755         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 756         if (user_pages == NULL)
 757                 return -ENOMEM;
 758
 759         mutex_unlock(&dev->struct_mutex);
 760         down_read(&mm->mmap_sem);
 761         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 762                                       num_pages, 0, 0, user_pages, NULL);
 763         up_read(&mm->mmap_sem);
 764         mutex_lock(&dev->struct_mutex);
 765         if (pinned_pages < num_pages) {
 766                 ret = -EFAULT;
 767                 goto out_unpin_pages;
 768         }
 769
 770         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 771         if (ret)
 772                 goto out_unpin_pages;
 773
 774         obj_priv = to_intel_bo(obj);
 775         offset = obj_priv->gtt_offset + args->offset;
 776
 777         while (remain > 0) {
 778                 /* Operation in this page
 779                  *
 780                  * gtt_page_base = page offset within aperture
 781                  * gtt_page_offset = offset within page in aperture
 782                  * data_page_index = page number in get_user_pages return
 783                  * data_page_offset = offset with data_page_index page.
 784                  * page_length = bytes to copy for this page
 785                  */
 786                 gtt_page_base = offset & PAGE_MASK;
 787                 gtt_page_offset = offset & ~PAGE_MASK;
 788                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 789                 data_page_offset = data_ptr & ~PAGE_MASK;
 790
 791                 page_length = remain;
 792                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 793                         page_length = PAGE_SIZE - gtt_page_offset;
 794                 if ((data_page_offset + page_length) > PAGE_SIZE)
 795                         page_length = PAGE_SIZE - data_page_offset;
 796
 797                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 798                                   gtt_page_base, gtt_page_offset,
 799                                   user_pages[data_page_index],
 800                                   data_page_offset,
 801                                   page_length);
 802
 803                 remain -= page_length;
 804                 offset += page_length;
 805                 data_ptr += page_length;
 806         }
 807
 808 out_unpin_pages:
 809         for (i = 0; i < pinned_pages; i++)
 810                 page_cache_release(user_pages[i]);
 811         drm_free_large(user_pages);
 812
 813         return ret;
 814 }
 815
 816 /**
 817  * This is the fast shmem pwrite path, which attempts to directly
 818  * copy_from_user into the kmapped pages backing the object.
 819  */
 820 static int
 821 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 822                            struct drm_i915_gem_pwrite *args,
 823                            struct drm_file *file_priv)
 824 {
 825         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 826         ssize_t remain;
 827         loff_t offset, page_base;
 828         char __user *user_data;
 829         int page_offset, page_length;
 830
 831         user_data = (char __user *) (uintptr_t) args->data_ptr;
 832         remain = args->size;
 833
 834         obj_priv = to_intel_bo(obj);
 835         offset = args->offset;
 836         obj_priv->dirty = 1;
 837
 838         while (remain > 0) {
 839                 /* Operation in this page
 840                  *
 841                  * page_base = page offset within aperture
 842                  * page_offset = offset within page
 843                  * page_length = bytes to copy for this page
 844                  */
 845                 page_base = (offset & ~(PAGE_SIZE-1));
 846                 page_offset = offset & (PAGE_SIZE-1);
 847                 page_length = remain;
 848                 if ((page_offset + remain) > PAGE_SIZE)
 849                         page_length = PAGE_SIZE - page_offset;
 850
 851                 if (fast_shmem_write(obj_priv->pages,
 852                                        page_base, page_offset,
 853                                        user_data, page_length))
 854                         return -EFAULT;
 855
 856                 remain -= page_length;
 857                 user_data += page_length;
 858                 offset += page_length;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /**
 865  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 866  * the memory and maps it using kmap_atomic for copying.
 867  *
 868  * This avoids taking mmap_sem for faulting on the user's address while the
 869  * struct_mutex is held.
 870  */
 871 static int
 872 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 873                            struct drm_i915_gem_pwrite *args,
 874                            struct drm_file *file_priv)
 875 {
 876         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 877         struct mm_struct *mm = current->mm;
 878         struct page **user_pages;
 879         ssize_t remain;
 880         loff_t offset, pinned_pages, i;
 881         loff_t first_data_page, last_data_page, num_pages;
 882         int shmem_page_index, shmem_page_offset;
 883         int data_page_index,  data_page_offset;
 884         int page_length;
 885         int ret;
 886         uint64_t data_ptr = args->data_ptr;
 887         int do_bit17_swizzling;
 888
 889         remain = args->size;
 890
 891         /* Pin the user pages containing the data.  We can't fault while
 892          * holding the struct mutex, and all of the pwrite implementations
 893          * want to hold it while dereferencing the user data.
 894          */
 895         first_data_page = data_ptr / PAGE_SIZE;
 896         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 897         num_pages = last_data_page - first_data_page + 1;
 898
 899         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 900         if (user_pages == NULL)
 901                 return -ENOMEM;
 902
 903         mutex_unlock(&dev->struct_mutex);
 904         down_read(&mm->mmap_sem);
 905         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 906                                       num_pages, 0, 0, user_pages, NULL);
 907         up_read(&mm->mmap_sem);
 908         mutex_lock(&dev->struct_mutex);
 909         if (pinned_pages < num_pages) {
 910                 ret = -EFAULT;
 911                 goto out;
 912         }
 913
 914         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 915         if (ret)
 916                 goto out;
 917
 918         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 919
 920         obj_priv = to_intel_bo(obj);
 921         offset = args->offset;
 922         obj_priv->dirty = 1;
 923
 924         while (remain > 0) {
 925                 /* Operation in this page
 926                  *
 927                  * shmem_page_index = page number within shmem file
 928                  * shmem_page_offset = offset within page in shmem file
 929                  * data_page_index = page number in get_user_pages return
 930                  * data_page_offset = offset with data_page_index page.
 931                  * page_length = bytes to copy for this page
 932                  */
 933                 shmem_page_index = offset / PAGE_SIZE;
 934                 shmem_page_offset = offset & ~PAGE_MASK;
 935                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 936                 data_page_offset = data_ptr & ~PAGE_MASK;
 937
 938                 page_length = remain;
 939                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 940                         page_length = PAGE_SIZE - shmem_page_offset;
 941                 if ((data_page_offset + page_length) > PAGE_SIZE)
 942                         page_length = PAGE_SIZE - data_page_offset;
 943
 944                 if (do_bit17_swizzling) {
 945                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 946                                               shmem_page_offset,
 947                                               user_pages[data_page_index],
 948                                               data_page_offset,
 949                                               page_length,
 950                                               0);
 951                 } else {
 952                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 953                                         shmem_page_offset,
 954                                         user_pages[data_page_index],
 955                                         data_page_offset,
 956                                         page_length);
 957                 }
 958
 959                 remain -= page_length;
 960                 data_ptr += page_length;
 961                 offset += page_length;
 962         }
 963
 964 out:
 965         for (i = 0; i < pinned_pages; i++)
 966                 page_cache_release(user_pages[i]);
 967         drm_free_large(user_pages);
 968
 969         return ret;
 970 }
 971
 972 /**
 973  * Writes data to the object referenced by handle.
 974  *
 975  * On error, the contents of the buffer that were to be modified are undefined.
 976  */
 977 int
 978 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 979                       struct drm_file *file)
 980 {
 981         struct drm_i915_gem_pwrite *args = data;
 982         struct drm_gem_object *obj;
 983         struct drm_i915_gem_object *obj_priv;
 984         int ret = 0;
 985
 986         ret = i915_mutex_lock_interruptible(dev);
 987         if (ret)
 988                 return ret;
 989
 990         obj = drm_gem_object_lookup(dev, file, args->handle);
 991         if (obj == NULL) {
 992                 ret = -ENOENT;
 993                 goto unlock;
 994         }
 995         obj_priv = to_intel_bo(obj);
 996
 997
 998         /* Bounds check destination. */
 999         if (args->offset > obj->size || args->size > obj->size - args->offset) {
1000                 ret = -EINVAL;
1001                 goto out;
1002         }
1003
1004         if (args->size == 0)
1005                 goto out;
1006
1007         if (!access_ok(VERIFY_READ,
1008                        (char __user *)(uintptr_t)args->data_ptr,
1009                        args->size)) {
1010                 ret = -EFAULT;
1011                 goto out;
1012         }
1013
1014         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
1015                                       args->size);
1016         if (ret) {
1017                 ret = -EFAULT;
1018                 goto out;
1019         }
1020
1021         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1022          * it would end up going through the fenced access, and we'll get
1023          * different detiling behavior between reading and writing.
1024          * pread/pwrite currently are reading and writing from the CPU
1025          * perspective, requiring manual detiling by the client.
1026          */
1027         if (obj_priv->phys_obj)
1028                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1029         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1030                  obj_priv->gtt_space &&
1031                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
1032                 ret = i915_gem_object_pin(obj, 0);
1033                 if (ret)
1034                         goto out;
1035
1036                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1037                 if (ret)
1038                         goto out_unpin;
1039
1040                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1041                 if (ret == -EFAULT)
1042                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1043
1044 out_unpin:
1045                 i915_gem_object_unpin(obj);
1046         } else {
1047                 ret = i915_gem_object_get_pages_or_evict(obj);
1048                 if (ret)
1049                         goto out;
1050
1051                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1052                 if (ret)
1053                         goto out_put;
1054
1055                 ret = -EFAULT;
1056                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1057                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1058                 if (ret == -EFAULT)
1059                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1060
1061 out_put:
1062                 i915_gem_object_put_pages(obj);
1063         }
1064
1065 out:
1066         drm_gem_object_unreference(obj);
1067 unlock:
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space prepares to use an object with the CPU, either
1074  * through the mmap ioctl's mapping or a GTT mapping.
1075  */
1076 int
1077 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1078                           struct drm_file *file_priv)
1079 {
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         struct drm_i915_gem_set_domain *args = data;
1082         struct drm_gem_object *obj;
1083         struct drm_i915_gem_object *obj_priv;
1084         uint32_t read_domains = args->read_domains;
1085         uint32_t write_domain = args->write_domain;
1086         int ret;
1087
1088         if (!(dev->driver->driver_features & DRIVER_GEM))
1089                 return -ENODEV;
1090
1091         /* Only handle setting domains to types used by the CPU. */
1092         if (write_domain & I915_GEM_GPU_DOMAINS)
1093                 return -EINVAL;
1094
1095         if (read_domains & I915_GEM_GPU_DOMAINS)
1096                 return -EINVAL;
1097
1098         /* Having something in the write domain implies it's in the read
1099          * domain, and only that read domain.  Enforce that in the request.
1100          */
1101         if (write_domain != 0 && read_domains != write_domain)
1102                 return -EINVAL;
1103
1104         ret = i915_mutex_lock_interruptible(dev);
1105         if (ret)
1106                 return ret;
1107
1108         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1109         if (obj == NULL) {
1110                 ret = -ENOENT;
1111                 goto unlock;
1112         }
1113         obj_priv = to_intel_bo(obj);
1114
1115         intel_mark_busy(dev, obj);
1116
1117         if (read_domains & I915_GEM_DOMAIN_GTT) {
1118                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1119
1120                 /* Update the LRU on the fence for the CPU access that's
1121                  * about to occur.
1122                  */
1123                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1124                         struct drm_i915_fence_reg *reg =
1125                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1126                         list_move_tail(&reg->lru_list,
1127                                        &dev_priv->mm.fence_list);
1128                 }
1129
1130                 /* Silently promote "you're not bound, there was nothing to do"
1131                  * to success, since the client was just asking us to
1132                  * make sure everything was done.
1133                  */
1134                 if (ret == -EINVAL)
1135                         ret = 0;
1136         } else {
1137                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1138         }
1139
1140         /* Maintain LRU order of "inactive" objects */
1141         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1142                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1143
1144         drm_gem_object_unreference(obj);
1145 unlock:
1146         mutex_unlock(&dev->struct_mutex);
1147         return ret;
1148 }
1149
1150 /**
1151  * Called when user space has done writes to this buffer
1152  */
1153 int
1154 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1155                       struct drm_file *file_priv)
1156 {
1157         struct drm_i915_gem_sw_finish *args = data;
1158         struct drm_gem_object *obj;
1159         int ret = 0;
1160
1161         if (!(dev->driver->driver_features & DRIVER_GEM))
1162                 return -ENODEV;
1163
1164         ret = i915_mutex_lock_interruptible(dev);
1165         if (ret)
1166                 return ret;
1167
1168         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1169         if (obj == NULL) {
1170                 ret = -ENOENT;
1171                 goto unlock;
1172         }
1173
1174         /* Pinned buffers may be scanout, so flush the cache */
1175         if (to_intel_bo(obj)->pin_count)
1176                 i915_gem_object_flush_cpu_write_domain(obj);
1177
1178         drm_gem_object_unreference(obj);
1179 unlock:
1180         mutex_unlock(&dev->struct_mutex);
1181         return ret;
1182 }
1183
1184 /**
1185  * Maps the contents of an object, returning the address it is mapped
1186  * into.
1187  *
1188  * While the mapping holds a reference on the contents of the object, it doesn't
1189  * imply a ref on the object itself.
1190  */
1191 int
1192 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1193                    struct drm_file *file_priv)
1194 {
1195         struct drm_i915_gem_mmap *args = data;
1196         struct drm_gem_object *obj;
1197         loff_t offset;
1198         unsigned long addr;
1199
1200         if (!(dev->driver->driver_features & DRIVER_GEM))
1201                 return -ENODEV;
1202
1203         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1204         if (obj == NULL)
1205                 return -ENOENT;
1206
1207         offset = args->offset;
1208
1209         down_write(&current->mm->mmap_sem);
1210         addr = do_mmap(obj->filp, 0, args->size,
1211                        PROT_READ | PROT_WRITE, MAP_SHARED,
1212                        args->offset);
1213         up_write(&current->mm->mmap_sem);
1214         drm_gem_object_unreference_unlocked(obj);
1215         if (IS_ERR((void *)addr))
1216                 return addr;
1217
1218         args->addr_ptr = (uint64_t) addr;
1219
1220         return 0;
1221 }
1222
1223 /**
1224  * i915_gem_fault - fault a page into the GTT
1225  * vma: VMA in question
1226  * vmf: fault info
1227  *
1228  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1229  * from userspace.  The fault handler takes care of binding the object to
1230  * the GTT (if needed), allocating and programming a fence register (again,
1231  * only if needed based on whether the old reg is still valid or the object
1232  * is tiled) and inserting a new PTE into the faulting process.
1233  *
1234  * Note that the faulting process may involve evicting existing objects
1235  * from the GTT and/or fence registers to make room.  So performance may
1236  * suffer if the GTT working set is large or there are few fence registers
1237  * left.
1238  */
1239 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1240 {
1241         struct drm_gem_object *obj = vma->vm_private_data;
1242         struct drm_device *dev = obj->dev;
1243         drm_i915_private_t *dev_priv = dev->dev_private;
1244         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1245         pgoff_t page_offset;
1246         unsigned long pfn;
1247         int ret = 0;
1248         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1249
1250         /* We don't use vmf->pgoff since that has the fake offset */
1251         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1252                 PAGE_SHIFT;
1253
1254         /* Now bind it into the GTT if needed */
1255         mutex_lock(&dev->struct_mutex);
1256         if (!obj_priv->gtt_space) {
1257                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1258                 if (ret)
1259                         goto unlock;
1260
1261                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1262                 if (ret)
1263                         goto unlock;
1264         }
1265
1266         /* Need a new fence register? */
1267         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1268                 ret = i915_gem_object_get_fence_reg(obj, true);
1269                 if (ret)
1270                         goto unlock;
1271         }
1272
1273         if (i915_gem_object_is_inactive(obj_priv))
1274                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1275
1276         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1277                 page_offset;
1278
1279         /* Finally, remap it using the new GTT offset */
1280         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1281 unlock:
1282         mutex_unlock(&dev->struct_mutex);
1283
1284         switch (ret) {
1285         case 0:
1286         case -ERESTARTSYS:
1287                 return VM_FAULT_NOPAGE;
1288         case -ENOMEM:
1289         case -EAGAIN:
1290                 return VM_FAULT_OOM;
1291         default:
1292                 return VM_FAULT_SIGBUS;
1293         }
1294 }
1295
1296 /**
1297  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1298  * @obj: obj in question
1299  *
1300  * GEM memory mapping works by handing back to userspace a fake mmap offset
1301  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1302  * up the object based on the offset and sets up the various memory mapping
1303  * structures.
1304  *
1305  * This routine allocates and attaches a fake offset for @obj.
1306  */
1307 static int
1308 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_gem_mm *mm = dev->mm_private;
1312         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1313         struct drm_map_list *list;
1314         struct drm_local_map *map;
1315         int ret = 0;
1316
1317         /* Set the object up for mmap'ing */
1318         list = &obj->map_list;
1319         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1320         if (!list->map)
1321                 return -ENOMEM;
1322
1323         map = list->map;
1324         map->type = _DRM_GEM;
1325         map->size = obj->size;
1326         map->handle = obj;
1327
1328         /* Get a DRM GEM mmap offset allocated... */
1329         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1330                                                     obj->size / PAGE_SIZE, 0, 0);
1331         if (!list->file_offset_node) {
1332                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1333                 ret = -ENOSPC;
1334                 goto out_free_list;
1335         }
1336
1337         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1338                                                   obj->size / PAGE_SIZE, 0);
1339         if (!list->file_offset_node) {
1340                 ret = -ENOMEM;
1341                 goto out_free_list;
1342         }
1343
1344         list->hash.key = list->file_offset_node->start;
1345         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1346         if (ret) {
1347                 DRM_ERROR("failed to add to map hash\n");
1348                 goto out_free_mm;
1349         }
1350
1351         /* By now we should be all set, any drm_mmap request on the offset
1352          * below will get to our mmap & fault handler */
1353         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1354
1355         return 0;
1356
1357 out_free_mm:
1358         drm_mm_put_block(list->file_offset_node);
1359 out_free_list:
1360         kfree(list->map);
1361
1362         return ret;
1363 }
1364
1365 /**
1366  * i915_gem_release_mmap - remove physical page mappings
1367  * @obj: obj in question
1368  *
1369  * Preserve the reservation of the mmapping with the DRM core code, but
1370  * relinquish ownership of the pages back to the system.
1371  *
1372  * It is vital that we remove the page mapping if we have mapped a tiled
1373  * object through the GTT and then lose the fence register due to
1374  * resource pressure. Similarly if the object has been moved out of the
1375  * aperture, than pages mapped into userspace must be revoked. Removing the
1376  * mapping will then trigger a page fault on the next user access, allowing
1377  * fixup by i915_gem_fault().
1378  */
1379 void
1380 i915_gem_release_mmap(struct drm_gem_object *obj)
1381 {
1382         struct drm_device *dev = obj->dev;
1383         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1384
1385         if (dev->dev_mapping)
1386                 unmap_mapping_range(dev->dev_mapping,
1387                                     obj_priv->mmap_offset, obj->size, 1);
1388 }
1389
1390 static void
1391 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1392 {
1393         struct drm_device *dev = obj->dev;
1394         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1395         struct drm_gem_mm *mm = dev->mm_private;
1396         struct drm_map_list *list;
1397
1398         list = &obj->map_list;
1399         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1400
1401         if (list->file_offset_node) {
1402                 drm_mm_put_block(list->file_offset_node);
1403                 list->file_offset_node = NULL;
1404         }
1405
1406         if (list->map) {
1407                 kfree(list->map);
1408                 list->map = NULL;
1409         }
1410
1411         obj_priv->mmap_offset = 0;
1412 }
1413
1414 /**
1415  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1416  * @obj: object to check
1417  *
1418  * Return the required GTT alignment for an object, taking into account
1419  * potential fence register mapping if needed.
1420  */
1421 static uint32_t
1422 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1423 {
1424         struct drm_device *dev = obj->dev;
1425         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1426         int start, i;
1427
1428         /*
1429          * Minimum alignment is 4k (GTT page size), but might be greater
1430          * if a fence register is needed for the object.
1431          */
1432         if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1433                 return 4096;
1434
1435         /*
1436          * Previous chips need to be aligned to the size of the smallest
1437          * fence register that can contain the object.
1438          */
1439         if (INTEL_INFO(dev)->gen == 3)
1440                 start = 1024*1024;
1441         else
1442                 start = 512*1024;
1443
1444         for (i = start; i < obj->size; i <<= 1)
1445                 ;
1446
1447         return i;
1448 }
1449
1450 /**
1451  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1452  * @dev: DRM device
1453  * @data: GTT mapping ioctl data
1454  * @file_priv: GEM object info
1455  *
1456  * Simply returns the fake offset to userspace so it can mmap it.
1457  * The mmap call will end up in drm_gem_mmap(), which will set things
1458  * up so we can get faults in the handler above.
1459  *
1460  * The fault handler will take care of binding the object into the GTT
1461  * (since it may have been evicted to make room for something), allocating
1462  * a fence register, and mapping the appropriate aperture address into
1463  * userspace.
1464  */
1465 int
1466 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1467                         struct drm_file *file_priv)
1468 {
1469         struct drm_i915_gem_mmap_gtt *args = data;
1470         struct drm_gem_object *obj;
1471         struct drm_i915_gem_object *obj_priv;
1472         int ret;
1473
1474         if (!(dev->driver->driver_features & DRIVER_GEM))
1475                 return -ENODEV;
1476
1477         ret = i915_mutex_lock_interruptible(dev);
1478         if (ret)
1479                 return ret;
1480
1481         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1482         if (obj == NULL) {
1483                 ret = -ENOENT;
1484                 goto unlock;
1485         }
1486         obj_priv = to_intel_bo(obj);
1487
1488         if (obj_priv->madv != I915_MADV_WILLNEED) {
1489                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1490                 ret = -EINVAL;
1491                 goto out;
1492         }
1493
1494         if (!obj_priv->mmap_offset) {
1495                 ret = i915_gem_create_mmap_offset(obj);
1496                 if (ret)
1497                         goto out;
1498         }
1499
1500         args->offset = obj_priv->mmap_offset;
1501
1502         /*
1503          * Pull it into the GTT so that we have a page list (makes the
1504          * initial fault faster and any subsequent flushing possible).
1505          */
1506         if (!obj_priv->agp_mem) {
1507                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1508                 if (ret)
1509                         goto out;
1510         }
1511
1512 out:
1513         drm_gem_object_unreference(obj);
1514 unlock:
1515         mutex_unlock(&dev->struct_mutex);
1516         return ret;
1517 }
1518
1519 static void
1520 i915_gem_object_put_pages(struct drm_gem_object *obj)
1521 {
1522         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1523         int page_count = obj->size / PAGE_SIZE;
1524         int i;
1525
1526         BUG_ON(obj_priv->pages_refcount == 0);
1527         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1528
1529         if (--obj_priv->pages_refcount != 0)
1530                 return;
1531
1532         if (obj_priv->tiling_mode != I915_TILING_NONE)
1533                 i915_gem_object_save_bit_17_swizzle(obj);
1534
1535         if (obj_priv->madv == I915_MADV_DONTNEED)
1536                 obj_priv->dirty = 0;
1537
1538         for (i = 0; i < page_count; i++) {
1539                 if (obj_priv->dirty)
1540                         set_page_dirty(obj_priv->pages[i]);
1541
1542                 if (obj_priv->madv == I915_MADV_WILLNEED)
1543                         mark_page_accessed(obj_priv->pages[i]);
1544
1545                 page_cache_release(obj_priv->pages[i]);
1546         }
1547         obj_priv->dirty = 0;
1548
1549         drm_free_large(obj_priv->pages);
1550         obj_priv->pages = NULL;
1551 }
1552
1553 static uint32_t
1554 i915_gem_next_request_seqno(struct drm_device *dev,
1555                             struct intel_ring_buffer *ring)
1556 {
1557         drm_i915_private_t *dev_priv = dev->dev_private;
1558
1559         ring->outstanding_lazy_request = true;
1560         return dev_priv->next_seqno;
1561 }
1562
1563 static void
1564 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1565                                struct intel_ring_buffer *ring)
1566 {
1567         struct drm_device *dev = obj->dev;
1568         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1569         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1570
1571         BUG_ON(ring == NULL);
1572         obj_priv->ring = ring;
1573
1574         /* Add a reference if we're newly entering the active list. */
1575         if (!obj_priv->active) {
1576                 drm_gem_object_reference(obj);
1577                 obj_priv->active = 1;
1578         }
1579
1580         /* Move from whatever list we were on to the tail of execution. */
1581         list_move_tail(&obj_priv->list, &ring->active_list);
1582         obj_priv->last_rendering_seqno = seqno;
1583 }
1584
1585 static void
1586 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1587 {
1588         struct drm_device *dev = obj->dev;
1589         drm_i915_private_t *dev_priv = dev->dev_private;
1590         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1591
1592         BUG_ON(!obj_priv->active);
1593         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1594         obj_priv->last_rendering_seqno = 0;
1595 }
1596
1597 /* Immediately discard the backing storage */
1598 static void
1599 i915_gem_object_truncate(struct drm_gem_object *obj)
1600 {
1601         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1602         struct inode *inode;
1603
1604         /* Our goal here is to return as much of the memory as
1605          * is possible back to the system as we are called from OOM.
1606          * To do this we must instruct the shmfs to drop all of its
1607          * backing pages, *now*. Here we mirror the actions taken
1608          * when by shmem_delete_inode() to release the backing store.
1609          */
1610         inode = obj->filp->f_path.dentry->d_inode;
1611         truncate_inode_pages(inode->i_mapping, 0);
1612         if (inode->i_op->truncate_range)
1613                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1614
1615         obj_priv->madv = __I915_MADV_PURGED;
1616 }
1617
1618 static inline int
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1620 {
1621         return obj_priv->madv == I915_MADV_DONTNEED;
1622 }
1623
1624 static void
1625 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1626 {
1627         struct drm_device *dev = obj->dev;
1628         drm_i915_private_t *dev_priv = dev->dev_private;
1629         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1630
1631         if (obj_priv->pin_count != 0)
1632                 list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list);
1633         else
1634                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1635
1636         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1637
1638         obj_priv->last_rendering_seqno = 0;
1639         obj_priv->ring = NULL;
1640         if (obj_priv->active) {
1641                 obj_priv->active = 0;
1642                 drm_gem_object_unreference(obj);
1643         }
1644         WARN_ON(i915_verify_lists(dev));
1645 }
1646
1647 static void
1648 i915_gem_process_flushing_list(struct drm_device *dev,
1649                                uint32_t flush_domains,
1650                                struct intel_ring_buffer *ring)
1651 {
1652         drm_i915_private_t *dev_priv = dev->dev_private;
1653         struct drm_i915_gem_object *obj_priv, *next;
1654
1655         list_for_each_entry_safe(obj_priv, next,
1656                                  &dev_priv->mm.gpu_write_list,
1657                                  gpu_write_list) {
1658                 struct drm_gem_object *obj = &obj_priv->base;
1659
1660                 if (obj->write_domain & flush_domains &&
1661                     obj_priv->ring == ring) {
1662                         uint32_t old_write_domain = obj->write_domain;
1663
1664                         obj->write_domain = 0;
1665                         list_del_init(&obj_priv->gpu_write_list);
1666                         i915_gem_object_move_to_active(obj, ring);
1667
1668                         /* update the fence lru list */
1669                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1670                                 struct drm_i915_fence_reg *reg =
1671                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1672                                 list_move_tail(&reg->lru_list,
1673                                                 &dev_priv->mm.fence_list);
1674                         }
1675
1676                         trace_i915_gem_object_change_domain(obj,
1677                                                             obj->read_domains,
1678                                                             old_write_domain);
1679                 }
1680         }
1681 }
1682
1683 uint32_t
1684 i915_add_request(struct drm_device *dev,
1685                  struct drm_file *file,
1686                  struct drm_i915_gem_request *request,
1687                  struct intel_ring_buffer *ring)
1688 {
1689         drm_i915_private_t *dev_priv = dev->dev_private;
1690         struct drm_i915_file_private *file_priv = NULL;
1691         uint32_t seqno;
1692         int was_empty;
1693
1694         if (file != NULL)
1695                 file_priv = file->driver_priv;
1696
1697         if (request == NULL) {
1698                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1699                 if (request == NULL)
1700                         return 0;
1701         }
1702
1703         seqno = ring->add_request(dev, ring, 0);
1704         ring->outstanding_lazy_request = false;
1705
1706         request->seqno = seqno;
1707         request->ring = ring;
1708         request->emitted_jiffies = jiffies;
1709         was_empty = list_empty(&ring->request_list);
1710         list_add_tail(&request->list, &ring->request_list);
1711
1712         if (file_priv) {
1713                 spin_lock(&file_priv->mm.lock);
1714                 request->file_priv = file_priv;
1715                 list_add_tail(&request->client_list,
1716                               &file_priv->mm.request_list);
1717                 spin_unlock(&file_priv->mm.lock);
1718         }
1719
1720         if (!dev_priv->mm.suspended) {
1721                 mod_timer(&dev_priv->hangcheck_timer,
1722                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1723                 if (was_empty)
1724                         queue_delayed_work(dev_priv->wq,
1725                                            &dev_priv->mm.retire_work, HZ);
1726         }
1727         return seqno;
1728 }
1729
1730 /**
1731  * Command execution barrier
1732  *
1733  * Ensures that all commands in the ring are finished
1734  * before signalling the CPU
1735  */
1736 static void
1737 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1738 {
1739         uint32_t flush_domains = 0;
1740
1741         /* The sampler always gets flushed on i965 (sigh) */
1742         if (INTEL_INFO(dev)->gen >= 4)
1743                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1744
1745         ring->flush(dev, ring,
1746                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1747 }
1748
1749 static inline void
1750 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1751 {
1752         struct drm_i915_file_private *file_priv = request->file_priv;
1753
1754         if (!file_priv)
1755                 return;
1756
1757         spin_lock(&file_priv->mm.lock);
1758         list_del(&request->client_list);
1759         request->file_priv = NULL;
1760         spin_unlock(&file_priv->mm.lock);
1761 }
1762
1763 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1764                                       struct intel_ring_buffer *ring)
1765 {
1766         while (!list_empty(&ring->request_list)) {
1767                 struct drm_i915_gem_request *request;
1768
1769                 request = list_first_entry(&ring->request_list,
1770                                            struct drm_i915_gem_request,
1771                                            list);
1772
1773                 list_del(&request->list);
1774                 i915_gem_request_remove_from_client(request);
1775                 kfree(request);
1776         }
1777
1778         while (!list_empty(&ring->active_list)) {
1779                 struct drm_i915_gem_object *obj_priv;
1780
1781                 obj_priv = list_first_entry(&ring->active_list,
1782                                             struct drm_i915_gem_object,
1783                                             list);
1784
1785                 obj_priv->base.write_domain = 0;
1786                 list_del_init(&obj_priv->gpu_write_list);
1787                 i915_gem_object_move_to_inactive(&obj_priv->base);
1788         }
1789 }
1790
1791 void i915_gem_reset(struct drm_device *dev)
1792 {
1793         struct drm_i915_private *dev_priv = dev->dev_private;
1794         struct drm_i915_gem_object *obj_priv;
1795         int i;
1796
1797         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1798         if (HAS_BSD(dev))
1799                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1800
1801         /* Remove anything from the flushing lists. The GPU cache is likely
1802          * to be lost on reset along with the data, so simply move the
1803          * lost bo to the inactive list.
1804          */
1805         while (!list_empty(&dev_priv->mm.flushing_list)) {
1806                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1807                                             struct drm_i915_gem_object,
1808                                             list);
1809
1810                 obj_priv->base.write_domain = 0;
1811                 list_del_init(&obj_priv->gpu_write_list);
1812                 i915_gem_object_move_to_inactive(&obj_priv->base);
1813         }
1814
1815         /* Move everything out of the GPU domains to ensure we do any
1816          * necessary invalidation upon reuse.
1817          */
1818         list_for_each_entry(obj_priv,
1819                             &dev_priv->mm.inactive_list,
1820                             list)
1821         {
1822                 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1823         }
1824
1825         /* The fence registers are invalidated so clear them out */
1826         for (i = 0; i < 16; i++) {
1827                 struct drm_i915_fence_reg *reg;
1828
1829                 reg = &dev_priv->fence_regs[i];
1830                 if (!reg->obj)
1831                         continue;
1832
1833                 i915_gem_clear_fence_reg(reg->obj);
1834         }
1835 }
1836
1837 /**
1838  * This function clears the request list as sequence numbers are passed.
1839  */
1840 static void
1841 i915_gem_retire_requests_ring(struct drm_device *dev,
1842                               struct intel_ring_buffer *ring)
1843 {
1844         drm_i915_private_t *dev_priv = dev->dev_private;
1845         uint32_t seqno;
1846
1847         if (!ring->status_page.page_addr ||
1848             list_empty(&ring->request_list))
1849                 return;
1850
1851         WARN_ON(i915_verify_lists(dev));
1852
1853         seqno = ring->get_seqno(dev, ring);
1854         while (!list_empty(&ring->request_list)) {
1855                 struct drm_i915_gem_request *request;
1856
1857                 request = list_first_entry(&ring->request_list,
1858                                            struct drm_i915_gem_request,
1859                                            list);
1860
1861                 if (!i915_seqno_passed(seqno, request->seqno))
1862                         break;
1863
1864                 trace_i915_gem_request_retire(dev, request->seqno);
1865
1866                 list_del(&request->list);
1867                 i915_gem_request_remove_from_client(request);
1868                 kfree(request);
1869         }
1870
1871         /* Move any buffers on the active list that are no longer referenced
1872          * by the ringbuffer to the flushing/inactive lists as appropriate.
1873          */
1874         while (!list_empty(&ring->active_list)) {
1875                 struct drm_gem_object *obj;
1876                 struct drm_i915_gem_object *obj_priv;
1877
1878                 obj_priv = list_first_entry(&ring->active_list,
1879                                             struct drm_i915_gem_object,
1880                                             list);
1881
1882                 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1883                         break;
1884
1885                 obj = &obj_priv->base;
1886                 if (obj->write_domain != 0)
1887                         i915_gem_object_move_to_flushing(obj);
1888                 else
1889                         i915_gem_object_move_to_inactive(obj);
1890         }
1891
1892         if (unlikely (dev_priv->trace_irq_seqno &&
1893                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1894                 ring->user_irq_put(dev, ring);
1895                 dev_priv->trace_irq_seqno = 0;
1896         }
1897
1898         WARN_ON(i915_verify_lists(dev));
1899 }
1900
1901 void
1902 i915_gem_retire_requests(struct drm_device *dev)
1903 {
1904         drm_i915_private_t *dev_priv = dev->dev_private;
1905
1906         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1907             struct drm_i915_gem_object *obj_priv, *tmp;
1908
1909             /* We must be careful that during unbind() we do not
1910              * accidentally infinitely recurse into retire requests.
1911              * Currently:
1912              *   retire -> free -> unbind -> wait -> retire_ring
1913              */
1914             list_for_each_entry_safe(obj_priv, tmp,
1915                                      &dev_priv->mm.deferred_free_list,
1916                                      list)
1917                     i915_gem_free_object_tail(&obj_priv->base);
1918         }
1919
1920         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1921         if (HAS_BSD(dev))
1922                 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1923 }
1924
1925 static void
1926 i915_gem_retire_work_handler(struct work_struct *work)
1927 {
1928         drm_i915_private_t *dev_priv;
1929         struct drm_device *dev;
1930
1931         dev_priv = container_of(work, drm_i915_private_t,
1932                                 mm.retire_work.work);
1933         dev = dev_priv->dev;
1934
1935         /* Come back later if the device is busy... */
1936         if (!mutex_trylock(&dev->struct_mutex)) {
1937                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1938                 return;
1939         }
1940
1941         i915_gem_retire_requests(dev);
1942
1943         if (!dev_priv->mm.suspended &&
1944                 (!list_empty(&dev_priv->render_ring.request_list) ||
1945                         (HAS_BSD(dev) &&
1946                          !list_empty(&dev_priv->bsd_ring.request_list))))
1947                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1948         mutex_unlock(&dev->struct_mutex);
1949 }
1950
1951 int
1952 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1953                      bool interruptible, struct intel_ring_buffer *ring)
1954 {
1955         drm_i915_private_t *dev_priv = dev->dev_private;
1956         u32 ier;
1957         int ret = 0;
1958
1959         BUG_ON(seqno == 0);
1960
1961         if (atomic_read(&dev_priv->mm.wedged))
1962                 return -EAGAIN;
1963
1964         if (ring->outstanding_lazy_request) {
1965                 seqno = i915_add_request(dev, NULL, NULL, ring);
1966                 if (seqno == 0)
1967                         return -ENOMEM;
1968         }
1969         BUG_ON(seqno == dev_priv->next_seqno);
1970
1971         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
1972                 if (HAS_PCH_SPLIT(dev))
1973                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1974                 else
1975                         ier = I915_READ(IER);
1976                 if (!ier) {
1977                         DRM_ERROR("something (likely vbetool) disabled "
1978                                   "interrupts, re-enabling\n");
1979                         i915_driver_irq_preinstall(dev);
1980                         i915_driver_irq_postinstall(dev);
1981                 }
1982
1983                 trace_i915_gem_request_wait_begin(dev, seqno);
1984
1985                 ring->waiting_gem_seqno = seqno;
1986                 ring->user_irq_get(dev, ring);
1987                 if (interruptible)
1988                         ret = wait_event_interruptible(ring->irq_queue,
1989                                 i915_seqno_passed(
1990                                         ring->get_seqno(dev, ring), seqno)
1991                                 || atomic_read(&dev_priv->mm.wedged));
1992                 else
1993                         wait_event(ring->irq_queue,
1994                                 i915_seqno_passed(
1995                                         ring->get_seqno(dev, ring), seqno)
1996                                 || atomic_read(&dev_priv->mm.wedged));
1997
1998                 ring->user_irq_put(dev, ring);
1999                 ring->waiting_gem_seqno = 0;
2000
2001                 trace_i915_gem_request_wait_end(dev, seqno);
2002         }
2003         if (atomic_read(&dev_priv->mm.wedged))
2004                 ret = -EAGAIN;
2005
2006         if (ret && ret != -ERESTARTSYS)
2007                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2008                           __func__, ret, seqno, ring->get_seqno(dev, ring),
2009                           dev_priv->next_seqno);
2010
2011         /* Directly dispatch request retiring.  While we have the work queue
2012          * to handle this, the waiter on a request often wants an associated
2013          * buffer to have made it to the inactive list, and we would need
2014          * a separate wait queue to handle that.
2015          */
2016         if (ret == 0)
2017                 i915_gem_retire_requests_ring(dev, ring);
2018
2019         return ret;
2020 }
2021
2022 /**
2023  * Waits for a sequence number to be signaled, and cleans up the
2024  * request and object lists appropriately for that event.
2025  */
2026 static int
2027 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2028                   struct intel_ring_buffer *ring)
2029 {
2030         return i915_do_wait_request(dev, seqno, 1, ring);
2031 }
2032
2033 static void
2034 i915_gem_flush_ring(struct drm_device *dev,
2035                     struct drm_file *file_priv,
2036                     struct intel_ring_buffer *ring,
2037                     uint32_t invalidate_domains,
2038                     uint32_t flush_domains)
2039 {
2040         ring->flush(dev, ring, invalidate_domains, flush_domains);
2041         i915_gem_process_flushing_list(dev, flush_domains, ring);
2042 }
2043
2044 static void
2045 i915_gem_flush(struct drm_device *dev,
2046                struct drm_file *file_priv,
2047                uint32_t invalidate_domains,
2048                uint32_t flush_domains,
2049                uint32_t flush_rings)
2050 {
2051         drm_i915_private_t *dev_priv = dev->dev_private;
2052
2053         if (flush_domains & I915_GEM_DOMAIN_CPU)
2054                 drm_agp_chipset_flush(dev);
2055
2056         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2057                 if (flush_rings & RING_RENDER)
2058                         i915_gem_flush_ring(dev, file_priv,
2059                                             &dev_priv->render_ring,
2060                                             invalidate_domains, flush_domains);
2061                 if (flush_rings & RING_BSD)
2062                         i915_gem_flush_ring(dev, file_priv,
2063                                             &dev_priv->bsd_ring,
2064                                             invalidate_domains, flush_domains);
2065         }
2066 }
2067
2068 /**
2069  * Ensures that all rendering to the object has completed and the object is
2070  * safe to unbind from the GTT or access from the CPU.
2071  */
2072 static int
2073 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2074                                bool interruptible)
2075 {
2076         struct drm_device *dev = obj->dev;
2077         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2078         int ret;
2079
2080         /* This function only exists to support waiting for existing rendering,
2081          * not for emitting required flushes.
2082          */
2083         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2084
2085         /* If there is rendering queued on the buffer being evicted, wait for
2086          * it.
2087          */
2088         if (obj_priv->active) {
2089                 ret = i915_do_wait_request(dev,
2090                                            obj_priv->last_rendering_seqno,
2091                                            interruptible,
2092                                            obj_priv->ring);
2093                 if (ret)
2094                         return ret;
2095         }
2096
2097         return 0;
2098 }
2099
2100 /**
2101  * Unbinds an object from the GTT aperture.
2102  */
2103 int
2104 i915_gem_object_unbind(struct drm_gem_object *obj)
2105 {
2106         struct drm_device *dev = obj->dev;
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2109         int ret = 0;
2110
2111         if (obj_priv->gtt_space == NULL)
2112                 return 0;
2113
2114         if (obj_priv->pin_count != 0) {
2115                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2116                 return -EINVAL;
2117         }
2118
2119         /* blow away mappings if mapped through GTT */
2120         i915_gem_release_mmap(obj);
2121
2122         /* Move the object to the CPU domain to ensure that
2123          * any possible CPU writes while it's not in the GTT
2124          * are flushed when we go to remap it. This will
2125          * also ensure that all pending GPU writes are finished
2126          * before we unbind.
2127          */
2128         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2129         if (ret == -ERESTARTSYS)
2130                 return ret;
2131         /* Continue on if we fail due to EIO, the GPU is hung so we
2132          * should be safe and we need to cleanup or else we might
2133          * cause memory corruption through use-after-free.
2134          */
2135         if (ret) {
2136                 i915_gem_clflush_object(obj);
2137                 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2138         }
2139
2140         /* release the fence reg _after_ flushing */
2141         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2142                 i915_gem_clear_fence_reg(obj);
2143
2144         drm_unbind_agp(obj_priv->agp_mem);
2145         drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2146
2147         i915_gem_object_put_pages(obj);
2148         BUG_ON(obj_priv->pages_refcount);
2149
2150         i915_gem_info_remove_gtt(dev_priv, obj->size);
2151         list_del_init(&obj_priv->list);
2152
2153         drm_mm_put_block(obj_priv->gtt_space);
2154         obj_priv->gtt_space = NULL;
2155         obj_priv->gtt_offset = 0;
2156
2157         if (i915_gem_object_is_purgeable(obj_priv))
2158                 i915_gem_object_truncate(obj);
2159
2160         trace_i915_gem_object_unbind(obj);
2161
2162         return ret;
2163 }
2164
2165 static int i915_ring_idle(struct drm_device *dev,
2166                           struct intel_ring_buffer *ring)
2167 {
2168         i915_gem_flush_ring(dev, NULL, ring,
2169                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2170         return i915_wait_request(dev,
2171                                  i915_gem_next_request_seqno(dev, ring),
2172                                  ring);
2173 }
2174
2175 int
2176 i915_gpu_idle(struct drm_device *dev)
2177 {
2178         drm_i915_private_t *dev_priv = dev->dev_private;
2179         bool lists_empty;
2180         int ret;
2181
2182         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2183                        list_empty(&dev_priv->render_ring.active_list) &&
2184                        (!HAS_BSD(dev) ||
2185                         list_empty(&dev_priv->bsd_ring.active_list)));
2186         if (lists_empty)
2187                 return 0;
2188
2189         /* Flush everything onto the inactive list. */
2190         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2191         if (ret)
2192                 return ret;
2193
2194         if (HAS_BSD(dev)) {
2195                 ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2196                 if (ret)
2197                         return ret;
2198         }
2199
2200         return 0;
2201 }
2202
2203 static int
2204 i915_gem_object_get_pages(struct drm_gem_object *obj,
2205                           gfp_t gfpmask)
2206 {
2207         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2208         int page_count, i;
2209         struct address_space *mapping;
2210         struct inode *inode;
2211         struct page *page;
2212
2213         BUG_ON(obj_priv->pages_refcount
2214                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2215
2216         if (obj_priv->pages_refcount++ != 0)
2217                 return 0;
2218
2219         /* Get the list of pages out of our struct file.  They'll be pinned
2220          * at this point until we release them.
2221          */
2222         page_count = obj->size / PAGE_SIZE;
2223         BUG_ON(obj_priv->pages != NULL);
2224         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2225         if (obj_priv->pages == NULL) {
2226                 obj_priv->pages_refcount--;
2227                 return -ENOMEM;
2228         }
2229
2230         inode = obj->filp->f_path.dentry->d_inode;
2231         mapping = inode->i_mapping;
2232         for (i = 0; i < page_count; i++) {
2233                 page = read_cache_page_gfp(mapping, i,
2234                                            GFP_HIGHUSER |
2235                                            __GFP_COLD |
2236                                            __GFP_RECLAIMABLE |
2237                                            gfpmask);
2238                 if (IS_ERR(page))
2239                         goto err_pages;
2240
2241                 obj_priv->pages[i] = page;
2242         }
2243
2244         if (obj_priv->tiling_mode != I915_TILING_NONE)
2245                 i915_gem_object_do_bit_17_swizzle(obj);
2246
2247         return 0;
2248
2249 err_pages:
2250         while (i--)
2251                 page_cache_release(obj_priv->pages[i]);
2252
2253         drm_free_large(obj_priv->pages);
2254         obj_priv->pages = NULL;
2255         obj_priv->pages_refcount--;
2256         return PTR_ERR(page);
2257 }
2258
2259 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2260 {
2261         struct drm_gem_object *obj = reg->obj;
2262         struct drm_device *dev = obj->dev;
2263         drm_i915_private_t *dev_priv = dev->dev_private;
2264         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2265         int regnum = obj_priv->fence_reg;
2266         uint64_t val;
2267
2268         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2269                     0xfffff000) << 32;
2270         val |= obj_priv->gtt_offset & 0xfffff000;
2271         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2272                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2273
2274         if (obj_priv->tiling_mode == I915_TILING_Y)
2275                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2276         val |= I965_FENCE_REG_VALID;
2277
2278         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2279 }
2280
2281 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2282 {
2283         struct drm_gem_object *obj = reg->obj;
2284         struct drm_device *dev = obj->dev;
2285         drm_i915_private_t *dev_priv = dev->dev_private;
2286         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2287         int regnum = obj_priv->fence_reg;
2288         uint64_t val;
2289
2290         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2291                     0xfffff000) << 32;
2292         val |= obj_priv->gtt_offset & 0xfffff000;
2293         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2294         if (obj_priv->tiling_mode == I915_TILING_Y)
2295                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2296         val |= I965_FENCE_REG_VALID;
2297
2298         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2299 }
2300
2301 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2302 {
2303         struct drm_gem_object *obj = reg->obj;
2304         struct drm_device *dev = obj->dev;
2305         drm_i915_private_t *dev_priv = dev->dev_private;
2306         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2307         int regnum = obj_priv->fence_reg;
2308         int tile_width;
2309         uint32_t fence_reg, val;
2310         uint32_t pitch_val;
2311
2312         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2313             (obj_priv->gtt_offset & (obj->size - 1))) {
2314                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2315                      __func__, obj_priv->gtt_offset, obj->size);
2316                 return;
2317         }
2318
2319         if (obj_priv->tiling_mode == I915_TILING_Y &&
2320             HAS_128_BYTE_Y_TILING(dev))
2321                 tile_width = 128;
2322         else
2323                 tile_width = 512;
2324
2325         /* Note: pitch better be a power of two tile widths */
2326         pitch_val = obj_priv->stride / tile_width;
2327         pitch_val = ffs(pitch_val) - 1;
2328
2329         if (obj_priv->tiling_mode == I915_TILING_Y &&
2330             HAS_128_BYTE_Y_TILING(dev))
2331                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2332         else
2333                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2334
2335         val = obj_priv->gtt_offset;
2336         if (obj_priv->tiling_mode == I915_TILING_Y)
2337                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2338         val |= I915_FENCE_SIZE_BITS(obj->size);
2339         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2340         val |= I830_FENCE_REG_VALID;
2341
2342         if (regnum < 8)
2343                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2344         else
2345                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2346         I915_WRITE(fence_reg, val);
2347 }
2348
2349 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2350 {
2351         struct drm_gem_object *obj = reg->obj;
2352         struct drm_device *dev = obj->dev;
2353         drm_i915_private_t *dev_priv = dev->dev_private;
2354         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2355         int regnum = obj_priv->fence_reg;
2356         uint32_t val;
2357         uint32_t pitch_val;
2358         uint32_t fence_size_bits;
2359
2360         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2361             (obj_priv->gtt_offset & (obj->size - 1))) {
2362                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2363                      __func__, obj_priv->gtt_offset);
2364                 return;
2365         }
2366
2367         pitch_val = obj_priv->stride / 128;
2368         pitch_val = ffs(pitch_val) - 1;
2369         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2370
2371         val = obj_priv->gtt_offset;
2372         if (obj_priv->tiling_mode == I915_TILING_Y)
2373                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2374         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2375         WARN_ON(fence_size_bits & ~0x00000f00);
2376         val |= fence_size_bits;
2377         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2378         val |= I830_FENCE_REG_VALID;
2379
2380         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2381 }
2382
2383 static int i915_find_fence_reg(struct drm_device *dev,
2384                                bool interruptible)
2385 {
2386         struct drm_i915_fence_reg *reg = NULL;
2387         struct drm_i915_gem_object *obj_priv = NULL;
2388         struct drm_i915_private *dev_priv = dev->dev_private;
2389         struct drm_gem_object *obj = NULL;
2390         int i, avail, ret;
2391
2392         /* First try to find a free reg */
2393         avail = 0;
2394         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2395                 reg = &dev_priv->fence_regs[i];
2396                 if (!reg->obj)
2397                         return i;
2398
2399                 obj_priv = to_intel_bo(reg->obj);
2400                 if (!obj_priv->pin_count)
2401                     avail++;
2402         }
2403
2404         if (avail == 0)
2405                 return -ENOSPC;
2406
2407         /* None available, try to steal one or wait for a user to finish */
2408         i = I915_FENCE_REG_NONE;
2409         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2410                             lru_list) {
2411                 obj = reg->obj;
2412                 obj_priv = to_intel_bo(obj);
2413
2414                 if (obj_priv->pin_count)
2415                         continue;
2416
2417                 /* found one! */
2418                 i = obj_priv->fence_reg;
2419                 break;
2420         }
2421
2422         BUG_ON(i == I915_FENCE_REG_NONE);
2423
2424         /* We only have a reference on obj from the active list. put_fence_reg
2425          * might drop that one, causing a use-after-free in it. So hold a
2426          * private reference to obj like the other callers of put_fence_reg
2427          * (set_tiling ioctl) do. */
2428         drm_gem_object_reference(obj);
2429         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2430         drm_gem_object_unreference(obj);
2431         if (ret != 0)
2432                 return ret;
2433
2434         return i;
2435 }
2436
2437 /**
2438  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2439  * @obj: object to map through a fence reg
2440  *
2441  * When mapping objects through the GTT, userspace wants to be able to write
2442  * to them without having to worry about swizzling if the object is tiled.
2443  *
2444  * This function walks the fence regs looking for a free one for @obj,
2445  * stealing one if it can't find any.
2446  *
2447  * It then sets up the reg based on the object's properties: address, pitch
2448  * and tiling format.
2449  */
2450 int
2451 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2452                               bool interruptible)
2453 {
2454         struct drm_device *dev = obj->dev;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2457         struct drm_i915_fence_reg *reg = NULL;
2458         int ret;
2459
2460         /* Just update our place in the LRU if our fence is getting used. */
2461         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2462                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2463                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2464                 return 0;
2465         }
2466
2467         switch (obj_priv->tiling_mode) {
2468         case I915_TILING_NONE:
2469                 WARN(1, "allocating a fence for non-tiled object?\n");
2470                 break;
2471         case I915_TILING_X:
2472                 if (!obj_priv->stride)
2473                         return -EINVAL;
2474                 WARN((obj_priv->stride & (512 - 1)),
2475                      "object 0x%08x is X tiled but has non-512B pitch\n",
2476                      obj_priv->gtt_offset);
2477                 break;
2478         case I915_TILING_Y:
2479                 if (!obj_priv->stride)
2480                         return -EINVAL;
2481                 WARN((obj_priv->stride & (128 - 1)),
2482                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2483                      obj_priv->gtt_offset);
2484                 break;
2485         }
2486
2487         ret = i915_find_fence_reg(dev, interruptible);
2488         if (ret < 0)
2489                 return ret;
2490
2491         obj_priv->fence_reg = ret;
2492         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2493         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2494
2495         reg->obj = obj;
2496
2497         switch (INTEL_INFO(dev)->gen) {
2498         case 6:
2499                 sandybridge_write_fence_reg(reg);
2500                 break;
2501         case 5:
2502         case 4:
2503                 i965_write_fence_reg(reg);
2504                 break;
2505         case 3:
2506                 i915_write_fence_reg(reg);
2507                 break;
2508         case 2:
2509                 i830_write_fence_reg(reg);
2510                 break;
2511         }
2512
2513         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2514                         obj_priv->tiling_mode);
2515
2516         return 0;
2517 }
2518
2519 /**
2520  * i915_gem_clear_fence_reg - clear out fence register info
2521  * @obj: object to clear
2522  *
2523  * Zeroes out the fence register itself and clears out the associated
2524  * data structures in dev_priv and obj_priv.
2525  */
2526 static void
2527 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2528 {
2529         struct drm_device *dev = obj->dev;
2530         drm_i915_private_t *dev_priv = dev->dev_private;
2531         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2532         struct drm_i915_fence_reg *reg =
2533                 &dev_priv->fence_regs[obj_priv->fence_reg];
2534         uint32_t fence_reg;
2535
2536         switch (INTEL_INFO(dev)->gen) {
2537         case 6:
2538                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2539                              (obj_priv->fence_reg * 8), 0);
2540                 break;
2541         case 5:
2542         case 4:
2543                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2544                 break;
2545         case 3:
2546                 if (obj_priv->fence_reg >= 8)
2547                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2548                 else
2549         case 2:
2550                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2551
2552                 I915_WRITE(fence_reg, 0);
2553                 break;
2554         }
2555
2556         reg->obj = NULL;
2557         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2558         list_del_init(&reg->lru_list);
2559 }
2560
2561 /**
2562  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2563  * to the buffer to finish, and then resets the fence register.
2564  * @obj: tiled object holding a fence register.
2565  * @bool: whether the wait upon the fence is interruptible
2566  *
2567  * Zeroes out the fence register itself and clears out the associated
2568  * data structures in dev_priv and obj_priv.
2569  */
2570 int
2571 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2572                               bool interruptible)
2573 {
2574         struct drm_device *dev = obj->dev;
2575         struct drm_i915_private *dev_priv = dev->dev_private;
2576         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2577         struct drm_i915_fence_reg *reg;
2578
2579         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2580                 return 0;
2581
2582         /* If we've changed tiling, GTT-mappings of the object
2583          * need to re-fault to ensure that the correct fence register
2584          * setup is in place.
2585          */
2586         i915_gem_release_mmap(obj);
2587
2588         /* On the i915, GPU access to tiled buffers is via a fence,
2589          * therefore we must wait for any outstanding access to complete
2590          * before clearing the fence.
2591          */
2592         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2593         if (reg->gpu) {
2594                 int ret;
2595
2596                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2597                 if (ret)
2598                         return ret;
2599
2600                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2601                 if (ret)
2602                         return ret;
2603
2604                 reg->gpu = false;
2605         }
2606
2607         i915_gem_object_flush_gtt_write_domain(obj);
2608         i915_gem_clear_fence_reg(obj);
2609
2610         return 0;
2611 }
2612
2613 /**
2614  * Finds free space in the GTT aperture and binds the object there.
2615  */
2616 static int
2617 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2618 {
2619         struct drm_device *dev = obj->dev;
2620         drm_i915_private_t *dev_priv = dev->dev_private;
2621         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2622         struct drm_mm_node *free_space;
2623         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2624         int ret;
2625
2626         if (obj_priv->madv != I915_MADV_WILLNEED) {
2627                 DRM_ERROR("Attempting to bind a purgeable object\n");
2628                 return -EINVAL;
2629         }
2630
2631         if (alignment == 0)
2632                 alignment = i915_gem_get_gtt_alignment(obj);
2633         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2634                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2635                 return -EINVAL;
2636         }
2637
2638         /* If the object is bigger than the entire aperture, reject it early
2639          * before evicting everything in a vain attempt to find space.
2640          */
2641         if (obj->size > dev_priv->mm.gtt_total) {
2642                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2643                 return -E2BIG;
2644         }
2645
2646  search_free:
2647         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2648                                         obj->size, alignment, 0);
2649         if (free_space != NULL)
2650                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2651                                                        alignment);
2652         if (obj_priv->gtt_space == NULL) {
2653                 /* If the gtt is empty and we're still having trouble
2654                  * fitting our object in, we're out of memory.
2655                  */
2656                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2657                 if (ret)
2658                         return ret;
2659
2660                 goto search_free;
2661         }
2662
2663         ret = i915_gem_object_get_pages(obj, gfpmask);
2664         if (ret) {
2665                 drm_mm_put_block(obj_priv->gtt_space);
2666                 obj_priv->gtt_space = NULL;
2667
2668                 if (ret == -ENOMEM) {
2669                         /* first try to clear up some space from the GTT */
2670                         ret = i915_gem_evict_something(dev, obj->size,
2671                                                        alignment);
2672                         if (ret) {
2673                                 /* now try to shrink everyone else */
2674                                 if (gfpmask) {
2675                                         gfpmask = 0;
2676                                         goto search_free;
2677                                 }
2678
2679                                 return ret;
2680                         }
2681
2682                         goto search_free;
2683                 }
2684
2685                 return ret;
2686         }
2687
2688         /* Create an AGP memory structure pointing at our pages, and bind it
2689          * into the GTT.
2690          */
2691         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2692                                                obj_priv->pages,
2693                                                obj->size >> PAGE_SHIFT,
2694                                                obj_priv->gtt_space->start,
2695                                                obj_priv->agp_type);
2696         if (obj_priv->agp_mem == NULL) {
2697                 i915_gem_object_put_pages(obj);
2698                 drm_mm_put_block(obj_priv->gtt_space);
2699                 obj_priv->gtt_space = NULL;
2700
2701                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2702                 if (ret)
2703                         return ret;
2704
2705                 goto search_free;
2706         }
2707
2708         /* keep track of bounds object by adding it to the inactive list */
2709         list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2710         i915_gem_info_add_gtt(dev_priv, obj->size);
2711
2712         /* Assert that the object is not currently in any GPU domain. As it
2713          * wasn't in the GTT, there shouldn't be any way it could have been in
2714          * a GPU cache
2715          */
2716         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2717         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2718
2719         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2720         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2721
2722         return 0;
2723 }
2724
2725 void
2726 i915_gem_clflush_object(struct drm_gem_object *obj)
2727 {
2728         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2729
2730         /* If we don't have a page list set up, then we're not pinned
2731          * to GPU, and we can ignore the cache flush because it'll happen
2732          * again at bind time.
2733          */
2734         if (obj_priv->pages == NULL)
2735                 return;
2736
2737         trace_i915_gem_object_clflush(obj);
2738
2739         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2740 }
2741
2742 /** Flushes any GPU write domain for the object if it's dirty. */
2743 static int
2744 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2745                                        bool pipelined)
2746 {
2747         struct drm_device *dev = obj->dev;
2748         uint32_t old_write_domain;
2749
2750         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2751                 return 0;
2752
2753         /* Queue the GPU write cache flushing we need. */
2754         old_write_domain = obj->write_domain;
2755         i915_gem_flush_ring(dev, NULL,
2756                             to_intel_bo(obj)->ring,
2757                             0, obj->write_domain);
2758         BUG_ON(obj->write_domain);
2759
2760         trace_i915_gem_object_change_domain(obj,
2761                                             obj->read_domains,
2762                                             old_write_domain);
2763
2764         if (pipelined)
2765                 return 0;
2766
2767         return i915_gem_object_wait_rendering(obj, true);
2768 }
2769
2770 /** Flushes the GTT write domain for the object if it's dirty. */
2771 static void
2772 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2773 {
2774         uint32_t old_write_domain;
2775
2776         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2777                 return;
2778
2779         /* No actual flushing is required for the GTT write domain.   Writes
2780          * to it immediately go to main memory as far as we know, so there's
2781          * no chipset flush.  It also doesn't land in render cache.
2782          */
2783         old_write_domain = obj->write_domain;
2784         obj->write_domain = 0;
2785
2786         trace_i915_gem_object_change_domain(obj,
2787                                             obj->read_domains,
2788                                             old_write_domain);
2789 }
2790
2791 /** Flushes the CPU write domain for the object if it's dirty. */
2792 static void
2793 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2794 {
2795         struct drm_device *dev = obj->dev;
2796         uint32_t old_write_domain;
2797
2798         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2799                 return;
2800
2801         i915_gem_clflush_object(obj);
2802         drm_agp_chipset_flush(dev);
2803         old_write_domain = obj->write_domain;
2804         obj->write_domain = 0;
2805
2806         trace_i915_gem_object_change_domain(obj,
2807                                             obj->read_domains,
2808                                             old_write_domain);
2809 }
2810
2811 /**
2812  * Moves a single object to the GTT read, and possibly write domain.
2813  *
2814  * This function returns when the move is complete, including waiting on
2815  * flushes to occur.
2816  */
2817 int
2818 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2819 {
2820         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2821         uint32_t old_write_domain, old_read_domains;
2822         int ret;
2823
2824         /* Not valid to be called on unbound objects. */
2825         if (obj_priv->gtt_space == NULL)
2826                 return -EINVAL;
2827
2828         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2829         if (ret != 0)
2830                 return ret;
2831
2832         i915_gem_object_flush_cpu_write_domain(obj);
2833
2834         if (write) {
2835                 ret = i915_gem_object_wait_rendering(obj, true);
2836                 if (ret)
2837                         return ret;
2838         }
2839
2840         old_write_domain = obj->write_domain;
2841         old_read_domains = obj->read_domains;
2842
2843         /* It should now be out of any other write domains, and we can update
2844          * the domain values for our changes.
2845          */
2846         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2847         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2848         if (write) {
2849                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2850                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2851                 obj_priv->dirty = 1;
2852         }
2853
2854         trace_i915_gem_object_change_domain(obj,
2855                                             old_read_domains,
2856                                             old_write_domain);
2857
2858         return 0;
2859 }
2860
2861 /*
2862  * Prepare buffer for display plane. Use uninterruptible for possible flush
2863  * wait, as in modesetting process we're not supposed to be interrupted.
2864  */
2865 int
2866 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2867                                      bool pipelined)
2868 {
2869         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2870         uint32_t old_read_domains;
2871         int ret;
2872
2873         /* Not valid to be called on unbound objects. */
2874         if (obj_priv->gtt_space == NULL)
2875                 return -EINVAL;
2876
2877         ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2878         if (ret)
2879                 return ret;
2880
2881         /* Currently, we are always called from an non-interruptible context. */
2882         if (!pipelined) {
2883                 ret = i915_gem_object_wait_rendering(obj, false);
2884                 if (ret)
2885                         return ret;
2886         }
2887
2888         i915_gem_object_flush_cpu_write_domain(obj);
2889
2890         old_read_domains = obj->read_domains;
2891         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2892
2893         trace_i915_gem_object_change_domain(obj,
2894                                             old_read_domains,
2895                                             obj->write_domain);
2896
2897         return 0;
2898 }
2899
2900 /**
2901  * Moves a single object to the CPU read, and possibly write domain.
2902  *
2903  * This function returns when the move is complete, including waiting on
2904  * flushes to occur.
2905  */
2906 static int
2907 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2908 {
2909         uint32_t old_write_domain, old_read_domains;
2910         int ret;
2911
2912         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2913         if (ret != 0)
2914                 return ret;
2915
2916         i915_gem_object_flush_gtt_write_domain(obj);
2917
2918         /* If we have a partially-valid cache of the object in the CPU,
2919          * finish invalidating it and free the per-page flags.
2920          */
2921         i915_gem_object_set_to_full_cpu_read_domain(obj);
2922
2923         if (write) {
2924                 ret = i915_gem_object_wait_rendering(obj, true);
2925                 if (ret)
2926                         return ret;
2927         }
2928
2929         old_write_domain = obj->write_domain;
2930         old_read_domains = obj->read_domains;
2931
2932         /* Flush the CPU cache if it's still invalid. */
2933         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2934                 i915_gem_clflush_object(obj);
2935
2936                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2937         }
2938
2939         /* It should now be out of any other write domains, and we can update
2940          * the domain values for our changes.
2941          */
2942         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2943
2944         /* If we're writing through the CPU, then the GPU read domains will
2945          * need to be invalidated at next use.
2946          */
2947         if (write) {
2948                 obj->read_domains = I915_GEM_DOMAIN_CPU;
2949                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2950         }
2951
2952         trace_i915_gem_object_change_domain(obj,
2953                                             old_read_domains,
2954                                             old_write_domain);
2955
2956         return 0;
2957 }
2958
2959 /*
2960  * Set the next domain for the specified object. This
2961  * may not actually perform the necessary flushing/invaliding though,
2962  * as that may want to be batched with other set_domain operations
2963  *
2964  * This is (we hope) the only really tricky part of gem. The goal
2965  * is fairly simple -- track which caches hold bits of the object
2966  * and make sure they remain coherent. A few concrete examples may
2967  * help to explain how it works. For shorthand, we use the notation
2968  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2969  * a pair of read and write domain masks.
2970  *
2971  * Case 1: the batch buffer
2972  *
2973  *      1. Allocated
2974  *      2. Written by CPU
2975  *      3. Mapped to GTT
2976  *      4. Read by GPU
2977  *      5. Unmapped from GTT
2978  *      6. Freed
2979  *
2980  *      Let's take these a step at a time
2981  *
2982  *      1. Allocated
2983  *              Pages allocated from the kernel may still have
2984  *              cache contents, so we set them to (CPU, CPU) always.
2985  *      2. Written by CPU (using pwrite)
2986  *              The pwrite function calls set_domain (CPU, CPU) and
2987  *              this function does nothing (as nothing changes)
2988  *      3. Mapped by GTT
2989  *              This function asserts that the object is not
2990  *              currently in any GPU-based read or write domains
2991  *      4. Read by GPU
2992  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2993  *              As write_domain is zero, this function adds in the
2994  *              current read domains (CPU+COMMAND, 0).
2995  *              flush_domains is set to CPU.
2996  *              invalidate_domains is set to COMMAND
2997  *              clflush is run to get data out of the CPU caches
2998  *              then i915_dev_set_domain calls i915_gem_flush to
2999  *              emit an MI_FLUSH and drm_agp_chipset_flush
3000  *      5. Unmapped from GTT
3001  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3002  *              flush_domains and invalidate_domains end up both zero
3003  *              so no flushing/invalidating happens
3004  *      6. Freed
3005  *              yay, done
3006  *
3007  * Case 2: The shared render buffer
3008  *
3009  *      1. Allocated
3010  *      2. Mapped to GTT
3011  *      3. Read/written by GPU
3012  *      4. set_domain to (CPU,CPU)
3013  *      5. Read/written by CPU
3014  *      6. Read/written by GPU
3015  *
3016  *      1. Allocated
3017  *              Same as last example, (CPU, CPU)
3018  *      2. Mapped to GTT
3019  *              Nothing changes (assertions find that it is not in the GPU)
3020  *      3. Read/written by GPU
3021  *              execbuffer calls set_domain (RENDER, RENDER)
3022  *              flush_domains gets CPU
3023  *              invalidate_domains gets GPU
3024  *              clflush (obj)
3025  *              MI_FLUSH and drm_agp_chipset_flush
3026  *      4. set_domain (CPU, CPU)
3027  *              flush_domains gets GPU
3028  *              invalidate_domains gets CPU
3029  *              wait_rendering (obj) to make sure all drawing is complete.
3030  *              This will include an MI_FLUSH to get the data from GPU
3031  *              to memory
3032  *              clflush (obj) to invalidate the CPU cache
3033  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3034  *      5. Read/written by CPU
3035  *              cache lines are loaded and dirtied
3036  *      6. Read written by GPU
3037  *              Same as last GPU access
3038  *
3039  * Case 3: The constant buffer
3040  *
3041  *      1. Allocated
3042  *      2. Written by CPU
3043  *      3. Read by GPU
3044  *      4. Updated (written) by CPU again
3045  *      5. Read by GPU
3046  *
3047  *      1. Allocated
3048  *              (CPU, CPU)
3049  *      2. Written by CPU
3050  *              (CPU, CPU)
3051  *      3. Read by GPU
3052  *              (CPU+RENDER, 0)
3053  *              flush_domains = CPU
3054  *              invalidate_domains = RENDER
3055  *              clflush (obj)
3056  *              MI_FLUSH
3057  *              drm_agp_chipset_flush
3058  *      4. Updated (written) by CPU again
3059  *              (CPU, CPU)
3060  *              flush_domains = 0 (no previous write domain)
3061  *              invalidate_domains = 0 (no new read domains)
3062  *      5. Read by GPU
3063  *              (CPU+RENDER, 0)
3064  *              flush_domains = CPU
3065  *              invalidate_domains = RENDER
3066  *              clflush (obj)
3067  *              MI_FLUSH
3068  *              drm_agp_chipset_flush
3069  */
3070 static void
3071 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3072 {
3073         struct drm_device               *dev = obj->dev;
3074         struct drm_i915_private         *dev_priv = dev->dev_private;
3075         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3076         uint32_t                        invalidate_domains = 0;
3077         uint32_t                        flush_domains = 0;
3078         uint32_t                        old_read_domains;
3079
3080         intel_mark_busy(dev, obj);
3081
3082         /*
3083          * If the object isn't moving to a new write domain,
3084          * let the object stay in multiple read domains
3085          */
3086         if (obj->pending_write_domain == 0)
3087                 obj->pending_read_domains |= obj->read_domains;
3088         else
3089                 obj_priv->dirty = 1;
3090
3091         /*
3092          * Flush the current write domain if
3093          * the new read domains don't match. Invalidate
3094          * any read domains which differ from the old
3095          * write domain
3096          */
3097         if (obj->write_domain &&
3098             obj->write_domain != obj->pending_read_domains) {
3099                 flush_domains |= obj->write_domain;
3100                 invalidate_domains |=
3101                         obj->pending_read_domains & ~obj->write_domain;
3102         }
3103         /*
3104          * Invalidate any read caches which may have
3105          * stale data. That is, any new read domains.
3106          */
3107         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3108         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3109                 i915_gem_clflush_object(obj);
3110
3111         old_read_domains = obj->read_domains;
3112
3113         /* The actual obj->write_domain will be updated with
3114          * pending_write_domain after we emit the accumulated flush for all
3115          * of our domain changes in execbuffers (which clears objects'
3116          * write_domains).  So if we have a current write domain that we
3117          * aren't changing, set pending_write_domain to that.
3118          */
3119         if (flush_domains == 0 && obj->pending_write_domain == 0)
3120                 obj->pending_write_domain = obj->write_domain;
3121         obj->read_domains = obj->pending_read_domains;
3122
3123         dev->invalidate_domains |= invalidate_domains;
3124         dev->flush_domains |= flush_domains;
3125         if (obj_priv->ring)
3126                 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3127
3128         trace_i915_gem_object_change_domain(obj,
3129                                             old_read_domains,
3130                                             obj->write_domain);
3131 }
3132
3133 /**
3134  * Moves the object from a partially CPU read to a full one.
3135  *
3136  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3137  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3138  */
3139 static void
3140 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3141 {
3142         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3143
3144         if (!obj_priv->page_cpu_valid)
3145                 return;
3146
3147         /* If we're partially in the CPU read domain, finish moving it in.
3148          */
3149         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3150                 int i;
3151
3152                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3153                         if (obj_priv->page_cpu_valid[i])
3154                                 continue;
3155                         drm_clflush_pages(obj_priv->pages + i, 1);
3156                 }
3157         }
3158
3159         /* Free the page_cpu_valid mappings which are now stale, whether
3160          * or not we've got I915_GEM_DOMAIN_CPU.
3161          */
3162         kfree(obj_priv->page_cpu_valid);
3163         obj_priv->page_cpu_valid = NULL;
3164 }
3165
3166 /**
3167  * Set the CPU read domain on a range of the object.
3168  *
3169  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3170  * not entirely valid.  The page_cpu_valid member of the object flags which
3171  * pages have been flushed, and will be respected by
3172  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3173  * of the whole object.
3174  *
3175  * This function returns when the move is complete, including waiting on
3176  * flushes to occur.
3177  */
3178 static int
3179 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3180                                           uint64_t offset, uint64_t size)
3181 {
3182         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3183         uint32_t old_read_domains;
3184         int i, ret;
3185
3186         if (offset == 0 && size == obj->size)
3187                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3188
3189         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3190         if (ret != 0)
3191                 return ret;
3192         i915_gem_object_flush_gtt_write_domain(obj);
3193
3194         /* If we're already fully in the CPU read domain, we're done. */
3195         if (obj_priv->page_cpu_valid == NULL &&
3196             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3197                 return 0;
3198
3199         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3200          * newly adding I915_GEM_DOMAIN_CPU
3201          */
3202         if (obj_priv->page_cpu_valid == NULL) {
3203                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3204                                                    GFP_KERNEL);
3205                 if (obj_priv->page_cpu_valid == NULL)
3206                         return -ENOMEM;
3207         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3208                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3209
3210         /* Flush the cache on any pages that are still invalid from the CPU's
3211          * perspective.
3212          */
3213         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3214              i++) {
3215                 if (obj_priv->page_cpu_valid[i])
3216                         continue;
3217
3218                 drm_clflush_pages(obj_priv->pages + i, 1);
3219
3220                 obj_priv->page_cpu_valid[i] = 1;
3221         }
3222
3223         /* It should now be out of any other write domains, and we can update
3224          * the domain values for our changes.
3225          */
3226         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3227
3228         old_read_domains = obj->read_domains;
3229         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3230
3231         trace_i915_gem_object_change_domain(obj,
3232                                             old_read_domains,
3233                                             obj->write_domain);
3234
3235         return 0;
3236 }
3237
3238 /**
3239  * Pin an object to the GTT and evaluate the relocations landing in it.
3240  */
3241 static int
3242 i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
3243                              struct drm_file *file_priv,
3244                              struct drm_i915_gem_exec_object2 *entry)
3245 {
3246         struct drm_device *dev = obj->base.dev;
3247         drm_i915_private_t *dev_priv = dev->dev_private;
3248         struct drm_i915_gem_relocation_entry __user *user_relocs;
3249         struct drm_gem_object *target_obj = NULL;
3250         uint32_t target_handle = 0;
3251         int i, ret = 0;
3252
3253         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3254         for (i = 0; i < entry->relocation_count; i++) {
3255                 struct drm_i915_gem_relocation_entry reloc;
3256                 uint32_t target_offset;
3257
3258                 if (__copy_from_user_inatomic(&reloc,
3259                                               user_relocs+i,
3260                                               sizeof(reloc))) {
3261                         ret = -EFAULT;
3262                         break;
3263                 }
3264
3265                 if (reloc.target_handle != target_handle) {
3266                         drm_gem_object_unreference(target_obj);
3267
3268                         target_obj = drm_gem_object_lookup(dev, file_priv,
3269                                                            reloc.target_handle);
3270                         if (target_obj == NULL) {
3271                                 ret = -ENOENT;
3272                                 break;
3273                         }
3274
3275                         target_handle = reloc.target_handle;
3276                 }
3277                 target_offset = to_intel_bo(target_obj)->gtt_offset;
3278
3279 #if WATCH_RELOC
3280                 DRM_INFO("%s: obj %p offset %08x target %d "
3281                          "read %08x write %08x gtt %08x "
3282                          "presumed %08x delta %08x\n",
3283                          __func__,
3284                          obj,
3285                          (int) reloc.offset,
3286                          (int) reloc.target_handle,
3287                          (int) reloc.read_domains,
3288                          (int) reloc.write_domain,
3289                          (int) target_offset,
3290                          (int) reloc.presumed_offset,
3291                          reloc.delta);
3292 #endif
3293
3294                 /* The target buffer should have appeared before us in the
3295                  * exec_object list, so it should have a GTT space bound by now.
3296                  */
3297                 if (target_offset == 0) {
3298                         DRM_ERROR("No GTT space found for object %d\n",
3299                                   reloc.target_handle);
3300                         ret = -EINVAL;
3301                         break;
3302                 }
3303
3304                 /* Validate that the target is in a valid r/w GPU domain */
3305                 if (reloc.write_domain & (reloc.write_domain - 1)) {
3306                         DRM_ERROR("reloc with multiple write domains: "
3307                                   "obj %p target %d offset %d "
3308                                   "read %08x write %08x",
3309                                   obj, reloc.target_handle,
3310                                   (int) reloc.offset,
3311                                   reloc.read_domains,
3312                                   reloc.write_domain);
3313                         ret = -EINVAL;
3314                         break;
3315                 }
3316                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3317                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3318                         DRM_ERROR("reloc with read/write CPU domains: "
3319                                   "obj %p target %d offset %d "
3320                                   "read %08x write %08x",
3321                                   obj, reloc.target_handle,
3322                                   (int) reloc.offset,
3323                                   reloc.read_domains,
3324                                   reloc.write_domain);
3325                         ret = -EINVAL;
3326                         break;
3327                 }
3328                 if (reloc.write_domain && target_obj->pending_write_domain &&
3329                     reloc.write_domain != target_obj->pending_write_domain) {
3330                         DRM_ERROR("Write domain conflict: "
3331                                   "obj %p target %d offset %d "
3332                                   "new %08x old %08x\n",
3333                                   obj, reloc.target_handle,
3334                                   (int) reloc.offset,
3335                                   reloc.write_domain,
3336                                   target_obj->pending_write_domain);
3337                         ret = -EINVAL;
3338                         break;
3339                 }
3340
3341                 target_obj->pending_read_domains |= reloc.read_domains;
3342                 target_obj->pending_write_domain = reloc.write_domain;
3343
3344                 /* If the relocation already has the right value in it, no
3345                  * more work needs to be done.
3346                  */
3347                 if (target_offset == reloc.presumed_offset)
3348                         continue;
3349
3350                 /* Check that the relocation address is valid... */
3351                 if (reloc.offset > obj->base.size - 4) {
3352                         DRM_ERROR("Relocation beyond object bounds: "
3353                                   "obj %p target %d offset %d size %d.\n",
3354                                   obj, reloc.target_handle,
3355                                   (int) reloc.offset, (int) obj->base.size);
3356                         ret = -EINVAL;
3357                         break;
3358                 }
3359                 if (reloc.offset & 3) {
3360                         DRM_ERROR("Relocation not 4-byte aligned: "
3361                                   "obj %p target %d offset %d.\n",
3362                                   obj, reloc.target_handle,
3363                                   (int) reloc.offset);
3364                         ret = -EINVAL;
3365                         break;
3366                 }
3367
3368                 /* and points to somewhere within the target object. */
3369                 if (reloc.delta >= target_obj->size) {
3370                         DRM_ERROR("Relocation beyond target object bounds: "
3371                                   "obj %p target %d delta %d size %d.\n",
3372                                   obj, reloc.target_handle,
3373                                   (int) reloc.delta, (int) target_obj->size);
3374                         ret = -EINVAL;
3375                         break;
3376                 }
3377
3378                 reloc.delta += target_offset;
3379                 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3380                         uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3381                         char *vaddr;
3382
3383                         vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT], KM_USER0);
3384                         *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3385                         kunmap_atomic(vaddr, KM_USER0);
3386                 } else {
3387                         uint32_t __iomem *reloc_entry;
3388                         void __iomem *reloc_page;
3389
3390                         ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3391                         if (ret)
3392                                 break;
3393
3394                         /* Map the page containing the relocation we're going to perform.  */
3395                         reloc.offset += obj->gtt_offset;
3396                         reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3397                                                               reloc.offset & PAGE_MASK,
3398                                                               KM_USER0);
3399                         reloc_entry = (uint32_t __iomem *)
3400                                 (reloc_page + (reloc.offset & ~PAGE_MASK));
3401                         iowrite32(reloc.delta, reloc_entry);
3402                         io_mapping_unmap_atomic(reloc_page, KM_USER0);
3403                 }
3404         }
3405
3406         drm_gem_object_unreference(target_obj);
3407         return ret;
3408 }
3409
3410 static int
3411 i915_gem_execbuffer_pin(struct drm_device *dev,
3412                         struct drm_file *file,
3413                         struct drm_gem_object **object_list,
3414                         struct drm_i915_gem_exec_object2 *exec_list,
3415                         int count)
3416 {
3417         struct drm_i915_private *dev_priv = dev->dev_private;
3418         int ret, i, retry;
3419
3420         /* attempt to pin all of the buffers into the GTT */
3421         for (retry = 0; retry < 2; retry++) {
3422                 ret = 0;
3423                 for (i = 0; i < count; i++) {
3424                         struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
3425                         struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]);
3426                         bool need_fence =
3427                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3428                                 obj->tiling_mode != I915_TILING_NONE;
3429
3430                         /* Check fence reg constraints and rebind if necessary */
3431                         if (need_fence &&
3432                             !i915_gem_object_fence_offset_ok(&obj->base,
3433                                                              obj->tiling_mode)) {
3434                                 ret = i915_gem_object_unbind(&obj->base);
3435                                 if (ret)
3436                                         break;
3437                         }
3438
3439                         ret = i915_gem_object_pin(&obj->base, entry->alignment);
3440                         if (ret)
3441                                 break;
3442
3443                         /*
3444                          * Pre-965 chips need a fence register set up in order
3445                          * to properly handle blits to/from tiled surfaces.
3446                          */
3447                         if (need_fence) {
3448                                 ret = i915_gem_object_get_fence_reg(&obj->base, true);
3449                                 if (ret) {
3450                                         i915_gem_object_unpin(&obj->base);
3451                                         break;
3452                                 }
3453
3454                                 dev_priv->fence_regs[obj->fence_reg].gpu = true;
3455                         }
3456
3457                         entry->offset = obj->gtt_offset;
3458                 }
3459
3460                 while (i--)
3461                         i915_gem_object_unpin(object_list[i]);
3462
3463                 if (ret == 0)
3464                         break;
3465
3466                 if (ret != -ENOSPC || retry)
3467                         return ret;
3468
3469                 ret = i915_gem_evict_everything(dev);
3470                 if (ret)
3471                         return ret;
3472         }
3473
3474         return 0;
3475 }
3476
3477 /* Throttle our rendering by waiting until the ring has completed our requests
3478  * emitted over 20 msec ago.
3479  *
3480  * Note that if we were to use the current jiffies each time around the loop,
3481  * we wouldn't escape the function with any frames outstanding if the time to
3482  * render a frame was over 20ms.
3483  *
3484  * This should get us reasonable parallelism between CPU and GPU but also
3485  * relatively low latency when blocking on a particular request to finish.
3486  */
3487 static int
3488 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3489 {
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         struct drm_i915_file_private *file_priv = file->driver_priv;
3492         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3493         struct drm_i915_gem_request *request;
3494         struct intel_ring_buffer *ring = NULL;
3495         u32 seqno = 0;
3496         int ret;
3497
3498         spin_lock(&file_priv->mm.lock);
3499         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3500                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3501                         break;
3502
3503                 ring = request->ring;
3504                 seqno = request->seqno;
3505         }
3506         spin_unlock(&file_priv->mm.lock);
3507
3508         if (seqno == 0)
3509                 return 0;
3510
3511         ret = 0;
3512         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
3513                 /* And wait for the seqno passing without holding any locks and
3514                  * causing extra latency for others. This is safe as the irq
3515                  * generation is designed to be run atomically and so is
3516                  * lockless.
3517                  */
3518                 ring->user_irq_get(dev, ring);
3519                 ret = wait_event_interruptible(ring->irq_queue,
3520                                                i915_seqno_passed(ring->get_seqno(dev, ring), seqno)
3521                                                || atomic_read(&dev_priv->mm.wedged));
3522                 ring->user_irq_put(dev, ring);
3523
3524                 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3525                         ret = -EIO;
3526         }
3527
3528         if (ret == 0)
3529                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3530
3531         return ret;
3532 }
3533
3534 static int
3535 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3536                           uint64_t exec_offset)
3537 {
3538         uint32_t exec_start, exec_len;
3539
3540         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3541         exec_len = (uint32_t) exec->batch_len;
3542
3543         if ((exec_start | exec_len) & 0x7)
3544                 return -EINVAL;
3545
3546         if (!exec_start)
3547                 return -EINVAL;
3548
3549         return 0;
3550 }
3551
3552 static int
3553 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3554                    int count)
3555 {
3556         int i;
3557
3558         for (i = 0; i < count; i++) {
3559                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3560                 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3561
3562                 if (!access_ok(VERIFY_READ, ptr, length))
3563                         return -EFAULT;
3564
3565                 if (fault_in_pages_readable(ptr, length))
3566                         return -EFAULT;
3567         }
3568
3569         return 0;
3570 }
3571
3572 static int
3573 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3574                        struct drm_file *file,
3575                        struct drm_i915_gem_execbuffer2 *args,
3576                        struct drm_i915_gem_exec_object2 *exec_list)
3577 {
3578         drm_i915_private_t *dev_priv = dev->dev_private;
3579         struct drm_gem_object **object_list = NULL;
3580         struct drm_gem_object *batch_obj;
3581         struct drm_i915_gem_object *obj_priv;
3582         struct drm_clip_rect *cliprects = NULL;
3583         struct drm_i915_gem_request *request = NULL;
3584         int ret, i, flips;
3585         uint64_t exec_offset;
3586
3587         struct intel_ring_buffer *ring = NULL;
3588
3589         ret = i915_gem_check_is_wedged(dev);
3590         if (ret)
3591                 return ret;
3592
3593         ret = validate_exec_list(exec_list, args->buffer_count);
3594         if (ret)
3595                 return ret;
3596
3597 #if WATCH_EXEC
3598         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3599                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3600 #endif
3601         if (args->flags & I915_EXEC_BSD) {
3602                 if (!HAS_BSD(dev)) {
3603                         DRM_ERROR("execbuf with wrong flag\n");
3604                         return -EINVAL;
3605                 }
3606                 ring = &dev_priv->bsd_ring;
3607         } else {
3608                 ring = &dev_priv->render_ring;
3609         }
3610
3611         if (args->buffer_count < 1) {
3612                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3613                 return -EINVAL;
3614         }
3615         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3616         if (object_list == NULL) {
3617                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3618                           args->buffer_count);
3619                 ret = -ENOMEM;
3620                 goto pre_mutex_err;
3621         }
3622
3623         if (args->num_cliprects != 0) {
3624                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3625                                     GFP_KERNEL);
3626                 if (cliprects == NULL) {
3627                         ret = -ENOMEM;
3628                         goto pre_mutex_err;
3629                 }
3630
3631                 ret = copy_from_user(cliprects,
3632                                      (struct drm_clip_rect __user *)
3633                                      (uintptr_t) args->cliprects_ptr,
3634                                      sizeof(*cliprects) * args->num_cliprects);
3635                 if (ret != 0) {
3636                         DRM_ERROR("copy %d cliprects failed: %d\n",
3637                                   args->num_cliprects, ret);
3638                         ret = -EFAULT;
3639                         goto pre_mutex_err;
3640                 }
3641         }
3642
3643         request = kzalloc(sizeof(*request), GFP_KERNEL);
3644         if (request == NULL) {
3645                 ret = -ENOMEM;
3646                 goto pre_mutex_err;
3647         }
3648
3649         ret = i915_mutex_lock_interruptible(dev);
3650         if (ret)
3651                 goto pre_mutex_err;
3652
3653         if (dev_priv->mm.suspended) {
3654                 mutex_unlock(&dev->struct_mutex);
3655                 ret = -EBUSY;
3656                 goto pre_mutex_err;
3657         }
3658
3659         /* Look up object handles */
3660         for (i = 0; i < args->buffer_count; i++) {
3661                 object_list[i] = drm_gem_object_lookup(dev, file,
3662                                                        exec_list[i].handle);
3663                 if (object_list[i] == NULL) {
3664                         DRM_ERROR("Invalid object handle %d at index %d\n",
3665                                    exec_list[i].handle, i);
3666                         /* prevent error path from reading uninitialized data */
3667                         args->buffer_count = i + 1;
3668                         ret = -ENOENT;
3669                         goto err;
3670                 }
3671
3672                 obj_priv = to_intel_bo(object_list[i]);
3673                 if (obj_priv->in_execbuffer) {
3674                         DRM_ERROR("Object %p appears more than once in object list\n",
3675                                    object_list[i]);
3676                         /* prevent error path from reading uninitialized data */
3677                         args->buffer_count = i + 1;
3678                         ret = -EINVAL;
3679                         goto err;
3680                 }
3681                 obj_priv->in_execbuffer = true;
3682         }
3683
3684         /* Move the objects en-masse into the GTT, evicting if necessary. */
3685         ret = i915_gem_execbuffer_pin(dev, file,
3686                                       object_list, exec_list,
3687                                       args->buffer_count);
3688         if (ret)
3689                 goto err;
3690
3691         /* The objects are in their final locations, apply the relocations. */
3692         for (i = 0; i < args->buffer_count; i++) {
3693                 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3694                 obj->base.pending_read_domains = 0;
3695                 obj->base.pending_write_domain = 0;
3696                 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
3697                 if (ret)
3698                         goto err;
3699         }
3700
3701         /* Set the pending read domains for the batch buffer to COMMAND */
3702         batch_obj = object_list[args->buffer_count-1];
3703         if (batch_obj->pending_write_domain) {
3704                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3705                 ret = -EINVAL;
3706                 goto err;
3707         }
3708         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3709
3710         /* Sanity check the batch buffer */
3711         exec_offset = to_intel_bo(batch_obj)->gtt_offset;
3712         ret = i915_gem_check_execbuffer(args, exec_offset);
3713         if (ret != 0) {
3714                 DRM_ERROR("execbuf with invalid offset/length\n");
3715                 goto err;
3716         }
3717
3718         /* Zero the global flush/invalidate flags. These
3719          * will be modified as new domains are computed
3720          * for each object
3721          */
3722         dev->invalidate_domains = 0;
3723         dev->flush_domains = 0;
3724         dev_priv->mm.flush_rings = 0;
3725
3726         for (i = 0; i < args->buffer_count; i++) {
3727                 struct drm_gem_object *obj = object_list[i];
3728
3729                 /* Compute new gpu domains and update invalidate/flush */
3730                 i915_gem_object_set_to_gpu_domain(obj);
3731         }
3732
3733         if (dev->invalidate_domains | dev->flush_domains) {
3734 #if WATCH_EXEC
3735                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3736                           __func__,
3737                          dev->invalidate_domains,
3738                          dev->flush_domains);
3739 #endif
3740                 i915_gem_flush(dev, file,
3741                                dev->invalidate_domains,
3742                                dev->flush_domains,
3743                                dev_priv->mm.flush_rings);
3744         }
3745
3746         for (i = 0; i < args->buffer_count; i++) {
3747                 struct drm_gem_object *obj = object_list[i];
3748                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3749                 uint32_t old_write_domain = obj->write_domain;
3750
3751                 obj->write_domain = obj->pending_write_domain;
3752                 if (obj->write_domain)
3753                         list_move_tail(&obj_priv->gpu_write_list,
3754                                        &dev_priv->mm.gpu_write_list);
3755
3756                 trace_i915_gem_object_change_domain(obj,
3757                                                     obj->read_domains,
3758                                                     old_write_domain);
3759         }
3760
3761 #if WATCH_COHERENCY
3762         for (i = 0; i < args->buffer_count; i++) {
3763                 i915_gem_object_check_coherency(object_list[i],
3764                                                 exec_list[i].handle);
3765         }
3766 #endif
3767
3768 #if WATCH_EXEC
3769         i915_gem_dump_object(batch_obj,
3770                               args->batch_len,
3771                               __func__,
3772                               ~0);
3773 #endif
3774
3775         /* Check for any pending flips. As we only maintain a flip queue depth
3776          * of 1, we can simply insert a WAIT for the next display flip prior
3777          * to executing the batch and avoid stalling the CPU.
3778          */
3779         flips = 0;
3780         for (i = 0; i < args->buffer_count; i++) {
3781                 if (object_list[i]->write_domain)
3782                         flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3783         }
3784         if (flips) {
3785                 int plane, flip_mask;
3786
3787                 for (plane = 0; flips >> plane; plane++) {
3788                         if (((flips >> plane) & 1) == 0)
3789                                 continue;
3790
3791                         if (plane)
3792                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3793                         else
3794                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3795
3796                         intel_ring_begin(dev, ring, 2);
3797                         intel_ring_emit(dev, ring,
3798                                         MI_WAIT_FOR_EVENT | flip_mask);
3799                         intel_ring_emit(dev, ring, MI_NOOP);
3800                         intel_ring_advance(dev, ring);
3801                 }
3802         }
3803
3804         /* Exec the batchbuffer */
3805         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3806                                             cliprects, exec_offset);
3807         if (ret) {
3808                 DRM_ERROR("dispatch failed %d\n", ret);
3809                 goto err;
3810         }
3811
3812         /*
3813          * Ensure that the commands in the batch buffer are
3814          * finished before the interrupt fires
3815          */
3816         i915_retire_commands(dev, ring);
3817
3818         for (i = 0; i < args->buffer_count; i++) {
3819                 struct drm_gem_object *obj = object_list[i];
3820                 obj_priv = to_intel_bo(obj);
3821
3822                 i915_gem_object_move_to_active(obj, ring);
3823         }
3824
3825         i915_add_request(dev, file, request, ring);
3826         request = NULL;
3827
3828 err:
3829         for (i = 0; i < args->buffer_count; i++) {
3830                 if (object_list[i]) {
3831                         obj_priv = to_intel_bo(object_list[i]);
3832                         obj_priv->in_execbuffer = false;
3833                 }
3834                 drm_gem_object_unreference(object_list[i]);
3835         }
3836
3837         mutex_unlock(&dev->struct_mutex);
3838
3839 pre_mutex_err:
3840         drm_free_large(object_list);
3841         kfree(cliprects);
3842         kfree(request);
3843
3844         return ret;
3845 }
3846
3847 /*
3848  * Legacy execbuffer just creates an exec2 list from the original exec object
3849  * list array and passes it to the real function.
3850  */
3851 int
3852 i915_gem_execbuffer(struct drm_device *dev, void *data,
3853                     struct drm_file *file_priv)
3854 {
3855         struct drm_i915_gem_execbuffer *args = data;
3856         struct drm_i915_gem_execbuffer2 exec2;
3857         struct drm_i915_gem_exec_object *exec_list = NULL;
3858         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3859         int ret, i;
3860
3861 #if WATCH_EXEC
3862         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3863                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3864 #endif
3865
3866         if (args->buffer_count < 1) {
3867                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3868                 return -EINVAL;
3869         }
3870
3871         /* Copy in the exec list from userland */
3872         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3873         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3874         if (exec_list == NULL || exec2_list == NULL) {
3875                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3876                           args->buffer_count);
3877                 drm_free_large(exec_list);
3878                 drm_free_large(exec2_list);
3879                 return -ENOMEM;
3880         }
3881         ret = copy_from_user(exec_list,
3882                              (struct drm_i915_relocation_entry __user *)
3883                              (uintptr_t) args->buffers_ptr,
3884                              sizeof(*exec_list) * args->buffer_count);
3885         if (ret != 0) {
3886                 DRM_ERROR("copy %d exec entries failed %d\n",
3887                           args->buffer_count, ret);
3888                 drm_free_large(exec_list);
3889                 drm_free_large(exec2_list);
3890                 return -EFAULT;
3891         }
3892
3893         for (i = 0; i < args->buffer_count; i++) {
3894                 exec2_list[i].handle = exec_list[i].handle;
3895                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3896                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3897                 exec2_list[i].alignment = exec_list[i].alignment;
3898                 exec2_list[i].offset = exec_list[i].offset;
3899                 if (INTEL_INFO(dev)->gen < 4)
3900                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3901                 else
3902                         exec2_list[i].flags = 0;
3903         }
3904
3905         exec2.buffers_ptr = args->buffers_ptr;
3906         exec2.buffer_count = args->buffer_count;
3907         exec2.batch_start_offset = args->batch_start_offset;
3908         exec2.batch_len = args->batch_len;
3909         exec2.DR1 = args->DR1;
3910         exec2.DR4 = args->DR4;
3911         exec2.num_cliprects = args->num_cliprects;
3912         exec2.cliprects_ptr = args->cliprects_ptr;
3913         exec2.flags = I915_EXEC_RENDER;
3914
3915         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3916         if (!ret) {
3917                 /* Copy the new buffer offsets back to the user's exec list. */
3918                 for (i = 0; i < args->buffer_count; i++)
3919                         exec_list[i].offset = exec2_list[i].offset;
3920                 /* ... and back out to userspace */
3921                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3922                                    (uintptr_t) args->buffers_ptr,
3923                                    exec_list,
3924                                    sizeof(*exec_list) * args->buffer_count);
3925                 if (ret) {
3926                         ret = -EFAULT;
3927                         DRM_ERROR("failed to copy %d exec entries "
3928                                   "back to user (%d)\n",
3929                                   args->buffer_count, ret);
3930                 }
3931         }
3932
3933         drm_free_large(exec_list);
3934         drm_free_large(exec2_list);
3935         return ret;
3936 }
3937
3938 int
3939 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3940                      struct drm_file *file_priv)
3941 {
3942         struct drm_i915_gem_execbuffer2 *args = data;
3943         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3944         int ret;
3945
3946 #if WATCH_EXEC
3947         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3948                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3949 #endif
3950
3951         if (args->buffer_count < 1) {
3952                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3953                 return -EINVAL;
3954         }
3955
3956         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3957         if (exec2_list == NULL) {
3958                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3959                           args->buffer_count);
3960                 return -ENOMEM;
3961         }
3962         ret = copy_from_user(exec2_list,
3963                              (struct drm_i915_relocation_entry __user *)
3964                              (uintptr_t) args->buffers_ptr,
3965                              sizeof(*exec2_list) * args->buffer_count);
3966         if (ret != 0) {
3967                 DRM_ERROR("copy %d exec entries failed %d\n",
3968                           args->buffer_count, ret);
3969                 drm_free_large(exec2_list);
3970                 return -EFAULT;
3971         }
3972
3973         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
3974         if (!ret) {
3975                 /* Copy the new buffer offsets back to the user's exec list. */
3976                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3977                                    (uintptr_t) args->buffers_ptr,
3978                                    exec2_list,
3979                                    sizeof(*exec2_list) * args->buffer_count);
3980                 if (ret) {
3981                         ret = -EFAULT;
3982                         DRM_ERROR("failed to copy %d exec entries "
3983                                   "back to user (%d)\n",
3984                                   args->buffer_count, ret);
3985                 }
3986         }
3987
3988         drm_free_large(exec2_list);
3989         return ret;
3990 }
3991
3992 int
3993 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3994 {
3995         struct drm_device *dev = obj->dev;
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3998         int ret;
3999
4000         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4001         WARN_ON(i915_verify_lists(dev));
4002
4003         if (obj_priv->gtt_space != NULL) {
4004                 if (alignment == 0)
4005                         alignment = i915_gem_get_gtt_alignment(obj);
4006                 if (obj_priv->gtt_offset & (alignment - 1)) {
4007                         WARN(obj_priv->pin_count,
4008                              "bo is already pinned with incorrect alignment:"
4009                              " offset=%x, req.alignment=%x\n",
4010                              obj_priv->gtt_offset, alignment);
4011                         ret = i915_gem_object_unbind(obj);
4012                         if (ret)
4013                                 return ret;
4014                 }
4015         }
4016
4017         if (obj_priv->gtt_space == NULL) {
4018                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4019                 if (ret)
4020                         return ret;
4021         }
4022
4023         obj_priv->pin_count++;
4024
4025         /* If the object is not active and not pending a flush,
4026          * remove it from the inactive list
4027          */
4028         if (obj_priv->pin_count == 1) {
4029                 i915_gem_info_add_pin(dev_priv, obj->size);
4030                 if (!obj_priv->active)
4031                         list_move_tail(&obj_priv->list,
4032                                        &dev_priv->mm.pinned_list);
4033         }
4034
4035         WARN_ON(i915_verify_lists(dev));
4036         return 0;
4037 }
4038
4039 void
4040 i915_gem_object_unpin(struct drm_gem_object *obj)
4041 {
4042         struct drm_device *dev = obj->dev;
4043         drm_i915_private_t *dev_priv = dev->dev_private;
4044         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4045
4046         WARN_ON(i915_verify_lists(dev));
4047         obj_priv->pin_count--;
4048         BUG_ON(obj_priv->pin_count < 0);
4049         BUG_ON(obj_priv->gtt_space == NULL);
4050
4051         /* If the object is no longer pinned, and is
4052          * neither active nor being flushed, then stick it on
4053          * the inactive list
4054          */
4055         if (obj_priv->pin_count == 0) {
4056                 if (!obj_priv->active)
4057                         list_move_tail(&obj_priv->list,
4058                                        &dev_priv->mm.inactive_list);
4059                 i915_gem_info_remove_pin(dev_priv, obj->size);
4060         }
4061         WARN_ON(i915_verify_lists(dev));
4062 }
4063
4064 int
4065 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4066                    struct drm_file *file_priv)
4067 {
4068         struct drm_i915_gem_pin *args = data;
4069         struct drm_gem_object *obj;
4070         struct drm_i915_gem_object *obj_priv;
4071         int ret;
4072
4073         ret = i915_mutex_lock_interruptible(dev);
4074         if (ret)
4075                 return ret;
4076
4077         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4078         if (obj == NULL) {
4079                 ret = -ENOENT;
4080                 goto unlock;
4081         }
4082         obj_priv = to_intel_bo(obj);
4083
4084         if (obj_priv->madv != I915_MADV_WILLNEED) {
4085                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4086                 ret = -EINVAL;
4087                 goto out;
4088         }
4089
4090         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4091                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4092                           args->handle);
4093                 ret = -EINVAL;
4094                 goto out;
4095         }
4096
4097         obj_priv->user_pin_count++;
4098         obj_priv->pin_filp = file_priv;
4099         if (obj_priv->user_pin_count == 1) {
4100                 ret = i915_gem_object_pin(obj, args->alignment);
4101                 if (ret)
4102                         goto out;
4103         }
4104
4105         /* XXX - flush the CPU caches for pinned objects
4106          * as the X server doesn't manage domains yet
4107          */
4108         i915_gem_object_flush_cpu_write_domain(obj);
4109         args->offset = obj_priv->gtt_offset;
4110 out:
4111         drm_gem_object_unreference(obj);
4112 unlock:
4113         mutex_unlock(&dev->struct_mutex);
4114         return ret;
4115 }
4116
4117 int
4118 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4119                      struct drm_file *file_priv)
4120 {
4121         struct drm_i915_gem_pin *args = data;
4122         struct drm_gem_object *obj;
4123         struct drm_i915_gem_object *obj_priv;
4124         int ret;
4125
4126         ret = i915_mutex_lock_interruptible(dev);
4127         if (ret)
4128                 return ret;
4129
4130         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4131         if (obj == NULL) {
4132                 ret = -ENOENT;
4133                 goto unlock;
4134         }
4135         obj_priv = to_intel_bo(obj);
4136
4137         if (obj_priv->pin_filp != file_priv) {
4138                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4139                           args->handle);
4140                 ret = -EINVAL;
4141                 goto out;
4142         }
4143         obj_priv->user_pin_count--;
4144         if (obj_priv->user_pin_count == 0) {
4145                 obj_priv->pin_filp = NULL;
4146                 i915_gem_object_unpin(obj);
4147         }
4148
4149 out:
4150         drm_gem_object_unreference(obj);
4151 unlock:
4152         mutex_unlock(&dev->struct_mutex);
4153         return ret;
4154 }
4155
4156 int
4157 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4158                     struct drm_file *file_priv)
4159 {
4160         struct drm_i915_gem_busy *args = data;
4161         struct drm_gem_object *obj;
4162         struct drm_i915_gem_object *obj_priv;
4163         int ret;
4164
4165         ret = i915_mutex_lock_interruptible(dev);
4166         if (ret)
4167                 return ret;
4168
4169         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4170         if (obj == NULL) {
4171                 ret = -ENOENT;
4172                 goto unlock;
4173         }
4174         obj_priv = to_intel_bo(obj);
4175
4176         /* Count all active objects as busy, even if they are currently not used
4177          * by the gpu. Users of this interface expect objects to eventually
4178          * become non-busy without any further actions, therefore emit any
4179          * necessary flushes here.
4180          */
4181         args->busy = obj_priv->active;
4182         if (args->busy) {
4183                 /* Unconditionally flush objects, even when the gpu still uses this
4184                  * object. Userspace calling this function indicates that it wants to
4185                  * use this buffer rather sooner than later, so issuing the required
4186                  * flush earlier is beneficial.
4187                  */
4188                 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4189                         i915_gem_flush_ring(dev, file_priv,
4190                                             obj_priv->ring,
4191                                             0, obj->write_domain);
4192
4193                 /* Update the active list for the hardware's current position.
4194                  * Otherwise this only updates on a delayed timer or when irqs
4195                  * are actually unmasked, and our working set ends up being
4196                  * larger than required.
4197                  */
4198                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4199
4200                 args->busy = obj_priv->active;
4201         }
4202
4203         drm_gem_object_unreference(obj);
4204 unlock:
4205         mutex_unlock(&dev->struct_mutex);
4206         return ret;
4207 }
4208
4209 int
4210 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4211                         struct drm_file *file_priv)
4212 {
4213     return i915_gem_ring_throttle(dev, file_priv);
4214 }
4215
4216 int
4217 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4218                        struct drm_file *file_priv)
4219 {
4220         struct drm_i915_gem_madvise *args = data;
4221         struct drm_gem_object *obj;
4222         struct drm_i915_gem_object *obj_priv;
4223         int ret;
4224
4225         switch (args->madv) {
4226         case I915_MADV_DONTNEED:
4227         case I915_MADV_WILLNEED:
4228             break;
4229         default:
4230             return -EINVAL;
4231         }
4232
4233         ret = i915_mutex_lock_interruptible(dev);
4234         if (ret)
4235                 return ret;
4236
4237         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4238         if (obj == NULL) {
4239                 ret = -ENOENT;
4240                 goto unlock;
4241         }
4242         obj_priv = to_intel_bo(obj);
4243
4244         if (obj_priv->pin_count) {
4245                 ret = -EINVAL;
4246                 goto out;
4247         }
4248
4249         if (obj_priv->madv != __I915_MADV_PURGED)
4250                 obj_priv->madv = args->madv;
4251
4252         /* if the object is no longer bound, discard its backing storage */
4253         if (i915_gem_object_is_purgeable(obj_priv) &&
4254             obj_priv->gtt_space == NULL)
4255                 i915_gem_object_truncate(obj);
4256
4257         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4258
4259 out:
4260         drm_gem_object_unreference(obj);
4261 unlock:
4262         mutex_unlock(&dev->struct_mutex);
4263         return ret;
4264 }
4265
4266 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4267                                               size_t size)
4268 {
4269         struct drm_i915_private *dev_priv = dev->dev_private;
4270         struct drm_i915_gem_object *obj;
4271
4272         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4273         if (obj == NULL)
4274                 return NULL;
4275
4276         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4277                 kfree(obj);
4278                 return NULL;
4279         }
4280
4281         i915_gem_info_add_obj(dev_priv, size);
4282
4283         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4284         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4285
4286         obj->agp_type = AGP_USER_MEMORY;
4287         obj->base.driver_private = NULL;
4288         obj->fence_reg = I915_FENCE_REG_NONE;
4289         INIT_LIST_HEAD(&obj->list);
4290         INIT_LIST_HEAD(&obj->gpu_write_list);
4291         obj->madv = I915_MADV_WILLNEED;
4292
4293         return &obj->base;
4294 }
4295
4296 int i915_gem_init_object(struct drm_gem_object *obj)
4297 {
4298         BUG();
4299
4300         return 0;
4301 }
4302
4303 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4304 {
4305         struct drm_device *dev = obj->dev;
4306         drm_i915_private_t *dev_priv = dev->dev_private;
4307         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4308         int ret;
4309
4310         ret = i915_gem_object_unbind(obj);
4311         if (ret == -ERESTARTSYS) {
4312                 list_move(&obj_priv->list,
4313                           &dev_priv->mm.deferred_free_list);
4314                 return;
4315         }
4316
4317         if (obj_priv->mmap_offset)
4318                 i915_gem_free_mmap_offset(obj);
4319
4320         drm_gem_object_release(obj);
4321         i915_gem_info_remove_obj(dev_priv, obj->size);
4322
4323         kfree(obj_priv->page_cpu_valid);
4324         kfree(obj_priv->bit_17);
4325         kfree(obj_priv);
4326 }
4327
4328 void i915_gem_free_object(struct drm_gem_object *obj)
4329 {
4330         struct drm_device *dev = obj->dev;
4331         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4332
4333         trace_i915_gem_object_destroy(obj);
4334
4335         while (obj_priv->pin_count > 0)
4336                 i915_gem_object_unpin(obj);
4337
4338         if (obj_priv->phys_obj)
4339                 i915_gem_detach_phys_object(dev, obj);
4340
4341         i915_gem_free_object_tail(obj);
4342 }
4343
4344 int
4345 i915_gem_idle(struct drm_device *dev)
4346 {
4347         drm_i915_private_t *dev_priv = dev->dev_private;
4348         int ret;
4349
4350         mutex_lock(&dev->struct_mutex);
4351
4352         if (dev_priv->mm.suspended ||
4353                         (dev_priv->render_ring.gem_object == NULL) ||
4354                         (HAS_BSD(dev) &&
4355                          dev_priv->bsd_ring.gem_object == NULL)) {
4356                 mutex_unlock(&dev->struct_mutex);
4357                 return 0;
4358         }
4359
4360         ret = i915_gpu_idle(dev);
4361         if (ret) {
4362                 mutex_unlock(&dev->struct_mutex);
4363                 return ret;
4364         }
4365
4366         /* Under UMS, be paranoid and evict. */
4367         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4368                 ret = i915_gem_evict_inactive(dev);
4369                 if (ret) {
4370                         mutex_unlock(&dev->struct_mutex);
4371                         return ret;
4372                 }
4373         }
4374
4375         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4376          * We need to replace this with a semaphore, or something.
4377          * And not confound mm.suspended!
4378          */
4379         dev_priv->mm.suspended = 1;
4380         del_timer_sync(&dev_priv->hangcheck_timer);
4381
4382         i915_kernel_lost_context(dev);
4383         i915_gem_cleanup_ringbuffer(dev);
4384
4385         mutex_unlock(&dev->struct_mutex);
4386
4387         /* Cancel the retire work handler, which should be idle now. */
4388         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4389
4390         return 0;
4391 }
4392
4393 /*
4394  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4395  * over cache flushing.
4396  */
4397 static int
4398 i915_gem_init_pipe_control(struct drm_device *dev)
4399 {
4400         drm_i915_private_t *dev_priv = dev->dev_private;
4401         struct drm_gem_object *obj;
4402         struct drm_i915_gem_object *obj_priv;
4403         int ret;
4404
4405         obj = i915_gem_alloc_object(dev, 4096);
4406         if (obj == NULL) {
4407                 DRM_ERROR("Failed to allocate seqno page\n");
4408                 ret = -ENOMEM;
4409                 goto err;
4410         }
4411         obj_priv = to_intel_bo(obj);
4412         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4413
4414         ret = i915_gem_object_pin(obj, 4096);
4415         if (ret)
4416                 goto err_unref;
4417
4418         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4419         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4420         if (dev_priv->seqno_page == NULL)
4421                 goto err_unpin;
4422
4423         dev_priv->seqno_obj = obj;
4424         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4425
4426         return 0;
4427
4428 err_unpin:
4429         i915_gem_object_unpin(obj);
4430 err_unref:
4431         drm_gem_object_unreference(obj);
4432 err:
4433         return ret;
4434 }
4435
4436
4437 static void
4438 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4439 {
4440         drm_i915_private_t *dev_priv = dev->dev_private;
4441         struct drm_gem_object *obj;
4442         struct drm_i915_gem_object *obj_priv;
4443
4444         obj = dev_priv->seqno_obj;
4445         obj_priv = to_intel_bo(obj);
4446         kunmap(obj_priv->pages[0]);
4447         i915_gem_object_unpin(obj);
4448         drm_gem_object_unreference(obj);
4449         dev_priv->seqno_obj = NULL;
4450
4451         dev_priv->seqno_page = NULL;
4452 }
4453
4454 int
4455 i915_gem_init_ringbuffer(struct drm_device *dev)
4456 {
4457         drm_i915_private_t *dev_priv = dev->dev_private;
4458         int ret;
4459
4460         if (HAS_PIPE_CONTROL(dev)) {
4461                 ret = i915_gem_init_pipe_control(dev);
4462                 if (ret)
4463                         return ret;
4464         }
4465
4466         ret = intel_init_render_ring_buffer(dev);
4467         if (ret)
4468                 goto cleanup_pipe_control;
4469
4470         if (HAS_BSD(dev)) {
4471                 ret = intel_init_bsd_ring_buffer(dev);
4472                 if (ret)
4473                         goto cleanup_render_ring;
4474         }
4475
4476         dev_priv->next_seqno = 1;
4477
4478         return 0;
4479
4480 cleanup_render_ring:
4481         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4482 cleanup_pipe_control:
4483         if (HAS_PIPE_CONTROL(dev))
4484                 i915_gem_cleanup_pipe_control(dev);
4485         return ret;
4486 }
4487
4488 void
4489 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4490 {
4491         drm_i915_private_t *dev_priv = dev->dev_private;
4492
4493         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4494         if (HAS_BSD(dev))
4495                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4496         if (HAS_PIPE_CONTROL(dev))
4497                 i915_gem_cleanup_pipe_control(dev);
4498 }
4499
4500 int
4501 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4502                        struct drm_file *file_priv)
4503 {
4504         drm_i915_private_t *dev_priv = dev->dev_private;
4505         int ret;
4506
4507         if (drm_core_check_feature(dev, DRIVER_MODESET))
4508                 return 0;
4509
4510         if (atomic_read(&dev_priv->mm.wedged)) {
4511                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4512                 atomic_set(&dev_priv->mm.wedged, 0);
4513         }
4514
4515         mutex_lock(&dev->struct_mutex);
4516         dev_priv->mm.suspended = 0;
4517
4518         ret = i915_gem_init_ringbuffer(dev);
4519         if (ret != 0) {
4520                 mutex_unlock(&dev->struct_mutex);
4521                 return ret;
4522         }
4523
4524         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4525         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4526         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4527         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4528         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4529         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4530         mutex_unlock(&dev->struct_mutex);
4531
4532         ret = drm_irq_install(dev);
4533         if (ret)
4534                 goto cleanup_ringbuffer;
4535
4536         return 0;
4537
4538 cleanup_ringbuffer:
4539         mutex_lock(&dev->struct_mutex);
4540         i915_gem_cleanup_ringbuffer(dev);
4541         dev_priv->mm.suspended = 1;
4542         mutex_unlock(&dev->struct_mutex);
4543
4544         return ret;
4545 }
4546
4547 int
4548 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4549                        struct drm_file *file_priv)
4550 {
4551         if (drm_core_check_feature(dev, DRIVER_MODESET))
4552                 return 0;
4553
4554         drm_irq_uninstall(dev);
4555         return i915_gem_idle(dev);
4556 }
4557
4558 void
4559 i915_gem_lastclose(struct drm_device *dev)
4560 {
4561         int ret;
4562
4563         if (drm_core_check_feature(dev, DRIVER_MODESET))
4564                 return;
4565
4566         ret = i915_gem_idle(dev);
4567         if (ret)
4568                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4569 }
4570
4571 void
4572 i915_gem_load(struct drm_device *dev)
4573 {
4574         int i;
4575         drm_i915_private_t *dev_priv = dev->dev_private;
4576
4577         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4578         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4579         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4580         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4581         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4582         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4583         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4584         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4585         if (HAS_BSD(dev)) {
4586                 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4587                 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4588         }
4589         for (i = 0; i < 16; i++)
4590                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4591         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4592                           i915_gem_retire_work_handler);
4593         init_completion(&dev_priv->error_completion);
4594         spin_lock(&shrink_list_lock);
4595         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4596         spin_unlock(&shrink_list_lock);
4597
4598         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4599         if (IS_GEN3(dev)) {
4600                 u32 tmp = I915_READ(MI_ARB_STATE);
4601                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4602                         /* arb state is a masked write, so set bit + bit in mask */
4603                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4604                         I915_WRITE(MI_ARB_STATE, tmp);
4605                 }
4606         }
4607
4608         /* Old X drivers will take 0-2 for front, back, depth buffers */
4609         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4610                 dev_priv->fence_reg_start = 3;
4611
4612         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4613                 dev_priv->num_fence_regs = 16;
4614         else
4615                 dev_priv->num_fence_regs = 8;
4616
4617         /* Initialize fence registers to zero */
4618         switch (INTEL_INFO(dev)->gen) {
4619         case 6:
4620                 for (i = 0; i < 16; i++)
4621                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4622                 break;
4623         case 5:
4624         case 4:
4625                 for (i = 0; i < 16; i++)
4626                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4627                 break;
4628         case 3:
4629                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4630                         for (i = 0; i < 8; i++)
4631                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4632         case 2:
4633                 for (i = 0; i < 8; i++)
4634                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4635                 break;
4636         }
4637         i915_gem_detect_bit_6_swizzle(dev);
4638         init_waitqueue_head(&dev_priv->pending_flip_queue);
4639 }
4640
4641 /*
4642  * Create a physically contiguous memory object for this object
4643  * e.g. for cursor + overlay regs
4644  */
4645 static int i915_gem_init_phys_object(struct drm_device *dev,
4646                                      int id, int size, int align)
4647 {
4648         drm_i915_private_t *dev_priv = dev->dev_private;
4649         struct drm_i915_gem_phys_object *phys_obj;
4650         int ret;
4651
4652         if (dev_priv->mm.phys_objs[id - 1] || !size)
4653                 return 0;
4654
4655         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4656         if (!phys_obj)
4657                 return -ENOMEM;
4658
4659         phys_obj->id = id;
4660
4661         phys_obj->handle = drm_pci_alloc(dev, size, align);
4662         if (!phys_obj->handle) {
4663                 ret = -ENOMEM;
4664                 goto kfree_obj;
4665         }
4666 #ifdef CONFIG_X86
4667         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4668 #endif
4669
4670         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4671
4672         return 0;
4673 kfree_obj:
4674         kfree(phys_obj);
4675         return ret;
4676 }
4677
4678 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4679 {
4680         drm_i915_private_t *dev_priv = dev->dev_private;
4681         struct drm_i915_gem_phys_object *phys_obj;
4682
4683         if (!dev_priv->mm.phys_objs[id - 1])
4684                 return;
4685
4686         phys_obj = dev_priv->mm.phys_objs[id - 1];
4687         if (phys_obj->cur_obj) {
4688                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4689         }
4690
4691 #ifdef CONFIG_X86
4692         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4693 #endif
4694         drm_pci_free(dev, phys_obj->handle);
4695         kfree(phys_obj);
4696         dev_priv->mm.phys_objs[id - 1] = NULL;
4697 }
4698
4699 void i915_gem_free_all_phys_object(struct drm_device *dev)
4700 {
4701         int i;
4702
4703         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4704                 i915_gem_free_phys_object(dev, i);
4705 }
4706
4707 void i915_gem_detach_phys_object(struct drm_device *dev,
4708                                  struct drm_gem_object *obj)
4709 {
4710         struct drm_i915_gem_object *obj_priv;
4711         int i;
4712         int ret;
4713         int page_count;
4714
4715         obj_priv = to_intel_bo(obj);
4716         if (!obj_priv->phys_obj)
4717                 return;
4718
4719         ret = i915_gem_object_get_pages(obj, 0);
4720         if (ret)
4721                 goto out;
4722
4723         page_count = obj->size / PAGE_SIZE;
4724
4725         for (i = 0; i < page_count; i++) {
4726                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4727                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4728
4729                 memcpy(dst, src, PAGE_SIZE);
4730                 kunmap_atomic(dst, KM_USER0);
4731         }
4732         drm_clflush_pages(obj_priv->pages, page_count);
4733         drm_agp_chipset_flush(dev);
4734
4735         i915_gem_object_put_pages(obj);
4736 out:
4737         obj_priv->phys_obj->cur_obj = NULL;
4738         obj_priv->phys_obj = NULL;
4739 }
4740
4741 int
4742 i915_gem_attach_phys_object(struct drm_device *dev,
4743                             struct drm_gem_object *obj,
4744                             int id,
4745                             int align)
4746 {
4747         drm_i915_private_t *dev_priv = dev->dev_private;
4748         struct drm_i915_gem_object *obj_priv;
4749         int ret = 0;
4750         int page_count;
4751         int i;
4752
4753         if (id > I915_MAX_PHYS_OBJECT)
4754                 return -EINVAL;
4755
4756         obj_priv = to_intel_bo(obj);
4757
4758         if (obj_priv->phys_obj) {
4759                 if (obj_priv->phys_obj->id == id)
4760                         return 0;
4761                 i915_gem_detach_phys_object(dev, obj);
4762         }
4763
4764         /* create a new object */
4765         if (!dev_priv->mm.phys_objs[id - 1]) {
4766                 ret = i915_gem_init_phys_object(dev, id,
4767                                                 obj->size, align);
4768                 if (ret) {
4769                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4770                         goto out;
4771                 }
4772         }
4773
4774         /* bind to the object */
4775         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4776         obj_priv->phys_obj->cur_obj = obj;
4777
4778         ret = i915_gem_object_get_pages(obj, 0);
4779         if (ret) {
4780                 DRM_ERROR("failed to get page list\n");
4781                 goto out;
4782         }
4783
4784         page_count = obj->size / PAGE_SIZE;
4785
4786         for (i = 0; i < page_count; i++) {
4787                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4788                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4789
4790                 memcpy(dst, src, PAGE_SIZE);
4791                 kunmap_atomic(src, KM_USER0);
4792         }
4793
4794         i915_gem_object_put_pages(obj);
4795
4796         return 0;
4797 out:
4798         return ret;
4799 }
4800
4801 static int
4802 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4803                      struct drm_i915_gem_pwrite *args,
4804                      struct drm_file *file_priv)
4805 {
4806         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4807         void *obj_addr;
4808         int ret;
4809         char __user *user_data;
4810
4811         user_data = (char __user *) (uintptr_t) args->data_ptr;
4812         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4813
4814         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4815         ret = copy_from_user(obj_addr, user_data, args->size);
4816         if (ret)
4817                 return -EFAULT;
4818
4819         drm_agp_chipset_flush(dev);
4820         return 0;
4821 }
4822
4823 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4824 {
4825         struct drm_i915_file_private *file_priv = file->driver_priv;
4826
4827         /* Clean up our request list when the client is going away, so that
4828          * later retire_requests won't dereference our soon-to-be-gone
4829          * file_priv.
4830          */
4831         spin_lock(&file_priv->mm.lock);
4832         while (!list_empty(&file_priv->mm.request_list)) {
4833                 struct drm_i915_gem_request *request;
4834
4835                 request = list_first_entry(&file_priv->mm.request_list,
4836                                            struct drm_i915_gem_request,
4837                                            client_list);
4838                 list_del(&request->client_list);
4839                 request->file_priv = NULL;
4840         }
4841         spin_unlock(&file_priv->mm.lock);
4842 }
4843
4844 static int
4845 i915_gpu_is_active(struct drm_device *dev)
4846 {
4847         drm_i915_private_t *dev_priv = dev->dev_private;
4848         int lists_empty;
4849
4850         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4851                       list_empty(&dev_priv->render_ring.active_list);
4852         if (HAS_BSD(dev))
4853                 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4854
4855         return !lists_empty;
4856 }
4857
4858 static int
4859 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4860 {
4861         drm_i915_private_t *dev_priv, *next_dev;
4862         struct drm_i915_gem_object *obj_priv, *next_obj;
4863         int cnt = 0;
4864         int would_deadlock = 1;
4865
4866         /* "fast-path" to count number of available objects */
4867         if (nr_to_scan == 0) {
4868                 spin_lock(&shrink_list_lock);
4869                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4870                         struct drm_device *dev = dev_priv->dev;
4871
4872                         if (mutex_trylock(&dev->struct_mutex)) {
4873                                 list_for_each_entry(obj_priv,
4874                                                     &dev_priv->mm.inactive_list,
4875                                                     list)
4876                                         cnt++;
4877                                 mutex_unlock(&dev->struct_mutex);
4878                         }
4879                 }
4880                 spin_unlock(&shrink_list_lock);
4881
4882                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4883         }
4884
4885         spin_lock(&shrink_list_lock);
4886
4887 rescan:
4888         /* first scan for clean buffers */
4889         list_for_each_entry_safe(dev_priv, next_dev,
4890                                  &shrink_list, mm.shrink_list) {
4891                 struct drm_device *dev = dev_priv->dev;
4892
4893                 if (! mutex_trylock(&dev->struct_mutex))
4894                         continue;
4895
4896                 spin_unlock(&shrink_list_lock);
4897                 i915_gem_retire_requests(dev);
4898
4899                 list_for_each_entry_safe(obj_priv, next_obj,
4900                                          &dev_priv->mm.inactive_list,
4901                                          list) {
4902                         if (i915_gem_object_is_purgeable(obj_priv)) {
4903                                 i915_gem_object_unbind(&obj_priv->base);
4904                                 if (--nr_to_scan <= 0)
4905                                         break;
4906                         }
4907                 }
4908
4909                 spin_lock(&shrink_list_lock);
4910                 mutex_unlock(&dev->struct_mutex);
4911
4912                 would_deadlock = 0;
4913
4914                 if (nr_to_scan <= 0)
4915                         break;
4916         }
4917
4918         /* second pass, evict/count anything still on the inactive list */
4919         list_for_each_entry_safe(dev_priv, next_dev,
4920                                  &shrink_list, mm.shrink_list) {
4921                 struct drm_device *dev = dev_priv->dev;
4922
4923                 if (! mutex_trylock(&dev->struct_mutex))
4924                         continue;
4925
4926                 spin_unlock(&shrink_list_lock);
4927
4928                 list_for_each_entry_safe(obj_priv, next_obj,
4929                                          &dev_priv->mm.inactive_list,
4930                                          list) {
4931                         if (nr_to_scan > 0) {
4932                                 i915_gem_object_unbind(&obj_priv->base);
4933                                 nr_to_scan--;
4934                         } else
4935                                 cnt++;
4936                 }
4937
4938                 spin_lock(&shrink_list_lock);
4939                 mutex_unlock(&dev->struct_mutex);
4940
4941                 would_deadlock = 0;
4942         }
4943
4944         if (nr_to_scan) {
4945                 int active = 0;
4946
4947                 /*
4948                  * We are desperate for pages, so as a last resort, wait
4949                  * for the GPU to finish and discard whatever we can.
4950                  * This has a dramatic impact to reduce the number of
4951                  * OOM-killer events whilst running the GPU aggressively.
4952                  */
4953                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4954                         struct drm_device *dev = dev_priv->dev;
4955
4956                         if (!mutex_trylock(&dev->struct_mutex))
4957                                 continue;
4958
4959                         spin_unlock(&shrink_list_lock);
4960
4961                         if (i915_gpu_is_active(dev)) {
4962                                 i915_gpu_idle(dev);
4963                                 active++;
4964                         }
4965
4966                         spin_lock(&shrink_list_lock);
4967                         mutex_unlock(&dev->struct_mutex);
4968                 }
4969
4970                 if (active)
4971                         goto rescan;
4972         }
4973
4974         spin_unlock(&shrink_list_lock);
4975
4976         if (would_deadlock)
4977                 return -1;
4978         else if (cnt > 0)
4979                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4980         else
4981                 return 0;
4982 }
4983
4984 static struct shrinker shrinker = {
4985         .shrink = i915_gem_shrink,
4986         .seeks = DEFAULT_SEEKS,
4987 };
4988
4989 __init void
4990 i915_gem_shrinker_init(void)
4991 {
4992     register_shrinker(&shrinker);
4993 }
4994
4995 __exit void
4996 i915_gem_shrinker_exit(void)
4997 {
4998     unregister_shrinker(&shrinker);
4999 }