drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                                           bool write);
  43 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                                   uint64_t offset,
  45                                                                   uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                                     unsigned alignment,
  49                                                     bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     int nr_to_scan,
  60                                     gfp_t gfp_mask);
  61
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 static int
  79 i915_gem_wait_for_error(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         if (atomic_read(&dev_priv->mm.wedged)) {
  94                 /* GPU is hung, bump the completion count to account for
  95                  * the token we just consumed so that we never hit zero and
  96                  * end up waiting upon a subsequent completion event that
  97                  * will never happen.
  98                  */
  99                 spin_lock_irqsave(&x->wait.lock, flags);
 100                 x->done++;
 101                 spin_unlock_irqrestore(&x->wait.lock, flags);
 102         }
 103         return 0;
 104 }
 105
 106 int i915_mutex_lock_interruptible(struct drm_device *dev)
 107 {
 108         int ret;
 109
 110         ret = i915_gem_wait_for_error(dev);
 111         if (ret)
 112                 return ret;
 113
 114         ret = mutex_lock_interruptible(&dev->struct_mutex);
 115         if (ret)
 116                 return ret;
 117
 118         WARN_ON(i915_verify_lists(dev));
 119         return 0;
 120 }
 121
 122 static inline bool
 123 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 124 {
 125         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 126 }
 127
 128 void i915_gem_do_init(struct drm_device *dev,
 129                       unsigned long start,
 130                       unsigned long mappable_end,
 131                       unsigned long end)
 132 {
 133         drm_i915_private_t *dev_priv = dev->dev_private;
 134
 135         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 136
 137         dev_priv->mm.gtt_start = start;
 138         dev_priv->mm.gtt_mappable_end = mappable_end;
 139         dev_priv->mm.gtt_end = end;
 140         dev_priv->mm.gtt_total = end - start;
 141         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 142
 143         /* Take over this portion of the GTT */
 144         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 145 }
 146
 147 int
 148 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 149                     struct drm_file *file)
 150 {
 151         struct drm_i915_gem_init *args = data;
 152
 153         if (args->gtt_start >= args->gtt_end ||
 154             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 155                 return -EINVAL;
 156
 157         mutex_lock(&dev->struct_mutex);
 158         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 159         mutex_unlock(&dev->struct_mutex);
 160
 161         return 0;
 162 }
 163
 164 int
 165 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 166                             struct drm_file *file)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         struct drm_i915_gem_get_aperture *args = data;
 170         struct drm_i915_gem_object *obj;
 171         size_t pinned;
 172
 173         if (!(dev->driver->driver_features & DRIVER_GEM))
 174                 return -ENODEV;
 175
 176         pinned = 0;
 177         mutex_lock(&dev->struct_mutex);
 178         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 179                 pinned += obj->gtt_space->size;
 180         mutex_unlock(&dev->struct_mutex);
 181
 182         args->aper_size = dev_priv->mm.gtt_total;
 183         args->aper_available_size = args->aper_size -pinned;
 184
 185         return 0;
 186 }
 187
 188 /**
 189  * Creates a new mm object and returns a handle to it.
 190  */
 191 int
 192 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 193                       struct drm_file *file)
 194 {
 195         struct drm_i915_gem_create *args = data;
 196         struct drm_i915_gem_object *obj;
 197         int ret;
 198         u32 handle;
 199
 200         args->size = roundup(args->size, PAGE_SIZE);
 201
 202         /* Allocate the new object */
 203         obj = i915_gem_alloc_object(dev, args->size);
 204         if (obj == NULL)
 205                 return -ENOMEM;
 206
 207         ret = drm_gem_handle_create(file, &obj->base, &handle);
 208         if (ret) {
 209                 drm_gem_object_release(&obj->base);
 210                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 211                 kfree(obj);
 212                 return ret;
 213         }
 214
 215         /* drop reference from allocate - handle holds it now */
 216         drm_gem_object_unreference(&obj->base);
 217         trace_i915_gem_object_create(obj);
 218
 219         args->handle = handle;
 220         return 0;
 221 }
 222
 223 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 224 {
 225         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 226
 227         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 228                 obj->tiling_mode != I915_TILING_NONE;
 229 }
 230
 231 static inline void
 232 slow_shmem_copy(struct page *dst_page,
 233                 int dst_offset,
 234                 struct page *src_page,
 235                 int src_offset,
 236                 int length)
 237 {
 238         char *dst_vaddr, *src_vaddr;
 239
 240         dst_vaddr = kmap(dst_page);
 241         src_vaddr = kmap(src_page);
 242
 243         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 244
 245         kunmap(src_page);
 246         kunmap(dst_page);
 247 }
 248
 249 static inline void
 250 slow_shmem_bit17_copy(struct page *gpu_page,
 251                       int gpu_offset,
 252                       struct page *cpu_page,
 253                       int cpu_offset,
 254                       int length,
 255                       int is_read)
 256 {
 257         char *gpu_vaddr, *cpu_vaddr;
 258
 259         /* Use the unswizzled path if this page isn't affected. */
 260         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 261                 if (is_read)
 262                         return slow_shmem_copy(cpu_page, cpu_offset,
 263                                                gpu_page, gpu_offset, length);
 264                 else
 265                         return slow_shmem_copy(gpu_page, gpu_offset,
 266                                                cpu_page, cpu_offset, length);
 267         }
 268
 269         gpu_vaddr = kmap(gpu_page);
 270         cpu_vaddr = kmap(cpu_page);
 271
 272         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 273          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 274          */
 275         while (length > 0) {
 276                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 277                 int this_length = min(cacheline_end - gpu_offset, length);
 278                 int swizzled_gpu_offset = gpu_offset ^ 64;
 279
 280                 if (is_read) {
 281                         memcpy(cpu_vaddr + cpu_offset,
 282                                gpu_vaddr + swizzled_gpu_offset,
 283                                this_length);
 284                 } else {
 285                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 286                                cpu_vaddr + cpu_offset,
 287                                this_length);
 288                 }
 289                 cpu_offset += this_length;
 290                 gpu_offset += this_length;
 291                 length -= this_length;
 292         }
 293
 294         kunmap(cpu_page);
 295         kunmap(gpu_page);
 296 }
 297
 298 /**
 299  * This is the fast shmem pread path, which attempts to copy_from_user directly
 300  * from the backing pages of the object to the user's address space.  On a
 301  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 302  */
 303 static int
 304 i915_gem_shmem_pread_fast(struct drm_device *dev,
 305                           struct drm_i915_gem_object *obj,
 306                           struct drm_i915_gem_pread *args,
 307                           struct drm_file *file)
 308 {
 309         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 310         ssize_t remain;
 311         loff_t offset;
 312         char __user *user_data;
 313         int page_offset, page_length;
 314
 315         user_data = (char __user *) (uintptr_t) args->data_ptr;
 316         remain = args->size;
 317
 318         offset = args->offset;
 319
 320         while (remain > 0) {
 321                 struct page *page;
 322                 char *vaddr;
 323                 int ret;
 324
 325                 /* Operation in this page
 326                  *
 327                  * page_offset = offset within page
 328                  * page_length = bytes to copy for this page
 329                  */
 330                 page_offset = offset & (PAGE_SIZE-1);
 331                 page_length = remain;
 332                 if ((page_offset + remain) > PAGE_SIZE)
 333                         page_length = PAGE_SIZE - page_offset;
 334
 335                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 336                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 337                 if (IS_ERR(page))
 338                         return PTR_ERR(page);
 339
 340                 vaddr = kmap_atomic(page);
 341                 ret = __copy_to_user_inatomic(user_data,
 342                                               vaddr + page_offset,
 343                                               page_length);
 344                 kunmap_atomic(vaddr);
 345
 346                 mark_page_accessed(page);
 347                 page_cache_release(page);
 348                 if (ret)
 349                         return -EFAULT;
 350
 351                 remain -= page_length;
 352                 user_data += page_length;
 353                 offset += page_length;
 354         }
 355
 356         return 0;
 357 }
 358
 359 /**
 360  * This is the fallback shmem pread path, which allocates temporary storage
 361  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 362  * can copy out of the object's backing pages while holding the struct mutex
 363  * and not take page faults.
 364  */
 365 static int
 366 i915_gem_shmem_pread_slow(struct drm_device *dev,
 367                           struct drm_i915_gem_object *obj,
 368                           struct drm_i915_gem_pread *args,
 369                           struct drm_file *file)
 370 {
 371         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 372         struct mm_struct *mm = current->mm;
 373         struct page **user_pages;
 374         ssize_t remain;
 375         loff_t offset, pinned_pages, i;
 376         loff_t first_data_page, last_data_page, num_pages;
 377         int shmem_page_offset;
 378         int data_page_index, data_page_offset;
 379         int page_length;
 380         int ret;
 381         uint64_t data_ptr = args->data_ptr;
 382         int do_bit17_swizzling;
 383
 384         remain = args->size;
 385
 386         /* Pin the user pages containing the data.  We can't fault while
 387          * holding the struct mutex, yet we want to hold it while
 388          * dereferencing the user data.
 389          */
 390         first_data_page = data_ptr / PAGE_SIZE;
 391         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 392         num_pages = last_data_page - first_data_page + 1;
 393
 394         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 395         if (user_pages == NULL)
 396                 return -ENOMEM;
 397
 398         mutex_unlock(&dev->struct_mutex);
 399         down_read(&mm->mmap_sem);
 400         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 401                                       num_pages, 1, 0, user_pages, NULL);
 402         up_read(&mm->mmap_sem);
 403         mutex_lock(&dev->struct_mutex);
 404         if (pinned_pages < num_pages) {
 405                 ret = -EFAULT;
 406                 goto out;
 407         }
 408
 409         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 410                                                         args->offset,
 411                                                         args->size);
 412         if (ret)
 413                 goto out;
 414
 415         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 416
 417         offset = args->offset;
 418
 419         while (remain > 0) {
 420                 struct page *page;
 421
 422                 /* Operation in this page
 423                  *
 424                  * shmem_page_offset = offset within page in shmem file
 425                  * data_page_index = page number in get_user_pages return
 426                  * data_page_offset = offset with data_page_index page.
 427                  * page_length = bytes to copy for this page
 428                  */
 429                 shmem_page_offset = offset & ~PAGE_MASK;
 430                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 431                 data_page_offset = data_ptr & ~PAGE_MASK;
 432
 433                 page_length = remain;
 434                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 435                         page_length = PAGE_SIZE - shmem_page_offset;
 436                 if ((data_page_offset + page_length) > PAGE_SIZE)
 437                         page_length = PAGE_SIZE - data_page_offset;
 438
 439                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 440                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 441                 if (IS_ERR(page))
 442                         return PTR_ERR(page);
 443
 444                 if (do_bit17_swizzling) {
 445                         slow_shmem_bit17_copy(page,
 446                                               shmem_page_offset,
 447                                               user_pages[data_page_index],
 448                                               data_page_offset,
 449                                               page_length,
 450                                               1);
 451                 } else {
 452                         slow_shmem_copy(user_pages[data_page_index],
 453                                         data_page_offset,
 454                                         page,
 455                                         shmem_page_offset,
 456                                         page_length);
 457                 }
 458
 459                 mark_page_accessed(page);
 460                 page_cache_release(page);
 461
 462                 remain -= page_length;
 463                 data_ptr += page_length;
 464                 offset += page_length;
 465         }
 466
 467 out:
 468         for (i = 0; i < pinned_pages; i++) {
 469                 SetPageDirty(user_pages[i]);
 470                 mark_page_accessed(user_pages[i]);
 471                 page_cache_release(user_pages[i]);
 472         }
 473         drm_free_large(user_pages);
 474
 475         return ret;
 476 }
 477
 478 /**
 479  * Reads data from the object referenced by handle.
 480  *
 481  * On error, the contents of *data are undefined.
 482  */
 483 int
 484 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 485                      struct drm_file *file)
 486 {
 487         struct drm_i915_gem_pread *args = data;
 488         struct drm_i915_gem_object *obj;
 489         int ret = 0;
 490
 491         if (args->size == 0)
 492                 return 0;
 493
 494         if (!access_ok(VERIFY_WRITE,
 495                        (char __user *)(uintptr_t)args->data_ptr,
 496                        args->size))
 497                 return -EFAULT;
 498
 499         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 500                                        args->size);
 501         if (ret)
 502                 return -EFAULT;
 503
 504         ret = i915_mutex_lock_interruptible(dev);
 505         if (ret)
 506                 return ret;
 507
 508         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 509         if (&obj->base == NULL) {
 510                 ret = -ENOENT;
 511                 goto unlock;
 512         }
 513
 514         /* Bounds check source.  */
 515         if (args->offset > obj->base.size ||
 516             args->size > obj->base.size - args->offset) {
 517                 ret = -EINVAL;
 518                 goto out;
 519         }
 520
 521         trace_i915_gem_object_pread(obj, args->offset, args->size);
 522
 523         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 524                                                         args->offset,
 525                                                         args->size);
 526         if (ret)
 527                 goto out;
 528
 529         ret = -EFAULT;
 530         if (!i915_gem_object_needs_bit17_swizzle(obj))
 531                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 532         if (ret == -EFAULT)
 533                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 534
 535 out:
 536         drm_gem_object_unreference(&obj->base);
 537 unlock:
 538         mutex_unlock(&dev->struct_mutex);
 539         return ret;
 540 }
 541
 542 /* This is the fast write path which cannot handle
 543  * page faults in the source data
 544  */
 545
 546 static inline int
 547 fast_user_write(struct io_mapping *mapping,
 548                 loff_t page_base, int page_offset,
 549                 char __user *user_data,
 550                 int length)
 551 {
 552         char *vaddr_atomic;
 553         unsigned long unwritten;
 554
 555         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 556         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 557                                                       user_data, length);
 558         io_mapping_unmap_atomic(vaddr_atomic);
 559         return unwritten;
 560 }
 561
 562 /* Here's the write path which can sleep for
 563  * page faults
 564  */
 565
 566 static inline void
 567 slow_kernel_write(struct io_mapping *mapping,
 568                   loff_t gtt_base, int gtt_offset,
 569                   struct page *user_page, int user_offset,
 570                   int length)
 571 {
 572         char __iomem *dst_vaddr;
 573         char *src_vaddr;
 574
 575         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 576         src_vaddr = kmap(user_page);
 577
 578         memcpy_toio(dst_vaddr + gtt_offset,
 579                     src_vaddr + user_offset,
 580                     length);
 581
 582         kunmap(user_page);
 583         io_mapping_unmap(dst_vaddr);
 584 }
 585
 586 /**
 587  * This is the fast pwrite path, where we copy the data directly from the
 588  * user into the GTT, uncached.
 589  */
 590 static int
 591 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 592                          struct drm_i915_gem_object *obj,
 593                          struct drm_i915_gem_pwrite *args,
 594                          struct drm_file *file)
 595 {
 596         drm_i915_private_t *dev_priv = dev->dev_private;
 597         ssize_t remain;
 598         loff_t offset, page_base;
 599         char __user *user_data;
 600         int page_offset, page_length;
 601
 602         user_data = (char __user *) (uintptr_t) args->data_ptr;
 603         remain = args->size;
 604
 605         offset = obj->gtt_offset + args->offset;
 606
 607         while (remain > 0) {
 608                 /* Operation in this page
 609                  *
 610                  * page_base = page offset within aperture
 611                  * page_offset = offset within page
 612                  * page_length = bytes to copy for this page
 613                  */
 614                 page_base = (offset & ~(PAGE_SIZE-1));
 615                 page_offset = offset & (PAGE_SIZE-1);
 616                 page_length = remain;
 617                 if ((page_offset + remain) > PAGE_SIZE)
 618                         page_length = PAGE_SIZE - page_offset;
 619
 620                 /* If we get a fault while copying data, then (presumably) our
 621                  * source page isn't available.  Return the error and we'll
 622                  * retry in the slow path.
 623                  */
 624                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 625                                     page_offset, user_data, page_length))
 626
 627                         return -EFAULT;
 628
 629                 remain -= page_length;
 630                 user_data += page_length;
 631                 offset += page_length;
 632         }
 633
 634         return 0;
 635 }
 636
 637 /**
 638  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 639  * the memory and maps it using kmap_atomic for copying.
 640  *
 641  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 642  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 643  */
 644 static int
 645 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 646                          struct drm_i915_gem_object *obj,
 647                          struct drm_i915_gem_pwrite *args,
 648                          struct drm_file *file)
 649 {
 650         drm_i915_private_t *dev_priv = dev->dev_private;
 651         ssize_t remain;
 652         loff_t gtt_page_base, offset;
 653         loff_t first_data_page, last_data_page, num_pages;
 654         loff_t pinned_pages, i;
 655         struct page **user_pages;
 656         struct mm_struct *mm = current->mm;
 657         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 658         int ret;
 659         uint64_t data_ptr = args->data_ptr;
 660
 661         remain = args->size;
 662
 663         /* Pin the user pages containing the data.  We can't fault while
 664          * holding the struct mutex, and all of the pwrite implementations
 665          * want to hold it while dereferencing the user data.
 666          */
 667         first_data_page = data_ptr / PAGE_SIZE;
 668         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 669         num_pages = last_data_page - first_data_page + 1;
 670
 671         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 672         if (user_pages == NULL)
 673                 return -ENOMEM;
 674
 675         mutex_unlock(&dev->struct_mutex);
 676         down_read(&mm->mmap_sem);
 677         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 678                                       num_pages, 0, 0, user_pages, NULL);
 679         up_read(&mm->mmap_sem);
 680         mutex_lock(&dev->struct_mutex);
 681         if (pinned_pages < num_pages) {
 682                 ret = -EFAULT;
 683                 goto out_unpin_pages;
 684         }
 685
 686         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 687         if (ret)
 688                 goto out_unpin_pages;
 689
 690         ret = i915_gem_object_put_fence(obj);
 691         if (ret)
 692                 goto out_unpin_pages;
 693
 694         offset = obj->gtt_offset + args->offset;
 695
 696         while (remain > 0) {
 697                 /* Operation in this page
 698                  *
 699                  * gtt_page_base = page offset within aperture
 700                  * gtt_page_offset = offset within page in aperture
 701                  * data_page_index = page number in get_user_pages return
 702                  * data_page_offset = offset with data_page_index page.
 703                  * page_length = bytes to copy for this page
 704                  */
 705                 gtt_page_base = offset & PAGE_MASK;
 706                 gtt_page_offset = offset & ~PAGE_MASK;
 707                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 708                 data_page_offset = data_ptr & ~PAGE_MASK;
 709
 710                 page_length = remain;
 711                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 712                         page_length = PAGE_SIZE - gtt_page_offset;
 713                 if ((data_page_offset + page_length) > PAGE_SIZE)
 714                         page_length = PAGE_SIZE - data_page_offset;
 715
 716                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 717                                   gtt_page_base, gtt_page_offset,
 718                                   user_pages[data_page_index],
 719                                   data_page_offset,
 720                                   page_length);
 721
 722                 remain -= page_length;
 723                 offset += page_length;
 724                 data_ptr += page_length;
 725         }
 726
 727 out_unpin_pages:
 728         for (i = 0; i < pinned_pages; i++)
 729                 page_cache_release(user_pages[i]);
 730         drm_free_large(user_pages);
 731
 732         return ret;
 733 }
 734
 735 /**
 736  * This is the fast shmem pwrite path, which attempts to directly
 737  * copy_from_user into the kmapped pages backing the object.
 738  */
 739 static int
 740 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 741                            struct drm_i915_gem_object *obj,
 742                            struct drm_i915_gem_pwrite *args,
 743                            struct drm_file *file)
 744 {
 745         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 746         ssize_t remain;
 747         loff_t offset;
 748         char __user *user_data;
 749         int page_offset, page_length;
 750
 751         user_data = (char __user *) (uintptr_t) args->data_ptr;
 752         remain = args->size;
 753
 754         offset = args->offset;
 755         obj->dirty = 1;
 756
 757         while (remain > 0) {
 758                 struct page *page;
 759                 char *vaddr;
 760                 int ret;
 761
 762                 /* Operation in this page
 763                  *
 764                  * page_offset = offset within page
 765                  * page_length = bytes to copy for this page
 766                  */
 767                 page_offset = offset & (PAGE_SIZE-1);
 768                 page_length = remain;
 769                 if ((page_offset + remain) > PAGE_SIZE)
 770                         page_length = PAGE_SIZE - page_offset;
 771
 772                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 773                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 774                 if (IS_ERR(page))
 775                         return PTR_ERR(page);
 776
 777                 vaddr = kmap_atomic(page, KM_USER0);
 778                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 779                                                 user_data,
 780                                                 page_length);
 781                 kunmap_atomic(vaddr, KM_USER0);
 782
 783                 set_page_dirty(page);
 784                 mark_page_accessed(page);
 785                 page_cache_release(page);
 786
 787                 /* If we get a fault while copying data, then (presumably) our
 788                  * source page isn't available.  Return the error and we'll
 789                  * retry in the slow path.
 790                  */
 791                 if (ret)
 792                         return -EFAULT;
 793
 794                 remain -= page_length;
 795                 user_data += page_length;
 796                 offset += page_length;
 797         }
 798
 799         return 0;
 800 }
 801
 802 /**
 803  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 804  * the memory and maps it using kmap_atomic for copying.
 805  *
 806  * This avoids taking mmap_sem for faulting on the user's address while the
 807  * struct_mutex is held.
 808  */
 809 static int
 810 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 811                            struct drm_i915_gem_object *obj,
 812                            struct drm_i915_gem_pwrite *args,
 813                            struct drm_file *file)
 814 {
 815         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 816         struct mm_struct *mm = current->mm;
 817         struct page **user_pages;
 818         ssize_t remain;
 819         loff_t offset, pinned_pages, i;
 820         loff_t first_data_page, last_data_page, num_pages;
 821         int shmem_page_offset;
 822         int data_page_index,  data_page_offset;
 823         int page_length;
 824         int ret;
 825         uint64_t data_ptr = args->data_ptr;
 826         int do_bit17_swizzling;
 827
 828         remain = args->size;
 829
 830         /* Pin the user pages containing the data.  We can't fault while
 831          * holding the struct mutex, and all of the pwrite implementations
 832          * want to hold it while dereferencing the user data.
 833          */
 834         first_data_page = data_ptr / PAGE_SIZE;
 835         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 836         num_pages = last_data_page - first_data_page + 1;
 837
 838         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 839         if (user_pages == NULL)
 840                 return -ENOMEM;
 841
 842         mutex_unlock(&dev->struct_mutex);
 843         down_read(&mm->mmap_sem);
 844         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 845                                       num_pages, 0, 0, user_pages, NULL);
 846         up_read(&mm->mmap_sem);
 847         mutex_lock(&dev->struct_mutex);
 848         if (pinned_pages < num_pages) {
 849                 ret = -EFAULT;
 850                 goto out;
 851         }
 852
 853         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 854         if (ret)
 855                 goto out;
 856
 857         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 858
 859         offset = args->offset;
 860         obj->dirty = 1;
 861
 862         while (remain > 0) {
 863                 struct page *page;
 864
 865                 /* Operation in this page
 866                  *
 867                  * shmem_page_offset = offset within page in shmem file
 868                  * data_page_index = page number in get_user_pages return
 869                  * data_page_offset = offset with data_page_index page.
 870                  * page_length = bytes to copy for this page
 871                  */
 872                 shmem_page_offset = offset & ~PAGE_MASK;
 873                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 874                 data_page_offset = data_ptr & ~PAGE_MASK;
 875
 876                 page_length = remain;
 877                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 878                         page_length = PAGE_SIZE - shmem_page_offset;
 879                 if ((data_page_offset + page_length) > PAGE_SIZE)
 880                         page_length = PAGE_SIZE - data_page_offset;
 881
 882                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 883                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 884                 if (IS_ERR(page)) {
 885                         ret = PTR_ERR(page);
 886                         goto out;
 887                 }
 888
 889                 if (do_bit17_swizzling) {
 890                         slow_shmem_bit17_copy(page,
 891                                               shmem_page_offset,
 892                                               user_pages[data_page_index],
 893                                               data_page_offset,
 894                                               page_length,
 895                                               0);
 896                 } else {
 897                         slow_shmem_copy(page,
 898                                         shmem_page_offset,
 899                                         user_pages[data_page_index],
 900                                         data_page_offset,
 901                                         page_length);
 902                 }
 903
 904                 set_page_dirty(page);
 905                 mark_page_accessed(page);
 906                 page_cache_release(page);
 907
 908                 remain -= page_length;
 909                 data_ptr += page_length;
 910                 offset += page_length;
 911         }
 912
 913 out:
 914         for (i = 0; i < pinned_pages; i++)
 915                 page_cache_release(user_pages[i]);
 916         drm_free_large(user_pages);
 917
 918         return ret;
 919 }
 920
 921 /**
 922  * Writes data to the object referenced by handle.
 923  *
 924  * On error, the contents of the buffer that were to be modified are undefined.
 925  */
 926 int
 927 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 928                       struct drm_file *file)
 929 {
 930         struct drm_i915_gem_pwrite *args = data;
 931         struct drm_i915_gem_object *obj;
 932         int ret;
 933
 934         if (args->size == 0)
 935                 return 0;
 936
 937         if (!access_ok(VERIFY_READ,
 938                        (char __user *)(uintptr_t)args->data_ptr,
 939                        args->size))
 940                 return -EFAULT;
 941
 942         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 943                                       args->size);
 944         if (ret)
 945                 return -EFAULT;
 946
 947         ret = i915_mutex_lock_interruptible(dev);
 948         if (ret)
 949                 return ret;
 950
 951         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 952         if (&obj->base == NULL) {
 953                 ret = -ENOENT;
 954                 goto unlock;
 955         }
 956
 957         /* Bounds check destination. */
 958         if (args->offset > obj->base.size ||
 959             args->size > obj->base.size - args->offset) {
 960                 ret = -EINVAL;
 961                 goto out;
 962         }
 963
 964         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 965
 966         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 967          * it would end up going through the fenced access, and we'll get
 968          * different detiling behavior between reading and writing.
 969          * pread/pwrite currently are reading and writing from the CPU
 970          * perspective, requiring manual detiling by the client.
 971          */
 972         if (obj->phys_obj)
 973                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 974         else if (obj->gtt_space &&
 975                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 976                 ret = i915_gem_object_pin(obj, 0, true);
 977                 if (ret)
 978                         goto out;
 979
 980                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
 981                 if (ret)
 982                         goto out_unpin;
 983
 984                 ret = i915_gem_object_put_fence(obj);
 985                 if (ret)
 986                         goto out_unpin;
 987
 988                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 989                 if (ret == -EFAULT)
 990                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
 991
 992 out_unpin:
 993                 i915_gem_object_unpin(obj);
 994         } else {
 995                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 996                 if (ret)
 997                         goto out;
 998
 999                 ret = -EFAULT;
1000                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1001                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1002                 if (ret == -EFAULT)
1003                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1004         }
1005
1006 out:
1007         drm_gem_object_unreference(&obj->base);
1008 unlock:
1009         mutex_unlock(&dev->struct_mutex);
1010         return ret;
1011 }
1012
1013 /**
1014  * Called when user space prepares to use an object with the CPU, either
1015  * through the mmap ioctl's mapping or a GTT mapping.
1016  */
1017 int
1018 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1019                           struct drm_file *file)
1020 {
1021         struct drm_i915_gem_set_domain *args = data;
1022         struct drm_i915_gem_object *obj;
1023         uint32_t read_domains = args->read_domains;
1024         uint32_t write_domain = args->write_domain;
1025         int ret;
1026
1027         if (!(dev->driver->driver_features & DRIVER_GEM))
1028                 return -ENODEV;
1029
1030         /* Only handle setting domains to types used by the CPU. */
1031         if (write_domain & I915_GEM_GPU_DOMAINS)
1032                 return -EINVAL;
1033
1034         if (read_domains & I915_GEM_GPU_DOMAINS)
1035                 return -EINVAL;
1036
1037         /* Having something in the write domain implies it's in the read
1038          * domain, and only that read domain.  Enforce that in the request.
1039          */
1040         if (write_domain != 0 && read_domains != write_domain)
1041                 return -EINVAL;
1042
1043         ret = i915_mutex_lock_interruptible(dev);
1044         if (ret)
1045                 return ret;
1046
1047         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1048         if (&obj->base == NULL) {
1049                 ret = -ENOENT;
1050                 goto unlock;
1051         }
1052
1053         if (read_domains & I915_GEM_DOMAIN_GTT) {
1054                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1055
1056                 /* Silently promote "you're not bound, there was nothing to do"
1057                  * to success, since the client was just asking us to
1058                  * make sure everything was done.
1059                  */
1060                 if (ret == -EINVAL)
1061                         ret = 0;
1062         } else {
1063                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1064         }
1065
1066         drm_gem_object_unreference(&obj->base);
1067 unlock:
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space has done writes to this buffer
1074  */
1075 int
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077                          struct drm_file *file)
1078 {
1079         struct drm_i915_gem_sw_finish *args = data;
1080         struct drm_i915_gem_object *obj;
1081         int ret = 0;
1082
1083         if (!(dev->driver->driver_features & DRIVER_GEM))
1084                 return -ENODEV;
1085
1086         ret = i915_mutex_lock_interruptible(dev);
1087         if (ret)
1088                 return ret;
1089
1090         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1091         if (&obj->base == NULL) {
1092                 ret = -ENOENT;
1093                 goto unlock;
1094         }
1095
1096         /* Pinned buffers may be scanout, so flush the cache */
1097         if (obj->pin_count)
1098                 i915_gem_object_flush_cpu_write_domain(obj);
1099
1100         drm_gem_object_unreference(&obj->base);
1101 unlock:
1102         mutex_unlock(&dev->struct_mutex);
1103         return ret;
1104 }
1105
1106 /**
1107  * Maps the contents of an object, returning the address it is mapped
1108  * into.
1109  *
1110  * While the mapping holds a reference on the contents of the object, it doesn't
1111  * imply a ref on the object itself.
1112  */
1113 int
1114 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1115                     struct drm_file *file)
1116 {
1117         struct drm_i915_private *dev_priv = dev->dev_private;
1118         struct drm_i915_gem_mmap *args = data;
1119         struct drm_gem_object *obj;
1120         unsigned long addr;
1121
1122         if (!(dev->driver->driver_features & DRIVER_GEM))
1123                 return -ENODEV;
1124
1125         obj = drm_gem_object_lookup(dev, file, args->handle);
1126         if (obj == NULL)
1127                 return -ENOENT;
1128
1129         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1130                 drm_gem_object_unreference_unlocked(obj);
1131                 return -E2BIG;
1132         }
1133
1134         down_write(&current->mm->mmap_sem);
1135         addr = do_mmap(obj->filp, 0, args->size,
1136                        PROT_READ | PROT_WRITE, MAP_SHARED,
1137                        args->offset);
1138         up_write(&current->mm->mmap_sem);
1139         drm_gem_object_unreference_unlocked(obj);
1140         if (IS_ERR((void *)addr))
1141                 return addr;
1142
1143         args->addr_ptr = (uint64_t) addr;
1144
1145         return 0;
1146 }
1147
1148 /**
1149  * i915_gem_fault - fault a page into the GTT
1150  * vma: VMA in question
1151  * vmf: fault info
1152  *
1153  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154  * from userspace.  The fault handler takes care of binding the object to
1155  * the GTT (if needed), allocating and programming a fence register (again,
1156  * only if needed based on whether the old reg is still valid or the object
1157  * is tiled) and inserting a new PTE into the faulting process.
1158  *
1159  * Note that the faulting process may involve evicting existing objects
1160  * from the GTT and/or fence registers to make room.  So performance may
1161  * suffer if the GTT working set is large or there are few fence registers
1162  * left.
1163  */
1164 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1165 {
1166         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1167         struct drm_device *dev = obj->base.dev;
1168         drm_i915_private_t *dev_priv = dev->dev_private;
1169         pgoff_t page_offset;
1170         unsigned long pfn;
1171         int ret = 0;
1172         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1173
1174         /* We don't use vmf->pgoff since that has the fake offset */
1175         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1176                 PAGE_SHIFT;
1177
1178         ret = i915_mutex_lock_interruptible(dev);
1179         if (ret)
1180                 goto out;
1181
1182         trace_i915_gem_object_fault(obj, page_offset, true, write);
1183
1184         /* Now bind it into the GTT if needed */
1185         if (!obj->map_and_fenceable) {
1186                 ret = i915_gem_object_unbind(obj);
1187                 if (ret)
1188                         goto unlock;
1189         }
1190         if (!obj->gtt_space) {
1191                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1192                 if (ret)
1193                         goto unlock;
1194         }
1195
1196         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1197         if (ret)
1198                 goto unlock;
1199
1200         if (obj->tiling_mode == I915_TILING_NONE)
1201                 ret = i915_gem_object_put_fence(obj);
1202         else
1203                 ret = i915_gem_object_get_fence(obj, NULL);
1204         if (ret)
1205                 goto unlock;
1206
1207         if (i915_gem_object_is_inactive(obj))
1208                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1209
1210         obj->fault_mappable = true;
1211
1212         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1213                 page_offset;
1214
1215         /* Finally, remap it using the new GTT offset */
1216         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1217 unlock:
1218         mutex_unlock(&dev->struct_mutex);
1219 out:
1220         switch (ret) {
1221         case -EIO:
1222         case -EAGAIN:
1223                 /* Give the error handler a chance to run and move the
1224                  * objects off the GPU active list. Next time we service the
1225                  * fault, we should be able to transition the page into the
1226                  * GTT without touching the GPU (and so avoid further
1227                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1228                  * with coherency, just lost writes.
1229                  */
1230                 set_need_resched();
1231         case 0:
1232         case -ERESTARTSYS:
1233         case -EINTR:
1234                 return VM_FAULT_NOPAGE;
1235         case -ENOMEM:
1236                 return VM_FAULT_OOM;
1237         default:
1238                 return VM_FAULT_SIGBUS;
1239         }
1240 }
1241
1242 /**
1243  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1244  * @obj: obj in question
1245  *
1246  * GEM memory mapping works by handing back to userspace a fake mmap offset
1247  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1248  * up the object based on the offset and sets up the various memory mapping
1249  * structures.
1250  *
1251  * This routine allocates and attaches a fake offset for @obj.
1252  */
1253 static int
1254 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1255 {
1256         struct drm_device *dev = obj->base.dev;
1257         struct drm_gem_mm *mm = dev->mm_private;
1258         struct drm_map_list *list;
1259         struct drm_local_map *map;
1260         int ret = 0;
1261
1262         /* Set the object up for mmap'ing */
1263         list = &obj->base.map_list;
1264         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1265         if (!list->map)
1266                 return -ENOMEM;
1267
1268         map = list->map;
1269         map->type = _DRM_GEM;
1270         map->size = obj->base.size;
1271         map->handle = obj;
1272
1273         /* Get a DRM GEM mmap offset allocated... */
1274         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1275                                                     obj->base.size / PAGE_SIZE,
1276                                                     0, 0);
1277         if (!list->file_offset_node) {
1278                 DRM_ERROR("failed to allocate offset for bo %d\n",
1279                           obj->base.name);
1280                 ret = -ENOSPC;
1281                 goto out_free_list;
1282         }
1283
1284         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1285                                                   obj->base.size / PAGE_SIZE,
1286                                                   0);
1287         if (!list->file_offset_node) {
1288                 ret = -ENOMEM;
1289                 goto out_free_list;
1290         }
1291
1292         list->hash.key = list->file_offset_node->start;
1293         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1294         if (ret) {
1295                 DRM_ERROR("failed to add to map hash\n");
1296                 goto out_free_mm;
1297         }
1298
1299         return 0;
1300
1301 out_free_mm:
1302         drm_mm_put_block(list->file_offset_node);
1303 out_free_list:
1304         kfree(list->map);
1305         list->map = NULL;
1306
1307         return ret;
1308 }
1309
1310 /**
1311  * i915_gem_release_mmap - remove physical page mappings
1312  * @obj: obj in question
1313  *
1314  * Preserve the reservation of the mmapping with the DRM core code, but
1315  * relinquish ownership of the pages back to the system.
1316  *
1317  * It is vital that we remove the page mapping if we have mapped a tiled
1318  * object through the GTT and then lose the fence register due to
1319  * resource pressure. Similarly if the object has been moved out of the
1320  * aperture, than pages mapped into userspace must be revoked. Removing the
1321  * mapping will then trigger a page fault on the next user access, allowing
1322  * fixup by i915_gem_fault().
1323  */
1324 void
1325 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1326 {
1327         if (!obj->fault_mappable)
1328                 return;
1329
1330         unmap_mapping_range(obj->base.dev->dev_mapping,
1331                             (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1332                             obj->base.size, 1);
1333
1334         obj->fault_mappable = false;
1335 }
1336
1337 static void
1338 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1339 {
1340         struct drm_device *dev = obj->base.dev;
1341         struct drm_gem_mm *mm = dev->mm_private;
1342         struct drm_map_list *list = &obj->base.map_list;
1343
1344         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1345         drm_mm_put_block(list->file_offset_node);
1346         kfree(list->map);
1347         list->map = NULL;
1348 }
1349
1350 static uint32_t
1351 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1352 {
1353         struct drm_device *dev = obj->base.dev;
1354         uint32_t size;
1355
1356         if (INTEL_INFO(dev)->gen >= 4 ||
1357             obj->tiling_mode == I915_TILING_NONE)
1358                 return obj->base.size;
1359
1360         /* Previous chips need a power-of-two fence region when tiling */
1361         if (INTEL_INFO(dev)->gen == 3)
1362                 size = 1024*1024;
1363         else
1364                 size = 512*1024;
1365
1366         while (size < obj->base.size)
1367                 size <<= 1;
1368
1369         return size;
1370 }
1371
1372 /**
1373  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1374  * @obj: object to check
1375  *
1376  * Return the required GTT alignment for an object, taking into account
1377  * potential fence register mapping.
1378  */
1379 static uint32_t
1380 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1381 {
1382         struct drm_device *dev = obj->base.dev;
1383
1384         /*
1385          * Minimum alignment is 4k (GTT page size), but might be greater
1386          * if a fence register is needed for the object.
1387          */
1388         if (INTEL_INFO(dev)->gen >= 4 ||
1389             obj->tiling_mode == I915_TILING_NONE)
1390                 return 4096;
1391
1392         /*
1393          * Previous chips need to be aligned to the size of the smallest
1394          * fence register that can contain the object.
1395          */
1396         return i915_gem_get_gtt_size(obj);
1397 }
1398
1399 /**
1400  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1401  *                                       unfenced object
1402  * @obj: object to check
1403  *
1404  * Return the required GTT alignment for an object, only taking into account
1405  * unfenced tiled surface requirements.
1406  */
1407 static uint32_t
1408 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1409 {
1410         struct drm_device *dev = obj->base.dev;
1411         int tile_height;
1412
1413         /*
1414          * Minimum alignment is 4k (GTT page size) for sane hw.
1415          */
1416         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1417             obj->tiling_mode == I915_TILING_NONE)
1418                 return 4096;
1419
1420         /*
1421          * Older chips need unfenced tiled buffers to be aligned to the left
1422          * edge of an even tile row (where tile rows are counted as if the bo is
1423          * placed in a fenced gtt region).
1424          */
1425         if (IS_GEN2(dev) ||
1426             (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1427                 tile_height = 32;
1428         else
1429                 tile_height = 8;
1430
1431         return tile_height * obj->stride * 2;
1432 }
1433
1434 /**
1435  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1436  * @dev: DRM device
1437  * @data: GTT mapping ioctl data
1438  * @file: GEM object info
1439  *
1440  * Simply returns the fake offset to userspace so it can mmap it.
1441  * The mmap call will end up in drm_gem_mmap(), which will set things
1442  * up so we can get faults in the handler above.
1443  *
1444  * The fault handler will take care of binding the object into the GTT
1445  * (since it may have been evicted to make room for something), allocating
1446  * a fence register, and mapping the appropriate aperture address into
1447  * userspace.
1448  */
1449 int
1450 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1451                         struct drm_file *file)
1452 {
1453         struct drm_i915_private *dev_priv = dev->dev_private;
1454         struct drm_i915_gem_mmap_gtt *args = data;
1455         struct drm_i915_gem_object *obj;
1456         int ret;
1457
1458         if (!(dev->driver->driver_features & DRIVER_GEM))
1459                 return -ENODEV;
1460
1461         ret = i915_mutex_lock_interruptible(dev);
1462         if (ret)
1463                 return ret;
1464
1465         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1466         if (&obj->base == NULL) {
1467                 ret = -ENOENT;
1468                 goto unlock;
1469         }
1470
1471         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1472                 ret = -E2BIG;
1473                 goto unlock;
1474         }
1475
1476         if (obj->madv != I915_MADV_WILLNEED) {
1477                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1478                 ret = -EINVAL;
1479                 goto out;
1480         }
1481
1482         if (!obj->base.map_list.map) {
1483                 ret = i915_gem_create_mmap_offset(obj);
1484                 if (ret)
1485                         goto out;
1486         }
1487
1488         args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1489
1490 out:
1491         drm_gem_object_unreference(&obj->base);
1492 unlock:
1493         mutex_unlock(&dev->struct_mutex);
1494         return ret;
1495 }
1496
1497 static int
1498 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1499                               gfp_t gfpmask)
1500 {
1501         int page_count, i;
1502         struct address_space *mapping;
1503         struct inode *inode;
1504         struct page *page;
1505
1506         /* Get the list of pages out of our struct file.  They'll be pinned
1507          * at this point until we release them.
1508          */
1509         page_count = obj->base.size / PAGE_SIZE;
1510         BUG_ON(obj->pages != NULL);
1511         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1512         if (obj->pages == NULL)
1513                 return -ENOMEM;
1514
1515         inode = obj->base.filp->f_path.dentry->d_inode;
1516         mapping = inode->i_mapping;
1517         for (i = 0; i < page_count; i++) {
1518                 page = read_cache_page_gfp(mapping, i,
1519                                            GFP_HIGHUSER |
1520                                            __GFP_COLD |
1521                                            __GFP_RECLAIMABLE |
1522                                            gfpmask);
1523                 if (IS_ERR(page))
1524                         goto err_pages;
1525
1526                 obj->pages[i] = page;
1527         }
1528
1529         if (obj->tiling_mode != I915_TILING_NONE)
1530                 i915_gem_object_do_bit_17_swizzle(obj);
1531
1532         return 0;
1533
1534 err_pages:
1535         while (i--)
1536                 page_cache_release(obj->pages[i]);
1537
1538         drm_free_large(obj->pages);
1539         obj->pages = NULL;
1540         return PTR_ERR(page);
1541 }
1542
1543 static void
1544 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1545 {
1546         int page_count = obj->base.size / PAGE_SIZE;
1547         int i;
1548
1549         BUG_ON(obj->madv == __I915_MADV_PURGED);
1550
1551         if (obj->tiling_mode != I915_TILING_NONE)
1552                 i915_gem_object_save_bit_17_swizzle(obj);
1553
1554         if (obj->madv == I915_MADV_DONTNEED)
1555                 obj->dirty = 0;
1556
1557         for (i = 0; i < page_count; i++) {
1558                 if (obj->dirty)
1559                         set_page_dirty(obj->pages[i]);
1560
1561                 if (obj->madv == I915_MADV_WILLNEED)
1562                         mark_page_accessed(obj->pages[i]);
1563
1564                 page_cache_release(obj->pages[i]);
1565         }
1566         obj->dirty = 0;
1567
1568         drm_free_large(obj->pages);
1569         obj->pages = NULL;
1570 }
1571
1572 void
1573 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1574                                struct intel_ring_buffer *ring,
1575                                u32 seqno)
1576 {
1577         struct drm_device *dev = obj->base.dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579
1580         BUG_ON(ring == NULL);
1581         obj->ring = ring;
1582
1583         /* Add a reference if we're newly entering the active list. */
1584         if (!obj->active) {
1585                 drm_gem_object_reference(&obj->base);
1586                 obj->active = 1;
1587         }
1588
1589         /* Move from whatever list we were on to the tail of execution. */
1590         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1591         list_move_tail(&obj->ring_list, &ring->active_list);
1592
1593         obj->last_rendering_seqno = seqno;
1594         if (obj->fenced_gpu_access) {
1595                 struct drm_i915_fence_reg *reg;
1596
1597                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1598
1599                 obj->last_fenced_seqno = seqno;
1600                 obj->last_fenced_ring = ring;
1601
1602                 reg = &dev_priv->fence_regs[obj->fence_reg];
1603                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1604         }
1605 }
1606
1607 static void
1608 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1609 {
1610         list_del_init(&obj->ring_list);
1611         obj->last_rendering_seqno = 0;
1612 }
1613
1614 static void
1615 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1616 {
1617         struct drm_device *dev = obj->base.dev;
1618         drm_i915_private_t *dev_priv = dev->dev_private;
1619
1620         BUG_ON(!obj->active);
1621         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1622
1623         i915_gem_object_move_off_active(obj);
1624 }
1625
1626 static void
1627 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1628 {
1629         struct drm_device *dev = obj->base.dev;
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631
1632         if (obj->pin_count != 0)
1633                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1634         else
1635                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1636
1637         BUG_ON(!list_empty(&obj->gpu_write_list));
1638         BUG_ON(!obj->active);
1639         obj->ring = NULL;
1640
1641         i915_gem_object_move_off_active(obj);
1642         obj->fenced_gpu_access = false;
1643
1644         obj->active = 0;
1645         obj->pending_gpu_write = false;
1646         drm_gem_object_unreference(&obj->base);
1647
1648         WARN_ON(i915_verify_lists(dev));
1649 }
1650
1651 /* Immediately discard the backing storage */
1652 static void
1653 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1654 {
1655         struct inode *inode;
1656
1657         /* Our goal here is to return as much of the memory as
1658          * is possible back to the system as we are called from OOM.
1659          * To do this we must instruct the shmfs to drop all of its
1660          * backing pages, *now*. Here we mirror the actions taken
1661          * when by shmem_delete_inode() to release the backing store.
1662          */
1663         inode = obj->base.filp->f_path.dentry->d_inode;
1664         truncate_inode_pages(inode->i_mapping, 0);
1665         if (inode->i_op->truncate_range)
1666                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1667
1668         obj->madv = __I915_MADV_PURGED;
1669 }
1670
1671 static inline int
1672 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1673 {
1674         return obj->madv == I915_MADV_DONTNEED;
1675 }
1676
1677 static void
1678 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1679                                uint32_t flush_domains)
1680 {
1681         struct drm_i915_gem_object *obj, *next;
1682
1683         list_for_each_entry_safe(obj, next,
1684                                  &ring->gpu_write_list,
1685                                  gpu_write_list) {
1686                 if (obj->base.write_domain & flush_domains) {
1687                         uint32_t old_write_domain = obj->base.write_domain;
1688
1689                         obj->base.write_domain = 0;
1690                         list_del_init(&obj->gpu_write_list);
1691                         i915_gem_object_move_to_active(obj, ring,
1692                                                        i915_gem_next_request_seqno(ring));
1693
1694                         trace_i915_gem_object_change_domain(obj,
1695                                                             obj->base.read_domains,
1696                                                             old_write_domain);
1697                 }
1698         }
1699 }
1700
1701 int
1702 i915_add_request(struct intel_ring_buffer *ring,
1703                  struct drm_file *file,
1704                  struct drm_i915_gem_request *request)
1705 {
1706         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1707         uint32_t seqno;
1708         int was_empty;
1709         int ret;
1710
1711         BUG_ON(request == NULL);
1712
1713         ret = ring->add_request(ring, &seqno);
1714         if (ret)
1715             return ret;
1716
1717         trace_i915_gem_request_add(ring, seqno);
1718
1719         request->seqno = seqno;
1720         request->ring = ring;
1721         request->emitted_jiffies = jiffies;
1722         was_empty = list_empty(&ring->request_list);
1723         list_add_tail(&request->list, &ring->request_list);
1724
1725         if (file) {
1726                 struct drm_i915_file_private *file_priv = file->driver_priv;
1727
1728                 spin_lock(&file_priv->mm.lock);
1729                 request->file_priv = file_priv;
1730                 list_add_tail(&request->client_list,
1731                               &file_priv->mm.request_list);
1732                 spin_unlock(&file_priv->mm.lock);
1733         }
1734
1735         ring->outstanding_lazy_request = false;
1736
1737         if (!dev_priv->mm.suspended) {
1738                 mod_timer(&dev_priv->hangcheck_timer,
1739                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1740                 if (was_empty)
1741                         queue_delayed_work(dev_priv->wq,
1742                                            &dev_priv->mm.retire_work, HZ);
1743         }
1744         return 0;
1745 }
1746
1747 static inline void
1748 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1749 {
1750         struct drm_i915_file_private *file_priv = request->file_priv;
1751
1752         if (!file_priv)
1753                 return;
1754
1755         spin_lock(&file_priv->mm.lock);
1756         list_del(&request->client_list);
1757         request->file_priv = NULL;
1758         spin_unlock(&file_priv->mm.lock);
1759 }
1760
1761 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1762                                       struct intel_ring_buffer *ring)
1763 {
1764         while (!list_empty(&ring->request_list)) {
1765                 struct drm_i915_gem_request *request;
1766
1767                 request = list_first_entry(&ring->request_list,
1768                                            struct drm_i915_gem_request,
1769                                            list);
1770
1771                 list_del(&request->list);
1772                 i915_gem_request_remove_from_client(request);
1773                 kfree(request);
1774         }
1775
1776         while (!list_empty(&ring->active_list)) {
1777                 struct drm_i915_gem_object *obj;
1778
1779                 obj = list_first_entry(&ring->active_list,
1780                                        struct drm_i915_gem_object,
1781                                        ring_list);
1782
1783                 obj->base.write_domain = 0;
1784                 list_del_init(&obj->gpu_write_list);
1785                 i915_gem_object_move_to_inactive(obj);
1786         }
1787 }
1788
1789 static void i915_gem_reset_fences(struct drm_device *dev)
1790 {
1791         struct drm_i915_private *dev_priv = dev->dev_private;
1792         int i;
1793
1794         for (i = 0; i < 16; i++) {
1795                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1796                 struct drm_i915_gem_object *obj = reg->obj;
1797
1798                 if (!obj)
1799                         continue;
1800
1801                 if (obj->tiling_mode)
1802                         i915_gem_release_mmap(obj);
1803
1804                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1805                 reg->obj->fenced_gpu_access = false;
1806                 reg->obj->last_fenced_seqno = 0;
1807                 reg->obj->last_fenced_ring = NULL;
1808                 i915_gem_clear_fence_reg(dev, reg);
1809         }
1810 }
1811
1812 void i915_gem_reset(struct drm_device *dev)
1813 {
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815         struct drm_i915_gem_object *obj;
1816         int i;
1817
1818         for (i = 0; i < I915_NUM_RINGS; i++)
1819                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1820
1821         /* Remove anything from the flushing lists. The GPU cache is likely
1822          * to be lost on reset along with the data, so simply move the
1823          * lost bo to the inactive list.
1824          */
1825         while (!list_empty(&dev_priv->mm.flushing_list)) {
1826                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1827                                       struct drm_i915_gem_object,
1828                                       mm_list);
1829
1830                 obj->base.write_domain = 0;
1831                 list_del_init(&obj->gpu_write_list);
1832                 i915_gem_object_move_to_inactive(obj);
1833         }
1834
1835         /* Move everything out of the GPU domains to ensure we do any
1836          * necessary invalidation upon reuse.
1837          */
1838         list_for_each_entry(obj,
1839                             &dev_priv->mm.inactive_list,
1840                             mm_list)
1841         {
1842                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1843         }
1844
1845         /* The fence registers are invalidated so clear them out */
1846         i915_gem_reset_fences(dev);
1847 }
1848
1849 /**
1850  * This function clears the request list as sequence numbers are passed.
1851  */
1852 static void
1853 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1854 {
1855         uint32_t seqno;
1856         int i;
1857
1858         if (list_empty(&ring->request_list))
1859                 return;
1860
1861         WARN_ON(i915_verify_lists(ring->dev));
1862
1863         seqno = ring->get_seqno(ring);
1864
1865         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1866                 if (seqno >= ring->sync_seqno[i])
1867                         ring->sync_seqno[i] = 0;
1868
1869         while (!list_empty(&ring->request_list)) {
1870                 struct drm_i915_gem_request *request;
1871
1872                 request = list_first_entry(&ring->request_list,
1873                                            struct drm_i915_gem_request,
1874                                            list);
1875
1876                 if (!i915_seqno_passed(seqno, request->seqno))
1877                         break;
1878
1879                 trace_i915_gem_request_retire(ring, request->seqno);
1880
1881                 list_del(&request->list);
1882                 i915_gem_request_remove_from_client(request);
1883                 kfree(request);
1884         }
1885
1886         /* Move any buffers on the active list that are no longer referenced
1887          * by the ringbuffer to the flushing/inactive lists as appropriate.
1888          */
1889         while (!list_empty(&ring->active_list)) {
1890                 struct drm_i915_gem_object *obj;
1891
1892                 obj= list_first_entry(&ring->active_list,
1893                                       struct drm_i915_gem_object,
1894                                       ring_list);
1895
1896                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1897                         break;
1898
1899                 if (obj->base.write_domain != 0)
1900                         i915_gem_object_move_to_flushing(obj);
1901                 else
1902                         i915_gem_object_move_to_inactive(obj);
1903         }
1904
1905         if (unlikely(ring->trace_irq_seqno &&
1906                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1907                 ring->irq_put(ring);
1908                 ring->trace_irq_seqno = 0;
1909         }
1910
1911         WARN_ON(i915_verify_lists(ring->dev));
1912 }
1913
1914 void
1915 i915_gem_retire_requests(struct drm_device *dev)
1916 {
1917         drm_i915_private_t *dev_priv = dev->dev_private;
1918         int i;
1919
1920         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1921             struct drm_i915_gem_object *obj, *next;
1922
1923             /* We must be careful that during unbind() we do not
1924              * accidentally infinitely recurse into retire requests.
1925              * Currently:
1926              *   retire -> free -> unbind -> wait -> retire_ring
1927              */
1928             list_for_each_entry_safe(obj, next,
1929                                      &dev_priv->mm.deferred_free_list,
1930                                      mm_list)
1931                     i915_gem_free_object_tail(obj);
1932         }
1933
1934         for (i = 0; i < I915_NUM_RINGS; i++)
1935                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1936 }
1937
1938 static void
1939 i915_gem_retire_work_handler(struct work_struct *work)
1940 {
1941         drm_i915_private_t *dev_priv;
1942         struct drm_device *dev;
1943         bool idle;
1944         int i;
1945
1946         dev_priv = container_of(work, drm_i915_private_t,
1947                                 mm.retire_work.work);
1948         dev = dev_priv->dev;
1949
1950         /* Come back later if the device is busy... */
1951         if (!mutex_trylock(&dev->struct_mutex)) {
1952                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1953                 return;
1954         }
1955
1956         i915_gem_retire_requests(dev);
1957
1958         /* Send a periodic flush down the ring so we don't hold onto GEM
1959          * objects indefinitely.
1960          */
1961         idle = true;
1962         for (i = 0; i < I915_NUM_RINGS; i++) {
1963                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1964
1965                 if (!list_empty(&ring->gpu_write_list)) {
1966                         struct drm_i915_gem_request *request;
1967                         int ret;
1968
1969                         ret = i915_gem_flush_ring(ring,
1970                                                   0, I915_GEM_GPU_DOMAINS);
1971                         request = kzalloc(sizeof(*request), GFP_KERNEL);
1972                         if (ret || request == NULL ||
1973                             i915_add_request(ring, NULL, request))
1974                             kfree(request);
1975                 }
1976
1977                 idle &= list_empty(&ring->request_list);
1978         }
1979
1980         if (!dev_priv->mm.suspended && !idle)
1981                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1982
1983         mutex_unlock(&dev->struct_mutex);
1984 }
1985
1986 /**
1987  * Waits for a sequence number to be signaled, and cleans up the
1988  * request and object lists appropriately for that event.
1989  */
1990 int
1991 i915_wait_request(struct intel_ring_buffer *ring,
1992                   uint32_t seqno)
1993 {
1994         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1995         u32 ier;
1996         int ret = 0;
1997
1998         BUG_ON(seqno == 0);
1999
2000         if (atomic_read(&dev_priv->mm.wedged)) {
2001                 struct completion *x = &dev_priv->error_completion;
2002                 bool recovery_complete;
2003                 unsigned long flags;
2004
2005                 /* Give the error handler a chance to run. */
2006                 spin_lock_irqsave(&x->wait.lock, flags);
2007                 recovery_complete = x->done > 0;
2008                 spin_unlock_irqrestore(&x->wait.lock, flags);
2009
2010                 return recovery_complete ? -EIO : -EAGAIN;
2011         }
2012
2013         if (seqno == ring->outstanding_lazy_request) {
2014                 struct drm_i915_gem_request *request;
2015
2016                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2017                 if (request == NULL)
2018                         return -ENOMEM;
2019
2020                 ret = i915_add_request(ring, NULL, request);
2021                 if (ret) {
2022                         kfree(request);
2023                         return ret;
2024                 }
2025
2026                 seqno = request->seqno;
2027         }
2028
2029         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2030                 if (HAS_PCH_SPLIT(ring->dev))
2031                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2032                 else
2033                         ier = I915_READ(IER);
2034                 if (!ier) {
2035                         DRM_ERROR("something (likely vbetool) disabled "
2036                                   "interrupts, re-enabling\n");
2037                         i915_driver_irq_preinstall(ring->dev);
2038                         i915_driver_irq_postinstall(ring->dev);
2039                 }
2040
2041                 trace_i915_gem_request_wait_begin(ring, seqno);
2042
2043                 ring->waiting_seqno = seqno;
2044                 if (ring->irq_get(ring)) {
2045                         if (dev_priv->mm.interruptible)
2046                                 ret = wait_event_interruptible(ring->irq_queue,
2047                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2048                                                                || atomic_read(&dev_priv->mm.wedged));
2049                         else
2050                                 wait_event(ring->irq_queue,
2051                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2052                                            || atomic_read(&dev_priv->mm.wedged));
2053
2054                         ring->irq_put(ring);
2055                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2056                                                       seqno) ||
2057                                     atomic_read(&dev_priv->mm.wedged), 3000))
2058                         ret = -EBUSY;
2059                 ring->waiting_seqno = 0;
2060
2061                 trace_i915_gem_request_wait_end(ring, seqno);
2062         }
2063         if (atomic_read(&dev_priv->mm.wedged))
2064                 ret = -EAGAIN;
2065
2066         if (ret && ret != -ERESTARTSYS)
2067                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2068                           __func__, ret, seqno, ring->get_seqno(ring),
2069                           dev_priv->next_seqno);
2070
2071         /* Directly dispatch request retiring.  While we have the work queue
2072          * to handle this, the waiter on a request often wants an associated
2073          * buffer to have made it to the inactive list, and we would need
2074          * a separate wait queue to handle that.
2075          */
2076         if (ret == 0)
2077                 i915_gem_retire_requests_ring(ring);
2078
2079         return ret;
2080 }
2081
2082 /**
2083  * Ensures that all rendering to the object has completed and the object is
2084  * safe to unbind from the GTT or access from the CPU.
2085  */
2086 int
2087 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2088 {
2089         int ret;
2090
2091         /* This function only exists to support waiting for existing rendering,
2092          * not for emitting required flushes.
2093          */
2094         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2095
2096         /* If there is rendering queued on the buffer being evicted, wait for
2097          * it.
2098          */
2099         if (obj->active) {
2100                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2101                 if (ret)
2102                         return ret;
2103         }
2104
2105         return 0;
2106 }
2107
2108 /**
2109  * Unbinds an object from the GTT aperture.
2110  */
2111 int
2112 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2113 {
2114         int ret = 0;
2115
2116         if (obj->gtt_space == NULL)
2117                 return 0;
2118
2119         if (obj->pin_count != 0) {
2120                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2121                 return -EINVAL;
2122         }
2123
2124         /* blow away mappings if mapped through GTT */
2125         i915_gem_release_mmap(obj);
2126
2127         /* Move the object to the CPU domain to ensure that
2128          * any possible CPU writes while it's not in the GTT
2129          * are flushed when we go to remap it. This will
2130          * also ensure that all pending GPU writes are finished
2131          * before we unbind.
2132          */
2133         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2134         if (ret == -ERESTARTSYS)
2135                 return ret;
2136         /* Continue on if we fail due to EIO, the GPU is hung so we
2137          * should be safe and we need to cleanup or else we might
2138          * cause memory corruption through use-after-free.
2139          */
2140         if (ret) {
2141                 i915_gem_clflush_object(obj);
2142                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2143         }
2144
2145         /* release the fence reg _after_ flushing */
2146         ret = i915_gem_object_put_fence(obj);
2147         if (ret == -ERESTARTSYS)
2148                 return ret;
2149
2150         trace_i915_gem_object_unbind(obj);
2151
2152         i915_gem_gtt_unbind_object(obj);
2153         i915_gem_object_put_pages_gtt(obj);
2154
2155         list_del_init(&obj->gtt_list);
2156         list_del_init(&obj->mm_list);
2157         /* Avoid an unnecessary call to unbind on rebind. */
2158         obj->map_and_fenceable = true;
2159
2160         drm_mm_put_block(obj->gtt_space);
2161         obj->gtt_space = NULL;
2162         obj->gtt_offset = 0;
2163
2164         if (i915_gem_object_is_purgeable(obj))
2165                 i915_gem_object_truncate(obj);
2166
2167         return ret;
2168 }
2169
2170 int
2171 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2172                     uint32_t invalidate_domains,
2173                     uint32_t flush_domains)
2174 {
2175         int ret;
2176
2177         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2178
2179         ret = ring->flush(ring, invalidate_domains, flush_domains);
2180         if (ret)
2181                 return ret;
2182
2183         i915_gem_process_flushing_list(ring, flush_domains);
2184         return 0;
2185 }
2186
2187 static int i915_ring_idle(struct intel_ring_buffer *ring)
2188 {
2189         int ret;
2190
2191         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2192                 return 0;
2193
2194         if (!list_empty(&ring->gpu_write_list)) {
2195                 ret = i915_gem_flush_ring(ring,
2196                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2197                 if (ret)
2198                         return ret;
2199         }
2200
2201         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2202 }
2203
2204 int
2205 i915_gpu_idle(struct drm_device *dev)
2206 {
2207         drm_i915_private_t *dev_priv = dev->dev_private;
2208         bool lists_empty;
2209         int ret, i;
2210
2211         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2212                        list_empty(&dev_priv->mm.active_list));
2213         if (lists_empty)
2214                 return 0;
2215
2216         /* Flush everything onto the inactive list. */
2217         for (i = 0; i < I915_NUM_RINGS; i++) {
2218                 ret = i915_ring_idle(&dev_priv->ring[i]);
2219                 if (ret)
2220                         return ret;
2221         }
2222
2223         return 0;
2224 }
2225
2226 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2227                                        struct intel_ring_buffer *pipelined)
2228 {
2229         struct drm_device *dev = obj->base.dev;
2230         drm_i915_private_t *dev_priv = dev->dev_private;
2231         u32 size = obj->gtt_space->size;
2232         int regnum = obj->fence_reg;
2233         uint64_t val;
2234
2235         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2236                          0xfffff000) << 32;
2237         val |= obj->gtt_offset & 0xfffff000;
2238         val |= (uint64_t)((obj->stride / 128) - 1) <<
2239                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2240
2241         if (obj->tiling_mode == I915_TILING_Y)
2242                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2243         val |= I965_FENCE_REG_VALID;
2244
2245         if (pipelined) {
2246                 int ret = intel_ring_begin(pipelined, 6);
2247                 if (ret)
2248                         return ret;
2249
2250                 intel_ring_emit(pipelined, MI_NOOP);
2251                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2252                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2253                 intel_ring_emit(pipelined, (u32)val);
2254                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2255                 intel_ring_emit(pipelined, (u32)(val >> 32));
2256                 intel_ring_advance(pipelined);
2257         } else
2258                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2259
2260         return 0;
2261 }
2262
2263 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2264                                 struct intel_ring_buffer *pipelined)
2265 {
2266         struct drm_device *dev = obj->base.dev;
2267         drm_i915_private_t *dev_priv = dev->dev_private;
2268         u32 size = obj->gtt_space->size;
2269         int regnum = obj->fence_reg;
2270         uint64_t val;
2271
2272         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2273                     0xfffff000) << 32;
2274         val |= obj->gtt_offset & 0xfffff000;
2275         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2276         if (obj->tiling_mode == I915_TILING_Y)
2277                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2278         val |= I965_FENCE_REG_VALID;
2279
2280         if (pipelined) {
2281                 int ret = intel_ring_begin(pipelined, 6);
2282                 if (ret)
2283                         return ret;
2284
2285                 intel_ring_emit(pipelined, MI_NOOP);
2286                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2287                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2288                 intel_ring_emit(pipelined, (u32)val);
2289                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2290                 intel_ring_emit(pipelined, (u32)(val >> 32));
2291                 intel_ring_advance(pipelined);
2292         } else
2293                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2294
2295         return 0;
2296 }
2297
2298 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2299                                 struct intel_ring_buffer *pipelined)
2300 {
2301         struct drm_device *dev = obj->base.dev;
2302         drm_i915_private_t *dev_priv = dev->dev_private;
2303         u32 size = obj->gtt_space->size;
2304         u32 fence_reg, val, pitch_val;
2305         int tile_width;
2306
2307         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2308                  (size & -size) != size ||
2309                  (obj->gtt_offset & (size - 1)),
2310                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2311                  obj->gtt_offset, obj->map_and_fenceable, size))
2312                 return -EINVAL;
2313
2314         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2315                 tile_width = 128;
2316         else
2317                 tile_width = 512;
2318
2319         /* Note: pitch better be a power of two tile widths */
2320         pitch_val = obj->stride / tile_width;
2321         pitch_val = ffs(pitch_val) - 1;
2322
2323         val = obj->gtt_offset;
2324         if (obj->tiling_mode == I915_TILING_Y)
2325                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2326         val |= I915_FENCE_SIZE_BITS(size);
2327         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2328         val |= I830_FENCE_REG_VALID;
2329
2330         fence_reg = obj->fence_reg;
2331         if (fence_reg < 8)
2332                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2333         else
2334                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2335
2336         if (pipelined) {
2337                 int ret = intel_ring_begin(pipelined, 4);
2338                 if (ret)
2339                         return ret;
2340
2341                 intel_ring_emit(pipelined, MI_NOOP);
2342                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2343                 intel_ring_emit(pipelined, fence_reg);
2344                 intel_ring_emit(pipelined, val);
2345                 intel_ring_advance(pipelined);
2346         } else
2347                 I915_WRITE(fence_reg, val);
2348
2349         return 0;
2350 }
2351
2352 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2353                                 struct intel_ring_buffer *pipelined)
2354 {
2355         struct drm_device *dev = obj->base.dev;
2356         drm_i915_private_t *dev_priv = dev->dev_private;
2357         u32 size = obj->gtt_space->size;
2358         int regnum = obj->fence_reg;
2359         uint32_t val;
2360         uint32_t pitch_val;
2361
2362         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2363                  (size & -size) != size ||
2364                  (obj->gtt_offset & (size - 1)),
2365                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2366                  obj->gtt_offset, size))
2367                 return -EINVAL;
2368
2369         pitch_val = obj->stride / 128;
2370         pitch_val = ffs(pitch_val) - 1;
2371
2372         val = obj->gtt_offset;
2373         if (obj->tiling_mode == I915_TILING_Y)
2374                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2375         val |= I830_FENCE_SIZE_BITS(size);
2376         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2377         val |= I830_FENCE_REG_VALID;
2378
2379         if (pipelined) {
2380                 int ret = intel_ring_begin(pipelined, 4);
2381                 if (ret)
2382                         return ret;
2383
2384                 intel_ring_emit(pipelined, MI_NOOP);
2385                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2386                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2387                 intel_ring_emit(pipelined, val);
2388                 intel_ring_advance(pipelined);
2389         } else
2390                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2391
2392         return 0;
2393 }
2394
2395 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2396 {
2397         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2398 }
2399
2400 static int
2401 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2402                             struct intel_ring_buffer *pipelined)
2403 {
2404         int ret;
2405
2406         if (obj->fenced_gpu_access) {
2407                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2408                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2409                                                   0, obj->base.write_domain);
2410                         if (ret)
2411                                 return ret;
2412                 }
2413
2414                 obj->fenced_gpu_access = false;
2415         }
2416
2417         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2418                 if (!ring_passed_seqno(obj->last_fenced_ring,
2419                                        obj->last_fenced_seqno)) {
2420                         ret = i915_wait_request(obj->last_fenced_ring,
2421                                                 obj->last_fenced_seqno);
2422                         if (ret)
2423                                 return ret;
2424                 }
2425
2426                 obj->last_fenced_seqno = 0;
2427                 obj->last_fenced_ring = NULL;
2428         }
2429
2430         /* Ensure that all CPU reads are completed before installing a fence
2431          * and all writes before removing the fence.
2432          */
2433         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2434                 mb();
2435
2436         return 0;
2437 }
2438
2439 int
2440 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2441 {
2442         int ret;
2443
2444         if (obj->tiling_mode)
2445                 i915_gem_release_mmap(obj);
2446
2447         ret = i915_gem_object_flush_fence(obj, NULL);
2448         if (ret)
2449                 return ret;
2450
2451         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2452                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2453                 i915_gem_clear_fence_reg(obj->base.dev,
2454                                          &dev_priv->fence_regs[obj->fence_reg]);
2455
2456                 obj->fence_reg = I915_FENCE_REG_NONE;
2457         }
2458
2459         return 0;
2460 }
2461
2462 static struct drm_i915_fence_reg *
2463 i915_find_fence_reg(struct drm_device *dev,
2464                     struct intel_ring_buffer *pipelined)
2465 {
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct drm_i915_fence_reg *reg, *first, *avail;
2468         int i;
2469
2470         /* First try to find a free reg */
2471         avail = NULL;
2472         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2473                 reg = &dev_priv->fence_regs[i];
2474                 if (!reg->obj)
2475                         return reg;
2476
2477                 if (!reg->obj->pin_count)
2478                         avail = reg;
2479         }
2480
2481         if (avail == NULL)
2482                 return NULL;
2483
2484         /* None available, try to steal one or wait for a user to finish */
2485         avail = first = NULL;
2486         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2487                 if (reg->obj->pin_count)
2488                         continue;
2489
2490                 if (first == NULL)
2491                         first = reg;
2492
2493                 if (!pipelined ||
2494                     !reg->obj->last_fenced_ring ||
2495                     reg->obj->last_fenced_ring == pipelined) {
2496                         avail = reg;
2497                         break;
2498                 }
2499         }
2500
2501         if (avail == NULL)
2502                 avail = first;
2503
2504         return avail;
2505 }
2506
2507 /**
2508  * i915_gem_object_get_fence - set up a fence reg for an object
2509  * @obj: object to map through a fence reg
2510  * @pipelined: ring on which to queue the change, or NULL for CPU access
2511  * @interruptible: must we wait uninterruptibly for the register to retire?
2512  *
2513  * When mapping objects through the GTT, userspace wants to be able to write
2514  * to them without having to worry about swizzling if the object is tiled.
2515  *
2516  * This function walks the fence regs looking for a free one for @obj,
2517  * stealing one if it can't find any.
2518  *
2519  * It then sets up the reg based on the object's properties: address, pitch
2520  * and tiling format.
2521  */
2522 int
2523 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2524                           struct intel_ring_buffer *pipelined)
2525 {
2526         struct drm_device *dev = obj->base.dev;
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528         struct drm_i915_fence_reg *reg;
2529         int ret;
2530
2531         /* XXX disable pipelining. There are bugs. Shocking. */
2532         pipelined = NULL;
2533
2534         /* Just update our place in the LRU if our fence is getting reused. */
2535         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2536                 reg = &dev_priv->fence_regs[obj->fence_reg];
2537                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2538
2539                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2540                         pipelined = NULL;
2541
2542                 if (!pipelined) {
2543                         if (reg->setup_seqno) {
2544                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2545                                                        reg->setup_seqno)) {
2546                                         ret = i915_wait_request(obj->last_fenced_ring,
2547                                                                 reg->setup_seqno);
2548                                         if (ret)
2549                                                 return ret;
2550                                 }
2551
2552                                 reg->setup_seqno = 0;
2553                         }
2554                 } else if (obj->last_fenced_ring &&
2555                            obj->last_fenced_ring != pipelined) {
2556                         ret = i915_gem_object_flush_fence(obj, pipelined);
2557                         if (ret)
2558                                 return ret;
2559                 } else if (obj->tiling_changed) {
2560                         if (obj->fenced_gpu_access) {
2561                                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2562                                         ret = i915_gem_flush_ring(obj->ring,
2563                                                                   0, obj->base.write_domain);
2564                                         if (ret)
2565                                                 return ret;
2566                                 }
2567
2568                                 obj->fenced_gpu_access = false;
2569                         }
2570                 }
2571
2572                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2573                         pipelined = NULL;
2574                 BUG_ON(!pipelined && reg->setup_seqno);
2575
2576                 if (obj->tiling_changed) {
2577                         if (pipelined) {
2578                                 reg->setup_seqno =
2579                                         i915_gem_next_request_seqno(pipelined);
2580                                 obj->last_fenced_seqno = reg->setup_seqno;
2581                                 obj->last_fenced_ring = pipelined;
2582                         }
2583                         goto update;
2584                 }
2585
2586                 return 0;
2587         }
2588
2589         reg = i915_find_fence_reg(dev, pipelined);
2590         if (reg == NULL)
2591                 return -ENOSPC;
2592
2593         ret = i915_gem_object_flush_fence(obj, pipelined);
2594         if (ret)
2595                 return ret;
2596
2597         if (reg->obj) {
2598                 struct drm_i915_gem_object *old = reg->obj;
2599
2600                 drm_gem_object_reference(&old->base);
2601
2602                 if (old->tiling_mode)
2603                         i915_gem_release_mmap(old);
2604
2605                 ret = i915_gem_object_flush_fence(old, pipelined);
2606                 if (ret) {
2607                         drm_gem_object_unreference(&old->base);
2608                         return ret;
2609                 }
2610
2611                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2612                         pipelined = NULL;
2613
2614                 old->fence_reg = I915_FENCE_REG_NONE;
2615                 old->last_fenced_ring = pipelined;
2616                 old->last_fenced_seqno =
2617                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2618
2619                 drm_gem_object_unreference(&old->base);
2620         } else if (obj->last_fenced_seqno == 0)
2621                 pipelined = NULL;
2622
2623         reg->obj = obj;
2624         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2625         obj->fence_reg = reg - dev_priv->fence_regs;
2626         obj->last_fenced_ring = pipelined;
2627
2628         reg->setup_seqno =
2629                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2630         obj->last_fenced_seqno = reg->setup_seqno;
2631
2632 update:
2633         obj->tiling_changed = false;
2634         switch (INTEL_INFO(dev)->gen) {
2635         case 6:
2636                 ret = sandybridge_write_fence_reg(obj, pipelined);
2637                 break;
2638         case 5:
2639         case 4:
2640                 ret = i965_write_fence_reg(obj, pipelined);
2641                 break;
2642         case 3:
2643                 ret = i915_write_fence_reg(obj, pipelined);
2644                 break;
2645         case 2:
2646                 ret = i830_write_fence_reg(obj, pipelined);
2647                 break;
2648         }
2649
2650         return ret;
2651 }
2652
2653 /**
2654  * i915_gem_clear_fence_reg - clear out fence register info
2655  * @obj: object to clear
2656  *
2657  * Zeroes out the fence register itself and clears out the associated
2658  * data structures in dev_priv and obj.
2659  */
2660 static void
2661 i915_gem_clear_fence_reg(struct drm_device *dev,
2662                          struct drm_i915_fence_reg *reg)
2663 {
2664         drm_i915_private_t *dev_priv = dev->dev_private;
2665         uint32_t fence_reg = reg - dev_priv->fence_regs;
2666
2667         switch (INTEL_INFO(dev)->gen) {
2668         case 6:
2669                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2670                 break;
2671         case 5:
2672         case 4:
2673                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2674                 break;
2675         case 3:
2676                 if (fence_reg >= 8)
2677                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2678                 else
2679         case 2:
2680                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2681
2682                 I915_WRITE(fence_reg, 0);
2683                 break;
2684         }
2685
2686         list_del_init(&reg->lru_list);
2687         reg->obj = NULL;
2688         reg->setup_seqno = 0;
2689 }
2690
2691 /**
2692  * Finds free space in the GTT aperture and binds the object there.
2693  */
2694 static int
2695 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2696                             unsigned alignment,
2697                             bool map_and_fenceable)
2698 {
2699         struct drm_device *dev = obj->base.dev;
2700         drm_i915_private_t *dev_priv = dev->dev_private;
2701         struct drm_mm_node *free_space;
2702         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2703         u32 size, fence_size, fence_alignment, unfenced_alignment;
2704         bool mappable, fenceable;
2705         int ret;
2706
2707         if (obj->madv != I915_MADV_WILLNEED) {
2708                 DRM_ERROR("Attempting to bind a purgeable object\n");
2709                 return -EINVAL;
2710         }
2711
2712         fence_size = i915_gem_get_gtt_size(obj);
2713         fence_alignment = i915_gem_get_gtt_alignment(obj);
2714         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2715
2716         if (alignment == 0)
2717                 alignment = map_and_fenceable ? fence_alignment :
2718                                                 unfenced_alignment;
2719         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2720                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2721                 return -EINVAL;
2722         }
2723
2724         size = map_and_fenceable ? fence_size : obj->base.size;
2725
2726         /* If the object is bigger than the entire aperture, reject it early
2727          * before evicting everything in a vain attempt to find space.
2728          */
2729         if (obj->base.size >
2730             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2731                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2732                 return -E2BIG;
2733         }
2734
2735  search_free:
2736         if (map_and_fenceable)
2737                 free_space =
2738                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2739                                                     size, alignment, 0,
2740                                                     dev_priv->mm.gtt_mappable_end,
2741                                                     0);
2742         else
2743                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2744                                                 size, alignment, 0);
2745
2746         if (free_space != NULL) {
2747                 if (map_and_fenceable)
2748                         obj->gtt_space =
2749                                 drm_mm_get_block_range_generic(free_space,
2750                                                                size, alignment, 0,
2751                                                                dev_priv->mm.gtt_mappable_end,
2752                                                                0);
2753                 else
2754                         obj->gtt_space =
2755                                 drm_mm_get_block(free_space, size, alignment);
2756         }
2757         if (obj->gtt_space == NULL) {
2758                 /* If the gtt is empty and we're still having trouble
2759                  * fitting our object in, we're out of memory.
2760                  */
2761                 ret = i915_gem_evict_something(dev, size, alignment,
2762                                                map_and_fenceable);
2763                 if (ret)
2764                         return ret;
2765
2766                 goto search_free;
2767         }
2768
2769         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2770         if (ret) {
2771                 drm_mm_put_block(obj->gtt_space);
2772                 obj->gtt_space = NULL;
2773
2774                 if (ret == -ENOMEM) {
2775                         /* first try to reclaim some memory by clearing the GTT */
2776                         ret = i915_gem_evict_everything(dev, false);
2777                         if (ret) {
2778                                 /* now try to shrink everyone else */
2779                                 if (gfpmask) {
2780                                         gfpmask = 0;
2781                                         goto search_free;
2782                                 }
2783
2784                                 return -ENOMEM;
2785                         }
2786
2787                         goto search_free;
2788                 }
2789
2790                 return ret;
2791         }
2792
2793         ret = i915_gem_gtt_bind_object(obj);
2794         if (ret) {
2795                 i915_gem_object_put_pages_gtt(obj);
2796                 drm_mm_put_block(obj->gtt_space);
2797                 obj->gtt_space = NULL;
2798
2799                 if (i915_gem_evict_everything(dev, false))
2800                         return ret;
2801
2802                 goto search_free;
2803         }
2804
2805         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2806         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2807
2808         /* Assert that the object is not currently in any GPU domain. As it
2809          * wasn't in the GTT, there shouldn't be any way it could have been in
2810          * a GPU cache
2811          */
2812         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2813         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2814
2815         obj->gtt_offset = obj->gtt_space->start;
2816
2817         fenceable =
2818                 obj->gtt_space->size == fence_size &&
2819                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2820
2821         mappable =
2822                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2823
2824         obj->map_and_fenceable = mappable && fenceable;
2825
2826         trace_i915_gem_object_bind(obj, map_and_fenceable);
2827         return 0;
2828 }
2829
2830 void
2831 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2832 {
2833         /* If we don't have a page list set up, then we're not pinned
2834          * to GPU, and we can ignore the cache flush because it'll happen
2835          * again at bind time.
2836          */
2837         if (obj->pages == NULL)
2838                 return;
2839
2840         trace_i915_gem_object_clflush(obj);
2841
2842         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2843 }
2844
2845 /** Flushes any GPU write domain for the object if it's dirty. */
2846 static int
2847 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2848 {
2849         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2850                 return 0;
2851
2852         /* Queue the GPU write cache flushing we need. */
2853         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2854 }
2855
2856 /** Flushes the GTT write domain for the object if it's dirty. */
2857 static void
2858 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2859 {
2860         uint32_t old_write_domain;
2861
2862         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2863                 return;
2864
2865         /* No actual flushing is required for the GTT write domain.  Writes
2866          * to it immediately go to main memory as far as we know, so there's
2867          * no chipset flush.  It also doesn't land in render cache.
2868          *
2869          * However, we do have to enforce the order so that all writes through
2870          * the GTT land before any writes to the device, such as updates to
2871          * the GATT itself.
2872          */
2873         wmb();
2874
2875         i915_gem_release_mmap(obj);
2876
2877         old_write_domain = obj->base.write_domain;
2878         obj->base.write_domain = 0;
2879
2880         trace_i915_gem_object_change_domain(obj,
2881                                             obj->base.read_domains,
2882                                             old_write_domain);
2883 }
2884
2885 /** Flushes the CPU write domain for the object if it's dirty. */
2886 static void
2887 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2888 {
2889         uint32_t old_write_domain;
2890
2891         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2892                 return;
2893
2894         i915_gem_clflush_object(obj);
2895         intel_gtt_chipset_flush();
2896         old_write_domain = obj->base.write_domain;
2897         obj->base.write_domain = 0;
2898
2899         trace_i915_gem_object_change_domain(obj,
2900                                             obj->base.read_domains,
2901                                             old_write_domain);
2902 }
2903
2904 /**
2905  * Moves a single object to the GTT read, and possibly write domain.
2906  *
2907  * This function returns when the move is complete, including waiting on
2908  * flushes to occur.
2909  */
2910 int
2911 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2912 {
2913         uint32_t old_write_domain, old_read_domains;
2914         int ret;
2915
2916         /* Not valid to be called on unbound objects. */
2917         if (obj->gtt_space == NULL)
2918                 return -EINVAL;
2919
2920         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2921                 return 0;
2922
2923         ret = i915_gem_object_flush_gpu_write_domain(obj);
2924         if (ret)
2925                 return ret;
2926
2927         if (obj->pending_gpu_write || write) {
2928                 ret = i915_gem_object_wait_rendering(obj);
2929                 if (ret)
2930                         return ret;
2931         }
2932
2933         i915_gem_object_flush_cpu_write_domain(obj);
2934
2935         old_write_domain = obj->base.write_domain;
2936         old_read_domains = obj->base.read_domains;
2937
2938         /* It should now be out of any other write domains, and we can update
2939          * the domain values for our changes.
2940          */
2941         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2942         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2943         if (write) {
2944                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2945                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2946                 obj->dirty = 1;
2947         }
2948
2949         trace_i915_gem_object_change_domain(obj,
2950                                             old_read_domains,
2951                                             old_write_domain);
2952
2953         return 0;
2954 }
2955
2956 /*
2957  * Prepare buffer for display plane. Use uninterruptible for possible flush
2958  * wait, as in modesetting process we're not supposed to be interrupted.
2959  */
2960 int
2961 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
2962                                      struct intel_ring_buffer *pipelined)
2963 {
2964         uint32_t old_read_domains;
2965         int ret;
2966
2967         /* Not valid to be called on unbound objects. */
2968         if (obj->gtt_space == NULL)
2969                 return -EINVAL;
2970
2971         ret = i915_gem_object_flush_gpu_write_domain(obj);
2972         if (ret)
2973                 return ret;
2974
2975
2976         /* Currently, we are always called from an non-interruptible context. */
2977         if (pipelined != obj->ring) {
2978                 ret = i915_gem_object_wait_rendering(obj);
2979                 if (ret)
2980                         return ret;
2981         }
2982
2983         i915_gem_object_flush_cpu_write_domain(obj);
2984
2985         old_read_domains = obj->base.read_domains;
2986         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2987
2988         trace_i915_gem_object_change_domain(obj,
2989                                             old_read_domains,
2990                                             obj->base.write_domain);
2991
2992         return 0;
2993 }
2994
2995 int
2996 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
2997 {
2998         int ret;
2999
3000         if (!obj->active)
3001                 return 0;
3002
3003         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3004                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3005                 if (ret)
3006                         return ret;
3007         }
3008
3009         return i915_gem_object_wait_rendering(obj);
3010 }
3011
3012 /**
3013  * Moves a single object to the CPU read, and possibly write domain.
3014  *
3015  * This function returns when the move is complete, including waiting on
3016  * flushes to occur.
3017  */
3018 static int
3019 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3020 {
3021         uint32_t old_write_domain, old_read_domains;
3022         int ret;
3023
3024         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3025                 return 0;
3026
3027         ret = i915_gem_object_flush_gpu_write_domain(obj);
3028         if (ret)
3029                 return ret;
3030
3031         ret = i915_gem_object_wait_rendering(obj);
3032         if (ret)
3033                 return ret;
3034
3035         i915_gem_object_flush_gtt_write_domain(obj);
3036
3037         /* If we have a partially-valid cache of the object in the CPU,
3038          * finish invalidating it and free the per-page flags.
3039          */
3040         i915_gem_object_set_to_full_cpu_read_domain(obj);
3041
3042         old_write_domain = obj->base.write_domain;
3043         old_read_domains = obj->base.read_domains;
3044
3045         /* Flush the CPU cache if it's still invalid. */
3046         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3047                 i915_gem_clflush_object(obj);
3048
3049                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3050         }
3051
3052         /* It should now be out of any other write domains, and we can update
3053          * the domain values for our changes.
3054          */
3055         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3056
3057         /* If we're writing through the CPU, then the GPU read domains will
3058          * need to be invalidated at next use.
3059          */
3060         if (write) {
3061                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3062                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3063         }
3064
3065         trace_i915_gem_object_change_domain(obj,
3066                                             old_read_domains,
3067                                             old_write_domain);
3068
3069         return 0;
3070 }
3071
3072 /**
3073  * Moves the object from a partially CPU read to a full one.
3074  *
3075  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3076  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3077  */
3078 static void
3079 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3080 {
3081         if (!obj->page_cpu_valid)
3082                 return;
3083
3084         /* If we're partially in the CPU read domain, finish moving it in.
3085          */
3086         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3087                 int i;
3088
3089                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3090                         if (obj->page_cpu_valid[i])
3091                                 continue;
3092                         drm_clflush_pages(obj->pages + i, 1);
3093                 }
3094         }
3095
3096         /* Free the page_cpu_valid mappings which are now stale, whether
3097          * or not we've got I915_GEM_DOMAIN_CPU.
3098          */
3099         kfree(obj->page_cpu_valid);
3100         obj->page_cpu_valid = NULL;
3101 }
3102
3103 /**
3104  * Set the CPU read domain on a range of the object.
3105  *
3106  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3107  * not entirely valid.  The page_cpu_valid member of the object flags which
3108  * pages have been flushed, and will be respected by
3109  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3110  * of the whole object.
3111  *
3112  * This function returns when the move is complete, including waiting on
3113  * flushes to occur.
3114  */
3115 static int
3116 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3117                                           uint64_t offset, uint64_t size)
3118 {
3119         uint32_t old_read_domains;
3120         int i, ret;
3121
3122         if (offset == 0 && size == obj->base.size)
3123                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3124
3125         ret = i915_gem_object_flush_gpu_write_domain(obj);
3126         if (ret)
3127                 return ret;
3128
3129         ret = i915_gem_object_wait_rendering(obj);
3130         if (ret)
3131                 return ret;
3132
3133         i915_gem_object_flush_gtt_write_domain(obj);
3134
3135         /* If we're already fully in the CPU read domain, we're done. */
3136         if (obj->page_cpu_valid == NULL &&
3137             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3138                 return 0;
3139
3140         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3141          * newly adding I915_GEM_DOMAIN_CPU
3142          */
3143         if (obj->page_cpu_valid == NULL) {
3144                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3145                                               GFP_KERNEL);
3146                 if (obj->page_cpu_valid == NULL)
3147                         return -ENOMEM;
3148         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3149                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3150
3151         /* Flush the cache on any pages that are still invalid from the CPU's
3152          * perspective.
3153          */
3154         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3155              i++) {
3156                 if (obj->page_cpu_valid[i])
3157                         continue;
3158
3159                 drm_clflush_pages(obj->pages + i, 1);
3160
3161                 obj->page_cpu_valid[i] = 1;
3162         }
3163
3164         /* It should now be out of any other write domains, and we can update
3165          * the domain values for our changes.
3166          */
3167         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3168
3169         old_read_domains = obj->base.read_domains;
3170         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3171
3172         trace_i915_gem_object_change_domain(obj,
3173                                             old_read_domains,
3174                                             obj->base.write_domain);
3175
3176         return 0;
3177 }
3178
3179 /* Throttle our rendering by waiting until the ring has completed our requests
3180  * emitted over 20 msec ago.
3181  *
3182  * Note that if we were to use the current jiffies each time around the loop,
3183  * we wouldn't escape the function with any frames outstanding if the time to
3184  * render a frame was over 20ms.
3185  *
3186  * This should get us reasonable parallelism between CPU and GPU but also
3187  * relatively low latency when blocking on a particular request to finish.
3188  */
3189 static int
3190 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3191 {
3192         struct drm_i915_private *dev_priv = dev->dev_private;
3193         struct drm_i915_file_private *file_priv = file->driver_priv;
3194         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3195         struct drm_i915_gem_request *request;
3196         struct intel_ring_buffer *ring = NULL;
3197         u32 seqno = 0;
3198         int ret;
3199
3200         if (atomic_read(&dev_priv->mm.wedged))
3201                 return -EIO;
3202
3203         spin_lock(&file_priv->mm.lock);
3204         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3205                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3206                         break;
3207
3208                 ring = request->ring;
3209                 seqno = request->seqno;
3210         }
3211         spin_unlock(&file_priv->mm.lock);
3212
3213         if (seqno == 0)
3214                 return 0;
3215
3216         ret = 0;
3217         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3218                 /* And wait for the seqno passing without holding any locks and
3219                  * causing extra latency for others. This is safe as the irq
3220                  * generation is designed to be run atomically and so is
3221                  * lockless.
3222                  */
3223                 if (ring->irq_get(ring)) {
3224                         ret = wait_event_interruptible(ring->irq_queue,
3225                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3226                                                        || atomic_read(&dev_priv->mm.wedged));
3227                         ring->irq_put(ring);
3228
3229                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3230                                 ret = -EIO;
3231                 }
3232         }
3233
3234         if (ret == 0)
3235                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3236
3237         return ret;
3238 }
3239
3240 int
3241 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3242                     uint32_t alignment,
3243                     bool map_and_fenceable)
3244 {
3245         struct drm_device *dev = obj->base.dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         int ret;
3248
3249         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3250         WARN_ON(i915_verify_lists(dev));
3251
3252         if (obj->gtt_space != NULL) {
3253                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3254                     (map_and_fenceable && !obj->map_and_fenceable)) {
3255                         WARN(obj->pin_count,
3256                              "bo is already pinned with incorrect alignment:"
3257                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3258                              " obj->map_and_fenceable=%d\n",
3259                              obj->gtt_offset, alignment,
3260                              map_and_fenceable,
3261                              obj->map_and_fenceable);
3262                         ret = i915_gem_object_unbind(obj);
3263                         if (ret)
3264                                 return ret;
3265                 }
3266         }
3267
3268         if (obj->gtt_space == NULL) {
3269                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3270                                                   map_and_fenceable);
3271                 if (ret)
3272                         return ret;
3273         }
3274
3275         if (obj->pin_count++ == 0) {
3276                 if (!obj->active)
3277                         list_move_tail(&obj->mm_list,
3278                                        &dev_priv->mm.pinned_list);
3279         }
3280         obj->pin_mappable |= map_and_fenceable;
3281
3282         WARN_ON(i915_verify_lists(dev));
3283         return 0;
3284 }
3285
3286 void
3287 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3288 {
3289         struct drm_device *dev = obj->base.dev;
3290         drm_i915_private_t *dev_priv = dev->dev_private;
3291
3292         WARN_ON(i915_verify_lists(dev));
3293         BUG_ON(obj->pin_count == 0);
3294         BUG_ON(obj->gtt_space == NULL);
3295
3296         if (--obj->pin_count == 0) {
3297                 if (!obj->active)
3298                         list_move_tail(&obj->mm_list,
3299                                        &dev_priv->mm.inactive_list);
3300                 obj->pin_mappable = false;
3301         }
3302         WARN_ON(i915_verify_lists(dev));
3303 }
3304
3305 int
3306 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3307                    struct drm_file *file)
3308 {
3309         struct drm_i915_gem_pin *args = data;
3310         struct drm_i915_gem_object *obj;
3311         int ret;
3312
3313         ret = i915_mutex_lock_interruptible(dev);
3314         if (ret)
3315                 return ret;
3316
3317         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3318         if (&obj->base == NULL) {
3319                 ret = -ENOENT;
3320                 goto unlock;
3321         }
3322
3323         if (obj->madv != I915_MADV_WILLNEED) {
3324                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3325                 ret = -EINVAL;
3326                 goto out;
3327         }
3328
3329         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3330                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3331                           args->handle);
3332                 ret = -EINVAL;
3333                 goto out;
3334         }
3335
3336         obj->user_pin_count++;
3337         obj->pin_filp = file;
3338         if (obj->user_pin_count == 1) {
3339                 ret = i915_gem_object_pin(obj, args->alignment, true);
3340                 if (ret)
3341                         goto out;
3342         }
3343
3344         /* XXX - flush the CPU caches for pinned objects
3345          * as the X server doesn't manage domains yet
3346          */
3347         i915_gem_object_flush_cpu_write_domain(obj);
3348         args->offset = obj->gtt_offset;
3349 out:
3350         drm_gem_object_unreference(&obj->base);
3351 unlock:
3352         mutex_unlock(&dev->struct_mutex);
3353         return ret;
3354 }
3355
3356 int
3357 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3358                      struct drm_file *file)
3359 {
3360         struct drm_i915_gem_pin *args = data;
3361         struct drm_i915_gem_object *obj;
3362         int ret;
3363
3364         ret = i915_mutex_lock_interruptible(dev);
3365         if (ret)
3366                 return ret;
3367
3368         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3369         if (&obj->base == NULL) {
3370                 ret = -ENOENT;
3371                 goto unlock;
3372         }
3373
3374         if (obj->pin_filp != file) {
3375                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3376                           args->handle);
3377                 ret = -EINVAL;
3378                 goto out;
3379         }
3380         obj->user_pin_count--;
3381         if (obj->user_pin_count == 0) {
3382                 obj->pin_filp = NULL;
3383                 i915_gem_object_unpin(obj);
3384         }
3385
3386 out:
3387         drm_gem_object_unreference(&obj->base);
3388 unlock:
3389         mutex_unlock(&dev->struct_mutex);
3390         return ret;
3391 }
3392
3393 int
3394 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3395                     struct drm_file *file)
3396 {
3397         struct drm_i915_gem_busy *args = data;
3398         struct drm_i915_gem_object *obj;
3399         int ret;
3400
3401         ret = i915_mutex_lock_interruptible(dev);
3402         if (ret)
3403                 return ret;
3404
3405         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3406         if (&obj->base == NULL) {
3407                 ret = -ENOENT;
3408                 goto unlock;
3409         }
3410
3411         /* Count all active objects as busy, even if they are currently not used
3412          * by the gpu. Users of this interface expect objects to eventually
3413          * become non-busy without any further actions, therefore emit any
3414          * necessary flushes here.
3415          */
3416         args->busy = obj->active;
3417         if (args->busy) {
3418                 /* Unconditionally flush objects, even when the gpu still uses this
3419                  * object. Userspace calling this function indicates that it wants to
3420                  * use this buffer rather sooner than later, so issuing the required
3421                  * flush earlier is beneficial.
3422                  */
3423                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3424                         ret = i915_gem_flush_ring(obj->ring,
3425                                                   0, obj->base.write_domain);
3426                 } else if (obj->ring->outstanding_lazy_request ==
3427                            obj->last_rendering_seqno) {
3428                         struct drm_i915_gem_request *request;
3429
3430                         /* This ring is not being cleared by active usage,
3431                          * so emit a request to do so.
3432                          */
3433                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3434                         if (request)
3435                                 ret = i915_add_request(obj->ring, NULL,request);
3436                         else
3437                                 ret = -ENOMEM;
3438                 }
3439
3440                 /* Update the active list for the hardware's current position.
3441                  * Otherwise this only updates on a delayed timer or when irqs
3442                  * are actually unmasked, and our working set ends up being
3443                  * larger than required.
3444                  */
3445                 i915_gem_retire_requests_ring(obj->ring);
3446
3447                 args->busy = obj->active;
3448         }
3449
3450         drm_gem_object_unreference(&obj->base);
3451 unlock:
3452         mutex_unlock(&dev->struct_mutex);
3453         return ret;
3454 }
3455
3456 int
3457 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3458                         struct drm_file *file_priv)
3459 {
3460     return i915_gem_ring_throttle(dev, file_priv);
3461 }
3462
3463 int
3464 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3465                        struct drm_file *file_priv)
3466 {
3467         struct drm_i915_gem_madvise *args = data;
3468         struct drm_i915_gem_object *obj;
3469         int ret;
3470
3471         switch (args->madv) {
3472         case I915_MADV_DONTNEED:
3473         case I915_MADV_WILLNEED:
3474             break;
3475         default:
3476             return -EINVAL;
3477         }
3478
3479         ret = i915_mutex_lock_interruptible(dev);
3480         if (ret)
3481                 return ret;
3482
3483         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3484         if (&obj->base == NULL) {
3485                 ret = -ENOENT;
3486                 goto unlock;
3487         }
3488
3489         if (obj->pin_count) {
3490                 ret = -EINVAL;
3491                 goto out;
3492         }
3493
3494         if (obj->madv != __I915_MADV_PURGED)
3495                 obj->madv = args->madv;
3496
3497         /* if the object is no longer bound, discard its backing storage */
3498         if (i915_gem_object_is_purgeable(obj) &&
3499             obj->gtt_space == NULL)
3500                 i915_gem_object_truncate(obj);
3501
3502         args->retained = obj->madv != __I915_MADV_PURGED;
3503
3504 out:
3505         drm_gem_object_unreference(&obj->base);
3506 unlock:
3507         mutex_unlock(&dev->struct_mutex);
3508         return ret;
3509 }
3510
3511 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3512                                                   size_t size)
3513 {
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         struct drm_i915_gem_object *obj;
3516
3517         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3518         if (obj == NULL)
3519                 return NULL;
3520
3521         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3522                 kfree(obj);
3523                 return NULL;
3524         }
3525
3526         i915_gem_info_add_obj(dev_priv, size);
3527
3528         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3529         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3530
3531         obj->agp_type = AGP_USER_MEMORY;
3532         obj->base.driver_private = NULL;
3533         obj->fence_reg = I915_FENCE_REG_NONE;
3534         INIT_LIST_HEAD(&obj->mm_list);
3535         INIT_LIST_HEAD(&obj->gtt_list);
3536         INIT_LIST_HEAD(&obj->ring_list);
3537         INIT_LIST_HEAD(&obj->exec_list);
3538         INIT_LIST_HEAD(&obj->gpu_write_list);
3539         obj->madv = I915_MADV_WILLNEED;
3540         /* Avoid an unnecessary call to unbind on the first bind. */
3541         obj->map_and_fenceable = true;
3542
3543         return obj;
3544 }
3545
3546 int i915_gem_init_object(struct drm_gem_object *obj)
3547 {
3548         BUG();
3549
3550         return 0;
3551 }
3552
3553 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3554 {
3555         struct drm_device *dev = obj->base.dev;
3556         drm_i915_private_t *dev_priv = dev->dev_private;
3557         int ret;
3558
3559         ret = i915_gem_object_unbind(obj);
3560         if (ret == -ERESTARTSYS) {
3561                 list_move(&obj->mm_list,
3562                           &dev_priv->mm.deferred_free_list);
3563                 return;
3564         }
3565
3566         if (obj->base.map_list.map)
3567                 i915_gem_free_mmap_offset(obj);
3568
3569         drm_gem_object_release(&obj->base);
3570         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3571
3572         kfree(obj->page_cpu_valid);
3573         kfree(obj->bit_17);
3574         kfree(obj);
3575
3576         trace_i915_gem_object_destroy(obj);
3577 }
3578
3579 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3580 {
3581         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3582         struct drm_device *dev = obj->base.dev;
3583
3584         while (obj->pin_count > 0)
3585                 i915_gem_object_unpin(obj);
3586
3587         if (obj->phys_obj)
3588                 i915_gem_detach_phys_object(dev, obj);
3589
3590         i915_gem_free_object_tail(obj);
3591 }
3592
3593 int
3594 i915_gem_idle(struct drm_device *dev)
3595 {
3596         drm_i915_private_t *dev_priv = dev->dev_private;
3597         int ret;
3598
3599         mutex_lock(&dev->struct_mutex);
3600
3601         if (dev_priv->mm.suspended) {
3602                 mutex_unlock(&dev->struct_mutex);
3603                 return 0;
3604         }
3605
3606         ret = i915_gpu_idle(dev);
3607         if (ret) {
3608                 mutex_unlock(&dev->struct_mutex);
3609                 return ret;
3610         }
3611
3612         /* Under UMS, be paranoid and evict. */
3613         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3614                 ret = i915_gem_evict_inactive(dev, false);
3615                 if (ret) {
3616                         mutex_unlock(&dev->struct_mutex);
3617                         return ret;
3618                 }
3619         }
3620
3621         i915_gem_reset_fences(dev);
3622
3623         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3624          * We need to replace this with a semaphore, or something.
3625          * And not confound mm.suspended!
3626          */
3627         dev_priv->mm.suspended = 1;
3628         del_timer_sync(&dev_priv->hangcheck_timer);
3629
3630         i915_kernel_lost_context(dev);
3631         i915_gem_cleanup_ringbuffer(dev);
3632
3633         mutex_unlock(&dev->struct_mutex);
3634
3635         /* Cancel the retire work handler, which should be idle now. */
3636         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3637
3638         return 0;
3639 }
3640
3641 int
3642 i915_gem_init_ringbuffer(struct drm_device *dev)
3643 {
3644         drm_i915_private_t *dev_priv = dev->dev_private;
3645         int ret;
3646
3647         ret = intel_init_render_ring_buffer(dev);
3648         if (ret)
3649                 return ret;
3650
3651         if (HAS_BSD(dev)) {
3652                 ret = intel_init_bsd_ring_buffer(dev);
3653                 if (ret)
3654                         goto cleanup_render_ring;
3655         }
3656
3657         if (HAS_BLT(dev)) {
3658                 ret = intel_init_blt_ring_buffer(dev);
3659                 if (ret)
3660                         goto cleanup_bsd_ring;
3661         }
3662
3663         dev_priv->next_seqno = 1;
3664
3665         return 0;
3666
3667 cleanup_bsd_ring:
3668         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3669 cleanup_render_ring:
3670         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3671         return ret;
3672 }
3673
3674 void
3675 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3676 {
3677         drm_i915_private_t *dev_priv = dev->dev_private;
3678         int i;
3679
3680         for (i = 0; i < I915_NUM_RINGS; i++)
3681                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3682 }
3683
3684 int
3685 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3686                        struct drm_file *file_priv)
3687 {
3688         drm_i915_private_t *dev_priv = dev->dev_private;
3689         int ret, i;
3690
3691         if (drm_core_check_feature(dev, DRIVER_MODESET))
3692                 return 0;
3693
3694         if (atomic_read(&dev_priv->mm.wedged)) {
3695                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3696                 atomic_set(&dev_priv->mm.wedged, 0);
3697         }
3698
3699         mutex_lock(&dev->struct_mutex);
3700         dev_priv->mm.suspended = 0;
3701
3702         ret = i915_gem_init_ringbuffer(dev);
3703         if (ret != 0) {
3704                 mutex_unlock(&dev->struct_mutex);
3705                 return ret;
3706         }
3707
3708         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3709         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3710         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3711         for (i = 0; i < I915_NUM_RINGS; i++) {
3712                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3713                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3714         }
3715         mutex_unlock(&dev->struct_mutex);
3716
3717         ret = drm_irq_install(dev);
3718         if (ret)
3719                 goto cleanup_ringbuffer;
3720
3721         return 0;
3722
3723 cleanup_ringbuffer:
3724         mutex_lock(&dev->struct_mutex);
3725         i915_gem_cleanup_ringbuffer(dev);
3726         dev_priv->mm.suspended = 1;
3727         mutex_unlock(&dev->struct_mutex);
3728
3729         return ret;
3730 }
3731
3732 int
3733 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3734                        struct drm_file *file_priv)
3735 {
3736         if (drm_core_check_feature(dev, DRIVER_MODESET))
3737                 return 0;
3738
3739         drm_irq_uninstall(dev);
3740         return i915_gem_idle(dev);
3741 }
3742
3743 void
3744 i915_gem_lastclose(struct drm_device *dev)
3745 {
3746         int ret;
3747
3748         if (drm_core_check_feature(dev, DRIVER_MODESET))
3749                 return;
3750
3751         ret = i915_gem_idle(dev);
3752         if (ret)
3753                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3754 }
3755
3756 static void
3757 init_ring_lists(struct intel_ring_buffer *ring)
3758 {
3759         INIT_LIST_HEAD(&ring->active_list);
3760         INIT_LIST_HEAD(&ring->request_list);
3761         INIT_LIST_HEAD(&ring->gpu_write_list);
3762 }
3763
3764 void
3765 i915_gem_load(struct drm_device *dev)
3766 {
3767         int i;
3768         drm_i915_private_t *dev_priv = dev->dev_private;
3769
3770         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3771         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3772         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3773         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3774         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3775         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3776         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3777         for (i = 0; i < I915_NUM_RINGS; i++)
3778                 init_ring_lists(&dev_priv->ring[i]);
3779         for (i = 0; i < 16; i++)
3780                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3781         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3782                           i915_gem_retire_work_handler);
3783         init_completion(&dev_priv->error_completion);
3784
3785         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3786         if (IS_GEN3(dev)) {
3787                 u32 tmp = I915_READ(MI_ARB_STATE);
3788                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3789                         /* arb state is a masked write, so set bit + bit in mask */
3790                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3791                         I915_WRITE(MI_ARB_STATE, tmp);
3792                 }
3793         }
3794
3795         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3796
3797         /* Old X drivers will take 0-2 for front, back, depth buffers */
3798         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3799                 dev_priv->fence_reg_start = 3;
3800
3801         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3802                 dev_priv->num_fence_regs = 16;
3803         else
3804                 dev_priv->num_fence_regs = 8;
3805
3806         /* Initialize fence registers to zero */
3807         switch (INTEL_INFO(dev)->gen) {
3808         case 6:
3809                 for (i = 0; i < 16; i++)
3810                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3811                 break;
3812         case 5:
3813         case 4:
3814                 for (i = 0; i < 16; i++)
3815                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3816                 break;
3817         case 3:
3818                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3819                         for (i = 0; i < 8; i++)
3820                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3821         case 2:
3822                 for (i = 0; i < 8; i++)
3823                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3824                 break;
3825         }
3826         i915_gem_detect_bit_6_swizzle(dev);
3827         init_waitqueue_head(&dev_priv->pending_flip_queue);
3828
3829         dev_priv->mm.interruptible = true;
3830
3831         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3832         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3833         register_shrinker(&dev_priv->mm.inactive_shrinker);
3834 }
3835
3836 /*
3837  * Create a physically contiguous memory object for this object
3838  * e.g. for cursor + overlay regs
3839  */
3840 static int i915_gem_init_phys_object(struct drm_device *dev,
3841                                      int id, int size, int align)
3842 {
3843         drm_i915_private_t *dev_priv = dev->dev_private;
3844         struct drm_i915_gem_phys_object *phys_obj;
3845         int ret;
3846
3847         if (dev_priv->mm.phys_objs[id - 1] || !size)
3848                 return 0;
3849
3850         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3851         if (!phys_obj)
3852                 return -ENOMEM;
3853
3854         phys_obj->id = id;
3855
3856         phys_obj->handle = drm_pci_alloc(dev, size, align);
3857         if (!phys_obj->handle) {
3858                 ret = -ENOMEM;
3859                 goto kfree_obj;
3860         }
3861 #ifdef CONFIG_X86
3862         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3863 #endif
3864
3865         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3866
3867         return 0;
3868 kfree_obj:
3869         kfree(phys_obj);
3870         return ret;
3871 }
3872
3873 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3874 {
3875         drm_i915_private_t *dev_priv = dev->dev_private;
3876         struct drm_i915_gem_phys_object *phys_obj;
3877
3878         if (!dev_priv->mm.phys_objs[id - 1])
3879                 return;
3880
3881         phys_obj = dev_priv->mm.phys_objs[id - 1];
3882         if (phys_obj->cur_obj) {
3883                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3884         }
3885
3886 #ifdef CONFIG_X86
3887         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3888 #endif
3889         drm_pci_free(dev, phys_obj->handle);
3890         kfree(phys_obj);
3891         dev_priv->mm.phys_objs[id - 1] = NULL;
3892 }
3893
3894 void i915_gem_free_all_phys_object(struct drm_device *dev)
3895 {
3896         int i;
3897
3898         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3899                 i915_gem_free_phys_object(dev, i);
3900 }
3901
3902 void i915_gem_detach_phys_object(struct drm_device *dev,
3903                                  struct drm_i915_gem_object *obj)
3904 {
3905         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3906         char *vaddr;
3907         int i;
3908         int page_count;
3909
3910         if (!obj->phys_obj)
3911                 return;
3912         vaddr = obj->phys_obj->handle->vaddr;
3913
3914         page_count = obj->base.size / PAGE_SIZE;
3915         for (i = 0; i < page_count; i++) {
3916                 struct page *page = read_cache_page_gfp(mapping, i,
3917                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3918                 if (!IS_ERR(page)) {
3919                         char *dst = kmap_atomic(page);
3920                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3921                         kunmap_atomic(dst);
3922
3923                         drm_clflush_pages(&page, 1);
3924
3925                         set_page_dirty(page);
3926                         mark_page_accessed(page);
3927                         page_cache_release(page);
3928                 }
3929         }
3930         intel_gtt_chipset_flush();
3931
3932         obj->phys_obj->cur_obj = NULL;
3933         obj->phys_obj = NULL;
3934 }
3935
3936 int
3937 i915_gem_attach_phys_object(struct drm_device *dev,
3938                             struct drm_i915_gem_object *obj,
3939                             int id,
3940                             int align)
3941 {
3942         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3943         drm_i915_private_t *dev_priv = dev->dev_private;
3944         int ret = 0;
3945         int page_count;
3946         int i;
3947
3948         if (id > I915_MAX_PHYS_OBJECT)
3949                 return -EINVAL;
3950
3951         if (obj->phys_obj) {
3952                 if (obj->phys_obj->id == id)
3953                         return 0;
3954                 i915_gem_detach_phys_object(dev, obj);
3955         }
3956
3957         /* create a new object */
3958         if (!dev_priv->mm.phys_objs[id - 1]) {
3959                 ret = i915_gem_init_phys_object(dev, id,
3960                                                 obj->base.size, align);
3961                 if (ret) {
3962                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3963                                   id, obj->base.size);
3964                         return ret;
3965                 }
3966         }
3967
3968         /* bind to the object */
3969         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3970         obj->phys_obj->cur_obj = obj;
3971
3972         page_count = obj->base.size / PAGE_SIZE;
3973
3974         for (i = 0; i < page_count; i++) {
3975                 struct page *page;
3976                 char *dst, *src;
3977
3978                 page = read_cache_page_gfp(mapping, i,
3979                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
3980                 if (IS_ERR(page))
3981                         return PTR_ERR(page);
3982
3983                 src = kmap_atomic(page);
3984                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3985                 memcpy(dst, src, PAGE_SIZE);
3986                 kunmap_atomic(src);
3987
3988                 mark_page_accessed(page);
3989                 page_cache_release(page);
3990         }
3991
3992         return 0;
3993 }
3994
3995 static int
3996 i915_gem_phys_pwrite(struct drm_device *dev,
3997                      struct drm_i915_gem_object *obj,
3998                      struct drm_i915_gem_pwrite *args,
3999                      struct drm_file *file_priv)
4000 {
4001         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4002         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4003
4004         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4005                 unsigned long unwritten;
4006
4007                 /* The physical object once assigned is fixed for the lifetime
4008                  * of the obj, so we can safely drop the lock and continue
4009                  * to access vaddr.
4010                  */
4011                 mutex_unlock(&dev->struct_mutex);
4012                 unwritten = copy_from_user(vaddr, user_data, args->size);
4013                 mutex_lock(&dev->struct_mutex);
4014                 if (unwritten)
4015                         return -EFAULT;
4016         }
4017
4018         intel_gtt_chipset_flush();
4019         return 0;
4020 }
4021
4022 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4023 {
4024         struct drm_i915_file_private *file_priv = file->driver_priv;
4025
4026         /* Clean up our request list when the client is going away, so that
4027          * later retire_requests won't dereference our soon-to-be-gone
4028          * file_priv.
4029          */
4030         spin_lock(&file_priv->mm.lock);
4031         while (!list_empty(&file_priv->mm.request_list)) {
4032                 struct drm_i915_gem_request *request;
4033
4034                 request = list_first_entry(&file_priv->mm.request_list,
4035                                            struct drm_i915_gem_request,
4036                                            client_list);
4037                 list_del(&request->client_list);
4038                 request->file_priv = NULL;
4039         }
4040         spin_unlock(&file_priv->mm.lock);
4041 }
4042
4043 static int
4044 i915_gpu_is_active(struct drm_device *dev)
4045 {
4046         drm_i915_private_t *dev_priv = dev->dev_private;
4047         int lists_empty;
4048
4049         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4050                       list_empty(&dev_priv->mm.active_list);
4051
4052         return !lists_empty;
4053 }
4054
4055 static int
4056 i915_gem_inactive_shrink(struct shrinker *shrinker,
4057                          int nr_to_scan,
4058                          gfp_t gfp_mask)
4059 {
4060         struct drm_i915_private *dev_priv =
4061                 container_of(shrinker,
4062                              struct drm_i915_private,
4063                              mm.inactive_shrinker);
4064         struct drm_device *dev = dev_priv->dev;
4065         struct drm_i915_gem_object *obj, *next;
4066         int cnt;
4067
4068         if (!mutex_trylock(&dev->struct_mutex))
4069                 return 0;
4070
4071         /* "fast-path" to count number of available objects */
4072         if (nr_to_scan == 0) {
4073                 cnt = 0;
4074                 list_for_each_entry(obj,
4075                                     &dev_priv->mm.inactive_list,
4076                                     mm_list)
4077                         cnt++;
4078                 mutex_unlock(&dev->struct_mutex);
4079                 return cnt / 100 * sysctl_vfs_cache_pressure;
4080         }
4081
4082 rescan:
4083         /* first scan for clean buffers */
4084         i915_gem_retire_requests(dev);
4085
4086         list_for_each_entry_safe(obj, next,
4087                                  &dev_priv->mm.inactive_list,
4088                                  mm_list) {
4089                 if (i915_gem_object_is_purgeable(obj)) {
4090                         if (i915_gem_object_unbind(obj) == 0 &&
4091                             --nr_to_scan == 0)
4092                                 break;
4093                 }
4094         }
4095
4096         /* second pass, evict/count anything still on the inactive list */
4097         cnt = 0;
4098         list_for_each_entry_safe(obj, next,
4099                                  &dev_priv->mm.inactive_list,
4100                                  mm_list) {
4101                 if (nr_to_scan &&
4102                     i915_gem_object_unbind(obj) == 0)
4103                         nr_to_scan--;
4104                 else
4105                         cnt++;
4106         }
4107
4108         if (nr_to_scan && i915_gpu_is_active(dev)) {
4109                 /*
4110                  * We are desperate for pages, so as a last resort, wait
4111                  * for the GPU to finish and discard whatever we can.
4112                  * This has a dramatic impact to reduce the number of
4113                  * OOM-killer events whilst running the GPU aggressively.
4114                  */
4115                 if (i915_gpu_idle(dev) == 0)
4116                         goto rescan;
4117         }
4118         mutex_unlock(&dev->struct_mutex);
4119         return cnt / 100 * sysctl_vfs_cache_pressure;
4120 }