drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static LIST_HEAD(shrink_list);
  62 static DEFINE_SPINLOCK(shrink_list_lock);
  63
  64 static inline bool
  65 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
  66 {
  67         return obj_priv->gtt_space &&
  68                 !obj_priv->active &&
  69                 obj_priv->pin_count == 0;
  70 }
  71
  72 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  73                      unsigned long end)
  74 {
  75         drm_i915_private_t *dev_priv = dev->dev_private;
  76
  77         if (start >= end ||
  78             (start & (PAGE_SIZE - 1)) != 0 ||
  79             (end & (PAGE_SIZE - 1)) != 0) {
  80                 return -EINVAL;
  81         }
  82
  83         drm_mm_init(&dev_priv->mm.gtt_space, start,
  84                     end - start);
  85
  86         dev->gtt_total = (uint32_t) (end - start);
  87
  88         return 0;
  89 }
  90
  91 int
  92 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  93                     struct drm_file *file_priv)
  94 {
  95         struct drm_i915_gem_init *args = data;
  96         int ret;
  97
  98         mutex_lock(&dev->struct_mutex);
  99         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 100         mutex_unlock(&dev->struct_mutex);
 101
 102         return ret;
 103 }
 104
 105 int
 106 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 107                             struct drm_file *file_priv)
 108 {
 109         struct drm_i915_gem_get_aperture *args = data;
 110
 111         if (!(dev->driver->driver_features & DRIVER_GEM))
 112                 return -ENODEV;
 113
 114         args->aper_size = dev->gtt_total;
 115         args->aper_available_size = (args->aper_size -
 116                                      atomic_read(&dev->pin_memory));
 117
 118         return 0;
 119 }
 120
 121
 122 /**
 123  * Creates a new mm object and returns a handle to it.
 124  */
 125 int
 126 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 127                       struct drm_file *file_priv)
 128 {
 129         struct drm_i915_gem_create *args = data;
 130         struct drm_gem_object *obj;
 131         int ret;
 132         u32 handle;
 133
 134         args->size = roundup(args->size, PAGE_SIZE);
 135
 136         /* Allocate the new object */
 137         obj = i915_gem_alloc_object(dev, args->size);
 138         if (obj == NULL)
 139                 return -ENOMEM;
 140
 141         ret = drm_gem_handle_create(file_priv, obj, &handle);
 142         if (ret) {
 143                 drm_gem_object_unreference_unlocked(obj);
 144                 return ret;
 145         }
 146
 147         /* Sink the floating reference from kref_init(handlecount) */
 148         drm_gem_object_handle_unreference_unlocked(obj);
 149
 150         args->handle = handle;
 151         return 0;
 152 }
 153
 154 static inline int
 155 fast_shmem_read(struct page **pages,
 156                 loff_t page_base, int page_offset,
 157                 char __user *data,
 158                 int length)
 159 {
 160         char __iomem *vaddr;
 161         int unwritten;
 162
 163         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 164         if (vaddr == NULL)
 165                 return -ENOMEM;
 166         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 167         kunmap_atomic(vaddr, KM_USER0);
 168
 169         if (unwritten)
 170                 return -EFAULT;
 171
 172         return 0;
 173 }
 174
 175 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 176 {
 177         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 178         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 179
 180         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 181                 obj_priv->tiling_mode != I915_TILING_NONE;
 182 }
 183
 184 static inline void
 185 slow_shmem_copy(struct page *dst_page,
 186                 int dst_offset,
 187                 struct page *src_page,
 188                 int src_offset,
 189                 int length)
 190 {
 191         char *dst_vaddr, *src_vaddr;
 192
 193         dst_vaddr = kmap(dst_page);
 194         src_vaddr = kmap(src_page);
 195
 196         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 197
 198         kunmap(src_page);
 199         kunmap(dst_page);
 200 }
 201
 202 static inline void
 203 slow_shmem_bit17_copy(struct page *gpu_page,
 204                       int gpu_offset,
 205                       struct page *cpu_page,
 206                       int cpu_offset,
 207                       int length,
 208                       int is_read)
 209 {
 210         char *gpu_vaddr, *cpu_vaddr;
 211
 212         /* Use the unswizzled path if this page isn't affected. */
 213         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 214                 if (is_read)
 215                         return slow_shmem_copy(cpu_page, cpu_offset,
 216                                                gpu_page, gpu_offset, length);
 217                 else
 218                         return slow_shmem_copy(gpu_page, gpu_offset,
 219                                                cpu_page, cpu_offset, length);
 220         }
 221
 222         gpu_vaddr = kmap(gpu_page);
 223         cpu_vaddr = kmap(cpu_page);
 224
 225         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 226          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 227          */
 228         while (length > 0) {
 229                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 230                 int this_length = min(cacheline_end - gpu_offset, length);
 231                 int swizzled_gpu_offset = gpu_offset ^ 64;
 232
 233                 if (is_read) {
 234                         memcpy(cpu_vaddr + cpu_offset,
 235                                gpu_vaddr + swizzled_gpu_offset,
 236                                this_length);
 237                 } else {
 238                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 239                                cpu_vaddr + cpu_offset,
 240                                this_length);
 241                 }
 242                 cpu_offset += this_length;
 243                 gpu_offset += this_length;
 244                 length -= this_length;
 245         }
 246
 247         kunmap(cpu_page);
 248         kunmap(gpu_page);
 249 }
 250
 251 /**
 252  * This is the fast shmem pread path, which attempts to copy_from_user directly
 253  * from the backing pages of the object to the user's address space.  On a
 254  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 255  */
 256 static int
 257 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 258                           struct drm_i915_gem_pread *args,
 259                           struct drm_file *file_priv)
 260 {
 261         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 262         ssize_t remain;
 263         loff_t offset, page_base;
 264         char __user *user_data;
 265         int page_offset, page_length;
 266         int ret;
 267
 268         user_data = (char __user *) (uintptr_t) args->data_ptr;
 269         remain = args->size;
 270
 271         mutex_lock(&dev->struct_mutex);
 272
 273         ret = i915_gem_object_get_pages(obj, 0);
 274         if (ret != 0)
 275                 goto fail_unlock;
 276
 277         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 278                                                         args->size);
 279         if (ret != 0)
 280                 goto fail_put_pages;
 281
 282         obj_priv = to_intel_bo(obj);
 283         offset = args->offset;
 284
 285         while (remain > 0) {
 286                 /* Operation in this page
 287                  *
 288                  * page_base = page offset within aperture
 289                  * page_offset = offset within page
 290                  * page_length = bytes to copy for this page
 291                  */
 292                 page_base = (offset & ~(PAGE_SIZE-1));
 293                 page_offset = offset & (PAGE_SIZE-1);
 294                 page_length = remain;
 295                 if ((page_offset + remain) > PAGE_SIZE)
 296                         page_length = PAGE_SIZE - page_offset;
 297
 298                 ret = fast_shmem_read(obj_priv->pages,
 299                                       page_base, page_offset,
 300                                       user_data, page_length);
 301                 if (ret)
 302                         goto fail_put_pages;
 303
 304                 remain -= page_length;
 305                 user_data += page_length;
 306                 offset += page_length;
 307         }
 308
 309 fail_put_pages:
 310         i915_gem_object_put_pages(obj);
 311 fail_unlock:
 312         mutex_unlock(&dev->struct_mutex);
 313
 314         return ret;
 315 }
 316
 317 static int
 318 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 319 {
 320         int ret;
 321
 322         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 323
 324         /* If we've insufficient memory to map in the pages, attempt
 325          * to make some space by throwing out some old buffers.
 326          */
 327         if (ret == -ENOMEM) {
 328                 struct drm_device *dev = obj->dev;
 329
 330                 ret = i915_gem_evict_something(dev, obj->size,
 331                                                i915_gem_get_gtt_alignment(obj));
 332                 if (ret)
 333                         return ret;
 334
 335                 ret = i915_gem_object_get_pages(obj, 0);
 336         }
 337
 338         return ret;
 339 }
 340
 341 /**
 342  * This is the fallback shmem pread path, which allocates temporary storage
 343  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 344  * can copy out of the object's backing pages while holding the struct mutex
 345  * and not take page faults.
 346  */
 347 static int
 348 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 349                           struct drm_i915_gem_pread *args,
 350                           struct drm_file *file_priv)
 351 {
 352         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 353         struct mm_struct *mm = current->mm;
 354         struct page **user_pages;
 355         ssize_t remain;
 356         loff_t offset, pinned_pages, i;
 357         loff_t first_data_page, last_data_page, num_pages;
 358         int shmem_page_index, shmem_page_offset;
 359         int data_page_index,  data_page_offset;
 360         int page_length;
 361         int ret;
 362         uint64_t data_ptr = args->data_ptr;
 363         int do_bit17_swizzling;
 364
 365         remain = args->size;
 366
 367         /* Pin the user pages containing the data.  We can't fault while
 368          * holding the struct mutex, yet we want to hold it while
 369          * dereferencing the user data.
 370          */
 371         first_data_page = data_ptr / PAGE_SIZE;
 372         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 373         num_pages = last_data_page - first_data_page + 1;
 374
 375         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 376         if (user_pages == NULL)
 377                 return -ENOMEM;
 378
 379         down_read(&mm->mmap_sem);
 380         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 381                                       num_pages, 1, 0, user_pages, NULL);
 382         up_read(&mm->mmap_sem);
 383         if (pinned_pages < num_pages) {
 384                 ret = -EFAULT;
 385                 goto fail_put_user_pages;
 386         }
 387
 388         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 389
 390         mutex_lock(&dev->struct_mutex);
 391
 392         ret = i915_gem_object_get_pages_or_evict(obj);
 393         if (ret)
 394                 goto fail_unlock;
 395
 396         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 397                                                         args->size);
 398         if (ret != 0)
 399                 goto fail_put_pages;
 400
 401         obj_priv = to_intel_bo(obj);
 402         offset = args->offset;
 403
 404         while (remain > 0) {
 405                 /* Operation in this page
 406                  *
 407                  * shmem_page_index = page number within shmem file
 408                  * shmem_page_offset = offset within page in shmem file
 409                  * data_page_index = page number in get_user_pages return
 410                  * data_page_offset = offset with data_page_index page.
 411                  * page_length = bytes to copy for this page
 412                  */
 413                 shmem_page_index = offset / PAGE_SIZE;
 414                 shmem_page_offset = offset & ~PAGE_MASK;
 415                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 416                 data_page_offset = data_ptr & ~PAGE_MASK;
 417
 418                 page_length = remain;
 419                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 420                         page_length = PAGE_SIZE - shmem_page_offset;
 421                 if ((data_page_offset + page_length) > PAGE_SIZE)
 422                         page_length = PAGE_SIZE - data_page_offset;
 423
 424                 if (do_bit17_swizzling) {
 425                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 426                                               shmem_page_offset,
 427                                               user_pages[data_page_index],
 428                                               data_page_offset,
 429                                               page_length,
 430                                               1);
 431                 } else {
 432                         slow_shmem_copy(user_pages[data_page_index],
 433                                         data_page_offset,
 434                                         obj_priv->pages[shmem_page_index],
 435                                         shmem_page_offset,
 436                                         page_length);
 437                 }
 438
 439                 remain -= page_length;
 440                 data_ptr += page_length;
 441                 offset += page_length;
 442         }
 443
 444 fail_put_pages:
 445         i915_gem_object_put_pages(obj);
 446 fail_unlock:
 447         mutex_unlock(&dev->struct_mutex);
 448 fail_put_user_pages:
 449         for (i = 0; i < pinned_pages; i++) {
 450                 SetPageDirty(user_pages[i]);
 451                 page_cache_release(user_pages[i]);
 452         }
 453         drm_free_large(user_pages);
 454
 455         return ret;
 456 }
 457
 458 /**
 459  * Reads data from the object referenced by handle.
 460  *
 461  * On error, the contents of *data are undefined.
 462  */
 463 int
 464 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 465                      struct drm_file *file_priv)
 466 {
 467         struct drm_i915_gem_pread *args = data;
 468         struct drm_gem_object *obj;
 469         struct drm_i915_gem_object *obj_priv;
 470         int ret;
 471
 472         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 473         if (obj == NULL)
 474                 return -ENOENT;
 475         obj_priv = to_intel_bo(obj);
 476
 477         /* Bounds check source.
 478          *
 479          * XXX: This could use review for overflow issues...
 480          */
 481         if (args->offset > obj->size || args->size > obj->size ||
 482             args->offset + args->size > obj->size) {
 483                 drm_gem_object_unreference_unlocked(obj);
 484                 return -EINVAL;
 485         }
 486
 487         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 488                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 489         } else {
 490                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 491                 if (ret != 0)
 492                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 493                                                         file_priv);
 494         }
 495
 496         drm_gem_object_unreference_unlocked(obj);
 497
 498         return ret;
 499 }
 500
 501 /* This is the fast write path which cannot handle
 502  * page faults in the source data
 503  */
 504
 505 static inline int
 506 fast_user_write(struct io_mapping *mapping,
 507                 loff_t page_base, int page_offset,
 508                 char __user *user_data,
 509                 int length)
 510 {
 511         char *vaddr_atomic;
 512         unsigned long unwritten;
 513
 514         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
 515         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 516                                                       user_data, length);
 517         io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
 518         if (unwritten)
 519                 return -EFAULT;
 520         return 0;
 521 }
 522
 523 /* Here's the write path which can sleep for
 524  * page faults
 525  */
 526
 527 static inline void
 528 slow_kernel_write(struct io_mapping *mapping,
 529                   loff_t gtt_base, int gtt_offset,
 530                   struct page *user_page, int user_offset,
 531                   int length)
 532 {
 533         char __iomem *dst_vaddr;
 534         char *src_vaddr;
 535
 536         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 537         src_vaddr = kmap(user_page);
 538
 539         memcpy_toio(dst_vaddr + gtt_offset,
 540                     src_vaddr + user_offset,
 541                     length);
 542
 543         kunmap(user_page);
 544         io_mapping_unmap(dst_vaddr);
 545 }
 546
 547 static inline int
 548 fast_shmem_write(struct page **pages,
 549                  loff_t page_base, int page_offset,
 550                  char __user *data,
 551                  int length)
 552 {
 553         char __iomem *vaddr;
 554         unsigned long unwritten;
 555
 556         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 557         if (vaddr == NULL)
 558                 return -ENOMEM;
 559         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 560         kunmap_atomic(vaddr, KM_USER0);
 561
 562         if (unwritten)
 563                 return -EFAULT;
 564         return 0;
 565 }
 566
 567 /**
 568  * This is the fast pwrite path, where we copy the data directly from the
 569  * user into the GTT, uncached.
 570  */
 571 static int
 572 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 573                          struct drm_i915_gem_pwrite *args,
 574                          struct drm_file *file_priv)
 575 {
 576         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 577         drm_i915_private_t *dev_priv = dev->dev_private;
 578         ssize_t remain;
 579         loff_t offset, page_base;
 580         char __user *user_data;
 581         int page_offset, page_length;
 582         int ret;
 583
 584         user_data = (char __user *) (uintptr_t) args->data_ptr;
 585         remain = args->size;
 586         if (!access_ok(VERIFY_READ, user_data, remain))
 587                 return -EFAULT;
 588
 589
 590         mutex_lock(&dev->struct_mutex);
 591         ret = i915_gem_object_pin(obj, 0);
 592         if (ret) {
 593                 mutex_unlock(&dev->struct_mutex);
 594                 return ret;
 595         }
 596         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 597         if (ret)
 598                 goto fail;
 599
 600         obj_priv = to_intel_bo(obj);
 601         offset = obj_priv->gtt_offset + args->offset;
 602
 603         while (remain > 0) {
 604                 /* Operation in this page
 605                  *
 606                  * page_base = page offset within aperture
 607                  * page_offset = offset within page
 608                  * page_length = bytes to copy for this page
 609                  */
 610                 page_base = (offset & ~(PAGE_SIZE-1));
 611                 page_offset = offset & (PAGE_SIZE-1);
 612                 page_length = remain;
 613                 if ((page_offset + remain) > PAGE_SIZE)
 614                         page_length = PAGE_SIZE - page_offset;
 615
 616                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 617                                        page_offset, user_data, page_length);
 618
 619                 /* If we get a fault while copying data, then (presumably) our
 620                  * source page isn't available.  Return the error and we'll
 621                  * retry in the slow path.
 622                  */
 623                 if (ret)
 624                         goto fail;
 625
 626                 remain -= page_length;
 627                 user_data += page_length;
 628                 offset += page_length;
 629         }
 630
 631 fail:
 632         i915_gem_object_unpin(obj);
 633         mutex_unlock(&dev->struct_mutex);
 634
 635         return ret;
 636 }
 637
 638 /**
 639  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 640  * the memory and maps it using kmap_atomic for copying.
 641  *
 642  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 643  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 644  */
 645 static int
 646 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 647                          struct drm_i915_gem_pwrite *args,
 648                          struct drm_file *file_priv)
 649 {
 650         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 651         drm_i915_private_t *dev_priv = dev->dev_private;
 652         ssize_t remain;
 653         loff_t gtt_page_base, offset;
 654         loff_t first_data_page, last_data_page, num_pages;
 655         loff_t pinned_pages, i;
 656         struct page **user_pages;
 657         struct mm_struct *mm = current->mm;
 658         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 659         int ret;
 660         uint64_t data_ptr = args->data_ptr;
 661
 662         remain = args->size;
 663
 664         /* Pin the user pages containing the data.  We can't fault while
 665          * holding the struct mutex, and all of the pwrite implementations
 666          * want to hold it while dereferencing the user data.
 667          */
 668         first_data_page = data_ptr / PAGE_SIZE;
 669         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 670         num_pages = last_data_page - first_data_page + 1;
 671
 672         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 673         if (user_pages == NULL)
 674                 return -ENOMEM;
 675
 676         down_read(&mm->mmap_sem);
 677         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 678                                       num_pages, 0, 0, user_pages, NULL);
 679         up_read(&mm->mmap_sem);
 680         if (pinned_pages < num_pages) {
 681                 ret = -EFAULT;
 682                 goto out_unpin_pages;
 683         }
 684
 685         mutex_lock(&dev->struct_mutex);
 686         ret = i915_gem_object_pin(obj, 0);
 687         if (ret)
 688                 goto out_unlock;
 689
 690         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 691         if (ret)
 692                 goto out_unpin_object;
 693
 694         obj_priv = to_intel_bo(obj);
 695         offset = obj_priv->gtt_offset + args->offset;
 696
 697         while (remain > 0) {
 698                 /* Operation in this page
 699                  *
 700                  * gtt_page_base = page offset within aperture
 701                  * gtt_page_offset = offset within page in aperture
 702                  * data_page_index = page number in get_user_pages return
 703                  * data_page_offset = offset with data_page_index page.
 704                  * page_length = bytes to copy for this page
 705                  */
 706                 gtt_page_base = offset & PAGE_MASK;
 707                 gtt_page_offset = offset & ~PAGE_MASK;
 708                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 709                 data_page_offset = data_ptr & ~PAGE_MASK;
 710
 711                 page_length = remain;
 712                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 713                         page_length = PAGE_SIZE - gtt_page_offset;
 714                 if ((data_page_offset + page_length) > PAGE_SIZE)
 715                         page_length = PAGE_SIZE - data_page_offset;
 716
 717                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 718                                   gtt_page_base, gtt_page_offset,
 719                                   user_pages[data_page_index],
 720                                   data_page_offset,
 721                                   page_length);
 722
 723                 remain -= page_length;
 724                 offset += page_length;
 725                 data_ptr += page_length;
 726         }
 727
 728 out_unpin_object:
 729         i915_gem_object_unpin(obj);
 730 out_unlock:
 731         mutex_unlock(&dev->struct_mutex);
 732 out_unpin_pages:
 733         for (i = 0; i < pinned_pages; i++)
 734                 page_cache_release(user_pages[i]);
 735         drm_free_large(user_pages);
 736
 737         return ret;
 738 }
 739
 740 /**
 741  * This is the fast shmem pwrite path, which attempts to directly
 742  * copy_from_user into the kmapped pages backing the object.
 743  */
 744 static int
 745 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 746                            struct drm_i915_gem_pwrite *args,
 747                            struct drm_file *file_priv)
 748 {
 749         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 750         ssize_t remain;
 751         loff_t offset, page_base;
 752         char __user *user_data;
 753         int page_offset, page_length;
 754         int ret;
 755
 756         user_data = (char __user *) (uintptr_t) args->data_ptr;
 757         remain = args->size;
 758
 759         mutex_lock(&dev->struct_mutex);
 760
 761         ret = i915_gem_object_get_pages(obj, 0);
 762         if (ret != 0)
 763                 goto fail_unlock;
 764
 765         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 766         if (ret != 0)
 767                 goto fail_put_pages;
 768
 769         obj_priv = to_intel_bo(obj);
 770         offset = args->offset;
 771         obj_priv->dirty = 1;
 772
 773         while (remain > 0) {
 774                 /* Operation in this page
 775                  *
 776                  * page_base = page offset within aperture
 777                  * page_offset = offset within page
 778                  * page_length = bytes to copy for this page
 779                  */
 780                 page_base = (offset & ~(PAGE_SIZE-1));
 781                 page_offset = offset & (PAGE_SIZE-1);
 782                 page_length = remain;
 783                 if ((page_offset + remain) > PAGE_SIZE)
 784                         page_length = PAGE_SIZE - page_offset;
 785
 786                 ret = fast_shmem_write(obj_priv->pages,
 787                                        page_base, page_offset,
 788                                        user_data, page_length);
 789                 if (ret)
 790                         goto fail_put_pages;
 791
 792                 remain -= page_length;
 793                 user_data += page_length;
 794                 offset += page_length;
 795         }
 796
 797 fail_put_pages:
 798         i915_gem_object_put_pages(obj);
 799 fail_unlock:
 800         mutex_unlock(&dev->struct_mutex);
 801
 802         return ret;
 803 }
 804
 805 /**
 806  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 807  * the memory and maps it using kmap_atomic for copying.
 808  *
 809  * This avoids taking mmap_sem for faulting on the user's address while the
 810  * struct_mutex is held.
 811  */
 812 static int
 813 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 814                            struct drm_i915_gem_pwrite *args,
 815                            struct drm_file *file_priv)
 816 {
 817         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 818         struct mm_struct *mm = current->mm;
 819         struct page **user_pages;
 820         ssize_t remain;
 821         loff_t offset, pinned_pages, i;
 822         loff_t first_data_page, last_data_page, num_pages;
 823         int shmem_page_index, shmem_page_offset;
 824         int data_page_index,  data_page_offset;
 825         int page_length;
 826         int ret;
 827         uint64_t data_ptr = args->data_ptr;
 828         int do_bit17_swizzling;
 829
 830         remain = args->size;
 831
 832         /* Pin the user pages containing the data.  We can't fault while
 833          * holding the struct mutex, and all of the pwrite implementations
 834          * want to hold it while dereferencing the user data.
 835          */
 836         first_data_page = data_ptr / PAGE_SIZE;
 837         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 838         num_pages = last_data_page - first_data_page + 1;
 839
 840         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 841         if (user_pages == NULL)
 842                 return -ENOMEM;
 843
 844         down_read(&mm->mmap_sem);
 845         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 846                                       num_pages, 0, 0, user_pages, NULL);
 847         up_read(&mm->mmap_sem);
 848         if (pinned_pages < num_pages) {
 849                 ret = -EFAULT;
 850                 goto fail_put_user_pages;
 851         }
 852
 853         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 854
 855         mutex_lock(&dev->struct_mutex);
 856
 857         ret = i915_gem_object_get_pages_or_evict(obj);
 858         if (ret)
 859                 goto fail_unlock;
 860
 861         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 862         if (ret != 0)
 863                 goto fail_put_pages;
 864
 865         obj_priv = to_intel_bo(obj);
 866         offset = args->offset;
 867         obj_priv->dirty = 1;
 868
 869         while (remain > 0) {
 870                 /* Operation in this page
 871                  *
 872                  * shmem_page_index = page number within shmem file
 873                  * shmem_page_offset = offset within page in shmem file
 874                  * data_page_index = page number in get_user_pages return
 875                  * data_page_offset = offset with data_page_index page.
 876                  * page_length = bytes to copy for this page
 877                  */
 878                 shmem_page_index = offset / PAGE_SIZE;
 879                 shmem_page_offset = offset & ~PAGE_MASK;
 880                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 881                 data_page_offset = data_ptr & ~PAGE_MASK;
 882
 883                 page_length = remain;
 884                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 885                         page_length = PAGE_SIZE - shmem_page_offset;
 886                 if ((data_page_offset + page_length) > PAGE_SIZE)
 887                         page_length = PAGE_SIZE - data_page_offset;
 888
 889                 if (do_bit17_swizzling) {
 890                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 891                                               shmem_page_offset,
 892                                               user_pages[data_page_index],
 893                                               data_page_offset,
 894                                               page_length,
 895                                               0);
 896                 } else {
 897                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 898                                         shmem_page_offset,
 899                                         user_pages[data_page_index],
 900                                         data_page_offset,
 901                                         page_length);
 902                 }
 903
 904                 remain -= page_length;
 905                 data_ptr += page_length;
 906                 offset += page_length;
 907         }
 908
 909 fail_put_pages:
 910         i915_gem_object_put_pages(obj);
 911 fail_unlock:
 912         mutex_unlock(&dev->struct_mutex);
 913 fail_put_user_pages:
 914         for (i = 0; i < pinned_pages; i++)
 915                 page_cache_release(user_pages[i]);
 916         drm_free_large(user_pages);
 917
 918         return ret;
 919 }
 920
 921 /**
 922  * Writes data to the object referenced by handle.
 923  *
 924  * On error, the contents of the buffer that were to be modified are undefined.
 925  */
 926 int
 927 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 928                       struct drm_file *file_priv)
 929 {
 930         struct drm_i915_gem_pwrite *args = data;
 931         struct drm_gem_object *obj;
 932         struct drm_i915_gem_object *obj_priv;
 933         int ret = 0;
 934
 935         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 936         if (obj == NULL)
 937                 return -ENOENT;
 938         obj_priv = to_intel_bo(obj);
 939
 940         /* Bounds check destination.
 941          *
 942          * XXX: This could use review for overflow issues...
 943          */
 944         if (args->offset > obj->size || args->size > obj->size ||
 945             args->offset + args->size > obj->size) {
 946                 drm_gem_object_unreference_unlocked(obj);
 947                 return -EINVAL;
 948         }
 949
 950         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 951          * it would end up going through the fenced access, and we'll get
 952          * different detiling behavior between reading and writing.
 953          * pread/pwrite currently are reading and writing from the CPU
 954          * perspective, requiring manual detiling by the client.
 955          */
 956         if (obj_priv->phys_obj)
 957                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 958         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 959                  dev->gtt_total != 0 &&
 960                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
 961                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 962                 if (ret == -EFAULT) {
 963                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 964                                                        file_priv);
 965                 }
 966         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 967                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 968         } else {
 969                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 970                 if (ret == -EFAULT) {
 971                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 972                                                          file_priv);
 973                 }
 974         }
 975
 976 #if WATCH_PWRITE
 977         if (ret)
 978                 DRM_INFO("pwrite failed %d\n", ret);
 979 #endif
 980
 981         drm_gem_object_unreference_unlocked(obj);
 982
 983         return ret;
 984 }
 985
 986 /**
 987  * Called when user space prepares to use an object with the CPU, either
 988  * through the mmap ioctl's mapping or a GTT mapping.
 989  */
 990 int
 991 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 992                           struct drm_file *file_priv)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         struct drm_i915_gem_set_domain *args = data;
 996         struct drm_gem_object *obj;
 997         struct drm_i915_gem_object *obj_priv;
 998         uint32_t read_domains = args->read_domains;
 999         uint32_t write_domain = args->write_domain;
1000         int ret;
1001
1002         if (!(dev->driver->driver_features & DRIVER_GEM))
1003                 return -ENODEV;
1004
1005         /* Only handle setting domains to types used by the CPU. */
1006         if (write_domain & I915_GEM_GPU_DOMAINS)
1007                 return -EINVAL;
1008
1009         if (read_domains & I915_GEM_GPU_DOMAINS)
1010                 return -EINVAL;
1011
1012         /* Having something in the write domain implies it's in the read
1013          * domain, and only that read domain.  Enforce that in the request.
1014          */
1015         if (write_domain != 0 && read_domains != write_domain)
1016                 return -EINVAL;
1017
1018         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1019         if (obj == NULL)
1020                 return -ENOENT;
1021         obj_priv = to_intel_bo(obj);
1022
1023         mutex_lock(&dev->struct_mutex);
1024
1025         intel_mark_busy(dev, obj);
1026
1027 #if WATCH_BUF
1028         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1029                  obj, obj->size, read_domains, write_domain);
1030 #endif
1031         if (read_domains & I915_GEM_DOMAIN_GTT) {
1032                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1033
1034                 /* Update the LRU on the fence for the CPU access that's
1035                  * about to occur.
1036                  */
1037                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1038                         struct drm_i915_fence_reg *reg =
1039                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1040                         list_move_tail(&reg->lru_list,
1041                                        &dev_priv->mm.fence_list);
1042                 }
1043
1044                 /* Silently promote "you're not bound, there was nothing to do"
1045                  * to success, since the client was just asking us to
1046                  * make sure everything was done.
1047                  */
1048                 if (ret == -EINVAL)
1049                         ret = 0;
1050         } else {
1051                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1052         }
1053
1054
1055         /* Maintain LRU order of "inactive" objects */
1056         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1057                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1058
1059         drm_gem_object_unreference(obj);
1060         mutex_unlock(&dev->struct_mutex);
1061         return ret;
1062 }
1063
1064 /**
1065  * Called when user space has done writes to this buffer
1066  */
1067 int
1068 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1069                       struct drm_file *file_priv)
1070 {
1071         struct drm_i915_gem_sw_finish *args = data;
1072         struct drm_gem_object *obj;
1073         struct drm_i915_gem_object *obj_priv;
1074         int ret = 0;
1075
1076         if (!(dev->driver->driver_features & DRIVER_GEM))
1077                 return -ENODEV;
1078
1079         mutex_lock(&dev->struct_mutex);
1080         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1081         if (obj == NULL) {
1082                 mutex_unlock(&dev->struct_mutex);
1083                 return -ENOENT;
1084         }
1085
1086 #if WATCH_BUF
1087         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1088                  __func__, args->handle, obj, obj->size);
1089 #endif
1090         obj_priv = to_intel_bo(obj);
1091
1092         /* Pinned buffers may be scanout, so flush the cache */
1093         if (obj_priv->pin_count)
1094                 i915_gem_object_flush_cpu_write_domain(obj);
1095
1096         drm_gem_object_unreference(obj);
1097         mutex_unlock(&dev->struct_mutex);
1098         return ret;
1099 }
1100
1101 /**
1102  * Maps the contents of an object, returning the address it is mapped
1103  * into.
1104  *
1105  * While the mapping holds a reference on the contents of the object, it doesn't
1106  * imply a ref on the object itself.
1107  */
1108 int
1109 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1110                    struct drm_file *file_priv)
1111 {
1112         struct drm_i915_gem_mmap *args = data;
1113         struct drm_gem_object *obj;
1114         loff_t offset;
1115         unsigned long addr;
1116
1117         if (!(dev->driver->driver_features & DRIVER_GEM))
1118                 return -ENODEV;
1119
1120         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1121         if (obj == NULL)
1122                 return -ENOENT;
1123
1124         offset = args->offset;
1125
1126         down_write(&current->mm->mmap_sem);
1127         addr = do_mmap(obj->filp, 0, args->size,
1128                        PROT_READ | PROT_WRITE, MAP_SHARED,
1129                        args->offset);
1130         up_write(&current->mm->mmap_sem);
1131         drm_gem_object_unreference_unlocked(obj);
1132         if (IS_ERR((void *)addr))
1133                 return addr;
1134
1135         args->addr_ptr = (uint64_t) addr;
1136
1137         return 0;
1138 }
1139
1140 /**
1141  * i915_gem_fault - fault a page into the GTT
1142  * vma: VMA in question
1143  * vmf: fault info
1144  *
1145  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146  * from userspace.  The fault handler takes care of binding the object to
1147  * the GTT (if needed), allocating and programming a fence register (again,
1148  * only if needed based on whether the old reg is still valid or the object
1149  * is tiled) and inserting a new PTE into the faulting process.
1150  *
1151  * Note that the faulting process may involve evicting existing objects
1152  * from the GTT and/or fence registers to make room.  So performance may
1153  * suffer if the GTT working set is large or there are few fence registers
1154  * left.
1155  */
1156 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1157 {
1158         struct drm_gem_object *obj = vma->vm_private_data;
1159         struct drm_device *dev = obj->dev;
1160         drm_i915_private_t *dev_priv = dev->dev_private;
1161         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1162         pgoff_t page_offset;
1163         unsigned long pfn;
1164         int ret = 0;
1165         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1166
1167         /* We don't use vmf->pgoff since that has the fake offset */
1168         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1169                 PAGE_SHIFT;
1170
1171         /* Now bind it into the GTT if needed */
1172         mutex_lock(&dev->struct_mutex);
1173         if (!obj_priv->gtt_space) {
1174                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1175                 if (ret)
1176                         goto unlock;
1177
1178                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1179                 if (ret)
1180                         goto unlock;
1181         }
1182
1183         /* Need a new fence register? */
1184         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1185                 ret = i915_gem_object_get_fence_reg(obj, true);
1186                 if (ret)
1187                         goto unlock;
1188         }
1189
1190         if (i915_gem_object_is_inactive(obj_priv))
1191                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192
1193         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1194                 page_offset;
1195
1196         /* Finally, remap it using the new GTT offset */
1197         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1198 unlock:
1199         mutex_unlock(&dev->struct_mutex);
1200
1201         switch (ret) {
1202         case 0:
1203         case -ERESTARTSYS:
1204                 return VM_FAULT_NOPAGE;
1205         case -ENOMEM:
1206         case -EAGAIN:
1207                 return VM_FAULT_OOM;
1208         default:
1209                 return VM_FAULT_SIGBUS;
1210         }
1211 }
1212
1213 /**
1214  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215  * @obj: obj in question
1216  *
1217  * GEM memory mapping works by handing back to userspace a fake mmap offset
1218  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1219  * up the object based on the offset and sets up the various memory mapping
1220  * structures.
1221  *
1222  * This routine allocates and attaches a fake offset for @obj.
1223  */
1224 static int
1225 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1226 {
1227         struct drm_device *dev = obj->dev;
1228         struct drm_gem_mm *mm = dev->mm_private;
1229         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1230         struct drm_map_list *list;
1231         struct drm_local_map *map;
1232         int ret = 0;
1233
1234         /* Set the object up for mmap'ing */
1235         list = &obj->map_list;
1236         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1237         if (!list->map)
1238                 return -ENOMEM;
1239
1240         map = list->map;
1241         map->type = _DRM_GEM;
1242         map->size = obj->size;
1243         map->handle = obj;
1244
1245         /* Get a DRM GEM mmap offset allocated... */
1246         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1247                                                     obj->size / PAGE_SIZE, 0, 0);
1248         if (!list->file_offset_node) {
1249                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1250                 ret = -ENOMEM;
1251                 goto out_free_list;
1252         }
1253
1254         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1255                                                   obj->size / PAGE_SIZE, 0);
1256         if (!list->file_offset_node) {
1257                 ret = -ENOMEM;
1258                 goto out_free_list;
1259         }
1260
1261         list->hash.key = list->file_offset_node->start;
1262         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1263                 DRM_ERROR("failed to add to map hash\n");
1264                 ret = -ENOMEM;
1265                 goto out_free_mm;
1266         }
1267
1268         /* By now we should be all set, any drm_mmap request on the offset
1269          * below will get to our mmap & fault handler */
1270         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1271
1272         return 0;
1273
1274 out_free_mm:
1275         drm_mm_put_block(list->file_offset_node);
1276 out_free_list:
1277         kfree(list->map);
1278
1279         return ret;
1280 }
1281
1282 /**
1283  * i915_gem_release_mmap - remove physical page mappings
1284  * @obj: obj in question
1285  *
1286  * Preserve the reservation of the mmapping with the DRM core code, but
1287  * relinquish ownership of the pages back to the system.
1288  *
1289  * It is vital that we remove the page mapping if we have mapped a tiled
1290  * object through the GTT and then lose the fence register due to
1291  * resource pressure. Similarly if the object has been moved out of the
1292  * aperture, than pages mapped into userspace must be revoked. Removing the
1293  * mapping will then trigger a page fault on the next user access, allowing
1294  * fixup by i915_gem_fault().
1295  */
1296 void
1297 i915_gem_release_mmap(struct drm_gem_object *obj)
1298 {
1299         struct drm_device *dev = obj->dev;
1300         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1301
1302         if (dev->dev_mapping)
1303                 unmap_mapping_range(dev->dev_mapping,
1304                                     obj_priv->mmap_offset, obj->size, 1);
1305 }
1306
1307 static void
1308 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1312         struct drm_gem_mm *mm = dev->mm_private;
1313         struct drm_map_list *list;
1314
1315         list = &obj->map_list;
1316         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1317
1318         if (list->file_offset_node) {
1319                 drm_mm_put_block(list->file_offset_node);
1320                 list->file_offset_node = NULL;
1321         }
1322
1323         if (list->map) {
1324                 kfree(list->map);
1325                 list->map = NULL;
1326         }
1327
1328         obj_priv->mmap_offset = 0;
1329 }
1330
1331 /**
1332  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333  * @obj: object to check
1334  *
1335  * Return the required GTT alignment for an object, taking into account
1336  * potential fence register mapping if needed.
1337  */
1338 static uint32_t
1339 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1340 {
1341         struct drm_device *dev = obj->dev;
1342         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1343         int start, i;
1344
1345         /*
1346          * Minimum alignment is 4k (GTT page size), but might be greater
1347          * if a fence register is needed for the object.
1348          */
1349         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1350                 return 4096;
1351
1352         /*
1353          * Previous chips need to be aligned to the size of the smallest
1354          * fence register that can contain the object.
1355          */
1356         if (IS_I9XX(dev))
1357                 start = 1024*1024;
1358         else
1359                 start = 512*1024;
1360
1361         for (i = start; i < obj->size; i <<= 1)
1362                 ;
1363
1364         return i;
1365 }
1366
1367 /**
1368  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1369  * @dev: DRM device
1370  * @data: GTT mapping ioctl data
1371  * @file_priv: GEM object info
1372  *
1373  * Simply returns the fake offset to userspace so it can mmap it.
1374  * The mmap call will end up in drm_gem_mmap(), which will set things
1375  * up so we can get faults in the handler above.
1376  *
1377  * The fault handler will take care of binding the object into the GTT
1378  * (since it may have been evicted to make room for something), allocating
1379  * a fence register, and mapping the appropriate aperture address into
1380  * userspace.
1381  */
1382 int
1383 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1384                         struct drm_file *file_priv)
1385 {
1386         struct drm_i915_gem_mmap_gtt *args = data;
1387         struct drm_gem_object *obj;
1388         struct drm_i915_gem_object *obj_priv;
1389         int ret;
1390
1391         if (!(dev->driver->driver_features & DRIVER_GEM))
1392                 return -ENODEV;
1393
1394         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1395         if (obj == NULL)
1396                 return -ENOENT;
1397
1398         mutex_lock(&dev->struct_mutex);
1399
1400         obj_priv = to_intel_bo(obj);
1401
1402         if (obj_priv->madv != I915_MADV_WILLNEED) {
1403                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404                 drm_gem_object_unreference(obj);
1405                 mutex_unlock(&dev->struct_mutex);
1406                 return -EINVAL;
1407         }
1408
1409
1410         if (!obj_priv->mmap_offset) {
1411                 ret = i915_gem_create_mmap_offset(obj);
1412                 if (ret) {
1413                         drm_gem_object_unreference(obj);
1414                         mutex_unlock(&dev->struct_mutex);
1415                         return ret;
1416                 }
1417         }
1418
1419         args->offset = obj_priv->mmap_offset;
1420
1421         /*
1422          * Pull it into the GTT so that we have a page list (makes the
1423          * initial fault faster and any subsequent flushing possible).
1424          */
1425         if (!obj_priv->agp_mem) {
1426                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1427                 if (ret) {
1428                         drm_gem_object_unreference(obj);
1429                         mutex_unlock(&dev->struct_mutex);
1430                         return ret;
1431                 }
1432         }
1433
1434         drm_gem_object_unreference(obj);
1435         mutex_unlock(&dev->struct_mutex);
1436
1437         return 0;
1438 }
1439
1440 void
1441 i915_gem_object_put_pages(struct drm_gem_object *obj)
1442 {
1443         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1444         int page_count = obj->size / PAGE_SIZE;
1445         int i;
1446
1447         BUG_ON(obj_priv->pages_refcount == 0);
1448         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1449
1450         if (--obj_priv->pages_refcount != 0)
1451                 return;
1452
1453         if (obj_priv->tiling_mode != I915_TILING_NONE)
1454                 i915_gem_object_save_bit_17_swizzle(obj);
1455
1456         if (obj_priv->madv == I915_MADV_DONTNEED)
1457                 obj_priv->dirty = 0;
1458
1459         for (i = 0; i < page_count; i++) {
1460                 if (obj_priv->dirty)
1461                         set_page_dirty(obj_priv->pages[i]);
1462
1463                 if (obj_priv->madv == I915_MADV_WILLNEED)
1464                         mark_page_accessed(obj_priv->pages[i]);
1465
1466                 page_cache_release(obj_priv->pages[i]);
1467         }
1468         obj_priv->dirty = 0;
1469
1470         drm_free_large(obj_priv->pages);
1471         obj_priv->pages = NULL;
1472 }
1473
1474 static uint32_t
1475 i915_gem_next_request_seqno(struct drm_device *dev,
1476                             struct intel_ring_buffer *ring)
1477 {
1478         drm_i915_private_t *dev_priv = dev->dev_private;
1479
1480         ring->outstanding_lazy_request = true;
1481
1482         return dev_priv->next_seqno;
1483 }
1484
1485 static void
1486 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1487                                struct intel_ring_buffer *ring)
1488 {
1489         struct drm_device *dev = obj->dev;
1490         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1492
1493         BUG_ON(ring == NULL);
1494         obj_priv->ring = ring;
1495
1496         /* Add a reference if we're newly entering the active list. */
1497         if (!obj_priv->active) {
1498                 drm_gem_object_reference(obj);
1499                 obj_priv->active = 1;
1500         }
1501
1502         /* Move from whatever list we were on to the tail of execution. */
1503         list_move_tail(&obj_priv->list, &ring->active_list);
1504         obj_priv->last_rendering_seqno = seqno;
1505 }
1506
1507 static void
1508 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509 {
1510         struct drm_device *dev = obj->dev;
1511         drm_i915_private_t *dev_priv = dev->dev_private;
1512         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1513
1514         BUG_ON(!obj_priv->active);
1515         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516         obj_priv->last_rendering_seqno = 0;
1517 }
1518
1519 /* Immediately discard the backing storage */
1520 static void
1521 i915_gem_object_truncate(struct drm_gem_object *obj)
1522 {
1523         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1524         struct inode *inode;
1525
1526         /* Our goal here is to return as much of the memory as
1527          * is possible back to the system as we are called from OOM.
1528          * To do this we must instruct the shmfs to drop all of its
1529          * backing pages, *now*. Here we mirror the actions taken
1530          * when by shmem_delete_inode() to release the backing store.
1531          */
1532         inode = obj->filp->f_path.dentry->d_inode;
1533         truncate_inode_pages(inode->i_mapping, 0);
1534         if (inode->i_op->truncate_range)
1535                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1536
1537         obj_priv->madv = __I915_MADV_PURGED;
1538 }
1539
1540 static inline int
1541 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1542 {
1543         return obj_priv->madv == I915_MADV_DONTNEED;
1544 }
1545
1546 static void
1547 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1548 {
1549         struct drm_device *dev = obj->dev;
1550         drm_i915_private_t *dev_priv = dev->dev_private;
1551         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1552
1553         i915_verify_inactive(dev, __FILE__, __LINE__);
1554         if (obj_priv->pin_count != 0)
1555                 list_del_init(&obj_priv->list);
1556         else
1557                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1558
1559         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1560
1561         obj_priv->last_rendering_seqno = 0;
1562         obj_priv->ring = NULL;
1563         if (obj_priv->active) {
1564                 obj_priv->active = 0;
1565                 drm_gem_object_unreference(obj);
1566         }
1567         i915_verify_inactive(dev, __FILE__, __LINE__);
1568 }
1569
1570 void
1571 i915_gem_process_flushing_list(struct drm_device *dev,
1572                                uint32_t flush_domains,
1573                                struct intel_ring_buffer *ring)
1574 {
1575         drm_i915_private_t *dev_priv = dev->dev_private;
1576         struct drm_i915_gem_object *obj_priv, *next;
1577
1578         list_for_each_entry_safe(obj_priv, next,
1579                                  &dev_priv->mm.gpu_write_list,
1580                                  gpu_write_list) {
1581                 struct drm_gem_object *obj = &obj_priv->base;
1582
1583                 if (obj->write_domain & flush_domains &&
1584                     obj_priv->ring == ring) {
1585                         uint32_t old_write_domain = obj->write_domain;
1586
1587                         obj->write_domain = 0;
1588                         list_del_init(&obj_priv->gpu_write_list);
1589                         i915_gem_object_move_to_active(obj, ring);
1590
1591                         /* update the fence lru list */
1592                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1593                                 struct drm_i915_fence_reg *reg =
1594                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1595                                 list_move_tail(&reg->lru_list,
1596                                                 &dev_priv->mm.fence_list);
1597                         }
1598
1599                         trace_i915_gem_object_change_domain(obj,
1600                                                             obj->read_domains,
1601                                                             old_write_domain);
1602                 }
1603         }
1604 }
1605
1606 uint32_t
1607 i915_add_request(struct drm_device *dev,
1608                  struct drm_file *file_priv,
1609                  struct drm_i915_gem_request *request,
1610                  struct intel_ring_buffer *ring)
1611 {
1612         drm_i915_private_t *dev_priv = dev->dev_private;
1613         struct drm_i915_file_private *i915_file_priv = NULL;
1614         uint32_t seqno;
1615         int was_empty;
1616
1617         if (file_priv != NULL)
1618                 i915_file_priv = file_priv->driver_priv;
1619
1620         if (request == NULL) {
1621                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1622                 if (request == NULL)
1623                         return 0;
1624         }
1625
1626         seqno = ring->add_request(dev, ring, file_priv, 0);
1627
1628         request->seqno = seqno;
1629         request->ring = ring;
1630         request->emitted_jiffies = jiffies;
1631         was_empty = list_empty(&ring->request_list);
1632         list_add_tail(&request->list, &ring->request_list);
1633
1634         if (i915_file_priv) {
1635                 list_add_tail(&request->client_list,
1636                               &i915_file_priv->mm.request_list);
1637         } else {
1638                 INIT_LIST_HEAD(&request->client_list);
1639         }
1640
1641         if (!dev_priv->mm.suspended) {
1642                 mod_timer(&dev_priv->hangcheck_timer,
1643                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1644                 if (was_empty)
1645                         queue_delayed_work(dev_priv->wq,
1646                                            &dev_priv->mm.retire_work, HZ);
1647         }
1648         return seqno;
1649 }
1650
1651 /**
1652  * Command execution barrier
1653  *
1654  * Ensures that all commands in the ring are finished
1655  * before signalling the CPU
1656  */
1657 static void
1658 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1659 {
1660         uint32_t flush_domains = 0;
1661
1662         /* The sampler always gets flushed on i965 (sigh) */
1663         if (IS_I965G(dev))
1664                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1665
1666         ring->flush(dev, ring,
1667                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1668 }
1669
1670 /**
1671  * Moves buffers associated only with the given active seqno from the active
1672  * to inactive list, potentially freeing them.
1673  */
1674 static void
1675 i915_gem_retire_request(struct drm_device *dev,
1676                         struct drm_i915_gem_request *request)
1677 {
1678         trace_i915_gem_request_retire(dev, request->seqno);
1679
1680         /* Move any buffers on the active list that are no longer referenced
1681          * by the ringbuffer to the flushing/inactive lists as appropriate.
1682          */
1683         while (!list_empty(&request->ring->active_list)) {
1684                 struct drm_gem_object *obj;
1685                 struct drm_i915_gem_object *obj_priv;
1686
1687                 obj_priv = list_first_entry(&request->ring->active_list,
1688                                             struct drm_i915_gem_object,
1689                                             list);
1690                 obj = &obj_priv->base;
1691
1692                 /* If the seqno being retired doesn't match the oldest in the
1693                  * list, then the oldest in the list must still be newer than
1694                  * this seqno.
1695                  */
1696                 if (obj_priv->last_rendering_seqno != request->seqno)
1697                         return;
1698
1699 #if WATCH_LRU
1700                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1701                          __func__, request->seqno, obj);
1702 #endif
1703
1704                 if (obj->write_domain != 0)
1705                         i915_gem_object_move_to_flushing(obj);
1706                 else
1707                         i915_gem_object_move_to_inactive(obj);
1708         }
1709 }
1710
1711 /**
1712  * Returns true if seq1 is later than seq2.
1713  */
1714 bool
1715 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1716 {
1717         return (int32_t)(seq1 - seq2) >= 0;
1718 }
1719
1720 uint32_t
1721 i915_get_gem_seqno(struct drm_device *dev,
1722                    struct intel_ring_buffer *ring)
1723 {
1724         return ring->get_gem_seqno(dev, ring);
1725 }
1726
1727 /**
1728  * This function clears the request list as sequence numbers are passed.
1729  */
1730 static void
1731 i915_gem_retire_requests_ring(struct drm_device *dev,
1732                               struct intel_ring_buffer *ring)
1733 {
1734         drm_i915_private_t *dev_priv = dev->dev_private;
1735         uint32_t seqno;
1736
1737         if (!ring->status_page.page_addr
1738                         || list_empty(&ring->request_list))
1739                 return;
1740
1741         seqno = i915_get_gem_seqno(dev, ring);
1742
1743         while (!list_empty(&ring->request_list)) {
1744                 struct drm_i915_gem_request *request;
1745                 uint32_t retiring_seqno;
1746
1747                 request = list_first_entry(&ring->request_list,
1748                                            struct drm_i915_gem_request,
1749                                            list);
1750                 retiring_seqno = request->seqno;
1751
1752                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1753                     atomic_read(&dev_priv->mm.wedged)) {
1754                         i915_gem_retire_request(dev, request);
1755
1756                         list_del(&request->list);
1757                         list_del(&request->client_list);
1758                         kfree(request);
1759                 } else
1760                         break;
1761         }
1762
1763         if (unlikely (dev_priv->trace_irq_seqno &&
1764                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1765
1766                 ring->user_irq_put(dev, ring);
1767                 dev_priv->trace_irq_seqno = 0;
1768         }
1769 }
1770
1771 void
1772 i915_gem_retire_requests(struct drm_device *dev)
1773 {
1774         drm_i915_private_t *dev_priv = dev->dev_private;
1775
1776         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1777             struct drm_i915_gem_object *obj_priv, *tmp;
1778
1779             /* We must be careful that during unbind() we do not
1780              * accidentally infinitely recurse into retire requests.
1781              * Currently:
1782              *   retire -> free -> unbind -> wait -> retire_ring
1783              */
1784             list_for_each_entry_safe(obj_priv, tmp,
1785                                      &dev_priv->mm.deferred_free_list,
1786                                      list)
1787                     i915_gem_free_object_tail(&obj_priv->base);
1788         }
1789
1790         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1791         if (HAS_BSD(dev))
1792                 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1793 }
1794
1795 static void
1796 i915_gem_retire_work_handler(struct work_struct *work)
1797 {
1798         drm_i915_private_t *dev_priv;
1799         struct drm_device *dev;
1800
1801         dev_priv = container_of(work, drm_i915_private_t,
1802                                 mm.retire_work.work);
1803         dev = dev_priv->dev;
1804
1805         mutex_lock(&dev->struct_mutex);
1806         i915_gem_retire_requests(dev);
1807
1808         if (!dev_priv->mm.suspended &&
1809                 (!list_empty(&dev_priv->render_ring.request_list) ||
1810                         (HAS_BSD(dev) &&
1811                          !list_empty(&dev_priv->bsd_ring.request_list))))
1812                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1813         mutex_unlock(&dev->struct_mutex);
1814 }
1815
1816 int
1817 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1818                      bool interruptible, struct intel_ring_buffer *ring)
1819 {
1820         drm_i915_private_t *dev_priv = dev->dev_private;
1821         u32 ier;
1822         int ret = 0;
1823
1824         BUG_ON(seqno == 0);
1825
1826         if (seqno == dev_priv->next_seqno) {
1827                 seqno = i915_add_request(dev, NULL, NULL, ring);
1828                 if (seqno == 0)
1829                         return -ENOMEM;
1830         }
1831
1832         if (atomic_read(&dev_priv->mm.wedged))
1833                 return -EIO;
1834
1835         if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1836                 if (HAS_PCH_SPLIT(dev))
1837                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1838                 else
1839                         ier = I915_READ(IER);
1840                 if (!ier) {
1841                         DRM_ERROR("something (likely vbetool) disabled "
1842                                   "interrupts, re-enabling\n");
1843                         i915_driver_irq_preinstall(dev);
1844                         i915_driver_irq_postinstall(dev);
1845                 }
1846
1847                 trace_i915_gem_request_wait_begin(dev, seqno);
1848
1849                 ring->waiting_gem_seqno = seqno;
1850                 ring->user_irq_get(dev, ring);
1851                 if (interruptible)
1852                         ret = wait_event_interruptible(ring->irq_queue,
1853                                 i915_seqno_passed(
1854                                         ring->get_gem_seqno(dev, ring), seqno)
1855                                 || atomic_read(&dev_priv->mm.wedged));
1856                 else
1857                         wait_event(ring->irq_queue,
1858                                 i915_seqno_passed(
1859                                         ring->get_gem_seqno(dev, ring), seqno)
1860                                 || atomic_read(&dev_priv->mm.wedged));
1861
1862                 ring->user_irq_put(dev, ring);
1863                 ring->waiting_gem_seqno = 0;
1864
1865                 trace_i915_gem_request_wait_end(dev, seqno);
1866         }
1867         if (atomic_read(&dev_priv->mm.wedged))
1868                 ret = -EIO;
1869
1870         if (ret && ret != -ERESTARTSYS)
1871                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1872                           __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1873                           dev_priv->next_seqno);
1874
1875         /* Directly dispatch request retiring.  While we have the work queue
1876          * to handle this, the waiter on a request often wants an associated
1877          * buffer to have made it to the inactive list, and we would need
1878          * a separate wait queue to handle that.
1879          */
1880         if (ret == 0)
1881                 i915_gem_retire_requests_ring(dev, ring);
1882
1883         return ret;
1884 }
1885
1886 /**
1887  * Waits for a sequence number to be signaled, and cleans up the
1888  * request and object lists appropriately for that event.
1889  */
1890 static int
1891 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1892                 struct intel_ring_buffer *ring)
1893 {
1894         return i915_do_wait_request(dev, seqno, 1, ring);
1895 }
1896
1897 static void
1898 i915_gem_flush(struct drm_device *dev,
1899                uint32_t invalidate_domains,
1900                uint32_t flush_domains)
1901 {
1902         drm_i915_private_t *dev_priv = dev->dev_private;
1903
1904         if (flush_domains & I915_GEM_DOMAIN_CPU)
1905                 drm_agp_chipset_flush(dev);
1906
1907         dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1908                         invalidate_domains,
1909                         flush_domains);
1910
1911         if (HAS_BSD(dev))
1912                 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1913                                 invalidate_domains,
1914                                 flush_domains);
1915 }
1916
1917 /**
1918  * Ensures that all rendering to the object has completed and the object is
1919  * safe to unbind from the GTT or access from the CPU.
1920  */
1921 static int
1922 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1923                                bool interruptible)
1924 {
1925         struct drm_device *dev = obj->dev;
1926         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1927         int ret;
1928
1929         /* This function only exists to support waiting for existing rendering,
1930          * not for emitting required flushes.
1931          */
1932         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1933
1934         /* If there is rendering queued on the buffer being evicted, wait for
1935          * it.
1936          */
1937         if (obj_priv->active) {
1938 #if WATCH_BUF
1939                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1940                           __func__, obj, obj_priv->last_rendering_seqno);
1941 #endif
1942                 ret = i915_do_wait_request(dev,
1943                                            obj_priv->last_rendering_seqno,
1944                                            interruptible,
1945                                            obj_priv->ring);
1946                 if (ret)
1947                         return ret;
1948         }
1949
1950         return 0;
1951 }
1952
1953 /**
1954  * Unbinds an object from the GTT aperture.
1955  */
1956 int
1957 i915_gem_object_unbind(struct drm_gem_object *obj)
1958 {
1959         struct drm_device *dev = obj->dev;
1960         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1961         int ret = 0;
1962
1963 #if WATCH_BUF
1964         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1965         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1966 #endif
1967         if (obj_priv->gtt_space == NULL)
1968                 return 0;
1969
1970         if (obj_priv->pin_count != 0) {
1971                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1972                 return -EINVAL;
1973         }
1974
1975         /* blow away mappings if mapped through GTT */
1976         i915_gem_release_mmap(obj);
1977
1978         /* Move the object to the CPU domain to ensure that
1979          * any possible CPU writes while it's not in the GTT
1980          * are flushed when we go to remap it. This will
1981          * also ensure that all pending GPU writes are finished
1982          * before we unbind.
1983          */
1984         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1985         if (ret == -ERESTARTSYS)
1986                 return ret;
1987         /* Continue on if we fail due to EIO, the GPU is hung so we
1988          * should be safe and we need to cleanup or else we might
1989          * cause memory corruption through use-after-free.
1990          */
1991
1992         /* release the fence reg _after_ flushing */
1993         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1994                 i915_gem_clear_fence_reg(obj);
1995
1996         if (obj_priv->agp_mem != NULL) {
1997                 drm_unbind_agp(obj_priv->agp_mem);
1998                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1999                 obj_priv->agp_mem = NULL;
2000         }
2001
2002         i915_gem_object_put_pages(obj);
2003         BUG_ON(obj_priv->pages_refcount);
2004
2005         if (obj_priv->gtt_space) {
2006                 atomic_dec(&dev->gtt_count);
2007                 atomic_sub(obj->size, &dev->gtt_memory);
2008
2009                 drm_mm_put_block(obj_priv->gtt_space);
2010                 obj_priv->gtt_space = NULL;
2011         }
2012
2013         /* Remove ourselves from the LRU list if present. */
2014         if (!list_empty(&obj_priv->list))
2015                 list_del_init(&obj_priv->list);
2016
2017         if (i915_gem_object_is_purgeable(obj_priv))
2018                 i915_gem_object_truncate(obj);
2019
2020         trace_i915_gem_object_unbind(obj);
2021
2022         return ret;
2023 }
2024
2025 int
2026 i915_gpu_idle(struct drm_device *dev)
2027 {
2028         drm_i915_private_t *dev_priv = dev->dev_private;
2029         bool lists_empty;
2030         int ret;
2031
2032         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2033                        list_empty(&dev_priv->render_ring.active_list) &&
2034                        (!HAS_BSD(dev) ||
2035                         list_empty(&dev_priv->bsd_ring.active_list)));
2036         if (lists_empty)
2037                 return 0;
2038
2039         /* Flush everything onto the inactive list. */
2040         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2041
2042         ret = i915_wait_request(dev,
2043                                 i915_gem_next_request_seqno(dev, &dev_priv->render_ring),
2044                                 &dev_priv->render_ring);
2045         if (ret)
2046                 return ret;
2047
2048         if (HAS_BSD(dev)) {
2049                 ret = i915_wait_request(dev,
2050                                         i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring),
2051                                         &dev_priv->bsd_ring);
2052                 if (ret)
2053                         return ret;
2054         }
2055
2056         return 0;
2057 }
2058
2059 int
2060 i915_gem_object_get_pages(struct drm_gem_object *obj,
2061                           gfp_t gfpmask)
2062 {
2063         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2064         int page_count, i;
2065         struct address_space *mapping;
2066         struct inode *inode;
2067         struct page *page;
2068
2069         BUG_ON(obj_priv->pages_refcount
2070                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2071
2072         if (obj_priv->pages_refcount++ != 0)
2073                 return 0;
2074
2075         /* Get the list of pages out of our struct file.  They'll be pinned
2076          * at this point until we release them.
2077          */
2078         page_count = obj->size / PAGE_SIZE;
2079         BUG_ON(obj_priv->pages != NULL);
2080         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2081         if (obj_priv->pages == NULL) {
2082                 obj_priv->pages_refcount--;
2083                 return -ENOMEM;
2084         }
2085
2086         inode = obj->filp->f_path.dentry->d_inode;
2087         mapping = inode->i_mapping;
2088         for (i = 0; i < page_count; i++) {
2089                 page = read_cache_page_gfp(mapping, i,
2090                                            GFP_HIGHUSER |
2091                                            __GFP_COLD |
2092                                            __GFP_RECLAIMABLE |
2093                                            gfpmask);
2094                 if (IS_ERR(page))
2095                         goto err_pages;
2096
2097                 obj_priv->pages[i] = page;
2098         }
2099
2100         if (obj_priv->tiling_mode != I915_TILING_NONE)
2101                 i915_gem_object_do_bit_17_swizzle(obj);
2102
2103         return 0;
2104
2105 err_pages:
2106         while (i--)
2107                 page_cache_release(obj_priv->pages[i]);
2108
2109         drm_free_large(obj_priv->pages);
2110         obj_priv->pages = NULL;
2111         obj_priv->pages_refcount--;
2112         return PTR_ERR(page);
2113 }
2114
2115 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2116 {
2117         struct drm_gem_object *obj = reg->obj;
2118         struct drm_device *dev = obj->dev;
2119         drm_i915_private_t *dev_priv = dev->dev_private;
2120         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2121         int regnum = obj_priv->fence_reg;
2122         uint64_t val;
2123
2124         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2125                     0xfffff000) << 32;
2126         val |= obj_priv->gtt_offset & 0xfffff000;
2127         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2128                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2129
2130         if (obj_priv->tiling_mode == I915_TILING_Y)
2131                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2132         val |= I965_FENCE_REG_VALID;
2133
2134         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2135 }
2136
2137 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2138 {
2139         struct drm_gem_object *obj = reg->obj;
2140         struct drm_device *dev = obj->dev;
2141         drm_i915_private_t *dev_priv = dev->dev_private;
2142         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2143         int regnum = obj_priv->fence_reg;
2144         uint64_t val;
2145
2146         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2147                     0xfffff000) << 32;
2148         val |= obj_priv->gtt_offset & 0xfffff000;
2149         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2150         if (obj_priv->tiling_mode == I915_TILING_Y)
2151                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2152         val |= I965_FENCE_REG_VALID;
2153
2154         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2155 }
2156
2157 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2158 {
2159         struct drm_gem_object *obj = reg->obj;
2160         struct drm_device *dev = obj->dev;
2161         drm_i915_private_t *dev_priv = dev->dev_private;
2162         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2163         int regnum = obj_priv->fence_reg;
2164         int tile_width;
2165         uint32_t fence_reg, val;
2166         uint32_t pitch_val;
2167
2168         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2169             (obj_priv->gtt_offset & (obj->size - 1))) {
2170                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2171                      __func__, obj_priv->gtt_offset, obj->size);
2172                 return;
2173         }
2174
2175         if (obj_priv->tiling_mode == I915_TILING_Y &&
2176             HAS_128_BYTE_Y_TILING(dev))
2177                 tile_width = 128;
2178         else
2179                 tile_width = 512;
2180
2181         /* Note: pitch better be a power of two tile widths */
2182         pitch_val = obj_priv->stride / tile_width;
2183         pitch_val = ffs(pitch_val) - 1;
2184
2185         if (obj_priv->tiling_mode == I915_TILING_Y &&
2186             HAS_128_BYTE_Y_TILING(dev))
2187                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2188         else
2189                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2190
2191         val = obj_priv->gtt_offset;
2192         if (obj_priv->tiling_mode == I915_TILING_Y)
2193                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2194         val |= I915_FENCE_SIZE_BITS(obj->size);
2195         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2196         val |= I830_FENCE_REG_VALID;
2197
2198         if (regnum < 8)
2199                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2200         else
2201                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2202         I915_WRITE(fence_reg, val);
2203 }
2204
2205 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2206 {
2207         struct drm_gem_object *obj = reg->obj;
2208         struct drm_device *dev = obj->dev;
2209         drm_i915_private_t *dev_priv = dev->dev_private;
2210         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2211         int regnum = obj_priv->fence_reg;
2212         uint32_t val;
2213         uint32_t pitch_val;
2214         uint32_t fence_size_bits;
2215
2216         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2217             (obj_priv->gtt_offset & (obj->size - 1))) {
2218                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2219                      __func__, obj_priv->gtt_offset);
2220                 return;
2221         }
2222
2223         pitch_val = obj_priv->stride / 128;
2224         pitch_val = ffs(pitch_val) - 1;
2225         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2226
2227         val = obj_priv->gtt_offset;
2228         if (obj_priv->tiling_mode == I915_TILING_Y)
2229                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2230         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2231         WARN_ON(fence_size_bits & ~0x00000f00);
2232         val |= fence_size_bits;
2233         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2234         val |= I830_FENCE_REG_VALID;
2235
2236         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2237 }
2238
2239 static int i915_find_fence_reg(struct drm_device *dev,
2240                                bool interruptible)
2241 {
2242         struct drm_i915_fence_reg *reg = NULL;
2243         struct drm_i915_gem_object *obj_priv = NULL;
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct drm_gem_object *obj = NULL;
2246         int i, avail, ret;
2247
2248         /* First try to find a free reg */
2249         avail = 0;
2250         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2251                 reg = &dev_priv->fence_regs[i];
2252                 if (!reg->obj)
2253                         return i;
2254
2255                 obj_priv = to_intel_bo(reg->obj);
2256                 if (!obj_priv->pin_count)
2257                     avail++;
2258         }
2259
2260         if (avail == 0)
2261                 return -ENOSPC;
2262
2263         /* None available, try to steal one or wait for a user to finish */
2264         i = I915_FENCE_REG_NONE;
2265         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2266                             lru_list) {
2267                 obj = reg->obj;
2268                 obj_priv = to_intel_bo(obj);
2269
2270                 if (obj_priv->pin_count)
2271                         continue;
2272
2273                 /* found one! */
2274                 i = obj_priv->fence_reg;
2275                 break;
2276         }
2277
2278         BUG_ON(i == I915_FENCE_REG_NONE);
2279
2280         /* We only have a reference on obj from the active list. put_fence_reg
2281          * might drop that one, causing a use-after-free in it. So hold a
2282          * private reference to obj like the other callers of put_fence_reg
2283          * (set_tiling ioctl) do. */
2284         drm_gem_object_reference(obj);
2285         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2286         drm_gem_object_unreference(obj);
2287         if (ret != 0)
2288                 return ret;
2289
2290         return i;
2291 }
2292
2293 /**
2294  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2295  * @obj: object to map through a fence reg
2296  *
2297  * When mapping objects through the GTT, userspace wants to be able to write
2298  * to them without having to worry about swizzling if the object is tiled.
2299  *
2300  * This function walks the fence regs looking for a free one for @obj,
2301  * stealing one if it can't find any.
2302  *
2303  * It then sets up the reg based on the object's properties: address, pitch
2304  * and tiling format.
2305  */
2306 int
2307 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2308                               bool interruptible)
2309 {
2310         struct drm_device *dev = obj->dev;
2311         struct drm_i915_private *dev_priv = dev->dev_private;
2312         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2313         struct drm_i915_fence_reg *reg = NULL;
2314         int ret;
2315
2316         /* Just update our place in the LRU if our fence is getting used. */
2317         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2318                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2319                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2320                 return 0;
2321         }
2322
2323         switch (obj_priv->tiling_mode) {
2324         case I915_TILING_NONE:
2325                 WARN(1, "allocating a fence for non-tiled object?\n");
2326                 break;
2327         case I915_TILING_X:
2328                 if (!obj_priv->stride)
2329                         return -EINVAL;
2330                 WARN((obj_priv->stride & (512 - 1)),
2331                      "object 0x%08x is X tiled but has non-512B pitch\n",
2332                      obj_priv->gtt_offset);
2333                 break;
2334         case I915_TILING_Y:
2335                 if (!obj_priv->stride)
2336                         return -EINVAL;
2337                 WARN((obj_priv->stride & (128 - 1)),
2338                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2339                      obj_priv->gtt_offset);
2340                 break;
2341         }
2342
2343         ret = i915_find_fence_reg(dev, interruptible);
2344         if (ret < 0)
2345                 return ret;
2346
2347         obj_priv->fence_reg = ret;
2348         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2349         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2350
2351         reg->obj = obj;
2352
2353         if (IS_GEN6(dev))
2354                 sandybridge_write_fence_reg(reg);
2355         else if (IS_I965G(dev))
2356                 i965_write_fence_reg(reg);
2357         else if (IS_I9XX(dev))
2358                 i915_write_fence_reg(reg);
2359         else
2360                 i830_write_fence_reg(reg);
2361
2362         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2363                         obj_priv->tiling_mode);
2364
2365         return 0;
2366 }
2367
2368 /**
2369  * i915_gem_clear_fence_reg - clear out fence register info
2370  * @obj: object to clear
2371  *
2372  * Zeroes out the fence register itself and clears out the associated
2373  * data structures in dev_priv and obj_priv.
2374  */
2375 static void
2376 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2377 {
2378         struct drm_device *dev = obj->dev;
2379         drm_i915_private_t *dev_priv = dev->dev_private;
2380         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2381         struct drm_i915_fence_reg *reg =
2382                 &dev_priv->fence_regs[obj_priv->fence_reg];
2383
2384         if (IS_GEN6(dev)) {
2385                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2386                              (obj_priv->fence_reg * 8), 0);
2387         } else if (IS_I965G(dev)) {
2388                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2389         } else {
2390                 uint32_t fence_reg;
2391
2392                 if (obj_priv->fence_reg < 8)
2393                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2394                 else
2395                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2396                                                        8) * 4;
2397
2398                 I915_WRITE(fence_reg, 0);
2399         }
2400
2401         reg->obj = NULL;
2402         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2403         list_del_init(&reg->lru_list);
2404 }
2405
2406 /**
2407  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2408  * to the buffer to finish, and then resets the fence register.
2409  * @obj: tiled object holding a fence register.
2410  * @bool: whether the wait upon the fence is interruptible
2411  *
2412  * Zeroes out the fence register itself and clears out the associated
2413  * data structures in dev_priv and obj_priv.
2414  */
2415 int
2416 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2417                               bool interruptible)
2418 {
2419         struct drm_device *dev = obj->dev;
2420         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2421
2422         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2423                 return 0;
2424
2425         /* If we've changed tiling, GTT-mappings of the object
2426          * need to re-fault to ensure that the correct fence register
2427          * setup is in place.
2428          */
2429         i915_gem_release_mmap(obj);
2430
2431         /* On the i915, GPU access to tiled buffers is via a fence,
2432          * therefore we must wait for any outstanding access to complete
2433          * before clearing the fence.
2434          */
2435         if (!IS_I965G(dev)) {
2436                 int ret;
2437
2438                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2439                 if (ret)
2440                         return ret;
2441
2442                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2443                 if (ret)
2444                         return ret;
2445         }
2446
2447         i915_gem_object_flush_gtt_write_domain(obj);
2448         i915_gem_clear_fence_reg(obj);
2449
2450         return 0;
2451 }
2452
2453 /**
2454  * Finds free space in the GTT aperture and binds the object there.
2455  */
2456 static int
2457 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2458 {
2459         struct drm_device *dev = obj->dev;
2460         drm_i915_private_t *dev_priv = dev->dev_private;
2461         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2462         struct drm_mm_node *free_space;
2463         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2464         int ret;
2465
2466         if (obj_priv->madv != I915_MADV_WILLNEED) {
2467                 DRM_ERROR("Attempting to bind a purgeable object\n");
2468                 return -EINVAL;
2469         }
2470
2471         if (alignment == 0)
2472                 alignment = i915_gem_get_gtt_alignment(obj);
2473         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2474                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2475                 return -EINVAL;
2476         }
2477
2478         /* If the object is bigger than the entire aperture, reject it early
2479          * before evicting everything in a vain attempt to find space.
2480          */
2481         if (obj->size > dev->gtt_total) {
2482                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2483                 return -E2BIG;
2484         }
2485
2486  search_free:
2487         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2488                                         obj->size, alignment, 0);
2489         if (free_space != NULL) {
2490                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2491                                                        alignment);
2492                 if (obj_priv->gtt_space != NULL)
2493                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2494         }
2495         if (obj_priv->gtt_space == NULL) {
2496                 /* If the gtt is empty and we're still having trouble
2497                  * fitting our object in, we're out of memory.
2498                  */
2499 #if WATCH_LRU
2500                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2501 #endif
2502                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2503                 if (ret)
2504                         return ret;
2505
2506                 goto search_free;
2507         }
2508
2509 #if WATCH_BUF
2510         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2511                  obj->size, obj_priv->gtt_offset);
2512 #endif
2513         ret = i915_gem_object_get_pages(obj, gfpmask);
2514         if (ret) {
2515                 drm_mm_put_block(obj_priv->gtt_space);
2516                 obj_priv->gtt_space = NULL;
2517
2518                 if (ret == -ENOMEM) {
2519                         /* first try to clear up some space from the GTT */
2520                         ret = i915_gem_evict_something(dev, obj->size,
2521                                                        alignment);
2522                         if (ret) {
2523                                 /* now try to shrink everyone else */
2524                                 if (gfpmask) {
2525                                         gfpmask = 0;
2526                                         goto search_free;
2527                                 }
2528
2529                                 return ret;
2530                         }
2531
2532                         goto search_free;
2533                 }
2534
2535                 return ret;
2536         }
2537
2538         /* Create an AGP memory structure pointing at our pages, and bind it
2539          * into the GTT.
2540          */
2541         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2542                                                obj_priv->pages,
2543                                                obj->size >> PAGE_SHIFT,
2544                                                obj_priv->gtt_offset,
2545                                                obj_priv->agp_type);
2546         if (obj_priv->agp_mem == NULL) {
2547                 i915_gem_object_put_pages(obj);
2548                 drm_mm_put_block(obj_priv->gtt_space);
2549                 obj_priv->gtt_space = NULL;
2550
2551                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2552                 if (ret)
2553                         return ret;
2554
2555                 goto search_free;
2556         }
2557         atomic_inc(&dev->gtt_count);
2558         atomic_add(obj->size, &dev->gtt_memory);
2559
2560         /* keep track of bounds object by adding it to the inactive list */
2561         list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2562
2563         /* Assert that the object is not currently in any GPU domain. As it
2564          * wasn't in the GTT, there shouldn't be any way it could have been in
2565          * a GPU cache
2566          */
2567         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2568         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2569
2570         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2571
2572         return 0;
2573 }
2574
2575 void
2576 i915_gem_clflush_object(struct drm_gem_object *obj)
2577 {
2578         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2579
2580         /* If we don't have a page list set up, then we're not pinned
2581          * to GPU, and we can ignore the cache flush because it'll happen
2582          * again at bind time.
2583          */
2584         if (obj_priv->pages == NULL)
2585                 return;
2586
2587         trace_i915_gem_object_clflush(obj);
2588
2589         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2590 }
2591
2592 /** Flushes any GPU write domain for the object if it's dirty. */
2593 static int
2594 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2595                                        bool pipelined)
2596 {
2597         struct drm_device *dev = obj->dev;
2598         uint32_t old_write_domain;
2599
2600         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2601                 return 0;
2602
2603         /* Queue the GPU write cache flushing we need. */
2604         old_write_domain = obj->write_domain;
2605         i915_gem_flush(dev, 0, obj->write_domain);
2606         BUG_ON(obj->write_domain);
2607
2608         trace_i915_gem_object_change_domain(obj,
2609                                             obj->read_domains,
2610                                             old_write_domain);
2611
2612         if (pipelined)
2613                 return 0;
2614
2615         return i915_gem_object_wait_rendering(obj, true);
2616 }
2617
2618 /** Flushes the GTT write domain for the object if it's dirty. */
2619 static void
2620 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2621 {
2622         uint32_t old_write_domain;
2623
2624         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2625                 return;
2626
2627         /* No actual flushing is required for the GTT write domain.   Writes
2628          * to it immediately go to main memory as far as we know, so there's
2629          * no chipset flush.  It also doesn't land in render cache.
2630          */
2631         old_write_domain = obj->write_domain;
2632         obj->write_domain = 0;
2633
2634         trace_i915_gem_object_change_domain(obj,
2635                                             obj->read_domains,
2636                                             old_write_domain);
2637 }
2638
2639 /** Flushes the CPU write domain for the object if it's dirty. */
2640 static void
2641 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2642 {
2643         struct drm_device *dev = obj->dev;
2644         uint32_t old_write_domain;
2645
2646         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2647                 return;
2648
2649         i915_gem_clflush_object(obj);
2650         drm_agp_chipset_flush(dev);
2651         old_write_domain = obj->write_domain;
2652         obj->write_domain = 0;
2653
2654         trace_i915_gem_object_change_domain(obj,
2655                                             obj->read_domains,
2656                                             old_write_domain);
2657 }
2658
2659 /**
2660  * Moves a single object to the GTT read, and possibly write domain.
2661  *
2662  * This function returns when the move is complete, including waiting on
2663  * flushes to occur.
2664  */
2665 int
2666 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2667 {
2668         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2669         uint32_t old_write_domain, old_read_domains;
2670         int ret;
2671
2672         /* Not valid to be called on unbound objects. */
2673         if (obj_priv->gtt_space == NULL)
2674                 return -EINVAL;
2675
2676         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2677         if (ret != 0)
2678                 return ret;
2679
2680         i915_gem_object_flush_cpu_write_domain(obj);
2681
2682         if (write) {
2683                 ret = i915_gem_object_wait_rendering(obj, true);
2684                 if (ret)
2685                         return ret;
2686         }
2687
2688         old_write_domain = obj->write_domain;
2689         old_read_domains = obj->read_domains;
2690
2691         /* It should now be out of any other write domains, and we can update
2692          * the domain values for our changes.
2693          */
2694         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2695         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2696         if (write) {
2697                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2698                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2699                 obj_priv->dirty = 1;
2700         }
2701
2702         trace_i915_gem_object_change_domain(obj,
2703                                             old_read_domains,
2704                                             old_write_domain);
2705
2706         return 0;
2707 }
2708
2709 /*
2710  * Prepare buffer for display plane. Use uninterruptible for possible flush
2711  * wait, as in modesetting process we're not supposed to be interrupted.
2712  */
2713 int
2714 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2715                                      bool pipelined)
2716 {
2717         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2718         uint32_t old_read_domains;
2719         int ret;
2720
2721         /* Not valid to be called on unbound objects. */
2722         if (obj_priv->gtt_space == NULL)
2723                 return -EINVAL;
2724
2725         ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
2726         if (ret)
2727                 return ret;
2728
2729         i915_gem_object_flush_cpu_write_domain(obj);
2730
2731         old_read_domains = obj->read_domains;
2732         obj->read_domains = I915_GEM_DOMAIN_GTT;
2733
2734         trace_i915_gem_object_change_domain(obj,
2735                                             old_read_domains,
2736                                             obj->write_domain);
2737
2738         return 0;
2739 }
2740
2741 /**
2742  * Moves a single object to the CPU read, and possibly write domain.
2743  *
2744  * This function returns when the move is complete, including waiting on
2745  * flushes to occur.
2746  */
2747 static int
2748 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2749 {
2750         uint32_t old_write_domain, old_read_domains;
2751         int ret;
2752
2753         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2754         if (ret != 0)
2755                 return ret;
2756
2757         i915_gem_object_flush_gtt_write_domain(obj);
2758
2759         /* If we have a partially-valid cache of the object in the CPU,
2760          * finish invalidating it and free the per-page flags.
2761          */
2762         i915_gem_object_set_to_full_cpu_read_domain(obj);
2763
2764         if (write) {
2765                 ret = i915_gem_object_wait_rendering(obj, true);
2766                 if (ret)
2767                         return ret;
2768         }
2769
2770         old_write_domain = obj->write_domain;
2771         old_read_domains = obj->read_domains;
2772
2773         /* Flush the CPU cache if it's still invalid. */
2774         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2775                 i915_gem_clflush_object(obj);
2776
2777                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2778         }
2779
2780         /* It should now be out of any other write domains, and we can update
2781          * the domain values for our changes.
2782          */
2783         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2784
2785         /* If we're writing through the CPU, then the GPU read domains will
2786          * need to be invalidated at next use.
2787          */
2788         if (write) {
2789                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2790                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2791         }
2792
2793         trace_i915_gem_object_change_domain(obj,
2794                                             old_read_domains,
2795                                             old_write_domain);
2796
2797         return 0;
2798 }
2799
2800 /*
2801  * Set the next domain for the specified object. This
2802  * may not actually perform the necessary flushing/invaliding though,
2803  * as that may want to be batched with other set_domain operations
2804  *
2805  * This is (we hope) the only really tricky part of gem. The goal
2806  * is fairly simple -- track which caches hold bits of the object
2807  * and make sure they remain coherent. A few concrete examples may
2808  * help to explain how it works. For shorthand, we use the notation
2809  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2810  * a pair of read and write domain masks.
2811  *
2812  * Case 1: the batch buffer
2813  *
2814  *      1. Allocated
2815  *      2. Written by CPU
2816  *      3. Mapped to GTT
2817  *      4. Read by GPU
2818  *      5. Unmapped from GTT
2819  *      6. Freed
2820  *
2821  *      Let's take these a step at a time
2822  *
2823  *      1. Allocated
2824  *              Pages allocated from the kernel may still have
2825  *              cache contents, so we set them to (CPU, CPU) always.
2826  *      2. Written by CPU (using pwrite)
2827  *              The pwrite function calls set_domain (CPU, CPU) and
2828  *              this function does nothing (as nothing changes)
2829  *      3. Mapped by GTT
2830  *              This function asserts that the object is not
2831  *              currently in any GPU-based read or write domains
2832  *      4. Read by GPU
2833  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2834  *              As write_domain is zero, this function adds in the
2835  *              current read domains (CPU+COMMAND, 0).
2836  *              flush_domains is set to CPU.
2837  *              invalidate_domains is set to COMMAND
2838  *              clflush is run to get data out of the CPU caches
2839  *              then i915_dev_set_domain calls i915_gem_flush to
2840  *              emit an MI_FLUSH and drm_agp_chipset_flush
2841  *      5. Unmapped from GTT
2842  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
2843  *              flush_domains and invalidate_domains end up both zero
2844  *              so no flushing/invalidating happens
2845  *      6. Freed
2846  *              yay, done
2847  *
2848  * Case 2: The shared render buffer
2849  *
2850  *      1. Allocated
2851  *      2. Mapped to GTT
2852  *      3. Read/written by GPU
2853  *      4. set_domain to (CPU,CPU)
2854  *      5. Read/written by CPU
2855  *      6. Read/written by GPU
2856  *
2857  *      1. Allocated
2858  *              Same as last example, (CPU, CPU)
2859  *      2. Mapped to GTT
2860  *              Nothing changes (assertions find that it is not in the GPU)
2861  *      3. Read/written by GPU
2862  *              execbuffer calls set_domain (RENDER, RENDER)
2863  *              flush_domains gets CPU
2864  *              invalidate_domains gets GPU
2865  *              clflush (obj)
2866  *              MI_FLUSH and drm_agp_chipset_flush
2867  *      4. set_domain (CPU, CPU)
2868  *              flush_domains gets GPU
2869  *              invalidate_domains gets CPU
2870  *              wait_rendering (obj) to make sure all drawing is complete.
2871  *              This will include an MI_FLUSH to get the data from GPU
2872  *              to memory
2873  *              clflush (obj) to invalidate the CPU cache
2874  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2875  *      5. Read/written by CPU
2876  *              cache lines are loaded and dirtied
2877  *      6. Read written by GPU
2878  *              Same as last GPU access
2879  *
2880  * Case 3: The constant buffer
2881  *
2882  *      1. Allocated
2883  *      2. Written by CPU
2884  *      3. Read by GPU
2885  *      4. Updated (written) by CPU again
2886  *      5. Read by GPU
2887  *
2888  *      1. Allocated
2889  *              (CPU, CPU)
2890  *      2. Written by CPU
2891  *              (CPU, CPU)
2892  *      3. Read by GPU
2893  *              (CPU+RENDER, 0)
2894  *              flush_domains = CPU
2895  *              invalidate_domains = RENDER
2896  *              clflush (obj)
2897  *              MI_FLUSH
2898  *              drm_agp_chipset_flush
2899  *      4. Updated (written) by CPU again
2900  *              (CPU, CPU)
2901  *              flush_domains = 0 (no previous write domain)
2902  *              invalidate_domains = 0 (no new read domains)
2903  *      5. Read by GPU
2904  *              (CPU+RENDER, 0)
2905  *              flush_domains = CPU
2906  *              invalidate_domains = RENDER
2907  *              clflush (obj)
2908  *              MI_FLUSH
2909  *              drm_agp_chipset_flush
2910  */
2911 static void
2912 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2913 {
2914         struct drm_device               *dev = obj->dev;
2915         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2916         uint32_t                        invalidate_domains = 0;
2917         uint32_t                        flush_domains = 0;
2918         uint32_t                        old_read_domains;
2919
2920         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2921         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2922
2923         intel_mark_busy(dev, obj);
2924
2925 #if WATCH_BUF
2926         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2927                  __func__, obj,
2928                  obj->read_domains, obj->pending_read_domains,
2929                  obj->write_domain, obj->pending_write_domain);
2930 #endif
2931         /*
2932          * If the object isn't moving to a new write domain,
2933          * let the object stay in multiple read domains
2934          */
2935         if (obj->pending_write_domain == 0)
2936                 obj->pending_read_domains |= obj->read_domains;
2937         else
2938                 obj_priv->dirty = 1;
2939
2940         /*
2941          * Flush the current write domain if
2942          * the new read domains don't match. Invalidate
2943          * any read domains which differ from the old
2944          * write domain
2945          */
2946         if (obj->write_domain &&
2947             obj->write_domain != obj->pending_read_domains) {
2948                 flush_domains |= obj->write_domain;
2949                 invalidate_domains |=
2950                         obj->pending_read_domains & ~obj->write_domain;
2951         }
2952         /*
2953          * Invalidate any read caches which may have
2954          * stale data. That is, any new read domains.
2955          */
2956         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2957         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2958 #if WATCH_BUF
2959                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2960                          __func__, flush_domains, invalidate_domains);
2961 #endif
2962                 i915_gem_clflush_object(obj);
2963         }
2964
2965         old_read_domains = obj->read_domains;
2966
2967         /* The actual obj->write_domain will be updated with
2968          * pending_write_domain after we emit the accumulated flush for all
2969          * of our domain changes in execbuffers (which clears objects'
2970          * write_domains).  So if we have a current write domain that we
2971          * aren't changing, set pending_write_domain to that.
2972          */
2973         if (flush_domains == 0 && obj->pending_write_domain == 0)
2974                 obj->pending_write_domain = obj->write_domain;
2975         obj->read_domains = obj->pending_read_domains;
2976
2977         dev->invalidate_domains |= invalidate_domains;
2978         dev->flush_domains |= flush_domains;
2979 #if WATCH_BUF
2980         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2981                  __func__,
2982                  obj->read_domains, obj->write_domain,
2983                  dev->invalidate_domains, dev->flush_domains);
2984 #endif
2985
2986         trace_i915_gem_object_change_domain(obj,
2987                                             old_read_domains,
2988                                             obj->write_domain);
2989 }
2990
2991 /**
2992  * Moves the object from a partially CPU read to a full one.
2993  *
2994  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2995  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2996  */
2997 static void
2998 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2999 {
3000         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3001
3002         if (!obj_priv->page_cpu_valid)
3003                 return;
3004
3005         /* If we're partially in the CPU read domain, finish moving it in.
3006          */
3007         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3008                 int i;
3009
3010                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3011                         if (obj_priv->page_cpu_valid[i])
3012                                 continue;
3013                         drm_clflush_pages(obj_priv->pages + i, 1);
3014                 }
3015         }
3016
3017         /* Free the page_cpu_valid mappings which are now stale, whether
3018          * or not we've got I915_GEM_DOMAIN_CPU.
3019          */
3020         kfree(obj_priv->page_cpu_valid);
3021         obj_priv->page_cpu_valid = NULL;
3022 }
3023
3024 /**
3025  * Set the CPU read domain on a range of the object.
3026  *
3027  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3028  * not entirely valid.  The page_cpu_valid member of the object flags which
3029  * pages have been flushed, and will be respected by
3030  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3031  * of the whole object.
3032  *
3033  * This function returns when the move is complete, including waiting on
3034  * flushes to occur.
3035  */
3036 static int
3037 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3038                                           uint64_t offset, uint64_t size)
3039 {
3040         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3041         uint32_t old_read_domains;
3042         int i, ret;
3043
3044         if (offset == 0 && size == obj->size)
3045                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3046
3047         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3048         if (ret != 0)
3049                 return ret;
3050         i915_gem_object_flush_gtt_write_domain(obj);
3051
3052         /* If we're already fully in the CPU read domain, we're done. */
3053         if (obj_priv->page_cpu_valid == NULL &&
3054             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3055                 return 0;
3056
3057         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3058          * newly adding I915_GEM_DOMAIN_CPU
3059          */
3060         if (obj_priv->page_cpu_valid == NULL) {
3061                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3062                                                    GFP_KERNEL);
3063                 if (obj_priv->page_cpu_valid == NULL)
3064                         return -ENOMEM;
3065         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3066                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3067
3068         /* Flush the cache on any pages that are still invalid from the CPU's
3069          * perspective.
3070          */
3071         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3072              i++) {
3073                 if (obj_priv->page_cpu_valid[i])
3074                         continue;
3075
3076                 drm_clflush_pages(obj_priv->pages + i, 1);
3077
3078                 obj_priv->page_cpu_valid[i] = 1;
3079         }
3080
3081         /* It should now be out of any other write domains, and we can update
3082          * the domain values for our changes.
3083          */
3084         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3085
3086         old_read_domains = obj->read_domains;
3087         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3088
3089         trace_i915_gem_object_change_domain(obj,
3090                                             old_read_domains,
3091                                             obj->write_domain);
3092
3093         return 0;
3094 }
3095
3096 /**
3097  * Pin an object to the GTT and evaluate the relocations landing in it.
3098  */
3099 static int
3100 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3101                                  struct drm_file *file_priv,
3102                                  struct drm_i915_gem_exec_object2 *entry,
3103                                  struct drm_i915_gem_relocation_entry *relocs)
3104 {
3105         struct drm_device *dev = obj->dev;
3106         drm_i915_private_t *dev_priv = dev->dev_private;
3107         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3108         int i, ret;
3109         void __iomem *reloc_page;
3110         bool need_fence;
3111
3112         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3113                      obj_priv->tiling_mode != I915_TILING_NONE;
3114
3115         /* Check fence reg constraints and rebind if necessary */
3116         if (need_fence &&
3117             !i915_gem_object_fence_offset_ok(obj,
3118                                              obj_priv->tiling_mode)) {
3119                 ret = i915_gem_object_unbind(obj);
3120                 if (ret)
3121                         return ret;
3122         }
3123
3124         /* Choose the GTT offset for our buffer and put it there. */
3125         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3126         if (ret)
3127                 return ret;
3128
3129         /*
3130          * Pre-965 chips need a fence register set up in order to
3131          * properly handle blits to/from tiled surfaces.
3132          */
3133         if (need_fence) {
3134                 ret = i915_gem_object_get_fence_reg(obj, false);
3135                 if (ret != 0) {
3136                         i915_gem_object_unpin(obj);
3137                         return ret;
3138                 }
3139         }
3140
3141         entry->offset = obj_priv->gtt_offset;
3142
3143         /* Apply the relocations, using the GTT aperture to avoid cache
3144          * flushing requirements.
3145          */
3146         for (i = 0; i < entry->relocation_count; i++) {
3147                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3148                 struct drm_gem_object *target_obj;
3149                 struct drm_i915_gem_object *target_obj_priv;
3150                 uint32_t reloc_val, reloc_offset;
3151                 uint32_t __iomem *reloc_entry;
3152
3153                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3154                                                    reloc->target_handle);
3155                 if (target_obj == NULL) {
3156                         i915_gem_object_unpin(obj);
3157                         return -ENOENT;
3158                 }
3159                 target_obj_priv = to_intel_bo(target_obj);
3160
3161 #if WATCH_RELOC
3162                 DRM_INFO("%s: obj %p offset %08x target %d "
3163                          "read %08x write %08x gtt %08x "
3164                          "presumed %08x delta %08x\n",
3165                          __func__,
3166                          obj,
3167                          (int) reloc->offset,
3168                          (int) reloc->target_handle,
3169                          (int) reloc->read_domains,
3170                          (int) reloc->write_domain,
3171                          (int) target_obj_priv->gtt_offset,
3172                          (int) reloc->presumed_offset,
3173                          reloc->delta);
3174 #endif
3175
3176                 /* The target buffer should have appeared before us in the
3177                  * exec_object list, so it should have a GTT space bound by now.
3178                  */
3179                 if (target_obj_priv->gtt_space == NULL) {
3180                         DRM_ERROR("No GTT space found for object %d\n",
3181                                   reloc->target_handle);
3182                         drm_gem_object_unreference(target_obj);
3183                         i915_gem_object_unpin(obj);
3184                         return -EINVAL;
3185                 }
3186
3187                 /* Validate that the target is in a valid r/w GPU domain */
3188                 if (reloc->write_domain & (reloc->write_domain - 1)) {
3189                         DRM_ERROR("reloc with multiple write domains: "
3190                                   "obj %p target %d offset %d "
3191                                   "read %08x write %08x",
3192                                   obj, reloc->target_handle,
3193                                   (int) reloc->offset,
3194                                   reloc->read_domains,
3195                                   reloc->write_domain);
3196                         return -EINVAL;
3197                 }
3198                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3199                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3200                         DRM_ERROR("reloc with read/write CPU domains: "
3201                                   "obj %p target %d offset %d "
3202                                   "read %08x write %08x",
3203                                   obj, reloc->target_handle,
3204                                   (int) reloc->offset,
3205                                   reloc->read_domains,
3206                                   reloc->write_domain);
3207                         drm_gem_object_unreference(target_obj);
3208                         i915_gem_object_unpin(obj);
3209                         return -EINVAL;
3210                 }
3211                 if (reloc->write_domain && target_obj->pending_write_domain &&
3212                     reloc->write_domain != target_obj->pending_write_domain) {
3213                         DRM_ERROR("Write domain conflict: "
3214                                   "obj %p target %d offset %d "
3215                                   "new %08x old %08x\n",
3216                                   obj, reloc->target_handle,
3217                                   (int) reloc->offset,
3218                                   reloc->write_domain,
3219                                   target_obj->pending_write_domain);
3220                         drm_gem_object_unreference(target_obj);
3221                         i915_gem_object_unpin(obj);
3222                         return -EINVAL;
3223                 }
3224
3225                 target_obj->pending_read_domains |= reloc->read_domains;
3226                 target_obj->pending_write_domain |= reloc->write_domain;
3227
3228                 /* If the relocation already has the right value in it, no
3229                  * more work needs to be done.
3230                  */
3231                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3232                         drm_gem_object_unreference(target_obj);
3233                         continue;
3234                 }
3235
3236                 /* Check that the relocation address is valid... */
3237                 if (reloc->offset > obj->size - 4) {
3238                         DRM_ERROR("Relocation beyond object bounds: "
3239                                   "obj %p target %d offset %d size %d.\n",
3240                                   obj, reloc->target_handle,
3241                                   (int) reloc->offset, (int) obj->size);
3242                         drm_gem_object_unreference(target_obj);
3243                         i915_gem_object_unpin(obj);
3244                         return -EINVAL;
3245                 }
3246                 if (reloc->offset & 3) {
3247                         DRM_ERROR("Relocation not 4-byte aligned: "
3248                                   "obj %p target %d offset %d.\n",
3249                                   obj, reloc->target_handle,
3250                                   (int) reloc->offset);
3251                         drm_gem_object_unreference(target_obj);
3252                         i915_gem_object_unpin(obj);
3253                         return -EINVAL;
3254                 }
3255
3256                 /* and points to somewhere within the target object. */
3257                 if (reloc->delta >= target_obj->size) {
3258                         DRM_ERROR("Relocation beyond target object bounds: "
3259                                   "obj %p target %d delta %d size %d.\n",
3260                                   obj, reloc->target_handle,
3261                                   (int) reloc->delta, (int) target_obj->size);
3262                         drm_gem_object_unreference(target_obj);
3263                         i915_gem_object_unpin(obj);
3264                         return -EINVAL;
3265                 }
3266
3267                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3268                 if (ret != 0) {
3269                         drm_gem_object_unreference(target_obj);
3270                         i915_gem_object_unpin(obj);
3271                         return -EINVAL;
3272                 }
3273
3274                 /* Map the page containing the relocation we're going to
3275                  * perform.
3276                  */
3277                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3278                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3279                                                       (reloc_offset &
3280                                                        ~(PAGE_SIZE - 1)),
3281                                                       KM_USER0);
3282                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3283                                                    (reloc_offset & (PAGE_SIZE - 1)));
3284                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3285
3286 #if WATCH_BUF
3287                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3288                           obj, (unsigned int) reloc->offset,
3289                           readl(reloc_entry), reloc_val);
3290 #endif
3291                 writel(reloc_val, reloc_entry);
3292                 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3293
3294                 /* The updated presumed offset for this entry will be
3295                  * copied back out to the user.
3296                  */
3297                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3298
3299                 drm_gem_object_unreference(target_obj);
3300         }
3301
3302 #if WATCH_BUF
3303         if (0)
3304                 i915_gem_dump_object(obj, 128, __func__, ~0);
3305 #endif
3306         return 0;
3307 }
3308
3309 /* Throttle our rendering by waiting until the ring has completed our requests
3310  * emitted over 20 msec ago.
3311  *
3312  * Note that if we were to use the current jiffies each time around the loop,
3313  * we wouldn't escape the function with any frames outstanding if the time to
3314  * render a frame was over 20ms.
3315  *
3316  * This should get us reasonable parallelism between CPU and GPU but also
3317  * relatively low latency when blocking on a particular request to finish.
3318  */
3319 static int
3320 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3321 {
3322         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3323         int ret = 0;
3324         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3325
3326         mutex_lock(&dev->struct_mutex);
3327         while (!list_empty(&i915_file_priv->mm.request_list)) {
3328                 struct drm_i915_gem_request *request;
3329
3330                 request = list_first_entry(&i915_file_priv->mm.request_list,
3331                                            struct drm_i915_gem_request,
3332                                            client_list);
3333
3334                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3335                         break;
3336
3337                 ret = i915_wait_request(dev, request->seqno, request->ring);
3338                 if (ret != 0)
3339                         break;
3340         }
3341         mutex_unlock(&dev->struct_mutex);
3342
3343         return ret;
3344 }
3345
3346 static int
3347 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3348                               uint32_t buffer_count,
3349                               struct drm_i915_gem_relocation_entry **relocs)
3350 {
3351         uint32_t reloc_count = 0, reloc_index = 0, i;
3352         int ret;
3353
3354         *relocs = NULL;
3355         for (i = 0; i < buffer_count; i++) {
3356                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3357                         return -EINVAL;
3358                 reloc_count += exec_list[i].relocation_count;
3359         }
3360
3361         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3362         if (*relocs == NULL) {
3363                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3364                 return -ENOMEM;
3365         }
3366
3367         for (i = 0; i < buffer_count; i++) {
3368                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3369
3370                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3371
3372                 ret = copy_from_user(&(*relocs)[reloc_index],
3373                                      user_relocs,
3374                                      exec_list[i].relocation_count *
3375                                      sizeof(**relocs));
3376                 if (ret != 0) {
3377                         drm_free_large(*relocs);
3378                         *relocs = NULL;
3379                         return -EFAULT;
3380                 }
3381
3382                 reloc_index += exec_list[i].relocation_count;
3383         }
3384
3385         return 0;
3386 }
3387
3388 static int
3389 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3390                             uint32_t buffer_count,
3391                             struct drm_i915_gem_relocation_entry *relocs)
3392 {
3393         uint32_t reloc_count = 0, i;
3394         int ret = 0;
3395
3396         if (relocs == NULL)
3397             return 0;
3398
3399         for (i = 0; i < buffer_count; i++) {
3400                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3401                 int unwritten;
3402
3403                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3404
3405                 unwritten = copy_to_user(user_relocs,
3406                                          &relocs[reloc_count],
3407                                          exec_list[i].relocation_count *
3408                                          sizeof(*relocs));
3409
3410                 if (unwritten) {
3411                         ret = -EFAULT;
3412                         goto err;
3413                 }
3414
3415                 reloc_count += exec_list[i].relocation_count;
3416         }
3417
3418 err:
3419         drm_free_large(relocs);
3420
3421         return ret;
3422 }
3423
3424 static int
3425 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3426                            uint64_t exec_offset)
3427 {
3428         uint32_t exec_start, exec_len;
3429
3430         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3431         exec_len = (uint32_t) exec->batch_len;
3432
3433         if ((exec_start | exec_len) & 0x7)
3434                 return -EINVAL;
3435
3436         if (!exec_start)
3437                 return -EINVAL;
3438
3439         return 0;
3440 }
3441
3442 static int
3443 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3444                                struct drm_gem_object **object_list,
3445                                int count)
3446 {
3447         drm_i915_private_t *dev_priv = dev->dev_private;
3448         struct drm_i915_gem_object *obj_priv;
3449         DEFINE_WAIT(wait);
3450         int i, ret = 0;
3451
3452         for (;;) {
3453                 prepare_to_wait(&dev_priv->pending_flip_queue,
3454                                 &wait, TASK_INTERRUPTIBLE);
3455                 for (i = 0; i < count; i++) {
3456                         obj_priv = to_intel_bo(object_list[i]);
3457                         if (atomic_read(&obj_priv->pending_flip) > 0)
3458                                 break;
3459                 }
3460                 if (i == count)
3461                         break;
3462
3463                 if (!signal_pending(current)) {
3464                         mutex_unlock(&dev->struct_mutex);
3465                         schedule();
3466                         mutex_lock(&dev->struct_mutex);
3467                         continue;
3468                 }
3469                 ret = -ERESTARTSYS;
3470                 break;
3471         }
3472         finish_wait(&dev_priv->pending_flip_queue, &wait);
3473
3474         return ret;
3475 }
3476
3477 static int
3478 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3479                        struct drm_file *file_priv,
3480                        struct drm_i915_gem_execbuffer2 *args,
3481                        struct drm_i915_gem_exec_object2 *exec_list)
3482 {
3483         drm_i915_private_t *dev_priv = dev->dev_private;
3484         struct drm_gem_object **object_list = NULL;
3485         struct drm_gem_object *batch_obj;
3486         struct drm_i915_gem_object *obj_priv;
3487         struct drm_clip_rect *cliprects = NULL;
3488         struct drm_i915_gem_relocation_entry *relocs = NULL;
3489         struct drm_i915_gem_request *request = NULL;
3490         int ret = 0, ret2, i, pinned = 0;
3491         uint64_t exec_offset;
3492         uint32_t seqno, reloc_index;
3493         int pin_tries, flips;
3494
3495         struct intel_ring_buffer *ring = NULL;
3496
3497 #if WATCH_EXEC
3498         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3499                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3500 #endif
3501         if (args->flags & I915_EXEC_BSD) {
3502                 if (!HAS_BSD(dev)) {
3503                         DRM_ERROR("execbuf with wrong flag\n");
3504                         return -EINVAL;
3505                 }
3506                 ring = &dev_priv->bsd_ring;
3507         } else {
3508                 ring = &dev_priv->render_ring;
3509         }
3510
3511         if (args->buffer_count < 1) {
3512                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3513                 return -EINVAL;
3514         }
3515         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3516         if (object_list == NULL) {
3517                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3518                           args->buffer_count);
3519                 ret = -ENOMEM;
3520                 goto pre_mutex_err;
3521         }
3522
3523         if (args->num_cliprects != 0) {
3524                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3525                                     GFP_KERNEL);
3526                 if (cliprects == NULL) {
3527                         ret = -ENOMEM;
3528                         goto pre_mutex_err;
3529                 }
3530
3531                 ret = copy_from_user(cliprects,
3532                                      (struct drm_clip_rect __user *)
3533                                      (uintptr_t) args->cliprects_ptr,
3534                                      sizeof(*cliprects) * args->num_cliprects);
3535                 if (ret != 0) {
3536                         DRM_ERROR("copy %d cliprects failed: %d\n",
3537                                   args->num_cliprects, ret);
3538                         ret = -EFAULT;
3539                         goto pre_mutex_err;
3540                 }
3541         }
3542
3543         request = kzalloc(sizeof(*request), GFP_KERNEL);
3544         if (request == NULL) {
3545                 ret = -ENOMEM;
3546                 goto pre_mutex_err;
3547         }
3548
3549         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3550                                             &relocs);
3551         if (ret != 0)
3552                 goto pre_mutex_err;
3553
3554         mutex_lock(&dev->struct_mutex);
3555
3556         i915_verify_inactive(dev, __FILE__, __LINE__);
3557
3558         if (atomic_read(&dev_priv->mm.wedged)) {
3559                 mutex_unlock(&dev->struct_mutex);
3560                 ret = -EIO;
3561                 goto pre_mutex_err;
3562         }
3563
3564         if (dev_priv->mm.suspended) {
3565                 mutex_unlock(&dev->struct_mutex);
3566                 ret = -EBUSY;
3567                 goto pre_mutex_err;
3568         }
3569
3570         /* Look up object handles */
3571         flips = 0;
3572         for (i = 0; i < args->buffer_count; i++) {
3573                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3574                                                        exec_list[i].handle);
3575                 if (object_list[i] == NULL) {
3576                         DRM_ERROR("Invalid object handle %d at index %d\n",
3577                                    exec_list[i].handle, i);
3578                         /* prevent error path from reading uninitialized data */
3579                         args->buffer_count = i + 1;
3580                         ret = -ENOENT;
3581                         goto err;
3582                 }
3583
3584                 obj_priv = to_intel_bo(object_list[i]);
3585                 if (obj_priv->in_execbuffer) {
3586                         DRM_ERROR("Object %p appears more than once in object list\n",
3587                                    object_list[i]);
3588                         /* prevent error path from reading uninitialized data */
3589                         args->buffer_count = i + 1;
3590                         ret = -EINVAL;
3591                         goto err;
3592                 }
3593                 obj_priv->in_execbuffer = true;
3594                 flips += atomic_read(&obj_priv->pending_flip);
3595         }
3596
3597         if (flips > 0) {
3598                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3599                                                      args->buffer_count);
3600                 if (ret)
3601                         goto err;
3602         }
3603
3604         /* Pin and relocate */
3605         for (pin_tries = 0; ; pin_tries++) {
3606                 ret = 0;
3607                 reloc_index = 0;
3608
3609                 for (i = 0; i < args->buffer_count; i++) {
3610                         object_list[i]->pending_read_domains = 0;
3611                         object_list[i]->pending_write_domain = 0;
3612                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3613                                                                file_priv,
3614                                                                &exec_list[i],
3615                                                                &relocs[reloc_index]);
3616                         if (ret)
3617                                 break;
3618                         pinned = i + 1;
3619                         reloc_index += exec_list[i].relocation_count;
3620                 }
3621                 /* success */
3622                 if (ret == 0)
3623                         break;
3624
3625                 /* error other than GTT full, or we've already tried again */
3626                 if (ret != -ENOSPC || pin_tries >= 1) {
3627                         if (ret != -ERESTARTSYS) {
3628                                 unsigned long long total_size = 0;
3629                                 int num_fences = 0;
3630                                 for (i = 0; i < args->buffer_count; i++) {
3631                                         obj_priv = to_intel_bo(object_list[i]);
3632
3633                                         total_size += object_list[i]->size;
3634                                         num_fences +=
3635                                                 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3636                                                 obj_priv->tiling_mode != I915_TILING_NONE;
3637                                 }
3638                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3639                                           pinned+1, args->buffer_count,
3640                                           total_size, num_fences,
3641                                           ret);
3642                                 DRM_ERROR("%d objects [%d pinned], "
3643                                           "%d object bytes [%d pinned], "
3644                                           "%d/%d gtt bytes\n",
3645                                           atomic_read(&dev->object_count),
3646                                           atomic_read(&dev->pin_count),
3647                                           atomic_read(&dev->object_memory),
3648                                           atomic_read(&dev->pin_memory),
3649                                           atomic_read(&dev->gtt_memory),
3650                                           dev->gtt_total);
3651                         }
3652                         goto err;
3653                 }
3654
3655                 /* unpin all of our buffers */
3656                 for (i = 0; i < pinned; i++)
3657                         i915_gem_object_unpin(object_list[i]);
3658                 pinned = 0;
3659
3660                 /* evict everyone we can from the aperture */
3661                 ret = i915_gem_evict_everything(dev);
3662                 if (ret && ret != -ENOSPC)
3663                         goto err;
3664         }
3665
3666         /* Set the pending read domains for the batch buffer to COMMAND */
3667         batch_obj = object_list[args->buffer_count-1];
3668         if (batch_obj->pending_write_domain) {
3669                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3670                 ret = -EINVAL;
3671                 goto err;
3672         }
3673         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3674
3675         /* Sanity check the batch buffer, prior to moving objects */
3676         exec_offset = exec_list[args->buffer_count - 1].offset;
3677         ret = i915_gem_check_execbuffer (args, exec_offset);
3678         if (ret != 0) {
3679                 DRM_ERROR("execbuf with invalid offset/length\n");
3680                 goto err;
3681         }
3682
3683         i915_verify_inactive(dev, __FILE__, __LINE__);
3684
3685         /* Zero the global flush/invalidate flags. These
3686          * will be modified as new domains are computed
3687          * for each object
3688          */
3689         dev->invalidate_domains = 0;
3690         dev->flush_domains = 0;
3691
3692         for (i = 0; i < args->buffer_count; i++) {
3693                 struct drm_gem_object *obj = object_list[i];
3694
3695                 /* Compute new gpu domains and update invalidate/flush */
3696                 i915_gem_object_set_to_gpu_domain(obj);
3697         }
3698
3699         i915_verify_inactive(dev, __FILE__, __LINE__);
3700
3701         if (dev->invalidate_domains | dev->flush_domains) {
3702 #if WATCH_EXEC
3703                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3704                           __func__,
3705                          dev->invalidate_domains,
3706                          dev->flush_domains);
3707 #endif
3708                 i915_gem_flush(dev,
3709                                dev->invalidate_domains,
3710                                dev->flush_domains);
3711         }
3712
3713         if (dev_priv->render_ring.outstanding_lazy_request) {
3714                 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring);
3715                 dev_priv->render_ring.outstanding_lazy_request = false;
3716         }
3717         if (dev_priv->bsd_ring.outstanding_lazy_request) {
3718                 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring);
3719                 dev_priv->bsd_ring.outstanding_lazy_request = false;
3720         }
3721
3722         for (i = 0; i < args->buffer_count; i++) {
3723                 struct drm_gem_object *obj = object_list[i];
3724                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3725                 uint32_t old_write_domain = obj->write_domain;
3726
3727                 obj->write_domain = obj->pending_write_domain;
3728                 if (obj->write_domain)
3729                         list_move_tail(&obj_priv->gpu_write_list,
3730                                        &dev_priv->mm.gpu_write_list);
3731                 else
3732                         list_del_init(&obj_priv->gpu_write_list);
3733
3734                 trace_i915_gem_object_change_domain(obj,
3735                                                     obj->read_domains,
3736                                                     old_write_domain);
3737         }
3738
3739         i915_verify_inactive(dev, __FILE__, __LINE__);
3740
3741 #if WATCH_COHERENCY
3742         for (i = 0; i < args->buffer_count; i++) {
3743                 i915_gem_object_check_coherency(object_list[i],
3744                                                 exec_list[i].handle);
3745         }
3746 #endif
3747
3748 #if WATCH_EXEC
3749         i915_gem_dump_object(batch_obj,
3750                               args->batch_len,
3751                               __func__,
3752                               ~0);
3753 #endif
3754
3755         /* Exec the batchbuffer */
3756         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3757                         cliprects, exec_offset);
3758         if (ret) {
3759                 DRM_ERROR("dispatch failed %d\n", ret);
3760                 goto err;
3761         }
3762
3763         /*
3764          * Ensure that the commands in the batch buffer are
3765          * finished before the interrupt fires
3766          */
3767         i915_retire_commands(dev, ring);
3768
3769         i915_verify_inactive(dev, __FILE__, __LINE__);
3770
3771         for (i = 0; i < args->buffer_count; i++) {
3772                 struct drm_gem_object *obj = object_list[i];
3773                 obj_priv = to_intel_bo(obj);
3774
3775                 i915_gem_object_move_to_active(obj, ring);
3776 #if WATCH_LRU
3777                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3778 #endif
3779         }
3780
3781         /*
3782          * Get a seqno representing the execution of the current buffer,
3783          * which we can wait on.  We would like to mitigate these interrupts,
3784          * likely by only creating seqnos occasionally (so that we have
3785          * *some* interrupts representing completion of buffers that we can
3786          * wait on when trying to clear up gtt space).
3787          */
3788         seqno = i915_add_request(dev, file_priv, request, ring);
3789         request = NULL;
3790
3791 #if WATCH_LRU
3792         i915_dump_lru(dev, __func__);
3793 #endif
3794
3795         i915_verify_inactive(dev, __FILE__, __LINE__);
3796
3797 err:
3798         for (i = 0; i < pinned; i++)
3799                 i915_gem_object_unpin(object_list[i]);
3800
3801         for (i = 0; i < args->buffer_count; i++) {
3802                 if (object_list[i]) {
3803                         obj_priv = to_intel_bo(object_list[i]);
3804                         obj_priv->in_execbuffer = false;
3805                 }
3806                 drm_gem_object_unreference(object_list[i]);
3807         }
3808
3809         mutex_unlock(&dev->struct_mutex);
3810
3811 pre_mutex_err:
3812         /* Copy the updated relocations out regardless of current error
3813          * state.  Failure to update the relocs would mean that the next
3814          * time userland calls execbuf, it would do so with presumed offset
3815          * state that didn't match the actual object state.
3816          */
3817         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3818                                            relocs);
3819         if (ret2 != 0) {
3820                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3821
3822                 if (ret == 0)
3823                         ret = ret2;
3824         }
3825
3826         drm_free_large(object_list);
3827         kfree(cliprects);
3828         kfree(request);
3829
3830         return ret;
3831 }
3832
3833 /*
3834  * Legacy execbuffer just creates an exec2 list from the original exec object
3835  * list array and passes it to the real function.
3836  */
3837 int
3838 i915_gem_execbuffer(struct drm_device *dev, void *data,
3839                     struct drm_file *file_priv)
3840 {
3841         struct drm_i915_gem_execbuffer *args = data;
3842         struct drm_i915_gem_execbuffer2 exec2;
3843         struct drm_i915_gem_exec_object *exec_list = NULL;
3844         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3845         int ret, i;
3846
3847 #if WATCH_EXEC
3848         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3849                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3850 #endif
3851
3852         if (args->buffer_count < 1) {
3853                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3854                 return -EINVAL;
3855         }
3856
3857         /* Copy in the exec list from userland */
3858         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3859         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3860         if (exec_list == NULL || exec2_list == NULL) {
3861                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3862                           args->buffer_count);
3863                 drm_free_large(exec_list);
3864                 drm_free_large(exec2_list);
3865                 return -ENOMEM;
3866         }
3867         ret = copy_from_user(exec_list,
3868                              (struct drm_i915_relocation_entry __user *)
3869                              (uintptr_t) args->buffers_ptr,
3870                              sizeof(*exec_list) * args->buffer_count);
3871         if (ret != 0) {
3872                 DRM_ERROR("copy %d exec entries failed %d\n",
3873                           args->buffer_count, ret);
3874                 drm_free_large(exec_list);
3875                 drm_free_large(exec2_list);
3876                 return -EFAULT;
3877         }
3878
3879         for (i = 0; i < args->buffer_count; i++) {
3880                 exec2_list[i].handle = exec_list[i].handle;
3881                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3882                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3883                 exec2_list[i].alignment = exec_list[i].alignment;
3884                 exec2_list[i].offset = exec_list[i].offset;
3885                 if (!IS_I965G(dev))
3886                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3887                 else
3888                         exec2_list[i].flags = 0;
3889         }
3890
3891         exec2.buffers_ptr = args->buffers_ptr;
3892         exec2.buffer_count = args->buffer_count;
3893         exec2.batch_start_offset = args->batch_start_offset;
3894         exec2.batch_len = args->batch_len;
3895         exec2.DR1 = args->DR1;
3896         exec2.DR4 = args->DR4;
3897         exec2.num_cliprects = args->num_cliprects;
3898         exec2.cliprects_ptr = args->cliprects_ptr;
3899         exec2.flags = I915_EXEC_RENDER;
3900
3901         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3902         if (!ret) {
3903                 /* Copy the new buffer offsets back to the user's exec list. */
3904                 for (i = 0; i < args->buffer_count; i++)
3905                         exec_list[i].offset = exec2_list[i].offset;
3906                 /* ... and back out to userspace */
3907                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3908                                    (uintptr_t) args->buffers_ptr,
3909                                    exec_list,
3910                                    sizeof(*exec_list) * args->buffer_count);
3911                 if (ret) {
3912                         ret = -EFAULT;
3913                         DRM_ERROR("failed to copy %d exec entries "
3914                                   "back to user (%d)\n",
3915                                   args->buffer_count, ret);
3916                 }
3917         }
3918
3919         drm_free_large(exec_list);
3920         drm_free_large(exec2_list);
3921         return ret;
3922 }
3923
3924 int
3925 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3926                      struct drm_file *file_priv)
3927 {
3928         struct drm_i915_gem_execbuffer2 *args = data;
3929         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3930         int ret;
3931
3932 #if WATCH_EXEC
3933         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3934                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3935 #endif
3936
3937         if (args->buffer_count < 1) {
3938                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3939                 return -EINVAL;
3940         }
3941
3942         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3943         if (exec2_list == NULL) {
3944                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3945                           args->buffer_count);
3946                 return -ENOMEM;
3947         }
3948         ret = copy_from_user(exec2_list,
3949                              (struct drm_i915_relocation_entry __user *)
3950                              (uintptr_t) args->buffers_ptr,
3951                              sizeof(*exec2_list) * args->buffer_count);
3952         if (ret != 0) {
3953                 DRM_ERROR("copy %d exec entries failed %d\n",
3954                           args->buffer_count, ret);
3955                 drm_free_large(exec2_list);
3956                 return -EFAULT;
3957         }
3958
3959         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
3960         if (!ret) {
3961                 /* Copy the new buffer offsets back to the user's exec list. */
3962                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3963                                    (uintptr_t) args->buffers_ptr,
3964                                    exec2_list,
3965                                    sizeof(*exec2_list) * args->buffer_count);
3966                 if (ret) {
3967                         ret = -EFAULT;
3968                         DRM_ERROR("failed to copy %d exec entries "
3969                                   "back to user (%d)\n",
3970                                   args->buffer_count, ret);
3971                 }
3972         }
3973
3974         drm_free_large(exec2_list);
3975         return ret;
3976 }
3977
3978 int
3979 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3980 {
3981         struct drm_device *dev = obj->dev;
3982         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3983         int ret;
3984
3985         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3986
3987         i915_verify_inactive(dev, __FILE__, __LINE__);
3988
3989         if (obj_priv->gtt_space != NULL) {
3990                 if (alignment == 0)
3991                         alignment = i915_gem_get_gtt_alignment(obj);
3992                 if (obj_priv->gtt_offset & (alignment - 1)) {
3993                         WARN(obj_priv->pin_count,
3994                              "bo is already pinned with incorrect alignment:"
3995                              " offset=%x, req.alignment=%x\n",
3996                              obj_priv->gtt_offset, alignment);
3997                         ret = i915_gem_object_unbind(obj);
3998                         if (ret)
3999                                 return ret;
4000                 }
4001         }
4002
4003         if (obj_priv->gtt_space == NULL) {
4004                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4005                 if (ret)
4006                         return ret;
4007         }
4008
4009         obj_priv->pin_count++;
4010
4011         /* If the object is not active and not pending a flush,
4012          * remove it from the inactive list
4013          */
4014         if (obj_priv->pin_count == 1) {
4015                 atomic_inc(&dev->pin_count);
4016                 atomic_add(obj->size, &dev->pin_memory);
4017                 if (!obj_priv->active &&
4018                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4019                         list_del_init(&obj_priv->list);
4020         }
4021         i915_verify_inactive(dev, __FILE__, __LINE__);
4022
4023         return 0;
4024 }
4025
4026 void
4027 i915_gem_object_unpin(struct drm_gem_object *obj)
4028 {
4029         struct drm_device *dev = obj->dev;
4030         drm_i915_private_t *dev_priv = dev->dev_private;
4031         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4032
4033         i915_verify_inactive(dev, __FILE__, __LINE__);
4034         obj_priv->pin_count--;
4035         BUG_ON(obj_priv->pin_count < 0);
4036         BUG_ON(obj_priv->gtt_space == NULL);
4037
4038         /* If the object is no longer pinned, and is
4039          * neither active nor being flushed, then stick it on
4040          * the inactive list
4041          */
4042         if (obj_priv->pin_count == 0) {
4043                 if (!obj_priv->active &&
4044                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4045                         list_move_tail(&obj_priv->list,
4046                                        &dev_priv->mm.inactive_list);
4047                 atomic_dec(&dev->pin_count);
4048                 atomic_sub(obj->size, &dev->pin_memory);
4049         }
4050         i915_verify_inactive(dev, __FILE__, __LINE__);
4051 }
4052
4053 int
4054 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4055                    struct drm_file *file_priv)
4056 {
4057         struct drm_i915_gem_pin *args = data;
4058         struct drm_gem_object *obj;
4059         struct drm_i915_gem_object *obj_priv;
4060         int ret;
4061
4062         mutex_lock(&dev->struct_mutex);
4063
4064         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4065         if (obj == NULL) {
4066                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4067                           args->handle);
4068                 mutex_unlock(&dev->struct_mutex);
4069                 return -ENOENT;
4070         }
4071         obj_priv = to_intel_bo(obj);
4072
4073         if (obj_priv->madv != I915_MADV_WILLNEED) {
4074                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4075                 drm_gem_object_unreference(obj);
4076                 mutex_unlock(&dev->struct_mutex);
4077                 return -EINVAL;
4078         }
4079
4080         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4081                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4082                           args->handle);
4083                 drm_gem_object_unreference(obj);
4084                 mutex_unlock(&dev->struct_mutex);
4085                 return -EINVAL;
4086         }
4087
4088         obj_priv->user_pin_count++;
4089         obj_priv->pin_filp = file_priv;
4090         if (obj_priv->user_pin_count == 1) {
4091                 ret = i915_gem_object_pin(obj, args->alignment);
4092                 if (ret != 0) {
4093                         drm_gem_object_unreference(obj);
4094                         mutex_unlock(&dev->struct_mutex);
4095                         return ret;
4096                 }
4097         }
4098
4099         /* XXX - flush the CPU caches for pinned objects
4100          * as the X server doesn't manage domains yet
4101          */
4102         i915_gem_object_flush_cpu_write_domain(obj);
4103         args->offset = obj_priv->gtt_offset;
4104         drm_gem_object_unreference(obj);
4105         mutex_unlock(&dev->struct_mutex);
4106
4107         return 0;
4108 }
4109
4110 int
4111 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4112                      struct drm_file *file_priv)
4113 {
4114         struct drm_i915_gem_pin *args = data;
4115         struct drm_gem_object *obj;
4116         struct drm_i915_gem_object *obj_priv;
4117
4118         mutex_lock(&dev->struct_mutex);
4119
4120         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4121         if (obj == NULL) {
4122                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4123                           args->handle);
4124                 mutex_unlock(&dev->struct_mutex);
4125                 return -ENOENT;
4126         }
4127
4128         obj_priv = to_intel_bo(obj);
4129         if (obj_priv->pin_filp != file_priv) {
4130                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4131                           args->handle);
4132                 drm_gem_object_unreference(obj);
4133                 mutex_unlock(&dev->struct_mutex);
4134                 return -EINVAL;
4135         }
4136         obj_priv->user_pin_count--;
4137         if (obj_priv->user_pin_count == 0) {
4138                 obj_priv->pin_filp = NULL;
4139                 i915_gem_object_unpin(obj);
4140         }
4141
4142         drm_gem_object_unreference(obj);
4143         mutex_unlock(&dev->struct_mutex);
4144         return 0;
4145 }
4146
4147 int
4148 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4149                     struct drm_file *file_priv)
4150 {
4151         struct drm_i915_gem_busy *args = data;
4152         struct drm_gem_object *obj;
4153         struct drm_i915_gem_object *obj_priv;
4154
4155         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4156         if (obj == NULL) {
4157                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4158                           args->handle);
4159                 return -ENOENT;
4160         }
4161
4162         mutex_lock(&dev->struct_mutex);
4163
4164         /* Count all active objects as busy, even if they are currently not used
4165          * by the gpu. Users of this interface expect objects to eventually
4166          * become non-busy without any further actions, therefore emit any
4167          * necessary flushes here.
4168          */
4169         obj_priv = to_intel_bo(obj);
4170         args->busy = obj_priv->active;
4171         if (args->busy) {
4172                 /* Unconditionally flush objects, even when the gpu still uses this
4173                  * object. Userspace calling this function indicates that it wants to
4174                  * use this buffer rather sooner than later, so issuing the required
4175                  * flush earlier is beneficial.
4176                  */
4177                 if (obj->write_domain) {
4178                         i915_gem_flush(dev, 0, obj->write_domain);
4179                         (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring);
4180                 }
4181
4182                 /* Update the active list for the hardware's current position.
4183                  * Otherwise this only updates on a delayed timer or when irqs
4184                  * are actually unmasked, and our working set ends up being
4185                  * larger than required.
4186                  */
4187                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4188
4189                 args->busy = obj_priv->active;
4190         }
4191
4192         drm_gem_object_unreference(obj);
4193         mutex_unlock(&dev->struct_mutex);
4194         return 0;
4195 }
4196
4197 int
4198 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4199                         struct drm_file *file_priv)
4200 {
4201     return i915_gem_ring_throttle(dev, file_priv);
4202 }
4203
4204 int
4205 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4206                        struct drm_file *file_priv)
4207 {
4208         struct drm_i915_gem_madvise *args = data;
4209         struct drm_gem_object *obj;
4210         struct drm_i915_gem_object *obj_priv;
4211
4212         switch (args->madv) {
4213         case I915_MADV_DONTNEED:
4214         case I915_MADV_WILLNEED:
4215             break;
4216         default:
4217             return -EINVAL;
4218         }
4219
4220         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4221         if (obj == NULL) {
4222                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4223                           args->handle);
4224                 return -ENOENT;
4225         }
4226
4227         mutex_lock(&dev->struct_mutex);
4228         obj_priv = to_intel_bo(obj);
4229
4230         if (obj_priv->pin_count) {
4231                 drm_gem_object_unreference(obj);
4232                 mutex_unlock(&dev->struct_mutex);
4233
4234                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4235                 return -EINVAL;
4236         }
4237
4238         if (obj_priv->madv != __I915_MADV_PURGED)
4239                 obj_priv->madv = args->madv;
4240
4241         /* if the object is no longer bound, discard its backing storage */
4242         if (i915_gem_object_is_purgeable(obj_priv) &&
4243             obj_priv->gtt_space == NULL)
4244                 i915_gem_object_truncate(obj);
4245
4246         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4247
4248         drm_gem_object_unreference(obj);
4249         mutex_unlock(&dev->struct_mutex);
4250
4251         return 0;
4252 }
4253
4254 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4255                                               size_t size)
4256 {
4257         struct drm_i915_gem_object *obj;
4258
4259         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4260         if (obj == NULL)
4261                 return NULL;
4262
4263         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4264                 kfree(obj);
4265                 return NULL;
4266         }
4267
4268         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4269         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4270
4271         obj->agp_type = AGP_USER_MEMORY;
4272         obj->base.driver_private = NULL;
4273         obj->fence_reg = I915_FENCE_REG_NONE;
4274         INIT_LIST_HEAD(&obj->list);
4275         INIT_LIST_HEAD(&obj->gpu_write_list);
4276         obj->madv = I915_MADV_WILLNEED;
4277
4278         trace_i915_gem_object_create(&obj->base);
4279
4280         return &obj->base;
4281 }
4282
4283 int i915_gem_init_object(struct drm_gem_object *obj)
4284 {
4285         BUG();
4286
4287         return 0;
4288 }
4289
4290 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4291 {
4292         struct drm_device *dev = obj->dev;
4293         drm_i915_private_t *dev_priv = dev->dev_private;
4294         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4295         int ret;
4296
4297         ret = i915_gem_object_unbind(obj);
4298         if (ret == -ERESTARTSYS) {
4299                 list_move(&obj_priv->list,
4300                           &dev_priv->mm.deferred_free_list);
4301                 return;
4302         }
4303
4304         if (obj_priv->mmap_offset)
4305                 i915_gem_free_mmap_offset(obj);
4306
4307         drm_gem_object_release(obj);
4308
4309         kfree(obj_priv->page_cpu_valid);
4310         kfree(obj_priv->bit_17);
4311         kfree(obj_priv);
4312 }
4313
4314 void i915_gem_free_object(struct drm_gem_object *obj)
4315 {
4316         struct drm_device *dev = obj->dev;
4317         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4318
4319         trace_i915_gem_object_destroy(obj);
4320
4321         while (obj_priv->pin_count > 0)
4322                 i915_gem_object_unpin(obj);
4323
4324         if (obj_priv->phys_obj)
4325                 i915_gem_detach_phys_object(dev, obj);
4326
4327         i915_gem_free_object_tail(obj);
4328 }
4329
4330 int
4331 i915_gem_idle(struct drm_device *dev)
4332 {
4333         drm_i915_private_t *dev_priv = dev->dev_private;
4334         int ret;
4335
4336         mutex_lock(&dev->struct_mutex);
4337
4338         if (dev_priv->mm.suspended ||
4339                         (dev_priv->render_ring.gem_object == NULL) ||
4340                         (HAS_BSD(dev) &&
4341                          dev_priv->bsd_ring.gem_object == NULL)) {
4342                 mutex_unlock(&dev->struct_mutex);
4343                 return 0;
4344         }
4345
4346         ret = i915_gpu_idle(dev);
4347         if (ret) {
4348                 mutex_unlock(&dev->struct_mutex);
4349                 return ret;
4350         }
4351
4352         /* Under UMS, be paranoid and evict. */
4353         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4354                 ret = i915_gem_evict_inactive(dev);
4355                 if (ret) {
4356                         mutex_unlock(&dev->struct_mutex);
4357                         return ret;
4358                 }
4359         }
4360
4361         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4362          * We need to replace this with a semaphore, or something.
4363          * And not confound mm.suspended!
4364          */
4365         dev_priv->mm.suspended = 1;
4366         del_timer_sync(&dev_priv->hangcheck_timer);
4367
4368         i915_kernel_lost_context(dev);
4369         i915_gem_cleanup_ringbuffer(dev);
4370
4371         mutex_unlock(&dev->struct_mutex);
4372
4373         /* Cancel the retire work handler, which should be idle now. */
4374         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4375
4376         return 0;
4377 }
4378
4379 /*
4380  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4381  * over cache flushing.
4382  */
4383 static int
4384 i915_gem_init_pipe_control(struct drm_device *dev)
4385 {
4386         drm_i915_private_t *dev_priv = dev->dev_private;
4387         struct drm_gem_object *obj;
4388         struct drm_i915_gem_object *obj_priv;
4389         int ret;
4390
4391         obj = i915_gem_alloc_object(dev, 4096);
4392         if (obj == NULL) {
4393                 DRM_ERROR("Failed to allocate seqno page\n");
4394                 ret = -ENOMEM;
4395                 goto err;
4396         }
4397         obj_priv = to_intel_bo(obj);
4398         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4399
4400         ret = i915_gem_object_pin(obj, 4096);
4401         if (ret)
4402                 goto err_unref;
4403
4404         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4405         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4406         if (dev_priv->seqno_page == NULL)
4407                 goto err_unpin;
4408
4409         dev_priv->seqno_obj = obj;
4410         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4411
4412         return 0;
4413
4414 err_unpin:
4415         i915_gem_object_unpin(obj);
4416 err_unref:
4417         drm_gem_object_unreference(obj);
4418 err:
4419         return ret;
4420 }
4421
4422
4423 static void
4424 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4425 {
4426         drm_i915_private_t *dev_priv = dev->dev_private;
4427         struct drm_gem_object *obj;
4428         struct drm_i915_gem_object *obj_priv;
4429
4430         obj = dev_priv->seqno_obj;
4431         obj_priv = to_intel_bo(obj);
4432         kunmap(obj_priv->pages[0]);
4433         i915_gem_object_unpin(obj);
4434         drm_gem_object_unreference(obj);
4435         dev_priv->seqno_obj = NULL;
4436
4437         dev_priv->seqno_page = NULL;
4438 }
4439
4440 int
4441 i915_gem_init_ringbuffer(struct drm_device *dev)
4442 {
4443         drm_i915_private_t *dev_priv = dev->dev_private;
4444         int ret;
4445
4446         dev_priv->render_ring = render_ring;
4447
4448         if (!I915_NEED_GFX_HWS(dev)) {
4449                 dev_priv->render_ring.status_page.page_addr
4450                         = dev_priv->status_page_dmah->vaddr;
4451                 memset(dev_priv->render_ring.status_page.page_addr,
4452                                 0, PAGE_SIZE);
4453         }
4454
4455         if (HAS_PIPE_CONTROL(dev)) {
4456                 ret = i915_gem_init_pipe_control(dev);
4457                 if (ret)
4458                         return ret;
4459         }
4460
4461         ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4462         if (ret)
4463                 goto cleanup_pipe_control;
4464
4465         if (HAS_BSD(dev)) {
4466                 dev_priv->bsd_ring = bsd_ring;
4467                 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4468                 if (ret)
4469                         goto cleanup_render_ring;
4470         }
4471
4472         dev_priv->next_seqno = 1;
4473
4474         return 0;
4475
4476 cleanup_render_ring:
4477         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4478 cleanup_pipe_control:
4479         if (HAS_PIPE_CONTROL(dev))
4480                 i915_gem_cleanup_pipe_control(dev);
4481         return ret;
4482 }
4483
4484 void
4485 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4486 {
4487         drm_i915_private_t *dev_priv = dev->dev_private;
4488
4489         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4490         if (HAS_BSD(dev))
4491                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4492         if (HAS_PIPE_CONTROL(dev))
4493                 i915_gem_cleanup_pipe_control(dev);
4494 }
4495
4496 int
4497 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4498                        struct drm_file *file_priv)
4499 {
4500         drm_i915_private_t *dev_priv = dev->dev_private;
4501         int ret;
4502
4503         if (drm_core_check_feature(dev, DRIVER_MODESET))
4504                 return 0;
4505
4506         if (atomic_read(&dev_priv->mm.wedged)) {
4507                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4508                 atomic_set(&dev_priv->mm.wedged, 0);
4509         }
4510
4511         mutex_lock(&dev->struct_mutex);
4512         dev_priv->mm.suspended = 0;
4513
4514         ret = i915_gem_init_ringbuffer(dev);
4515         if (ret != 0) {
4516                 mutex_unlock(&dev->struct_mutex);
4517                 return ret;
4518         }
4519
4520         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4521         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4522         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4523         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4524         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4525         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4526         mutex_unlock(&dev->struct_mutex);
4527
4528         ret = drm_irq_install(dev);
4529         if (ret)
4530                 goto cleanup_ringbuffer;
4531
4532         return 0;
4533
4534 cleanup_ringbuffer:
4535         mutex_lock(&dev->struct_mutex);
4536         i915_gem_cleanup_ringbuffer(dev);
4537         dev_priv->mm.suspended = 1;
4538         mutex_unlock(&dev->struct_mutex);
4539
4540         return ret;
4541 }
4542
4543 int
4544 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4545                        struct drm_file *file_priv)
4546 {
4547         if (drm_core_check_feature(dev, DRIVER_MODESET))
4548                 return 0;
4549
4550         drm_irq_uninstall(dev);
4551         return i915_gem_idle(dev);
4552 }
4553
4554 void
4555 i915_gem_lastclose(struct drm_device *dev)
4556 {
4557         int ret;
4558
4559         if (drm_core_check_feature(dev, DRIVER_MODESET))
4560                 return;
4561
4562         ret = i915_gem_idle(dev);
4563         if (ret)
4564                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4565 }
4566
4567 void
4568 i915_gem_load(struct drm_device *dev)
4569 {
4570         int i;
4571         drm_i915_private_t *dev_priv = dev->dev_private;
4572
4573         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4574         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4575         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4576         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4577         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4578         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4579         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4580         if (HAS_BSD(dev)) {
4581                 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4582                 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4583         }
4584         for (i = 0; i < 16; i++)
4585                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4586         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4587                           i915_gem_retire_work_handler);
4588         spin_lock(&shrink_list_lock);
4589         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4590         spin_unlock(&shrink_list_lock);
4591
4592         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4593         if (IS_GEN3(dev)) {
4594                 u32 tmp = I915_READ(MI_ARB_STATE);
4595                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4596                         /* arb state is a masked write, so set bit + bit in mask */
4597                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4598                         I915_WRITE(MI_ARB_STATE, tmp);
4599                 }
4600         }
4601
4602         /* Old X drivers will take 0-2 for front, back, depth buffers */
4603         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4604                 dev_priv->fence_reg_start = 3;
4605
4606         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4607                 dev_priv->num_fence_regs = 16;
4608         else
4609                 dev_priv->num_fence_regs = 8;
4610
4611         /* Initialize fence registers to zero */
4612         if (IS_I965G(dev)) {
4613                 for (i = 0; i < 16; i++)
4614                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4615         } else {
4616                 for (i = 0; i < 8; i++)
4617                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4618                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4619                         for (i = 0; i < 8; i++)
4620                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4621         }
4622         i915_gem_detect_bit_6_swizzle(dev);
4623         init_waitqueue_head(&dev_priv->pending_flip_queue);
4624 }
4625
4626 /*
4627  * Create a physically contiguous memory object for this object
4628  * e.g. for cursor + overlay regs
4629  */
4630 static int i915_gem_init_phys_object(struct drm_device *dev,
4631                                      int id, int size, int align)
4632 {
4633         drm_i915_private_t *dev_priv = dev->dev_private;
4634         struct drm_i915_gem_phys_object *phys_obj;
4635         int ret;
4636
4637         if (dev_priv->mm.phys_objs[id - 1] || !size)
4638                 return 0;
4639
4640         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4641         if (!phys_obj)
4642                 return -ENOMEM;
4643
4644         phys_obj->id = id;
4645
4646         phys_obj->handle = drm_pci_alloc(dev, size, align);
4647         if (!phys_obj->handle) {
4648                 ret = -ENOMEM;
4649                 goto kfree_obj;
4650         }
4651 #ifdef CONFIG_X86
4652         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4653 #endif
4654
4655         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4656
4657         return 0;
4658 kfree_obj:
4659         kfree(phys_obj);
4660         return ret;
4661 }
4662
4663 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4664 {
4665         drm_i915_private_t *dev_priv = dev->dev_private;
4666         struct drm_i915_gem_phys_object *phys_obj;
4667
4668         if (!dev_priv->mm.phys_objs[id - 1])
4669                 return;
4670
4671         phys_obj = dev_priv->mm.phys_objs[id - 1];
4672         if (phys_obj->cur_obj) {
4673                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4674         }
4675
4676 #ifdef CONFIG_X86
4677         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4678 #endif
4679         drm_pci_free(dev, phys_obj->handle);
4680         kfree(phys_obj);
4681         dev_priv->mm.phys_objs[id - 1] = NULL;
4682 }
4683
4684 void i915_gem_free_all_phys_object(struct drm_device *dev)
4685 {
4686         int i;
4687
4688         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4689                 i915_gem_free_phys_object(dev, i);
4690 }
4691
4692 void i915_gem_detach_phys_object(struct drm_device *dev,
4693                                  struct drm_gem_object *obj)
4694 {
4695         struct drm_i915_gem_object *obj_priv;
4696         int i;
4697         int ret;
4698         int page_count;
4699
4700         obj_priv = to_intel_bo(obj);
4701         if (!obj_priv->phys_obj)
4702                 return;
4703
4704         ret = i915_gem_object_get_pages(obj, 0);
4705         if (ret)
4706                 goto out;
4707
4708         page_count = obj->size / PAGE_SIZE;
4709
4710         for (i = 0; i < page_count; i++) {
4711                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4712                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4713
4714                 memcpy(dst, src, PAGE_SIZE);
4715                 kunmap_atomic(dst, KM_USER0);
4716         }
4717         drm_clflush_pages(obj_priv->pages, page_count);
4718         drm_agp_chipset_flush(dev);
4719
4720         i915_gem_object_put_pages(obj);
4721 out:
4722         obj_priv->phys_obj->cur_obj = NULL;
4723         obj_priv->phys_obj = NULL;
4724 }
4725
4726 int
4727 i915_gem_attach_phys_object(struct drm_device *dev,
4728                             struct drm_gem_object *obj,
4729                             int id,
4730                             int align)
4731 {
4732         drm_i915_private_t *dev_priv = dev->dev_private;
4733         struct drm_i915_gem_object *obj_priv;
4734         int ret = 0;
4735         int page_count;
4736         int i;
4737
4738         if (id > I915_MAX_PHYS_OBJECT)
4739                 return -EINVAL;
4740
4741         obj_priv = to_intel_bo(obj);
4742
4743         if (obj_priv->phys_obj) {
4744                 if (obj_priv->phys_obj->id == id)
4745                         return 0;
4746                 i915_gem_detach_phys_object(dev, obj);
4747         }
4748
4749         /* create a new object */
4750         if (!dev_priv->mm.phys_objs[id - 1]) {
4751                 ret = i915_gem_init_phys_object(dev, id,
4752                                                 obj->size, align);
4753                 if (ret) {
4754                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4755                         goto out;
4756                 }
4757         }
4758
4759         /* bind to the object */
4760         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4761         obj_priv->phys_obj->cur_obj = obj;
4762
4763         ret = i915_gem_object_get_pages(obj, 0);
4764         if (ret) {
4765                 DRM_ERROR("failed to get page list\n");
4766                 goto out;
4767         }
4768
4769         page_count = obj->size / PAGE_SIZE;
4770
4771         for (i = 0; i < page_count; i++) {
4772                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4773                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4774
4775                 memcpy(dst, src, PAGE_SIZE);
4776                 kunmap_atomic(src, KM_USER0);
4777         }
4778
4779         i915_gem_object_put_pages(obj);
4780
4781         return 0;
4782 out:
4783         return ret;
4784 }
4785
4786 static int
4787 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4788                      struct drm_i915_gem_pwrite *args,
4789                      struct drm_file *file_priv)
4790 {
4791         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4792         void *obj_addr;
4793         int ret;
4794         char __user *user_data;
4795
4796         user_data = (char __user *) (uintptr_t) args->data_ptr;
4797         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4798
4799         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4800         ret = copy_from_user(obj_addr, user_data, args->size);
4801         if (ret)
4802                 return -EFAULT;
4803
4804         drm_agp_chipset_flush(dev);
4805         return 0;
4806 }
4807
4808 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4809 {
4810         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4811
4812         /* Clean up our request list when the client is going away, so that
4813          * later retire_requests won't dereference our soon-to-be-gone
4814          * file_priv.
4815          */
4816         mutex_lock(&dev->struct_mutex);
4817         while (!list_empty(&i915_file_priv->mm.request_list))
4818                 list_del_init(i915_file_priv->mm.request_list.next);
4819         mutex_unlock(&dev->struct_mutex);
4820 }
4821
4822 static int
4823 i915_gpu_is_active(struct drm_device *dev)
4824 {
4825         drm_i915_private_t *dev_priv = dev->dev_private;
4826         int lists_empty;
4827
4828         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4829                       list_empty(&dev_priv->render_ring.active_list);
4830         if (HAS_BSD(dev))
4831                 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4832
4833         return !lists_empty;
4834 }
4835
4836 static int
4837 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4838 {
4839         drm_i915_private_t *dev_priv, *next_dev;
4840         struct drm_i915_gem_object *obj_priv, *next_obj;
4841         int cnt = 0;
4842         int would_deadlock = 1;
4843
4844         /* "fast-path" to count number of available objects */
4845         if (nr_to_scan == 0) {
4846                 spin_lock(&shrink_list_lock);
4847                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4848                         struct drm_device *dev = dev_priv->dev;
4849
4850                         if (mutex_trylock(&dev->struct_mutex)) {
4851                                 list_for_each_entry(obj_priv,
4852                                                     &dev_priv->mm.inactive_list,
4853                                                     list)
4854                                         cnt++;
4855                                 mutex_unlock(&dev->struct_mutex);
4856                         }
4857                 }
4858                 spin_unlock(&shrink_list_lock);
4859
4860                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4861         }
4862
4863         spin_lock(&shrink_list_lock);
4864
4865 rescan:
4866         /* first scan for clean buffers */
4867         list_for_each_entry_safe(dev_priv, next_dev,
4868                                  &shrink_list, mm.shrink_list) {
4869                 struct drm_device *dev = dev_priv->dev;
4870
4871                 if (! mutex_trylock(&dev->struct_mutex))
4872                         continue;
4873
4874                 spin_unlock(&shrink_list_lock);
4875                 i915_gem_retire_requests(dev);
4876
4877                 list_for_each_entry_safe(obj_priv, next_obj,
4878                                          &dev_priv->mm.inactive_list,
4879                                          list) {
4880                         if (i915_gem_object_is_purgeable(obj_priv)) {
4881                                 i915_gem_object_unbind(&obj_priv->base);
4882                                 if (--nr_to_scan <= 0)
4883                                         break;
4884                         }
4885                 }
4886
4887                 spin_lock(&shrink_list_lock);
4888                 mutex_unlock(&dev->struct_mutex);
4889
4890                 would_deadlock = 0;
4891
4892                 if (nr_to_scan <= 0)
4893                         break;
4894         }
4895
4896         /* second pass, evict/count anything still on the inactive list */
4897         list_for_each_entry_safe(dev_priv, next_dev,
4898                                  &shrink_list, mm.shrink_list) {
4899                 struct drm_device *dev = dev_priv->dev;
4900
4901                 if (! mutex_trylock(&dev->struct_mutex))
4902                         continue;
4903
4904                 spin_unlock(&shrink_list_lock);
4905
4906                 list_for_each_entry_safe(obj_priv, next_obj,
4907                                          &dev_priv->mm.inactive_list,
4908                                          list) {
4909                         if (nr_to_scan > 0) {
4910                                 i915_gem_object_unbind(&obj_priv->base);
4911                                 nr_to_scan--;
4912                         } else
4913                                 cnt++;
4914                 }
4915
4916                 spin_lock(&shrink_list_lock);
4917                 mutex_unlock(&dev->struct_mutex);
4918
4919                 would_deadlock = 0;
4920         }
4921
4922         if (nr_to_scan) {
4923                 int active = 0;
4924
4925                 /*
4926                  * We are desperate for pages, so as a last resort, wait
4927                  * for the GPU to finish and discard whatever we can.
4928                  * This has a dramatic impact to reduce the number of
4929                  * OOM-killer events whilst running the GPU aggressively.
4930                  */
4931                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4932                         struct drm_device *dev = dev_priv->dev;
4933
4934                         if (!mutex_trylock(&dev->struct_mutex))
4935                                 continue;
4936
4937                         spin_unlock(&shrink_list_lock);
4938
4939                         if (i915_gpu_is_active(dev)) {
4940                                 i915_gpu_idle(dev);
4941                                 active++;
4942                         }
4943
4944                         spin_lock(&shrink_list_lock);
4945                         mutex_unlock(&dev->struct_mutex);
4946                 }
4947
4948                 if (active)
4949                         goto rescan;
4950         }
4951
4952         spin_unlock(&shrink_list_lock);
4953
4954         if (would_deadlock)
4955                 return -1;
4956         else if (cnt > 0)
4957                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4958         else
4959                 return 0;
4960 }
4961
4962 static struct shrinker shrinker = {
4963         .shrink = i915_gem_shrink,
4964         .seeks = DEFAULT_SEEKS,
4965 };
4966
4967 __init void
4968 i915_gem_shrinker_init(void)
4969 {
4970     register_shrinker(&shrinker);
4971 }
4972
4973 __exit void
4974 i915_gem_shrinker_exit(void)
4975 {
4976     unregister_shrinker(&shrinker);
4977 }