1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
51 #define I915_NUM_PIPE 2
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
67 #define WATCH_COHERENCY 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
80 struct drm_i915_gem_phys_object {
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
87 typedef struct _drm_i915_ring_buffer {
95 struct drm_gem_object *ring_obj;
96 } drm_i915_ring_buffer_t;
99 struct mem_block *next;
100 struct mem_block *prev;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
111 struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
119 struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
123 #define I915_FENCE_REG_NONE -1
125 struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
129 struct sdvo_device_mapping {
136 struct drm_i915_error_state {
152 typedef struct drm_i915_private {
153 struct drm_device *dev;
159 drm_i915_ring_buffer_t ring;
161 drm_dma_handle_t *status_page_dmah;
162 void *hw_status_page;
163 dma_addr_t dma_status_page;
165 unsigned int status_gfx_addr;
166 drm_local_map_t hws_map;
167 struct drm_gem_object *hws_obj;
169 struct resource mch_res;
177 wait_queue_head_t irq_queue;
178 atomic_t irq_received;
179 /** Protects user_irq_refcount and irq_mask_reg */
180 spinlock_t user_irq_lock;
181 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
182 int user_irq_refcount;
183 /** Cached value of IMR to avoid reads in updating the bitfield */
186 /** splitted irq regs for graphics and display engine on IGDNG,
187 irq_mask_reg is still used for display irq. */
189 u32 gt_irq_enable_reg;
190 u32 de_irq_enable_reg;
192 u32 hotplug_supported_mask;
193 struct work_struct hotplug_work;
195 int tex_lru_log_granularity;
196 int allow_batchbuffer;
197 struct mem_block *agp_heap;
198 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
201 bool cursor_needs_physical;
207 struct intel_opregion opregion;
210 int backlight_duty_cycle; /* restore backlight to this value */
211 bool panel_wants_dither;
212 struct drm_display_mode *panel_fixed_mode;
213 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
214 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
216 /* Feature bits from the VBIOS */
217 unsigned int int_tv_support:1;
218 unsigned int lvds_dither:1;
219 unsigned int lvds_vbt:1;
220 unsigned int int_crt_support:1;
221 unsigned int lvds_use_ssc:1;
222 unsigned int edp_support:1;
225 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
226 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
227 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
229 unsigned int fsb_freq, mem_freq;
231 spinlock_t error_lock;
232 struct drm_i915_error_state *first_error;
233 struct work_struct error_work;
234 struct workqueue_struct *wq;
241 u32 saveRENDERSTANDBY;
265 u32 savePFIT_PGM_RATIOS;
267 u32 saveBLC_PWM_CTL2;
292 u32 savePP_ON_DELAYS;
293 u32 savePP_OFF_DELAYS;
301 u32 savePFIT_CONTROL;
302 u32 save_palette_a[256];
303 u32 save_palette_b[256];
304 u32 saveFBC_CFB_BASE;
307 u32 saveFBC_CONTROL2;
311 u32 saveCACHE_MODE_0;
314 u32 saveMI_ARB_STATE;
325 uint64_t saveFENCE[16];
336 u32 savePIPEA_GMCH_DATA_M;
337 u32 savePIPEB_GMCH_DATA_M;
338 u32 savePIPEA_GMCH_DATA_N;
339 u32 savePIPEB_GMCH_DATA_N;
340 u32 savePIPEA_DP_LINK_M;
341 u32 savePIPEB_DP_LINK_M;
342 u32 savePIPEA_DP_LINK_N;
343 u32 savePIPEB_DP_LINK_N;
346 struct drm_mm gtt_space;
348 struct io_mapping *gtt_mapping;
352 * List of objects currently involved in rendering from the
355 * Includes buffers having the contents of their GPU caches
356 * flushed, not necessarily primitives. last_rendering_seqno
357 * represents when the rendering involved will be completed.
359 * A reference is held on the buffer while on this list.
361 spinlock_t active_list_lock;
362 struct list_head active_list;
365 * List of objects which are not in the ringbuffer but which
366 * still have a write_domain which needs to be flushed before
369 * last_rendering_seqno is 0 while an object is in this list.
371 * A reference is held on the buffer while on this list.
373 struct list_head flushing_list;
376 * LRU list of objects which are not in the ringbuffer and
377 * are ready to unbind, but are still in the GTT.
379 * last_rendering_seqno is 0 while an object is in this list.
381 * A reference is not held on the buffer while on this list,
382 * as merely being GTT-bound shouldn't prevent its being
383 * freed, and we'll pull it off the list in the free path.
385 struct list_head inactive_list;
387 /** LRU list of objects with fence regs on them. */
388 struct list_head fence_list;
391 * List of breadcrumbs associated with GPU requests currently
394 struct list_head request_list;
397 * We leave the user IRQ off as much as possible,
398 * but this means that requests will finish and never
399 * be retired once the system goes idle. Set a timer to
400 * fire periodically while the ring is running. When it
401 * fires, go retire requests.
403 struct delayed_work retire_work;
405 uint32_t next_gem_seqno;
408 * Waiting sequence number, if any
410 uint32_t waiting_gem_seqno;
413 * Last seq seen at irq time
415 uint32_t irq_gem_seqno;
418 * Flag if the X Server, and thus DRM, is not currently in
419 * control of the device.
421 * This is set between LeaveVT and EnterVT. It needs to be
422 * replaced with a semaphore. It also needs to be
423 * transitioned away from for kernel modesetting.
428 * Flag if the hardware appears to be wedged.
430 * This is set when attempts to idle the device timeout.
431 * It prevents command submission from occuring and makes
432 * every pending request fail
436 /** Bit 6 swizzling required for X tiling */
437 uint32_t bit_6_swizzle_x;
438 /** Bit 6 swizzling required for Y tiling */
439 uint32_t bit_6_swizzle_y;
441 /* storage for physical objects */
442 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
444 struct sdvo_device_mapping sdvo_mappings[2];
445 } drm_i915_private_t;
447 /** driver private structure attached to each drm_gem_object */
448 struct drm_i915_gem_object {
449 struct drm_gem_object *obj;
451 /** Current space allocated to this object in the GTT, if any. */
452 struct drm_mm_node *gtt_space;
454 /** This object's place on the active/flushing/inactive lists */
455 struct list_head list;
457 /** This object's place on the fenced object LRU */
458 struct list_head fence_list;
461 * This is set if the object is on the active or flushing lists
462 * (has pending rendering), and is not set if it's on inactive (ready
468 * This is set if the object has been written to since last bound
473 /** AGP memory structure for our GTT binding. */
474 DRM_AGP_MEM *agp_mem;
480 * Current offset of the object in GTT space.
482 * This is the same as gtt_space->start
486 * Required alignment for the object
488 uint32_t gtt_alignment;
490 * Fake offset for use by mmap(2)
492 uint64_t mmap_offset;
495 * Fence register bits (if any) for this object. Will be set
496 * as needed when mapped into the GTT.
497 * Protected by dev->struct_mutex.
501 /** How many users have pinned this object in GTT space */
504 /** Breadcrumb of last rendering to the buffer. */
505 uint32_t last_rendering_seqno;
507 /** Current tiling mode for the object. */
508 uint32_t tiling_mode;
511 /** Record of address bit 17 of each page at last unbind. */
514 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
518 * If present, while GEM_DOMAIN_CPU is in the read domain this array
519 * flags which individual pages are valid.
521 uint8_t *page_cpu_valid;
523 /** User space pin count and filp owning the pin */
524 uint32_t user_pin_count;
525 struct drm_file *pin_filp;
527 /** for phy allocated objects */
528 struct drm_i915_gem_phys_object *phys_obj;
531 * Used for checking the object doesn't appear more than once
532 * in an execbuffer object list.
538 * Request queue structure.
540 * The request queue allows us to note sequence numbers that have been emitted
541 * and may be associated with active buffers to be retired.
543 * By keeping this list, we can avoid having to do questionable
544 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
545 * an emission time with seqnos for tracking how far ahead of the GPU we are.
547 struct drm_i915_gem_request {
548 /** GEM sequence number associated with this request. */
551 /** Time at which this request was emitted, in jiffies. */
552 unsigned long emitted_jiffies;
554 /** global list entry for this request */
555 struct list_head list;
557 /** file_priv list entry for this request */
558 struct list_head client_list;
561 struct drm_i915_file_private {
563 struct list_head request_list;
567 enum intel_chip_family {
574 extern struct drm_ioctl_desc i915_ioctls[];
575 extern int i915_max_ioctl;
576 extern unsigned int i915_fbpercrtc;
578 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
579 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
582 extern void i915_kernel_lost_context(struct drm_device * dev);
583 extern int i915_driver_load(struct drm_device *, unsigned long flags);
584 extern int i915_driver_unload(struct drm_device *);
585 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
586 extern void i915_driver_lastclose(struct drm_device * dev);
587 extern void i915_driver_preclose(struct drm_device *dev,
588 struct drm_file *file_priv);
589 extern void i915_driver_postclose(struct drm_device *dev,
590 struct drm_file *file_priv);
591 extern int i915_driver_device_is_agp(struct drm_device * dev);
592 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
594 extern int i915_emit_box(struct drm_device *dev,
595 struct drm_clip_rect *boxes,
596 int i, int DR1, int DR4);
599 extern int i915_irq_emit(struct drm_device *dev, void *data,
600 struct drm_file *file_priv);
601 extern int i915_irq_wait(struct drm_device *dev, void *data,
602 struct drm_file *file_priv);
603 void i915_user_irq_get(struct drm_device *dev);
604 void i915_user_irq_put(struct drm_device *dev);
605 extern void i915_enable_interrupt (struct drm_device *dev);
607 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
608 extern void i915_driver_irq_preinstall(struct drm_device * dev);
609 extern int i915_driver_irq_postinstall(struct drm_device *dev);
610 extern void i915_driver_irq_uninstall(struct drm_device * dev);
611 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
612 struct drm_file *file_priv);
613 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
614 struct drm_file *file_priv);
615 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
616 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
617 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
618 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
619 extern int i915_vblank_swap(struct drm_device *dev, void *data,
620 struct drm_file *file_priv);
621 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
624 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
627 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
631 extern int i915_mem_alloc(struct drm_device *dev, void *data,
632 struct drm_file *file_priv);
633 extern int i915_mem_free(struct drm_device *dev, void *data,
634 struct drm_file *file_priv);
635 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
636 struct drm_file *file_priv);
637 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
638 struct drm_file *file_priv);
639 extern void i915_mem_takedown(struct mem_block **heap);
640 extern void i915_mem_release(struct drm_device * dev,
641 struct drm_file *file_priv, struct mem_block *heap);
643 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
644 struct drm_file *file_priv);
645 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
646 struct drm_file *file_priv);
647 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
648 struct drm_file *file_priv);
649 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
650 struct drm_file *file_priv);
651 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
652 struct drm_file *file_priv);
653 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
654 struct drm_file *file_priv);
655 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
656 struct drm_file *file_priv);
657 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *file_priv);
659 int i915_gem_execbuffer(struct drm_device *dev, void *data,
660 struct drm_file *file_priv);
661 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
662 struct drm_file *file_priv);
663 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
664 struct drm_file *file_priv);
665 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
666 struct drm_file *file_priv);
667 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
668 struct drm_file *file_priv);
669 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
670 struct drm_file *file_priv);
671 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *file_priv);
673 int i915_gem_set_tiling(struct drm_device *dev, void *data,
674 struct drm_file *file_priv);
675 int i915_gem_get_tiling(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
679 void i915_gem_load(struct drm_device *dev);
680 int i915_gem_init_object(struct drm_gem_object *obj);
681 void i915_gem_free_object(struct drm_gem_object *obj);
682 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
683 void i915_gem_object_unpin(struct drm_gem_object *obj);
684 int i915_gem_object_unbind(struct drm_gem_object *obj);
685 void i915_gem_release_mmap(struct drm_gem_object *obj);
686 void i915_gem_lastclose(struct drm_device *dev);
687 uint32_t i915_get_gem_seqno(struct drm_device *dev);
688 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
689 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
690 void i915_gem_retire_requests(struct drm_device *dev);
691 void i915_gem_retire_work_handler(struct work_struct *work);
692 void i915_gem_clflush_object(struct drm_gem_object *obj);
693 int i915_gem_object_set_domain(struct drm_gem_object *obj,
694 uint32_t read_domains,
695 uint32_t write_domain);
696 int i915_gem_init_ringbuffer(struct drm_device *dev);
697 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
698 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
700 int i915_gem_idle(struct drm_device *dev);
701 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
702 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
704 int i915_gem_attach_phys_object(struct drm_device *dev,
705 struct drm_gem_object *obj, int id);
706 void i915_gem_detach_phys_object(struct drm_device *dev,
707 struct drm_gem_object *obj);
708 void i915_gem_free_all_phys_object(struct drm_device *dev);
709 int i915_gem_object_get_pages(struct drm_gem_object *obj);
710 void i915_gem_object_put_pages(struct drm_gem_object *obj);
711 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
713 /* i915_gem_tiling.c */
714 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
715 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
716 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
718 /* i915_gem_debug.c */
719 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
720 const char *where, uint32_t mark);
722 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
724 #define i915_verify_inactive(dev, file, line)
726 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
727 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
728 const char *where, uint32_t mark);
729 void i915_dump_lru(struct drm_device *dev, const char *where);
732 int i915_gem_debugfs_init(struct drm_minor *minor);
733 void i915_gem_debugfs_cleanup(struct drm_minor *minor);
736 extern int i915_save_state(struct drm_device *dev);
737 extern int i915_restore_state(struct drm_device *dev);
740 extern int i915_save_state(struct drm_device *dev);
741 extern int i915_restore_state(struct drm_device *dev);
744 /* i915_opregion.c */
745 extern int intel_opregion_init(struct drm_device *dev, int resume);
746 extern void intel_opregion_free(struct drm_device *dev, int suspend);
747 extern void opregion_asle_intr(struct drm_device *dev);
748 extern void opregion_enable_asle(struct drm_device *dev);
750 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
751 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
752 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
753 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
757 extern void intel_modeset_init(struct drm_device *dev);
758 extern void intel_modeset_cleanup(struct drm_device *dev);
761 * Lock test for when it's just for synchronization of ring access.
763 * In that case, we don't need to do it when GEM is initialized as nobody else
764 * has access to the ring.
766 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
767 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
768 LOCK_TEST_WITH_RETURN(dev, file_priv); \
771 #define I915_READ(reg) readl(dev_priv->regs + (reg))
772 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
773 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
774 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
775 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
776 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
777 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
778 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
779 #define POSTING_READ(reg) (void)I915_READ(reg)
781 #define I915_VERBOSE 0
783 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
786 #define BEGIN_LP_RING(n) do { \
788 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
789 if (dev_priv->ring.space < (n)*4) \
790 i915_wait_ring(dev, (n)*4, __func__); \
792 outring = dev_priv->ring.tail; \
793 ringmask = dev_priv->ring.tail_mask; \
794 virt = dev_priv->ring.virtual_start; \
797 #define OUT_RING(n) do { \
798 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
799 *(volatile unsigned int *)(virt + outring) = (n); \
802 outring &= ringmask; \
805 #define ADVANCE_LP_RING() do { \
806 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
807 dev_priv->ring.tail = outring; \
808 dev_priv->ring.space -= outcount * 4; \
809 I915_WRITE(PRB0_TAIL, outring); \
813 * Reads a dword out of the status page, which is written to from the command
814 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
817 * The following dwords have a reserved meaning:
818 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
819 * 0x04: ring 0 head pointer
820 * 0x05: ring 1 head pointer (915-class)
821 * 0x06: ring 2 head pointer (915-class)
822 * 0x10-0x1b: Context status DWords (GM45)
823 * 0x1f: Last written status offset. (GM45)
825 * The area from dword 0x20 to 0x3ff is available for driver usage.
827 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
828 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
829 #define I915_GEM_HWS_INDEX 0x20
830 #define I915_BREADCRUMB_INDEX 0x21
832 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
834 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
835 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
836 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
837 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
838 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
840 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
841 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
842 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
843 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
844 (dev)->pci_device == 0x27AE)
845 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
846 (dev)->pci_device == 0x2982 || \
847 (dev)->pci_device == 0x2992 || \
848 (dev)->pci_device == 0x29A2 || \
849 (dev)->pci_device == 0x2A02 || \
850 (dev)->pci_device == 0x2A12 || \
851 (dev)->pci_device == 0x2A42 || \
852 (dev)->pci_device == 0x2E02 || \
853 (dev)->pci_device == 0x2E12 || \
854 (dev)->pci_device == 0x2E22 || \
855 (dev)->pci_device == 0x2E32 || \
856 (dev)->pci_device == 0x0042 || \
857 (dev)->pci_device == 0x0046)
859 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
860 (dev)->pci_device == 0x2A12)
862 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
864 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
865 (dev)->pci_device == 0x2E12 || \
866 (dev)->pci_device == 0x2E22 || \
867 (dev)->pci_device == 0x2E32 || \
870 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
871 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
872 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
874 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
875 (dev)->pci_device == 0x29B2 || \
876 (dev)->pci_device == 0x29D2 || \
879 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
880 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
881 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
883 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
884 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
887 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
888 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
889 IS_IGD(dev) || IS_IGDNG_M(dev))
891 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
893 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
894 * rows, which changed the alignment requirements and fence programming.
896 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
898 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
899 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
900 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
901 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
902 /* dsparb controlled by hw only */
903 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
905 #define PRIMARY_RINGBUFFER_SIZE (128*1024)