drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "../../../platform/x86/intel_ips.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <linux/module.h>
  45 #include <acpi/video.h>
  46
  47 static void i915_write_hws_pga(struct drm_device *dev)
  48 {
  49         drm_i915_private_t *dev_priv = dev->dev_private;
  50         u32 addr;
  51
  52         addr = dev_priv->status_page_dmah->busaddr;
  53         if (INTEL_INFO(dev)->gen >= 4)
  54                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  55         I915_WRITE(HWS_PGA, addr);
  56 }
  57
  58 /**
  59  * Sets up the hardware status page for devices that need a physical address
  60  * in the register.
  61  */
  62 static int i915_init_phys_hws(struct drm_device *dev)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         /* Program Hardware Status Page */
  67         dev_priv->status_page_dmah =
  68                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  69
  70         if (!dev_priv->status_page_dmah) {
  71                 DRM_ERROR("Can not allocate hardware status page\n");
  72                 return -ENOMEM;
  73         }
  74
  75         memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
  76                   0, PAGE_SIZE);
  77
  78         i915_write_hws_pga(dev);
  79
  80         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  81         return 0;
  82 }
  83
  84 /**
  85  * Frees the hardware status page, whether it's a physical address or a virtual
  86  * address set up by the X Server.
  87  */
  88 static void i915_free_hws(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  92
  93         if (dev_priv->status_page_dmah) {
  94                 drm_pci_free(dev, dev_priv->status_page_dmah);
  95                 dev_priv->status_page_dmah = NULL;
  96         }
  97
  98         if (ring->status_page.gfx_addr) {
  99                 ring->status_page.gfx_addr = 0;
 100                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 101         }
 102
 103         /* Need to rewrite hardware status page */
 104         I915_WRITE(HWS_PGA, 0x1ffff000);
 105 }
 106
 107 void i915_kernel_lost_context(struct drm_device * dev)
 108 {
 109         drm_i915_private_t *dev_priv = dev->dev_private;
 110         struct drm_i915_master_private *master_priv;
 111         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 112
 113         /*
 114          * We should never lose context on the ring with modesetting
 115          * as we don't expose it to userspace
 116          */
 117         if (drm_core_check_feature(dev, DRIVER_MODESET))
 118                 return;
 119
 120         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 121         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 122         ring->space = ring->head - (ring->tail + 8);
 123         if (ring->space < 0)
 124                 ring->space += ring->size;
 125
 126         if (!dev->primary->master)
 127                 return;
 128
 129         master_priv = dev->primary->master->driver_priv;
 130         if (ring->head == ring->tail && master_priv->sarea_priv)
 131                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 132 }
 133
 134 static int i915_dma_cleanup(struct drm_device * dev)
 135 {
 136         drm_i915_private_t *dev_priv = dev->dev_private;
 137         int i;
 138
 139         /* Make sure interrupts are disabled here because the uninstall ioctl
 140          * may not have been called from userspace and after dev_private
 141          * is freed, it's too late.
 142          */
 143         if (dev->irq_enabled)
 144                 drm_irq_uninstall(dev);
 145
 146         mutex_lock(&dev->struct_mutex);
 147         for (i = 0; i < I915_NUM_RINGS; i++)
 148                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 149         mutex_unlock(&dev->struct_mutex);
 150
 151         /* Clear the HWS virtual address at teardown */
 152         if (I915_NEED_GFX_HWS(dev))
 153                 i915_free_hws(dev);
 154
 155         return 0;
 156 }
 157
 158 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 159 {
 160         drm_i915_private_t *dev_priv = dev->dev_private;
 161         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 162         int ret;
 163
 164         master_priv->sarea = drm_getsarea(dev);
 165         if (master_priv->sarea) {
 166                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 167                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 168         } else {
 169                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 170         }
 171
 172         if (init->ring_size != 0) {
 173                 if (LP_RING(dev_priv)->obj != NULL) {
 174                         i915_dma_cleanup(dev);
 175                         DRM_ERROR("Client tried to initialize ringbuffer in "
 176                                   "GEM mode\n");
 177                         return -EINVAL;
 178                 }
 179
 180                 ret = intel_render_ring_init_dri(dev,
 181                                                  init->ring_start,
 182                                                  init->ring_size);
 183                 if (ret) {
 184                         i915_dma_cleanup(dev);
 185                         return ret;
 186                 }
 187         }
 188
 189         dev_priv->cpp = init->cpp;
 190         dev_priv->back_offset = init->back_offset;
 191         dev_priv->front_offset = init->front_offset;
 192         dev_priv->current_page = 0;
 193         if (master_priv->sarea_priv)
 194                 master_priv->sarea_priv->pf_current_page = 0;
 195
 196         /* Allow hardware batchbuffers unless told otherwise.
 197          */
 198         dev_priv->allow_batchbuffer = 1;
 199
 200         return 0;
 201 }
 202
 203 static int i915_dma_resume(struct drm_device * dev)
 204 {
 205         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 206         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 207
 208         DRM_DEBUG_DRIVER("%s\n", __func__);
 209
 210         if (ring->map.handle == NULL) {
 211                 DRM_ERROR("can not ioremap virtual address for"
 212                           " ring buffer\n");
 213                 return -ENOMEM;
 214         }
 215
 216         /* Program Hardware Status Page */
 217         if (!ring->status_page.page_addr) {
 218                 DRM_ERROR("Can not find hardware status page\n");
 219                 return -EINVAL;
 220         }
 221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 222                                 ring->status_page.page_addr);
 223         if (ring->status_page.gfx_addr != 0)
 224                 intel_ring_setup_status_page(ring);
 225         else
 226                 i915_write_hws_pga(dev);
 227
 228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_init(struct drm_device *dev, void *data,
 234                          struct drm_file *file_priv)
 235 {
 236         drm_i915_init_t *init = data;
 237         int retcode = 0;
 238
 239         switch (init->func) {
 240         case I915_INIT_DMA:
 241                 retcode = i915_initialize(dev, init);
 242                 break;
 243         case I915_CLEANUP_DMA:
 244                 retcode = i915_dma_cleanup(dev);
 245                 break;
 246         case I915_RESUME_DMA:
 247                 retcode = i915_dma_resume(dev);
 248                 break;
 249         default:
 250                 retcode = -EINVAL;
 251                 break;
 252         }
 253
 254         return retcode;
 255 }
 256
 257 /* Implement basically the same security restrictions as hardware does
 258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 259  *
 260  * Most of the calculations below involve calculating the size of a
 261  * particular instruction.  It's important to get the size right as
 262  * that tells us where the next instruction to check is.  Any illegal
 263  * instruction detected will be given a size of zero, which is a
 264  * signal to abort the rest of the buffer.
 265  */
 266 static int validate_cmd(int cmd)
 267 {
 268         switch (((cmd >> 29) & 0x7)) {
 269         case 0x0:
 270                 switch ((cmd >> 23) & 0x3f) {
 271                 case 0x0:
 272                         return 1;       /* MI_NOOP */
 273                 case 0x4:
 274                         return 1;       /* MI_FLUSH */
 275                 default:
 276                         return 0;       /* disallow everything else */
 277                 }
 278                 break;
 279         case 0x1:
 280                 return 0;       /* reserved */
 281         case 0x2:
 282                 return (cmd & 0xff) + 2;        /* 2d commands */
 283         case 0x3:
 284                 if (((cmd >> 24) & 0x1f) <= 0x18)
 285                         return 1;
 286
 287                 switch ((cmd >> 24) & 0x1f) {
 288                 case 0x1c:
 289                         return 1;
 290                 case 0x1d:
 291                         switch ((cmd >> 16) & 0xff) {
 292                         case 0x3:
 293                                 return (cmd & 0x1f) + 2;
 294                         case 0x4:
 295                                 return (cmd & 0xf) + 2;
 296                         default:
 297                                 return (cmd & 0xffff) + 2;
 298                         }
 299                 case 0x1e:
 300                         if (cmd & (1 << 23))
 301                                 return (cmd & 0xffff) + 1;
 302                         else
 303                                 return 1;
 304                 case 0x1f:
 305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 306                                 return (cmd & 0x1ffff) + 2;
 307                         else if (cmd & (1 << 17))       /* indirect random */
 308                                 if ((cmd & 0xffff) == 0)
 309                                         return 0;       /* unknown length, too hard */
 310                                 else
 311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 312                         else
 313                                 return 2;       /* indirect sequential */
 314                 default:
 315                         return 0;
 316                 }
 317         default:
 318                 return 0;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 325 {
 326         drm_i915_private_t *dev_priv = dev->dev_private;
 327         int i, ret;
 328
 329         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 330                 return -EINVAL;
 331
 332         for (i = 0; i < dwords;) {
 333                 int sz = validate_cmd(buffer[i]);
 334                 if (sz == 0 || i + sz > dwords)
 335                         return -EINVAL;
 336                 i += sz;
 337         }
 338
 339         ret = BEGIN_LP_RING((dwords+1)&~1);
 340         if (ret)
 341                 return ret;
 342
 343         for (i = 0; i < dwords; i++)
 344                 OUT_RING(buffer[i]);
 345         if (dwords & 1)
 346                 OUT_RING(0);
 347
 348         ADVANCE_LP_RING();
 349
 350         return 0;
 351 }
 352
 353 int
 354 i915_emit_box(struct drm_device *dev,
 355               struct drm_clip_rect *box,
 356               int DR1, int DR4)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         int ret;
 360
 361         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 362             box->y2 <= 0 || box->x2 <= 0) {
 363                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 364                           box->x1, box->y1, box->x2, box->y2);
 365                 return -EINVAL;
 366         }
 367
 368         if (INTEL_INFO(dev)->gen >= 4) {
 369                 ret = BEGIN_LP_RING(4);
 370                 if (ret)
 371                         return ret;
 372
 373                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 374                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 375                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 376                 OUT_RING(DR4);
 377         } else {
 378                 ret = BEGIN_LP_RING(6);
 379                 if (ret)
 380                         return ret;
 381
 382                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 383                 OUT_RING(DR1);
 384                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 385                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 386                 OUT_RING(DR4);
 387                 OUT_RING(0);
 388         }
 389         ADVANCE_LP_RING();
 390
 391         return 0;
 392 }
 393
 394 /* XXX: Emitting the counter should really be moved to part of the IRQ
 395  * emit. For now, do it in both places:
 396  */
 397
 398 static void i915_emit_breadcrumb(struct drm_device *dev)
 399 {
 400         drm_i915_private_t *dev_priv = dev->dev_private;
 401         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 402
 403         dev_priv->counter++;
 404         if (dev_priv->counter > 0x7FFFFFFFUL)
 405                 dev_priv->counter = 0;
 406         if (master_priv->sarea_priv)
 407                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 408
 409         if (BEGIN_LP_RING(4) == 0) {
 410                 OUT_RING(MI_STORE_DWORD_INDEX);
 411                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 412                 OUT_RING(dev_priv->counter);
 413                 OUT_RING(0);
 414                 ADVANCE_LP_RING();
 415         }
 416 }
 417
 418 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 419                                    drm_i915_cmdbuffer_t *cmd,
 420                                    struct drm_clip_rect *cliprects,
 421                                    void *cmdbuf)
 422 {
 423         int nbox = cmd->num_cliprects;
 424         int i = 0, count, ret;
 425
 426         if (cmd->sz & 0x3) {
 427                 DRM_ERROR("alignment");
 428                 return -EINVAL;
 429         }
 430
 431         i915_kernel_lost_context(dev);
 432
 433         count = nbox ? nbox : 1;
 434
 435         for (i = 0; i < count; i++) {
 436                 if (i < nbox) {
 437                         ret = i915_emit_box(dev, &cliprects[i],
 438                                             cmd->DR1, cmd->DR4);
 439                         if (ret)
 440                                 return ret;
 441                 }
 442
 443                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         i915_emit_breadcrumb(dev);
 449         return 0;
 450 }
 451
 452 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 453                                      drm_i915_batchbuffer_t * batch,
 454                                      struct drm_clip_rect *cliprects)
 455 {
 456         struct drm_i915_private *dev_priv = dev->dev_private;
 457         int nbox = batch->num_cliprects;
 458         int i, count, ret;
 459
 460         if ((batch->start | batch->used) & 0x7) {
 461                 DRM_ERROR("alignment");
 462                 return -EINVAL;
 463         }
 464
 465         i915_kernel_lost_context(dev);
 466
 467         count = nbox ? nbox : 1;
 468         for (i = 0; i < count; i++) {
 469                 if (i < nbox) {
 470                         ret = i915_emit_box(dev, &cliprects[i],
 471                                             batch->DR1, batch->DR4);
 472                         if (ret)
 473                                 return ret;
 474                 }
 475
 476                 if (!IS_I830(dev) && !IS_845G(dev)) {
 477                         ret = BEGIN_LP_RING(2);
 478                         if (ret)
 479                                 return ret;
 480
 481                         if (INTEL_INFO(dev)->gen >= 4) {
 482                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 483                                 OUT_RING(batch->start);
 484                         } else {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 486                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 487                         }
 488                 } else {
 489                         ret = BEGIN_LP_RING(4);
 490                         if (ret)
 491                                 return ret;
 492
 493                         OUT_RING(MI_BATCH_BUFFER);
 494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 495                         OUT_RING(batch->start + batch->used - 4);
 496                         OUT_RING(0);
 497                 }
 498                 ADVANCE_LP_RING();
 499         }
 500
 501
 502         if (IS_G4X(dev) || IS_GEN5(dev)) {
 503                 if (BEGIN_LP_RING(2) == 0) {
 504                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 505                         OUT_RING(MI_NOOP);
 506                         ADVANCE_LP_RING();
 507                 }
 508         }
 509
 510         i915_emit_breadcrumb(dev);
 511         return 0;
 512 }
 513
 514 static int i915_dispatch_flip(struct drm_device * dev)
 515 {
 516         drm_i915_private_t *dev_priv = dev->dev_private;
 517         struct drm_i915_master_private *master_priv =
 518                 dev->primary->master->driver_priv;
 519         int ret;
 520
 521         if (!master_priv->sarea_priv)
 522                 return -EINVAL;
 523
 524         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 525                           __func__,
 526                          dev_priv->current_page,
 527                          master_priv->sarea_priv->pf_current_page);
 528
 529         i915_kernel_lost_context(dev);
 530
 531         ret = BEGIN_LP_RING(10);
 532         if (ret)
 533                 return ret;
 534
 535         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 536         OUT_RING(0);
 537
 538         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 539         OUT_RING(0);
 540         if (dev_priv->current_page == 0) {
 541                 OUT_RING(dev_priv->back_offset);
 542                 dev_priv->current_page = 1;
 543         } else {
 544                 OUT_RING(dev_priv->front_offset);
 545                 dev_priv->current_page = 0;
 546         }
 547         OUT_RING(0);
 548
 549         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 550         OUT_RING(0);
 551
 552         ADVANCE_LP_RING();
 553
 554         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 555
 556         if (BEGIN_LP_RING(4) == 0) {
 557                 OUT_RING(MI_STORE_DWORD_INDEX);
 558                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 559                 OUT_RING(dev_priv->counter);
 560                 OUT_RING(0);
 561                 ADVANCE_LP_RING();
 562         }
 563
 564         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 565         return 0;
 566 }
 567
 568 static int i915_quiescent(struct drm_device *dev)
 569 {
 570         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 571
 572         i915_kernel_lost_context(dev);
 573         return intel_wait_ring_idle(ring);
 574 }
 575
 576 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 577                             struct drm_file *file_priv)
 578 {
 579         int ret;
 580
 581         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 582
 583         mutex_lock(&dev->struct_mutex);
 584         ret = i915_quiescent(dev);
 585         mutex_unlock(&dev->struct_mutex);
 586
 587         return ret;
 588 }
 589
 590 static int i915_batchbuffer(struct drm_device *dev, void *data,
 591                             struct drm_file *file_priv)
 592 {
 593         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 594         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 595         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 596             master_priv->sarea_priv;
 597         drm_i915_batchbuffer_t *batch = data;
 598         int ret;
 599         struct drm_clip_rect *cliprects = NULL;
 600
 601         if (!dev_priv->allow_batchbuffer) {
 602                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 603                 return -EINVAL;
 604         }
 605
 606         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 607                         batch->start, batch->used, batch->num_cliprects);
 608
 609         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 610
 611         if (batch->num_cliprects < 0)
 612                 return -EINVAL;
 613
 614         if (batch->num_cliprects) {
 615                 cliprects = kcalloc(batch->num_cliprects,
 616                                     sizeof(struct drm_clip_rect),
 617                                     GFP_KERNEL);
 618                 if (cliprects == NULL)
 619                         return -ENOMEM;
 620
 621                 ret = copy_from_user(cliprects, batch->cliprects,
 622                                      batch->num_cliprects *
 623                                      sizeof(struct drm_clip_rect));
 624                 if (ret != 0) {
 625                         ret = -EFAULT;
 626                         goto fail_free;
 627                 }
 628         }
 629
 630         mutex_lock(&dev->struct_mutex);
 631         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         if (sarea_priv)
 635                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 636
 637 fail_free:
 638         kfree(cliprects);
 639
 640         return ret;
 641 }
 642
 643 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 644                           struct drm_file *file_priv)
 645 {
 646         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 647         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 648         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 649             master_priv->sarea_priv;
 650         drm_i915_cmdbuffer_t *cmdbuf = data;
 651         struct drm_clip_rect *cliprects = NULL;
 652         void *batch_data;
 653         int ret;
 654
 655         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 656                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 657
 658         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 659
 660         if (cmdbuf->num_cliprects < 0)
 661                 return -EINVAL;
 662
 663         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 664         if (batch_data == NULL)
 665                 return -ENOMEM;
 666
 667         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 668         if (ret != 0) {
 669                 ret = -EFAULT;
 670                 goto fail_batch_free;
 671         }
 672
 673         if (cmdbuf->num_cliprects) {
 674                 cliprects = kcalloc(cmdbuf->num_cliprects,
 675                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 676                 if (cliprects == NULL) {
 677                         ret = -ENOMEM;
 678                         goto fail_batch_free;
 679                 }
 680
 681                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 682                                      cmdbuf->num_cliprects *
 683                                      sizeof(struct drm_clip_rect));
 684                 if (ret != 0) {
 685                         ret = -EFAULT;
 686                         goto fail_clip_free;
 687                 }
 688         }
 689
 690         mutex_lock(&dev->struct_mutex);
 691         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 692         mutex_unlock(&dev->struct_mutex);
 693         if (ret) {
 694                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 695                 goto fail_clip_free;
 696         }
 697
 698         if (sarea_priv)
 699                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 700
 701 fail_clip_free:
 702         kfree(cliprects);
 703 fail_batch_free:
 704         kfree(batch_data);
 705
 706         return ret;
 707 }
 708
 709 static int i915_flip_bufs(struct drm_device *dev, void *data,
 710                           struct drm_file *file_priv)
 711 {
 712         int ret;
 713
 714         DRM_DEBUG_DRIVER("%s\n", __func__);
 715
 716         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 717
 718         mutex_lock(&dev->struct_mutex);
 719         ret = i915_dispatch_flip(dev);
 720         mutex_unlock(&dev->struct_mutex);
 721
 722         return ret;
 723 }
 724
 725 static int i915_getparam(struct drm_device *dev, void *data,
 726                          struct drm_file *file_priv)
 727 {
 728         drm_i915_private_t *dev_priv = dev->dev_private;
 729         drm_i915_getparam_t *param = data;
 730         int value;
 731
 732         if (!dev_priv) {
 733                 DRM_ERROR("called with no initialization\n");
 734                 return -EINVAL;
 735         }
 736
 737         switch (param->param) {
 738         case I915_PARAM_IRQ_ACTIVE:
 739                 value = dev->pdev->irq ? 1 : 0;
 740                 break;
 741         case I915_PARAM_ALLOW_BATCHBUFFER:
 742                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 743                 break;
 744         case I915_PARAM_LAST_DISPATCH:
 745                 value = READ_BREADCRUMB(dev_priv);
 746                 break;
 747         case I915_PARAM_CHIPSET_ID:
 748                 value = dev->pci_device;
 749                 break;
 750         case I915_PARAM_HAS_GEM:
 751                 value = dev_priv->has_gem;
 752                 break;
 753         case I915_PARAM_NUM_FENCES_AVAIL:
 754                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 755                 break;
 756         case I915_PARAM_HAS_OVERLAY:
 757                 value = dev_priv->overlay ? 1 : 0;
 758                 break;
 759         case I915_PARAM_HAS_PAGEFLIPPING:
 760                 value = 1;
 761                 break;
 762         case I915_PARAM_HAS_EXECBUF2:
 763                 /* depends on GEM */
 764                 value = dev_priv->has_gem;
 765                 break;
 766         case I915_PARAM_HAS_BSD:
 767                 value = HAS_BSD(dev);
 768                 break;
 769         case I915_PARAM_HAS_BLT:
 770                 value = HAS_BLT(dev);
 771                 break;
 772         case I915_PARAM_HAS_RELAXED_FENCING:
 773                 value = 1;
 774                 break;
 775         case I915_PARAM_HAS_COHERENT_RINGS:
 776                 value = 1;
 777                 break;
 778         case I915_PARAM_HAS_EXEC_CONSTANTS:
 779                 value = INTEL_INFO(dev)->gen >= 4;
 780                 break;
 781         case I915_PARAM_HAS_RELAXED_DELTA:
 782                 value = 1;
 783                 break;
 784         default:
 785                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 786                                  param->param);
 787                 return -EINVAL;
 788         }
 789
 790         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 791                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 792                 return -EFAULT;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int i915_setparam(struct drm_device *dev, void *data,
 799                          struct drm_file *file_priv)
 800 {
 801         drm_i915_private_t *dev_priv = dev->dev_private;
 802         drm_i915_setparam_t *param = data;
 803
 804         if (!dev_priv) {
 805                 DRM_ERROR("called with no initialization\n");
 806                 return -EINVAL;
 807         }
 808
 809         switch (param->param) {
 810         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 811                 break;
 812         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 813                 dev_priv->tex_lru_log_granularity = param->value;
 814                 break;
 815         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 816                 dev_priv->allow_batchbuffer = param->value;
 817                 break;
 818         case I915_SETPARAM_NUM_USED_FENCES:
 819                 if (param->value > dev_priv->num_fence_regs ||
 820                     param->value < 0)
 821                         return -EINVAL;
 822                 /* Userspace can use first N regs */
 823                 dev_priv->fence_reg_start = param->value;
 824                 break;
 825         default:
 826                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 827                                         param->param);
 828                 return -EINVAL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int i915_set_status_page(struct drm_device *dev, void *data,
 835                                 struct drm_file *file_priv)
 836 {
 837         drm_i915_private_t *dev_priv = dev->dev_private;
 838         drm_i915_hws_addr_t *hws = data;
 839         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 840
 841         if (!I915_NEED_GFX_HWS(dev))
 842                 return -EINVAL;
 843
 844         if (!dev_priv) {
 845                 DRM_ERROR("called with no initialization\n");
 846                 return -EINVAL;
 847         }
 848
 849         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 850                 WARN(1, "tried to set status page when mode setting active\n");
 851                 return 0;
 852         }
 853
 854         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 855
 856         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 857
 858         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 859         dev_priv->hws_map.size = 4*1024;
 860         dev_priv->hws_map.type = 0;
 861         dev_priv->hws_map.flags = 0;
 862         dev_priv->hws_map.mtrr = 0;
 863
 864         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 865         if (dev_priv->hws_map.handle == NULL) {
 866                 i915_dma_cleanup(dev);
 867                 ring->status_page.gfx_addr = 0;
 868                 DRM_ERROR("can not ioremap virtual address for"
 869                                 " G33 hw status page\n");
 870                 return -ENOMEM;
 871         }
 872         ring->status_page.page_addr =
 873                 (void __force __iomem *)dev_priv->hws_map.handle;
 874         memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
 875         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 876
 877         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 878                          ring->status_page.gfx_addr);
 879         DRM_DEBUG_DRIVER("load hws at %p\n",
 880                          ring->status_page.page_addr);
 881         return 0;
 882 }
 883
 884 static int i915_get_bridge_dev(struct drm_device *dev)
 885 {
 886         struct drm_i915_private *dev_priv = dev->dev_private;
 887
 888         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 889         if (!dev_priv->bridge_dev) {
 890                 DRM_ERROR("bridge device not found\n");
 891                 return -1;
 892         }
 893         return 0;
 894 }
 895
 896 #define MCHBAR_I915 0x44
 897 #define MCHBAR_I965 0x48
 898 #define MCHBAR_SIZE (4*4096)
 899
 900 #define DEVEN_REG 0x54
 901 #define   DEVEN_MCHBAR_EN (1 << 28)
 902
 903 /* Allocate space for the MCH regs if needed, return nonzero on error */
 904 static int
 905 intel_alloc_mchbar_resource(struct drm_device *dev)
 906 {
 907         drm_i915_private_t *dev_priv = dev->dev_private;
 908         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 909         u32 temp_lo, temp_hi = 0;
 910         u64 mchbar_addr;
 911         int ret;
 912
 913         if (INTEL_INFO(dev)->gen >= 4)
 914                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 915         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 916         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 917
 918         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 919 #ifdef CONFIG_PNP
 920         if (mchbar_addr &&
 921             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 922                 return 0;
 923 #endif
 924
 925         /* Get some space for it */
 926         dev_priv->mch_res.name = "i915 MCHBAR";
 927         dev_priv->mch_res.flags = IORESOURCE_MEM;
 928         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 929                                      &dev_priv->mch_res,
 930                                      MCHBAR_SIZE, MCHBAR_SIZE,
 931                                      PCIBIOS_MIN_MEM,
 932                                      0, pcibios_align_resource,
 933                                      dev_priv->bridge_dev);
 934         if (ret) {
 935                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 936                 dev_priv->mch_res.start = 0;
 937                 return ret;
 938         }
 939
 940         if (INTEL_INFO(dev)->gen >= 4)
 941                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 942                                        upper_32_bits(dev_priv->mch_res.start));
 943
 944         pci_write_config_dword(dev_priv->bridge_dev, reg,
 945                                lower_32_bits(dev_priv->mch_res.start));
 946         return 0;
 947 }
 948
 949 /* Setup MCHBAR if possible, return true if we should disable it again */
 950 static void
 951 intel_setup_mchbar(struct drm_device *dev)
 952 {
 953         drm_i915_private_t *dev_priv = dev->dev_private;
 954         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 955         u32 temp;
 956         bool enabled;
 957
 958         dev_priv->mchbar_need_disable = false;
 959
 960         if (IS_I915G(dev) || IS_I915GM(dev)) {
 961                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 962                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 963         } else {
 964                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 965                 enabled = temp & 1;
 966         }
 967
 968         /* If it's already enabled, don't have to do anything */
 969         if (enabled)
 970                 return;
 971
 972         if (intel_alloc_mchbar_resource(dev))
 973                 return;
 974
 975         dev_priv->mchbar_need_disable = true;
 976
 977         /* Space is allocated or reserved, so enable it. */
 978         if (IS_I915G(dev) || IS_I915GM(dev)) {
 979                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 980                                        temp | DEVEN_MCHBAR_EN);
 981         } else {
 982                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 983                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 984         }
 985 }
 986
 987 static void
 988 intel_teardown_mchbar(struct drm_device *dev)
 989 {
 990         drm_i915_private_t *dev_priv = dev->dev_private;
 991         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 992         u32 temp;
 993
 994         if (dev_priv->mchbar_need_disable) {
 995                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 996                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 997                         temp &= ~DEVEN_MCHBAR_EN;
 998                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 999                 } else {
1000                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1001                         temp &= ~1;
1002                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1003                 }
1004         }
1005
1006         if (dev_priv->mch_res.start)
1007                 release_resource(&dev_priv->mch_res);
1008 }
1009
1010 #define PTE_ADDRESS_MASK                0xfffff000
1011 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1012 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1013 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1014 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1015 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1016 #define PTE_VALID                       (1 << 0)
1017
1018 /**
1019  * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1020  *                       a physical one
1021  * @dev: drm device
1022  * @offset: address to translate
1023  *
1024  * Some chip functions require allocations from stolen space and need the
1025  * physical address of the memory in question.
1026  */
1027 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1028 {
1029         struct drm_i915_private *dev_priv = dev->dev_private;
1030         struct pci_dev *pdev = dev_priv->bridge_dev;
1031         u32 base;
1032
1033 #if 0
1034         /* On the machines I have tested the Graphics Base of Stolen Memory
1035          * is unreliable, so compute the base by subtracting the stolen memory
1036          * from the Top of Low Usable DRAM which is where the BIOS places
1037          * the graphics stolen memory.
1038          */
1039         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1040                 /* top 32bits are reserved = 0 */
1041                 pci_read_config_dword(pdev, 0xA4, &base);
1042         } else {
1043                 /* XXX presume 8xx is the same as i915 */
1044                 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1045         }
1046 #else
1047         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1048                 u16 val;
1049                 pci_read_config_word(pdev, 0xb0, &val);
1050                 base = val >> 4 << 20;
1051         } else {
1052                 u8 val;
1053                 pci_read_config_byte(pdev, 0x9c, &val);
1054                 base = val >> 3 << 27;
1055         }
1056         base -= dev_priv->mm.gtt->stolen_size;
1057 #endif
1058
1059         return base + offset;
1060 }
1061
1062 static void i915_warn_stolen(struct drm_device *dev)
1063 {
1064         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1065         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1066 }
1067
1068 static void i915_setup_compression(struct drm_device *dev, int size)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1072         unsigned long cfb_base;
1073         unsigned long ll_base = 0;
1074
1075         /* Just in case the BIOS is doing something questionable. */
1076         intel_disable_fbc(dev);
1077
1078         compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1079         if (compressed_fb)
1080                 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1081         if (!compressed_fb)
1082                 goto err;
1083
1084         cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1085         if (!cfb_base)
1086                 goto err_fb;
1087
1088         if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1089                 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1090                                                     4096, 4096, 0);
1091                 if (compressed_llb)
1092                         compressed_llb = drm_mm_get_block(compressed_llb,
1093                                                           4096, 4096);
1094                 if (!compressed_llb)
1095                         goto err_fb;
1096
1097                 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1098                 if (!ll_base)
1099                         goto err_llb;
1100         }
1101
1102         dev_priv->cfb_size = size;
1103
1104         dev_priv->compressed_fb = compressed_fb;
1105         if (HAS_PCH_SPLIT(dev))
1106                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1107         else if (IS_GM45(dev)) {
1108                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1109         } else {
1110                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1111                 I915_WRITE(FBC_LL_BASE, ll_base);
1112                 dev_priv->compressed_llb = compressed_llb;
1113         }
1114
1115         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1116                       cfb_base, ll_base, size >> 20);
1117         return;
1118
1119 err_llb:
1120         drm_mm_put_block(compressed_llb);
1121 err_fb:
1122         drm_mm_put_block(compressed_fb);
1123 err:
1124         dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1125         i915_warn_stolen(dev);
1126 }
1127
1128 static void i915_cleanup_compression(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         drm_mm_put_block(dev_priv->compressed_fb);
1133         if (dev_priv->compressed_llb)
1134                 drm_mm_put_block(dev_priv->compressed_llb);
1135 }
1136
1137 /* true = enable decode, false = disable decoder */
1138 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1139 {
1140         struct drm_device *dev = cookie;
1141
1142         intel_modeset_vga_set_state(dev, state);
1143         if (state)
1144                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1145                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1146         else
1147                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1148 }
1149
1150 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1151 {
1152         struct drm_device *dev = pci_get_drvdata(pdev);
1153         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1154         if (state == VGA_SWITCHEROO_ON) {
1155                 printk(KERN_INFO "i915: switched on\n");
1156                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1157                 /* i915 resume handler doesn't set to D0 */
1158                 pci_set_power_state(dev->pdev, PCI_D0);
1159                 i915_resume(dev);
1160                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1161         } else {
1162                 printk(KERN_ERR "i915: switched off\n");
1163                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1164                 i915_suspend(dev, pmm);
1165                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1166         }
1167 }
1168
1169 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1170 {
1171         struct drm_device *dev = pci_get_drvdata(pdev);
1172         bool can_switch;
1173
1174         spin_lock(&dev->count_lock);
1175         can_switch = (dev->open_count == 0);
1176         spin_unlock(&dev->count_lock);
1177         return can_switch;
1178 }
1179
1180 static int i915_load_gem_init(struct drm_device *dev)
1181 {
1182         struct drm_i915_private *dev_priv = dev->dev_private;
1183         unsigned long prealloc_size, gtt_size, mappable_size;
1184         int ret;
1185
1186         prealloc_size = dev_priv->mm.gtt->stolen_size;
1187         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1188         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1189
1190         /* Basic memrange allocator for stolen space */
1191         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1192
1193         /* Let GEM Manage all of the aperture.
1194          *
1195          * However, leave one page at the end still bound to the scratch page.
1196          * There are a number of places where the hardware apparently
1197          * prefetches past the end of the object, and we've seen multiple
1198          * hangs with the GPU head pointer stuck in a batchbuffer bound
1199          * at the last page of the aperture.  One page should be enough to
1200          * keep any prefetching inside of the aperture.
1201          */
1202         i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1203
1204         mutex_lock(&dev->struct_mutex);
1205         ret = i915_gem_init_ringbuffer(dev);
1206         mutex_unlock(&dev->struct_mutex);
1207         if (ret)
1208                 return ret;
1209
1210         /* Try to set up FBC with a reasonable compressed buffer size */
1211         if (I915_HAS_FBC(dev) && i915_powersave) {
1212                 int cfb_size;
1213
1214                 /* Leave 1M for line length buffer & misc. */
1215
1216                 /* Try to get a 32M buffer... */
1217                 if (prealloc_size > (36*1024*1024))
1218                         cfb_size = 32*1024*1024;
1219                 else /* fall back to 7/8 of the stolen space */
1220                         cfb_size = prealloc_size * 7 / 8;
1221                 i915_setup_compression(dev, cfb_size);
1222         }
1223
1224         /* Allow hardware batchbuffers unless told otherwise. */
1225         dev_priv->allow_batchbuffer = 1;
1226         return 0;
1227 }
1228
1229 static int i915_load_modeset_init(struct drm_device *dev)
1230 {
1231         struct drm_i915_private *dev_priv = dev->dev_private;
1232         int ret;
1233
1234         ret = intel_parse_bios(dev);
1235         if (ret)
1236                 DRM_INFO("failed to find VBIOS tables\n");
1237
1238         /* If we have > 1 VGA cards, then we need to arbitrate access
1239          * to the common VGA resources.
1240          *
1241          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1242          * then we do not take part in VGA arbitration and the
1243          * vga_client_register() fails with -ENODEV.
1244          */
1245         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1246         if (ret && ret != -ENODEV)
1247                 goto out;
1248
1249         intel_register_dsm_handler();
1250
1251         ret = vga_switcheroo_register_client(dev->pdev,
1252                                              i915_switcheroo_set_state,
1253                                              NULL,
1254                                              i915_switcheroo_can_switch);
1255         if (ret)
1256                 goto cleanup_vga_client;
1257
1258         /* IIR "flip pending" bit means done if this bit is set */
1259         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1260                 dev_priv->flip_pending_is_done = true;
1261
1262         intel_modeset_init(dev);
1263
1264         ret = i915_load_gem_init(dev);
1265         if (ret)
1266                 goto cleanup_vga_switcheroo;
1267
1268         intel_modeset_gem_init(dev);
1269
1270         ret = drm_irq_install(dev);
1271         if (ret)
1272                 goto cleanup_gem;
1273
1274         /* Always safe in the mode setting case. */
1275         /* FIXME: do pre/post-mode set stuff in core KMS code */
1276         dev->vblank_disable_allowed = 1;
1277
1278         ret = intel_fbdev_init(dev);
1279         if (ret)
1280                 goto cleanup_irq;
1281
1282         drm_kms_helper_poll_init(dev);
1283
1284         /* We're off and running w/KMS */
1285         dev_priv->mm.suspended = 0;
1286
1287         return 0;
1288
1289 cleanup_irq:
1290         drm_irq_uninstall(dev);
1291 cleanup_gem:
1292         mutex_lock(&dev->struct_mutex);
1293         i915_gem_cleanup_ringbuffer(dev);
1294         mutex_unlock(&dev->struct_mutex);
1295 cleanup_vga_switcheroo:
1296         vga_switcheroo_unregister_client(dev->pdev);
1297 cleanup_vga_client:
1298         vga_client_register(dev->pdev, NULL, NULL, NULL);
1299 out:
1300         return ret;
1301 }
1302
1303 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1304 {
1305         struct drm_i915_master_private *master_priv;
1306
1307         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1308         if (!master_priv)
1309                 return -ENOMEM;
1310
1311         master->driver_priv = master_priv;
1312         return 0;
1313 }
1314
1315 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1316 {
1317         struct drm_i915_master_private *master_priv = master->driver_priv;
1318
1319         if (!master_priv)
1320                 return;
1321
1322         kfree(master_priv);
1323
1324         master->driver_priv = NULL;
1325 }
1326
1327 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1328 {
1329         drm_i915_private_t *dev_priv = dev->dev_private;
1330         u32 tmp;
1331
1332         tmp = I915_READ(CLKCFG);
1333
1334         switch (tmp & CLKCFG_FSB_MASK) {
1335         case CLKCFG_FSB_533:
1336                 dev_priv->fsb_freq = 533; /* 133*4 */
1337                 break;
1338         case CLKCFG_FSB_800:
1339                 dev_priv->fsb_freq = 800; /* 200*4 */
1340                 break;
1341         case CLKCFG_FSB_667:
1342                 dev_priv->fsb_freq =  667; /* 167*4 */
1343                 break;
1344         case CLKCFG_FSB_400:
1345                 dev_priv->fsb_freq = 400; /* 100*4 */
1346                 break;
1347         }
1348
1349         switch (tmp & CLKCFG_MEM_MASK) {
1350         case CLKCFG_MEM_533:
1351                 dev_priv->mem_freq = 533;
1352                 break;
1353         case CLKCFG_MEM_667:
1354                 dev_priv->mem_freq = 667;
1355                 break;
1356         case CLKCFG_MEM_800:
1357                 dev_priv->mem_freq = 800;
1358                 break;
1359         }
1360
1361         /* detect pineview DDR3 setting */
1362         tmp = I915_READ(CSHRDDR3CTL);
1363         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1364 }
1365
1366 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1367 {
1368         drm_i915_private_t *dev_priv = dev->dev_private;
1369         u16 ddrpll, csipll;
1370
1371         ddrpll = I915_READ16(DDRMPLL1);
1372         csipll = I915_READ16(CSIPLL0);
1373
1374         switch (ddrpll & 0xff) {
1375         case 0xc:
1376                 dev_priv->mem_freq = 800;
1377                 break;
1378         case 0x10:
1379                 dev_priv->mem_freq = 1066;
1380                 break;
1381         case 0x14:
1382                 dev_priv->mem_freq = 1333;
1383                 break;
1384         case 0x18:
1385                 dev_priv->mem_freq = 1600;
1386                 break;
1387         default:
1388                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1389                                  ddrpll & 0xff);
1390                 dev_priv->mem_freq = 0;
1391                 break;
1392         }
1393
1394         dev_priv->r_t = dev_priv->mem_freq;
1395
1396         switch (csipll & 0x3ff) {
1397         case 0x00c:
1398                 dev_priv->fsb_freq = 3200;
1399                 break;
1400         case 0x00e:
1401                 dev_priv->fsb_freq = 3733;
1402                 break;
1403         case 0x010:
1404                 dev_priv->fsb_freq = 4266;
1405                 break;
1406         case 0x012:
1407                 dev_priv->fsb_freq = 4800;
1408                 break;
1409         case 0x014:
1410                 dev_priv->fsb_freq = 5333;
1411                 break;
1412         case 0x016:
1413                 dev_priv->fsb_freq = 5866;
1414                 break;
1415         case 0x018:
1416                 dev_priv->fsb_freq = 6400;
1417                 break;
1418         default:
1419                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1420                                  csipll & 0x3ff);
1421                 dev_priv->fsb_freq = 0;
1422                 break;
1423         }
1424
1425         if (dev_priv->fsb_freq == 3200) {
1426                 dev_priv->c_m = 0;
1427         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1428                 dev_priv->c_m = 1;
1429         } else {
1430                 dev_priv->c_m = 2;
1431         }
1432 }
1433
1434 static const struct cparams {
1435         u16 i;
1436         u16 t;
1437         u16 m;
1438         u16 c;
1439 } cparams[] = {
1440         { 1, 1333, 301, 28664 },
1441         { 1, 1066, 294, 24460 },
1442         { 1, 800, 294, 25192 },
1443         { 0, 1333, 276, 27605 },
1444         { 0, 1066, 276, 27605 },
1445         { 0, 800, 231, 23784 },
1446 };
1447
1448 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1449 {
1450         u64 total_count, diff, ret;
1451         u32 count1, count2, count3, m = 0, c = 0;
1452         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1453         int i;
1454
1455         diff1 = now - dev_priv->last_time1;
1456
1457         count1 = I915_READ(DMIEC);
1458         count2 = I915_READ(DDREC);
1459         count3 = I915_READ(CSIEC);
1460
1461         total_count = count1 + count2 + count3;
1462
1463         /* FIXME: handle per-counter overflow */
1464         if (total_count < dev_priv->last_count1) {
1465                 diff = ~0UL - dev_priv->last_count1;
1466                 diff += total_count;
1467         } else {
1468                 diff = total_count - dev_priv->last_count1;
1469         }
1470
1471         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1472                 if (cparams[i].i == dev_priv->c_m &&
1473                     cparams[i].t == dev_priv->r_t) {
1474                         m = cparams[i].m;
1475                         c = cparams[i].c;
1476                         break;
1477                 }
1478         }
1479
1480         diff = div_u64(diff, diff1);
1481         ret = ((m * diff) + c);
1482         ret = div_u64(ret, 10);
1483
1484         dev_priv->last_count1 = total_count;
1485         dev_priv->last_time1 = now;
1486
1487         return ret;
1488 }
1489
1490 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1491 {
1492         unsigned long m, x, b;
1493         u32 tsfs;
1494
1495         tsfs = I915_READ(TSFS);
1496
1497         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1498         x = I915_READ8(TR1);
1499
1500         b = tsfs & TSFS_INTR_MASK;
1501
1502         return ((m * x) / 127) - b;
1503 }
1504
1505 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1506 {
1507         static const struct v_table {
1508                 u16 vd; /* in .1 mil */
1509                 u16 vm; /* in .1 mil */
1510         } v_table[] = {
1511                 { 0, 0, },
1512                 { 375, 0, },
1513                 { 500, 0, },
1514                 { 625, 0, },
1515                 { 750, 0, },
1516                 { 875, 0, },
1517                 { 1000, 0, },
1518                 { 1125, 0, },
1519                 { 4125, 3000, },
1520                 { 4125, 3000, },
1521                 { 4125, 3000, },
1522                 { 4125, 3000, },
1523                 { 4125, 3000, },
1524                 { 4125, 3000, },
1525                 { 4125, 3000, },
1526                 { 4125, 3000, },
1527                 { 4125, 3000, },
1528                 { 4125, 3000, },
1529                 { 4125, 3000, },
1530                 { 4125, 3000, },
1531                 { 4125, 3000, },
1532                 { 4125, 3000, },
1533                 { 4125, 3000, },
1534                 { 4125, 3000, },
1535                 { 4125, 3000, },
1536                 { 4125, 3000, },
1537                 { 4125, 3000, },
1538                 { 4125, 3000, },
1539                 { 4125, 3000, },
1540                 { 4125, 3000, },
1541                 { 4125, 3000, },
1542                 { 4125, 3000, },
1543                 { 4250, 3125, },
1544                 { 4375, 3250, },
1545                 { 4500, 3375, },
1546                 { 4625, 3500, },
1547                 { 4750, 3625, },
1548                 { 4875, 3750, },
1549                 { 5000, 3875, },
1550                 { 5125, 4000, },
1551                 { 5250, 4125, },
1552                 { 5375, 4250, },
1553                 { 5500, 4375, },
1554                 { 5625, 4500, },
1555                 { 5750, 4625, },
1556                 { 5875, 4750, },
1557                 { 6000, 4875, },
1558                 { 6125, 5000, },
1559                 { 6250, 5125, },
1560                 { 6375, 5250, },
1561                 { 6500, 5375, },
1562                 { 6625, 5500, },
1563                 { 6750, 5625, },
1564                 { 6875, 5750, },
1565                 { 7000, 5875, },
1566                 { 7125, 6000, },
1567                 { 7250, 6125, },
1568                 { 7375, 6250, },
1569                 { 7500, 6375, },
1570                 { 7625, 6500, },
1571                 { 7750, 6625, },
1572                 { 7875, 6750, },
1573                 { 8000, 6875, },
1574                 { 8125, 7000, },
1575                 { 8250, 7125, },
1576                 { 8375, 7250, },
1577                 { 8500, 7375, },
1578                 { 8625, 7500, },
1579                 { 8750, 7625, },
1580                 { 8875, 7750, },
1581                 { 9000, 7875, },
1582                 { 9125, 8000, },
1583                 { 9250, 8125, },
1584                 { 9375, 8250, },
1585                 { 9500, 8375, },
1586                 { 9625, 8500, },
1587                 { 9750, 8625, },
1588                 { 9875, 8750, },
1589                 { 10000, 8875, },
1590                 { 10125, 9000, },
1591                 { 10250, 9125, },
1592                 { 10375, 9250, },
1593                 { 10500, 9375, },
1594                 { 10625, 9500, },
1595                 { 10750, 9625, },
1596                 { 10875, 9750, },
1597                 { 11000, 9875, },
1598                 { 11125, 10000, },
1599                 { 11250, 10125, },
1600                 { 11375, 10250, },
1601                 { 11500, 10375, },
1602                 { 11625, 10500, },
1603                 { 11750, 10625, },
1604                 { 11875, 10750, },
1605                 { 12000, 10875, },
1606                 { 12125, 11000, },
1607                 { 12250, 11125, },
1608                 { 12375, 11250, },
1609                 { 12500, 11375, },
1610                 { 12625, 11500, },
1611                 { 12750, 11625, },
1612                 { 12875, 11750, },
1613                 { 13000, 11875, },
1614                 { 13125, 12000, },
1615                 { 13250, 12125, },
1616                 { 13375, 12250, },
1617                 { 13500, 12375, },
1618                 { 13625, 12500, },
1619                 { 13750, 12625, },
1620                 { 13875, 12750, },
1621                 { 14000, 12875, },
1622                 { 14125, 13000, },
1623                 { 14250, 13125, },
1624                 { 14375, 13250, },
1625                 { 14500, 13375, },
1626                 { 14625, 13500, },
1627                 { 14750, 13625, },
1628                 { 14875, 13750, },
1629                 { 15000, 13875, },
1630                 { 15125, 14000, },
1631                 { 15250, 14125, },
1632                 { 15375, 14250, },
1633                 { 15500, 14375, },
1634                 { 15625, 14500, },
1635                 { 15750, 14625, },
1636                 { 15875, 14750, },
1637                 { 16000, 14875, },
1638                 { 16125, 15000, },
1639         };
1640         if (dev_priv->info->is_mobile)
1641                 return v_table[pxvid].vm;
1642         else
1643                 return v_table[pxvid].vd;
1644 }
1645
1646 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1647 {
1648         struct timespec now, diff1;
1649         u64 diff;
1650         unsigned long diffms;
1651         u32 count;
1652
1653         getrawmonotonic(&now);
1654         diff1 = timespec_sub(now, dev_priv->last_time2);
1655
1656         /* Don't divide by 0 */
1657         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1658         if (!diffms)
1659                 return;
1660
1661         count = I915_READ(GFXEC);
1662
1663         if (count < dev_priv->last_count2) {
1664                 diff = ~0UL - dev_priv->last_count2;
1665                 diff += count;
1666         } else {
1667                 diff = count - dev_priv->last_count2;
1668         }
1669
1670         dev_priv->last_count2 = count;
1671         dev_priv->last_time2 = now;
1672
1673         /* More magic constants... */
1674         diff = diff * 1181;
1675         diff = div_u64(diff, diffms * 10);
1676         dev_priv->gfx_power = diff;
1677 }
1678
1679 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1680 {
1681         unsigned long t, corr, state1, corr2, state2;
1682         u32 pxvid, ext_v;
1683
1684         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1685         pxvid = (pxvid >> 24) & 0x7f;
1686         ext_v = pvid_to_extvid(dev_priv, pxvid);
1687
1688         state1 = ext_v;
1689
1690         t = i915_mch_val(dev_priv);
1691
1692         /* Revel in the empirically derived constants */
1693
1694         /* Correction factor in 1/100000 units */
1695         if (t > 80)
1696                 corr = ((t * 2349) + 135940);
1697         else if (t >= 50)
1698                 corr = ((t * 964) + 29317);
1699         else /* < 50 */
1700                 corr = ((t * 301) + 1004);
1701
1702         corr = corr * ((150142 * state1) / 10000 - 78642);
1703         corr /= 100000;
1704         corr2 = (corr * dev_priv->corr);
1705
1706         state2 = (corr2 * state1) / 10000;
1707         state2 /= 100; /* convert to mW */
1708
1709         i915_update_gfx_val(dev_priv);
1710
1711         return dev_priv->gfx_power + state2;
1712 }
1713
1714 /* Global for IPS driver to get at the current i915 device */
1715 static struct drm_i915_private *i915_mch_dev;
1716 /*
1717  * Lock protecting IPS related data structures
1718  *   - i915_mch_dev
1719  *   - dev_priv->max_delay
1720  *   - dev_priv->min_delay
1721  *   - dev_priv->fmax
1722  *   - dev_priv->gpu_busy
1723  */
1724 static DEFINE_SPINLOCK(mchdev_lock);
1725
1726 /**
1727  * i915_read_mch_val - return value for IPS use
1728  *
1729  * Calculate and return a value for the IPS driver to use when deciding whether
1730  * we have thermal and power headroom to increase CPU or GPU power budget.
1731  */
1732 unsigned long i915_read_mch_val(void)
1733 {
1734         struct drm_i915_private *dev_priv;
1735         unsigned long chipset_val, graphics_val, ret = 0;
1736
1737         spin_lock(&mchdev_lock);
1738         if (!i915_mch_dev)
1739                 goto out_unlock;
1740         dev_priv = i915_mch_dev;
1741
1742         chipset_val = i915_chipset_val(dev_priv);
1743         graphics_val = i915_gfx_val(dev_priv);
1744
1745         ret = chipset_val + graphics_val;
1746
1747 out_unlock:
1748         spin_unlock(&mchdev_lock);
1749
1750         return ret;
1751 }
1752 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1753
1754 /**
1755  * i915_gpu_raise - raise GPU frequency limit
1756  *
1757  * Raise the limit; IPS indicates we have thermal headroom.
1758  */
1759 bool i915_gpu_raise(void)
1760 {
1761         struct drm_i915_private *dev_priv;
1762         bool ret = true;
1763
1764         spin_lock(&mchdev_lock);
1765         if (!i915_mch_dev) {
1766                 ret = false;
1767                 goto out_unlock;
1768         }
1769         dev_priv = i915_mch_dev;
1770
1771         if (dev_priv->max_delay > dev_priv->fmax)
1772                 dev_priv->max_delay--;
1773
1774 out_unlock:
1775         spin_unlock(&mchdev_lock);
1776
1777         return ret;
1778 }
1779 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1780
1781 /**
1782  * i915_gpu_lower - lower GPU frequency limit
1783  *
1784  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1785  * frequency maximum.
1786  */
1787 bool i915_gpu_lower(void)
1788 {
1789         struct drm_i915_private *dev_priv;
1790         bool ret = true;
1791
1792         spin_lock(&mchdev_lock);
1793         if (!i915_mch_dev) {
1794                 ret = false;
1795                 goto out_unlock;
1796         }
1797         dev_priv = i915_mch_dev;
1798
1799         if (dev_priv->max_delay < dev_priv->min_delay)
1800                 dev_priv->max_delay++;
1801
1802 out_unlock:
1803         spin_unlock(&mchdev_lock);
1804
1805         return ret;
1806 }
1807 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1808
1809 /**
1810  * i915_gpu_busy - indicate GPU business to IPS
1811  *
1812  * Tell the IPS driver whether or not the GPU is busy.
1813  */
1814 bool i915_gpu_busy(void)
1815 {
1816         struct drm_i915_private *dev_priv;
1817         bool ret = false;
1818
1819         spin_lock(&mchdev_lock);
1820         if (!i915_mch_dev)
1821                 goto out_unlock;
1822         dev_priv = i915_mch_dev;
1823
1824         ret = dev_priv->busy;
1825
1826 out_unlock:
1827         spin_unlock(&mchdev_lock);
1828
1829         return ret;
1830 }
1831 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1832
1833 /**
1834  * i915_gpu_turbo_disable - disable graphics turbo
1835  *
1836  * Disable graphics turbo by resetting the max frequency and setting the
1837  * current frequency to the default.
1838  */
1839 bool i915_gpu_turbo_disable(void)
1840 {
1841         struct drm_i915_private *dev_priv;
1842         bool ret = true;
1843
1844         spin_lock(&mchdev_lock);
1845         if (!i915_mch_dev) {
1846                 ret = false;
1847                 goto out_unlock;
1848         }
1849         dev_priv = i915_mch_dev;
1850
1851         dev_priv->max_delay = dev_priv->fstart;
1852
1853         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1854                 ret = false;
1855
1856 out_unlock:
1857         spin_unlock(&mchdev_lock);
1858
1859         return ret;
1860 }
1861 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1862
1863 /**
1864  * Tells the intel_ips driver that the i915 driver is now loaded, if
1865  * IPS got loaded first.
1866  *
1867  * This awkward dance is so that neither module has to depend on the
1868  * other in order for IPS to do the appropriate communication of
1869  * GPU turbo limits to i915.
1870  */
1871 static void
1872 ips_ping_for_i915_load(void)
1873 {
1874         void (*link)(void);
1875
1876         link = symbol_get(ips_link_to_i915_driver);
1877         if (link) {
1878                 link();
1879                 symbol_put(ips_link_to_i915_driver);
1880         }
1881 }
1882
1883 /**
1884  * i915_driver_load - setup chip and create an initial config
1885  * @dev: DRM device
1886  * @flags: startup flags
1887  *
1888  * The driver load routine has to do several things:
1889  *   - drive output discovery via intel_modeset_init()
1890  *   - initialize the memory manager
1891  *   - allocate initial config memory
1892  *   - setup the DRM framebuffer with the allocated memory
1893  */
1894 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1895 {
1896         struct drm_i915_private *dev_priv;
1897         int ret = 0, mmio_bar;
1898         uint32_t agp_size;
1899
1900         /* i915 has 4 more counters */
1901         dev->counters += 4;
1902         dev->types[6] = _DRM_STAT_IRQ;
1903         dev->types[7] = _DRM_STAT_PRIMARY;
1904         dev->types[8] = _DRM_STAT_SECONDARY;
1905         dev->types[9] = _DRM_STAT_DMA;
1906
1907         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1908         if (dev_priv == NULL)
1909                 return -ENOMEM;
1910
1911         dev->dev_private = (void *)dev_priv;
1912         dev_priv->dev = dev;
1913         dev_priv->info = (struct intel_device_info *) flags;
1914
1915         if (i915_get_bridge_dev(dev)) {
1916                 ret = -EIO;
1917                 goto free_priv;
1918         }
1919
1920         /* overlay on gen2 is broken and can't address above 1G */
1921         if (IS_GEN2(dev))
1922                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1923
1924         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1925          * using 32bit addressing, overwriting memory if HWS is located
1926          * above 4GB.
1927          *
1928          * The documentation also mentions an issue with undefined
1929          * behaviour if any general state is accessed within a page above 4GB,
1930          * which also needs to be handled carefully.
1931          */
1932         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1933                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1934
1935         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1936         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1937         if (!dev_priv->regs) {
1938                 DRM_ERROR("failed to map registers\n");
1939                 ret = -EIO;
1940                 goto put_bridge;
1941         }
1942
1943         dev_priv->mm.gtt = intel_gtt_get();
1944         if (!dev_priv->mm.gtt) {
1945                 DRM_ERROR("Failed to initialize GTT\n");
1946                 ret = -ENODEV;
1947                 goto out_rmmap;
1948         }
1949
1950         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1951
1952         dev_priv->mm.gtt_mapping =
1953                 io_mapping_create_wc(dev->agp->base, agp_size);
1954         if (dev_priv->mm.gtt_mapping == NULL) {
1955                 ret = -EIO;
1956                 goto out_rmmap;
1957         }
1958
1959         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1960          * one would think, because the kernel disables PAT on first
1961          * generation Core chips because WC PAT gets overridden by a UC
1962          * MTRR if present.  Even if a UC MTRR isn't present.
1963          */
1964         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1965                                          agp_size,
1966                                          MTRR_TYPE_WRCOMB, 1);
1967         if (dev_priv->mm.gtt_mtrr < 0) {
1968                 DRM_INFO("MTRR allocation failed.  Graphics "
1969                          "performance may suffer.\n");
1970         }
1971
1972         /* The i915 workqueue is primarily used for batched retirement of
1973          * requests (and thus managing bo) once the task has been completed
1974          * by the GPU. i915_gem_retire_requests() is called directly when we
1975          * need high-priority retirement, such as waiting for an explicit
1976          * bo.
1977          *
1978          * It is also used for periodic low-priority events, such as
1979          * idle-timers and recording error state.
1980          *
1981          * All tasks on the workqueue are expected to acquire the dev mutex
1982          * so there is no point in running more than one instance of the
1983          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1984          */
1985         dev_priv->wq = alloc_workqueue("i915",
1986                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1987                                        1);
1988         if (dev_priv->wq == NULL) {
1989                 DRM_ERROR("Failed to create our workqueue.\n");
1990                 ret = -ENOMEM;
1991                 goto out_mtrrfree;
1992         }
1993
1994         /* enable GEM by default */
1995         dev_priv->has_gem = 1;
1996
1997         intel_irq_init(dev);
1998
1999         /* Try to make sure MCHBAR is enabled before poking at it */
2000         intel_setup_mchbar(dev);
2001         intel_setup_gmbus(dev);
2002         intel_opregion_setup(dev);
2003
2004         /* Make sure the bios did its job and set up vital registers */
2005         intel_setup_bios(dev);
2006
2007         i915_gem_load(dev);
2008
2009         /* Init HWS */
2010         if (!I915_NEED_GFX_HWS(dev)) {
2011                 ret = i915_init_phys_hws(dev);
2012                 if (ret)
2013                         goto out_gem_unload;
2014         }
2015
2016         if (IS_PINEVIEW(dev))
2017                 i915_pineview_get_mem_freq(dev);
2018         else if (IS_GEN5(dev))
2019                 i915_ironlake_get_mem_freq(dev);
2020
2021         /* On the 945G/GM, the chipset reports the MSI capability on the
2022          * integrated graphics even though the support isn't actually there
2023          * according to the published specs.  It doesn't appear to function
2024          * correctly in testing on 945G.
2025          * This may be a side effect of MSI having been made available for PEG
2026          * and the registers being closely associated.
2027          *
2028          * According to chipset errata, on the 965GM, MSI interrupts may
2029          * be lost or delayed, but we use them anyways to avoid
2030          * stuck interrupts on some machines.
2031          */
2032         if (!IS_I945G(dev) && !IS_I945GM(dev))
2033                 pci_enable_msi(dev->pdev);
2034
2035         spin_lock_init(&dev_priv->irq_lock);
2036         spin_lock_init(&dev_priv->error_lock);
2037         spin_lock_init(&dev_priv->rps_lock);
2038
2039         if (IS_IVYBRIDGE(dev))
2040                 dev_priv->num_pipe = 3;
2041         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
2042                 dev_priv->num_pipe = 2;
2043         else
2044                 dev_priv->num_pipe = 1;
2045
2046         ret = drm_vblank_init(dev, dev_priv->num_pipe);
2047         if (ret)
2048                 goto out_gem_unload;
2049
2050         /* Start out suspended */
2051         dev_priv->mm.suspended = 1;
2052
2053         intel_detect_pch(dev);
2054
2055         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2056                 ret = i915_load_modeset_init(dev);
2057                 if (ret < 0) {
2058                         DRM_ERROR("failed to init modeset\n");
2059                         goto out_gem_unload;
2060                 }
2061         }
2062
2063         /* Must be done after probing outputs */
2064         intel_opregion_init(dev);
2065         acpi_video_register();
2066
2067         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2068                     (unsigned long) dev);
2069
2070         spin_lock(&mchdev_lock);
2071         i915_mch_dev = dev_priv;
2072         dev_priv->mchdev_lock = &mchdev_lock;
2073         spin_unlock(&mchdev_lock);
2074
2075         ips_ping_for_i915_load();
2076
2077         return 0;
2078
2079 out_gem_unload:
2080         if (dev_priv->mm.inactive_shrinker.shrink)
2081                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2082
2083         if (dev->pdev->msi_enabled)
2084                 pci_disable_msi(dev->pdev);
2085
2086         intel_teardown_gmbus(dev);
2087         intel_teardown_mchbar(dev);
2088         destroy_workqueue(dev_priv->wq);
2089 out_mtrrfree:
2090         if (dev_priv->mm.gtt_mtrr >= 0) {
2091                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2092                          dev->agp->agp_info.aper_size * 1024 * 1024);
2093                 dev_priv->mm.gtt_mtrr = -1;
2094         }
2095         io_mapping_free(dev_priv->mm.gtt_mapping);
2096 out_rmmap:
2097         pci_iounmap(dev->pdev, dev_priv->regs);
2098 put_bridge:
2099         pci_dev_put(dev_priv->bridge_dev);
2100 free_priv:
2101         kfree(dev_priv);
2102         return ret;
2103 }
2104
2105 int i915_driver_unload(struct drm_device *dev)
2106 {
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         int ret;
2109
2110         spin_lock(&mchdev_lock);
2111         i915_mch_dev = NULL;
2112         spin_unlock(&mchdev_lock);
2113
2114         if (dev_priv->mm.inactive_shrinker.shrink)
2115                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2116
2117         mutex_lock(&dev->struct_mutex);
2118         ret = i915_gpu_idle(dev);
2119         if (ret)
2120                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2121         mutex_unlock(&dev->struct_mutex);
2122
2123         /* Cancel the retire work handler, which should be idle now. */
2124         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2125
2126         io_mapping_free(dev_priv->mm.gtt_mapping);
2127         if (dev_priv->mm.gtt_mtrr >= 0) {
2128                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2129                          dev->agp->agp_info.aper_size * 1024 * 1024);
2130                 dev_priv->mm.gtt_mtrr = -1;
2131         }
2132
2133         acpi_video_unregister();
2134
2135         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2136                 intel_fbdev_fini(dev);
2137                 intel_modeset_cleanup(dev);
2138
2139                 /*
2140                  * free the memory space allocated for the child device
2141                  * config parsed from VBT
2142                  */
2143                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2144                         kfree(dev_priv->child_dev);
2145                         dev_priv->child_dev = NULL;
2146                         dev_priv->child_dev_num = 0;
2147                 }
2148
2149                 vga_switcheroo_unregister_client(dev->pdev);
2150                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2151         }
2152
2153         /* Free error state after interrupts are fully disabled. */
2154         del_timer_sync(&dev_priv->hangcheck_timer);
2155         cancel_work_sync(&dev_priv->error_work);
2156         i915_destroy_error_state(dev);
2157
2158         if (dev->pdev->msi_enabled)
2159                 pci_disable_msi(dev->pdev);
2160
2161         intel_opregion_fini(dev);
2162
2163         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2164                 /* Flush any outstanding unpin_work. */
2165                 flush_workqueue(dev_priv->wq);
2166
2167                 mutex_lock(&dev->struct_mutex);
2168                 i915_gem_free_all_phys_object(dev);
2169                 i915_gem_cleanup_ringbuffer(dev);
2170                 mutex_unlock(&dev->struct_mutex);
2171                 if (I915_HAS_FBC(dev) && i915_powersave)
2172                         i915_cleanup_compression(dev);
2173                 drm_mm_takedown(&dev_priv->mm.stolen);
2174
2175                 intel_cleanup_overlay(dev);
2176
2177                 if (!I915_NEED_GFX_HWS(dev))
2178                         i915_free_hws(dev);
2179         }
2180
2181         if (dev_priv->regs != NULL)
2182                 pci_iounmap(dev->pdev, dev_priv->regs);
2183
2184         intel_teardown_gmbus(dev);
2185         intel_teardown_mchbar(dev);
2186
2187         destroy_workqueue(dev_priv->wq);
2188
2189         pci_dev_put(dev_priv->bridge_dev);
2190         kfree(dev->dev_private);
2191
2192         return 0;
2193 }
2194
2195 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2196 {
2197         struct drm_i915_file_private *file_priv;
2198
2199         DRM_DEBUG_DRIVER("\n");
2200         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2201         if (!file_priv)
2202                 return -ENOMEM;
2203
2204         file->driver_priv = file_priv;
2205
2206         spin_lock_init(&file_priv->mm.lock);
2207         INIT_LIST_HEAD(&file_priv->mm.request_list);
2208
2209         return 0;
2210 }
2211
2212 /**
2213  * i915_driver_lastclose - clean up after all DRM clients have exited
2214  * @dev: DRM device
2215  *
2216  * Take care of cleaning up after all DRM clients have exited.  In the
2217  * mode setting case, we want to restore the kernel's initial mode (just
2218  * in case the last client left us in a bad state).
2219  *
2220  * Additionally, in the non-mode setting case, we'll tear down the AGP
2221  * and DMA structures, since the kernel won't be using them, and clea
2222  * up any GEM state.
2223  */
2224 void i915_driver_lastclose(struct drm_device * dev)
2225 {
2226         drm_i915_private_t *dev_priv = dev->dev_private;
2227
2228         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2229                 intel_fb_restore_mode(dev);
2230                 vga_switcheroo_process_delayed_switch();
2231                 return;
2232         }
2233
2234         i915_gem_lastclose(dev);
2235
2236         if (dev_priv->agp_heap)
2237                 i915_mem_takedown(&(dev_priv->agp_heap));
2238
2239         i915_dma_cleanup(dev);
2240 }
2241
2242 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2243 {
2244         drm_i915_private_t *dev_priv = dev->dev_private;
2245         i915_gem_release(dev, file_priv);
2246         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2247                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2248 }
2249
2250 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2251 {
2252         struct drm_i915_file_private *file_priv = file->driver_priv;
2253
2254         kfree(file_priv);
2255 }
2256
2257 struct drm_ioctl_desc i915_ioctls[] = {
2258         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2259         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2260         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2261         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2262         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2263         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2264         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2265         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2266         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2267         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2268         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2269         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2270         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2271         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2272         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2273         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2274         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2275         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2276         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2277         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2278         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2279         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2280         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2281         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2282         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2283         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2284         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2285         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2286         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2287         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2288         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2289         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2290         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2291         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2292         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2293         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2294         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2295         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2296         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2297         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2298 };
2299
2300 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2301
2302 /**
2303  * Determine if the device really is AGP or not.
2304  *
2305  * All Intel graphics chipsets are treated as AGP, even if they are really
2306  * PCI-e.
2307  *
2308  * \param dev   The device to be tested.
2309  *
2310  * \returns
2311  * A value of 1 is always retured to indictate every i9x5 is AGP.
2312  */
2313 int i915_driver_device_is_agp(struct drm_device * dev)
2314 {
2315         return 1;
2316 }