drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21
  22 #include <drm/drm_of.h>
  23 #include <drm/drmP.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_edid.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/bridge/dw_hdmi.h>
  28
  29 #include "dw_hdmi.h"
  30
  31 #define HDMI_EDID_LEN           512
  32
  33 #define RGB                     0
  34 #define YCBCR444                1
  35 #define YCBCR422_16BITS         2
  36 #define YCBCR422_8BITS          3
  37 #define XVYCC444                4
  38
  39 enum hdmi_datamap {
  40         RGB444_8B = 0x01,
  41         RGB444_10B = 0x03,
  42         RGB444_12B = 0x05,
  43         RGB444_16B = 0x07,
  44         YCbCr444_8B = 0x09,
  45         YCbCr444_10B = 0x0B,
  46         YCbCr444_12B = 0x0D,
  47         YCbCr444_16B = 0x0F,
  48         YCbCr422_8B = 0x16,
  49         YCbCr422_10B = 0x14,
  50         YCbCr422_12B = 0x12,
  51 };
  52
  53 static const u16 csc_coeff_default[3][4] = {
  54         { 0x2000, 0x0000, 0x0000, 0x0000 },
  55         { 0x0000, 0x2000, 0x0000, 0x0000 },
  56         { 0x0000, 0x0000, 0x2000, 0x0000 }
  57 };
  58
  59 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  60         { 0x2000, 0x6926, 0x74fd, 0x010e },
  61         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  62         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  63 };
  64
  65 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  66         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  67         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  68         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  69 };
  70
  71 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  72         { 0x2591, 0x1322, 0x074b, 0x0000 },
  73         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  74         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  75 };
  76
  77 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  78         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  79         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  80         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  81 };
  82
  83 struct hdmi_vmode {
  84         bool mdvi;
  85         bool mdataenablepolarity;
  86
  87         unsigned int mpixelclock;
  88         unsigned int mpixelrepetitioninput;
  89         unsigned int mpixelrepetitionoutput;
  90 };
  91
  92 struct hdmi_data_info {
  93         unsigned int enc_in_format;
  94         unsigned int enc_out_format;
  95         unsigned int enc_color_depth;
  96         unsigned int colorimetry;
  97         unsigned int pix_repet_factor;
  98         unsigned int hdcp_enable;
  99         struct hdmi_vmode video_mode;
 100 };
 101
 102 struct dw_hdmi {
 103         struct drm_connector connector;
 104         struct drm_encoder *encoder;
 105         struct drm_bridge *bridge;
 106
 107         enum dw_hdmi_devtype dev_type;
 108         struct device *dev;
 109         struct clk *isfr_clk;
 110         struct clk *iahb_clk;
 111
 112         struct hdmi_data_info hdmi_data;
 113         const struct dw_hdmi_plat_data *plat_data;
 114
 115         int vic;
 116
 117         u8 edid[HDMI_EDID_LEN];
 118         bool cable_plugin;
 119
 120         bool phy_enabled;
 121         struct drm_display_mode previous_mode;
 122
 123         struct i2c_adapter *ddc;
 124         void __iomem *regs;
 125
 126         struct mutex audio_mutex;
 127         unsigned int sample_rate;
 128         int ratio;
 129
 130         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 131         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 132 };
 133
 134 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 135 {
 136         writel(val, hdmi->regs + (offset << 2));
 137 }
 138
 139 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 140 {
 141         return readl(hdmi->regs + (offset << 2));
 142 }
 143
 144 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 145 {
 146         writeb(val, hdmi->regs + offset);
 147 }
 148
 149 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 150 {
 151         return readb(hdmi->regs + offset);
 152 }
 153
 154 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 155 {
 156         hdmi->write(hdmi, val, offset);
 157 }
 158
 159 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 160 {
 161         return hdmi->read(hdmi, offset);
 162 }
 163
 164 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 165 {
 166         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 167
 168         val |= data & mask;
 169         hdmi_writeb(hdmi, val, reg);
 170 }
 171
 172 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 173                              u8 shift, u8 mask)
 174 {
 175         hdmi_modb(hdmi, data << shift, mask, reg);
 176 }
 177
 178 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 179                            unsigned int n)
 180 {
 181         /* Must be set/cleared first */
 182         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 183
 184         /* nshift factor = 0 */
 185         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 186
 187         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 188                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 189         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 190         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 191
 192         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 193         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 194         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 195 }
 196
 197 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 198                                    unsigned int ratio)
 199 {
 200         unsigned int n = (128 * freq) / 1000;
 201
 202         switch (freq) {
 203         case 32000:
 204                 if (pixel_clk == 25170000)
 205                         n = (ratio == 150) ? 9152 : 4576;
 206                 else if (pixel_clk == 27020000)
 207                         n = (ratio == 150) ? 8192 : 4096;
 208                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 209                         n = 11648;
 210                 else
 211                         n = 4096;
 212                 break;
 213
 214         case 44100:
 215                 if (pixel_clk == 25170000)
 216                         n = 7007;
 217                 else if (pixel_clk == 74170000)
 218                         n = 17836;
 219                 else if (pixel_clk == 148350000)
 220                         n = (ratio == 150) ? 17836 : 8918;
 221                 else
 222                         n = 6272;
 223                 break;
 224
 225         case 48000:
 226                 if (pixel_clk == 25170000)
 227                         n = (ratio == 150) ? 9152 : 6864;
 228                 else if (pixel_clk == 27020000)
 229                         n = (ratio == 150) ? 8192 : 6144;
 230                 else if (pixel_clk == 74170000)
 231                         n = 11648;
 232                 else if (pixel_clk == 148350000)
 233                         n = (ratio == 150) ? 11648 : 5824;
 234                 else
 235                         n = 6144;
 236                 break;
 237
 238         case 88200:
 239                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 240                 break;
 241
 242         case 96000:
 243                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 244                 break;
 245
 246         case 176400:
 247                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 248                 break;
 249
 250         case 192000:
 251                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 252                 break;
 253
 254         default:
 255                 break;
 256         }
 257
 258         return n;
 259 }
 260
 261 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 262                                      unsigned int ratio)
 263 {
 264         unsigned int cts = 0;
 265
 266         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 267                  pixel_clk, ratio);
 268
 269         switch (freq) {
 270         case 32000:
 271                 if (pixel_clk == 297000000) {
 272                         cts = 222750;
 273                         break;
 274                 }
 275         case 48000:
 276         case 96000:
 277         case 192000:
 278                 switch (pixel_clk) {
 279                 case 25200000:
 280                 case 27000000:
 281                 case 54000000:
 282                 case 74250000:
 283                 case 148500000:
 284                         cts = pixel_clk / 1000;
 285                         break;
 286                 case 297000000:
 287                         cts = 247500;
 288                         break;
 289                 /*
 290                  * All other TMDS clocks are not supported by
 291                  * DWC_hdmi_tx. The TMDS clocks divided or
 292                  * multiplied by 1,001 coefficients are not
 293                  * supported.
 294                  */
 295                 default:
 296                         break;
 297                 }
 298                 break;
 299         case 44100:
 300         case 88200:
 301         case 176400:
 302                 switch (pixel_clk) {
 303                 case 25200000:
 304                         cts = 28000;
 305                         break;
 306                 case 27000000:
 307                         cts = 30000;
 308                         break;
 309                 case 54000000:
 310                         cts = 60000;
 311                         break;
 312                 case 74250000:
 313                         cts = 82500;
 314                         break;
 315                 case 148500000:
 316                         cts = 165000;
 317                         break;
 318                 case 297000000:
 319                         cts = 247500;
 320                         break;
 321                 default:
 322                         break;
 323                 }
 324                 break;
 325         default:
 326                 break;
 327         }
 328         if (ratio == 100)
 329                 return cts;
 330         return (cts * ratio) / 100;
 331 }
 332
 333 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 334         unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
 335 {
 336         unsigned int n, cts;
 337
 338         n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
 339         cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
 340         if (!cts) {
 341                 dev_err(hdmi->dev,
 342                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 343                         __func__, pixel_clk, sample_rate);
 344         }
 345
 346         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
 347                 __func__, sample_rate, ratio, pixel_clk, n, cts);
 348
 349         hdmi_set_cts_n(hdmi, cts, n);
 350 }
 351
 352 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 353 {
 354         mutex_lock(&hdmi->audio_mutex);
 355         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
 356                                  hdmi->ratio);
 357         mutex_unlock(&hdmi->audio_mutex);
 358 }
 359
 360 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 361 {
 362         mutex_lock(&hdmi->audio_mutex);
 363         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 364                                  hdmi->sample_rate, hdmi->ratio);
 365         mutex_unlock(&hdmi->audio_mutex);
 366 }
 367
 368 /*
 369  * this submodule is responsible for the video data synchronization.
 370  * for example, for RGB 4:4:4 input, the data map is defined as
 371  *                      pin{47~40} <==> R[7:0]
 372  *                      pin{31~24} <==> G[7:0]
 373  *                      pin{15~8}  <==> B[7:0]
 374  */
 375 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 376 {
 377         int color_format = 0;
 378         u8 val;
 379
 380         if (hdmi->hdmi_data.enc_in_format == RGB) {
 381                 if (hdmi->hdmi_data.enc_color_depth == 8)
 382                         color_format = 0x01;
 383                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 384                         color_format = 0x03;
 385                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 386                         color_format = 0x05;
 387                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 388                         color_format = 0x07;
 389                 else
 390                         return;
 391         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 392                 if (hdmi->hdmi_data.enc_color_depth == 8)
 393                         color_format = 0x09;
 394                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 395                         color_format = 0x0B;
 396                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 397                         color_format = 0x0D;
 398                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 399                         color_format = 0x0F;
 400                 else
 401                         return;
 402         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 403                 if (hdmi->hdmi_data.enc_color_depth == 8)
 404                         color_format = 0x16;
 405                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 406                         color_format = 0x14;
 407                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 408                         color_format = 0x12;
 409                 else
 410                         return;
 411         }
 412
 413         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 414                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 415                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 416         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 417
 418         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 419         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 420                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 421                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 422         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 423         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 424         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 425         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 426         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 427         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 428         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 429 }
 430
 431 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 432 {
 433         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 434 }
 435
 436 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 437 {
 438         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 439                 return 0;
 440         if (hdmi->hdmi_data.enc_in_format == RGB ||
 441             hdmi->hdmi_data.enc_in_format == YCBCR444)
 442                 return 1;
 443         return 0;
 444 }
 445
 446 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 447 {
 448         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 449                 return 0;
 450         if (hdmi->hdmi_data.enc_out_format == RGB ||
 451             hdmi->hdmi_data.enc_out_format == YCBCR444)
 452                 return 1;
 453         return 0;
 454 }
 455
 456 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 457 {
 458         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 459         unsigned i;
 460         u32 csc_scale = 1;
 461
 462         if (is_color_space_conversion(hdmi)) {
 463                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 464                         if (hdmi->hdmi_data.colorimetry ==
 465                                         HDMI_COLORIMETRY_ITU_601)
 466                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 467                         else
 468                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 469                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 470                         if (hdmi->hdmi_data.colorimetry ==
 471                                         HDMI_COLORIMETRY_ITU_601)
 472                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 473                         else
 474                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 475                         csc_scale = 0;
 476                 }
 477         }
 478
 479         /* The CSC registers are sequential, alternating MSB then LSB */
 480         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 481                 u16 coeff_a = (*csc_coeff)[0][i];
 482                 u16 coeff_b = (*csc_coeff)[1][i];
 483                 u16 coeff_c = (*csc_coeff)[2][i];
 484
 485                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 486                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 487                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 488                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 489                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 490                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 491         }
 492
 493         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 494                   HDMI_CSC_SCALE);
 495 }
 496
 497 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 498 {
 499         int color_depth = 0;
 500         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 501         int decimation = 0;
 502
 503         /* YCC422 interpolation to 444 mode */
 504         if (is_color_space_interpolation(hdmi))
 505                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 506         else if (is_color_space_decimation(hdmi))
 507                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 508
 509         if (hdmi->hdmi_data.enc_color_depth == 8)
 510                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 511         else if (hdmi->hdmi_data.enc_color_depth == 10)
 512                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 513         else if (hdmi->hdmi_data.enc_color_depth == 12)
 514                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 515         else if (hdmi->hdmi_data.enc_color_depth == 16)
 516                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 517         else
 518                 return;
 519
 520         /* Configure the CSC registers */
 521         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 522         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 523                   HDMI_CSC_SCALE);
 524
 525         dw_hdmi_update_csc_coeffs(hdmi);
 526 }
 527
 528 /*
 529  * HDMI video packetizer is used to packetize the data.
 530  * for example, if input is YCC422 mode or repeater is used,
 531  * data should be repacked this module can be bypassed.
 532  */
 533 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 534 {
 535         unsigned int color_depth = 0;
 536         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 537         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 538         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 539         u8 val, vp_conf;
 540
 541         if (hdmi_data->enc_out_format == RGB ||
 542             hdmi_data->enc_out_format == YCBCR444) {
 543                 if (!hdmi_data->enc_color_depth) {
 544                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 545                 } else if (hdmi_data->enc_color_depth == 8) {
 546                         color_depth = 4;
 547                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 548                 } else if (hdmi_data->enc_color_depth == 10) {
 549                         color_depth = 5;
 550                 } else if (hdmi_data->enc_color_depth == 12) {
 551                         color_depth = 6;
 552                 } else if (hdmi_data->enc_color_depth == 16) {
 553                         color_depth = 7;
 554                 } else {
 555                         return;
 556                 }
 557         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 558                 if (!hdmi_data->enc_color_depth ||
 559                     hdmi_data->enc_color_depth == 8)
 560                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 561                 else if (hdmi_data->enc_color_depth == 10)
 562                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 563                 else if (hdmi_data->enc_color_depth == 12)
 564                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 565                 else
 566                         return;
 567                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 568         } else {
 569                 return;
 570         }
 571
 572         /* set the packetizer registers */
 573         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 574                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 575                 ((hdmi_data->pix_repet_factor <<
 576                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 577                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 578         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 579
 580         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 581                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 582
 583         /* Data from pixel repeater block */
 584         if (hdmi_data->pix_repet_factor > 1) {
 585                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 586                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 587         } else { /* data from packetizer block */
 588                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 589                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 590         }
 591
 592         hdmi_modb(hdmi, vp_conf,
 593                   HDMI_VP_CONF_PR_EN_MASK |
 594                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 595
 596         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 597                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 598
 599         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 600
 601         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 602                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 603                           HDMI_VP_CONF_PP_EN_ENABLE |
 604                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 605         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 606                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 607                           HDMI_VP_CONF_PP_EN_DISABLE |
 608                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 609         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 610                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 611                           HDMI_VP_CONF_PP_EN_DISABLE |
 612                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 613         } else {
 614                 return;
 615         }
 616
 617         hdmi_modb(hdmi, vp_conf,
 618                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 619                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 620
 621         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 622                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 623                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 624                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 625
 626         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 627                   HDMI_VP_CONF);
 628 }
 629
 630 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 631                                        unsigned char bit)
 632 {
 633         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 634                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 635 }
 636
 637 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 638                                         unsigned char bit)
 639 {
 640         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 641                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 642 }
 643
 644 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 645                                        unsigned char bit)
 646 {
 647         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 648                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 649 }
 650
 651 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 652                                      unsigned char bit)
 653 {
 654         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 655 }
 656
 657 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 658                                       unsigned char bit)
 659 {
 660         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 661 }
 662
 663 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 664 {
 665         u32 val;
 666
 667         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 668                 if (msec-- == 0)
 669                         return false;
 670                 udelay(1000);
 671         }
 672         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 673
 674         return true;
 675 }
 676
 677 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 678                                  unsigned char addr)
 679 {
 680         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 681         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 682         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 683                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 684         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 685                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 686         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 687                     HDMI_PHY_I2CM_OPERATION_ADDR);
 688         hdmi_phy_wait_i2c_done(hdmi, 1000);
 689 }
 690
 691 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 692                               unsigned char addr)
 693 {
 694         __hdmi_phy_i2c_write(hdmi, data, addr);
 695         return 0;
 696 }
 697
 698 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
 699 {
 700         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 701                          HDMI_PHY_CONF0_PDZ_OFFSET,
 702                          HDMI_PHY_CONF0_PDZ_MASK);
 703 }
 704
 705 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 706 {
 707         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 708                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 709                          HDMI_PHY_CONF0_ENTMDS_MASK);
 710 }
 711
 712 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 713 {
 714         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 715                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 716                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 717 }
 718
 719 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 720 {
 721         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 722                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 723                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 724 }
 725
 726 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 727 {
 728         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 729                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 730                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 731 }
 732
 733 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 734 {
 735         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 736                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 737                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 738 }
 739
 740 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 741 {
 742         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 743                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 744                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 745 }
 746
 747 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 748                               unsigned char res, int cscon)
 749 {
 750         unsigned res_idx;
 751         u8 val, msec;
 752         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 753         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 754         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 755         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 756
 757         if (prep)
 758                 return -EINVAL;
 759
 760         switch (res) {
 761         case 0: /* color resolution 0 is 8 bit colour depth */
 762         case 8:
 763                 res_idx = DW_HDMI_RES_8;
 764                 break;
 765         case 10:
 766                 res_idx = DW_HDMI_RES_10;
 767                 break;
 768         case 12:
 769                 res_idx = DW_HDMI_RES_12;
 770                 break;
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         /* PLL/MPLL Cfg - always match on final entry */
 776         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 777                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 778                     mpll_config->mpixelclock)
 779                         break;
 780
 781         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 782                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 783                     curr_ctrl->mpixelclock)
 784                         break;
 785
 786         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 787                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 788                     phy_config->mpixelclock)
 789                         break;
 790
 791         if (mpll_config->mpixelclock == ~0UL ||
 792             curr_ctrl->mpixelclock == ~0UL ||
 793             phy_config->mpixelclock == ~0UL) {
 794                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 795                         hdmi->hdmi_data.video_mode.mpixelclock);
 796                 return -EINVAL;
 797         }
 798
 799         /* Enable csc path */
 800         if (cscon)
 801                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 802         else
 803                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 804
 805         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 806
 807         /* gen2 tx power off */
 808         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 809
 810         /* gen2 pddq */
 811         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 812
 813         /* PHY reset */
 814         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 815         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 816
 817         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 818
 819         hdmi_phy_test_clear(hdmi, 1);
 820         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 821                     HDMI_PHY_I2CM_SLAVE_ADDR);
 822         hdmi_phy_test_clear(hdmi, 0);
 823
 824         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 825         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 826
 827         /* CURRCTRL */
 828         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 829
 830         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 831         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 832
 833         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 834         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 835         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 836
 837         /* REMOVE CLK TERM */
 838         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 839
 840         dw_hdmi_phy_enable_power(hdmi, 1);
 841
 842         /* toggle TMDS enable */
 843         dw_hdmi_phy_enable_tmds(hdmi, 0);
 844         dw_hdmi_phy_enable_tmds(hdmi, 1);
 845
 846         /* gen2 tx power on */
 847         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 848         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 849
 850         if (hdmi->dev_type == RK3288_HDMI)
 851                 dw_hdmi_phy_enable_spare(hdmi, 1);
 852
 853         /*Wait for PHY PLL lock */
 854         msec = 5;
 855         do {
 856                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 857                 if (!val)
 858                         break;
 859
 860                 if (msec == 0) {
 861                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 862                         return -ETIMEDOUT;
 863                 }
 864
 865                 udelay(1000);
 866                 msec--;
 867         } while (1);
 868
 869         return 0;
 870 }
 871
 872 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 873 {
 874         int i, ret;
 875         bool cscon = false;
 876
 877         /*check csc whether needed activated in HDMI mode */
 878         cscon = (is_color_space_conversion(hdmi) &&
 879                         !hdmi->hdmi_data.video_mode.mdvi);
 880
 881         /* HDMI Phy spec says to do the phy initialization sequence twice */
 882         for (i = 0; i < 2; i++) {
 883                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 884                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 885                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 886                 dw_hdmi_phy_enable_power(hdmi, 0);
 887
 888                 /* Enable CSC */
 889                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 890                 if (ret)
 891                         return ret;
 892         }
 893
 894         hdmi->phy_enabled = true;
 895         return 0;
 896 }
 897
 898 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 899 {
 900         u8 de;
 901
 902         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 903                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 904         else
 905                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 906
 907         /* disable rx detect */
 908         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 909                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 910
 911         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 912
 913         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 914                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 915 }
 916
 917 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 918 {
 919         struct hdmi_avi_infoframe frame;
 920         u8 val;
 921
 922         /* Initialise info frame from DRM mode */
 923         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 924
 925         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 926                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 927         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 928                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 929         else
 930                 frame.colorspace = HDMI_COLORSPACE_RGB;
 931
 932         /* Set up colorimetry */
 933         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 934                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 935                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 936                         frame.extended_colorimetry =
 937                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 938                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 939                         frame.extended_colorimetry =
 940                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 941         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 942                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 943                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 944         } else { /* Carries no data */
 945                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 946                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 947         }
 948
 949         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 950
 951         /*
 952          * The Designware IP uses a different byte format from standard
 953          * AVI info frames, though generally the bits are in the correct
 954          * bytes.
 955          */
 956
 957         /*
 958          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
 959          * active aspect present in bit 6 rather than 4.
 960          */
 961         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
 962         if (frame.active_aspect & 15)
 963                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
 964         if (frame.top_bar || frame.bottom_bar)
 965                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
 966         if (frame.left_bar || frame.right_bar)
 967                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
 968         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 969
 970         /* AVI data byte 2 differences: none */
 971         val = ((frame.colorimetry & 0x3) << 6) |
 972               ((frame.picture_aspect & 0x3) << 4) |
 973               (frame.active_aspect & 0xf);
 974         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
 975
 976         /* AVI data byte 3 differences: none */
 977         val = ((frame.extended_colorimetry & 0x7) << 4) |
 978               ((frame.quantization_range & 0x3) << 2) |
 979               (frame.nups & 0x3);
 980         if (frame.itc)
 981                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
 982         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
 983
 984         /* AVI data byte 4 differences: none */
 985         val = frame.video_code & 0x7f;
 986         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
 987
 988         /* AVI Data Byte 5- set up input and output pixel repetition */
 989         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
 990                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
 991                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
 992                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
 993                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
 994                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
 995         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
 996
 997         /*
 998          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
 999          * ycc range in bits 2,3 rather than 6,7
1000          */
1001         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1002               (frame.content_type & 0x3);
1003         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1004
1005         /* AVI Data Bytes 6-13 */
1006         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1007         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1008         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1009         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1010         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1011         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1012         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1013         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1014 }
1015
1016 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1017                              const struct drm_display_mode *mode)
1018 {
1019         u8 inv_val;
1020         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1021         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1022
1023         vmode->mpixelclock = mode->clock * 1000;
1024
1025         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1026
1027         /* Set up HDMI_FC_INVIDCONF */
1028         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1029                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1030                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1031
1032         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1033                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1034                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1035
1036         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1037                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1038                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1039
1040         inv_val |= (vmode->mdataenablepolarity ?
1041                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1042                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1043
1044         if (hdmi->vic == 39)
1045                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1046         else
1047                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1048                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1049                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1050
1051         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1052                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1053                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1054
1055         inv_val |= (vmode->mdvi ?
1056                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1057                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1058
1059         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1060
1061         /* Set up horizontal active pixel width */
1062         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1063         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1064
1065         /* Set up vertical active lines */
1066         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1067         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1068
1069         /* Set up horizontal blanking pixel region width */
1070         hblank = mode->htotal - mode->hdisplay;
1071         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1072         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1073
1074         /* Set up vertical blanking pixel region width */
1075         vblank = mode->vtotal - mode->vdisplay;
1076         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1077
1078         /* Set up HSYNC active edge delay width (in pixel clks) */
1079         h_de_hs = mode->hsync_start - mode->hdisplay;
1080         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1081         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1082
1083         /* Set up VSYNC active edge delay (in lines) */
1084         v_de_vs = mode->vsync_start - mode->vdisplay;
1085         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1086
1087         /* Set up HSYNC active pulse width (in pixel clks) */
1088         hsync_len = mode->hsync_end - mode->hsync_start;
1089         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1090         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1091
1092         /* Set up VSYNC active edge delay (in lines) */
1093         vsync_len = mode->vsync_end - mode->vsync_start;
1094         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1095 }
1096
1097 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1098 {
1099         if (!hdmi->phy_enabled)
1100                 return;
1101
1102         dw_hdmi_phy_enable_tmds(hdmi, 0);
1103         dw_hdmi_phy_enable_power(hdmi, 0);
1104
1105         hdmi->phy_enabled = false;
1106 }
1107
1108 /* HDMI Initialization Step B.4 */
1109 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1110 {
1111         u8 clkdis;
1112
1113         /* control period minimum duration */
1114         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1115         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1116         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1117
1118         /* Set to fill TMDS data channels */
1119         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1120         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1121         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1122
1123         /* Enable pixel clock and tmds data path */
1124         clkdis = 0x7F;
1125         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1126         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1127
1128         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1129         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1130
1131         /* Enable csc path */
1132         if (is_color_space_conversion(hdmi)) {
1133                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1134                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1135         }
1136 }
1137
1138 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1139 {
1140         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1141 }
1142
1143 /* Workaround to clear the overflow condition */
1144 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1145 {
1146         int count;
1147         u8 val;
1148
1149         /* TMDS software reset */
1150         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1151
1152         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1153         if (hdmi->dev_type == IMX6DL_HDMI) {
1154                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1155                 return;
1156         }
1157
1158         for (count = 0; count < 4; count++)
1159                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1160 }
1161
1162 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1163 {
1164         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1165         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1166 }
1167
1168 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1169 {
1170         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1171                     HDMI_IH_MUTE_FC_STAT2);
1172 }
1173
1174 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1175 {
1176         int ret;
1177
1178         hdmi_disable_overflow_interrupts(hdmi);
1179
1180         hdmi->vic = drm_match_cea_mode(mode);
1181
1182         if (!hdmi->vic) {
1183                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1184                 hdmi->hdmi_data.video_mode.mdvi = true;
1185         } else {
1186                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1187                 hdmi->hdmi_data.video_mode.mdvi = false;
1188         }
1189
1190         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1191             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1192             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1193             (hdmi->vic == 17) || (hdmi->vic == 18))
1194                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1195         else
1196                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1197
1198         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1199             (hdmi->vic == 12) || (hdmi->vic == 13) ||
1200             (hdmi->vic == 14) || (hdmi->vic == 15) ||
1201             (hdmi->vic == 25) || (hdmi->vic == 26) ||
1202             (hdmi->vic == 27) || (hdmi->vic == 28) ||
1203             (hdmi->vic == 29) || (hdmi->vic == 30) ||
1204             (hdmi->vic == 35) || (hdmi->vic == 36) ||
1205             (hdmi->vic == 37) || (hdmi->vic == 38))
1206                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1207         else
1208                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1209
1210         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1211
1212         /* TODO: Get input format from IPU (via FB driver interface) */
1213         hdmi->hdmi_data.enc_in_format = RGB;
1214
1215         hdmi->hdmi_data.enc_out_format = RGB;
1216
1217         hdmi->hdmi_data.enc_color_depth = 8;
1218         hdmi->hdmi_data.pix_repet_factor = 0;
1219         hdmi->hdmi_data.hdcp_enable = 0;
1220         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1221
1222         /* HDMI Initialization Step B.1 */
1223         hdmi_av_composer(hdmi, mode);
1224
1225         /* HDMI Initializateion Step B.2 */
1226         ret = dw_hdmi_phy_init(hdmi);
1227         if (ret)
1228                 return ret;
1229
1230         /* HDMI Initialization Step B.3 */
1231         dw_hdmi_enable_video_path(hdmi);
1232
1233         /* not for DVI mode */
1234         if (hdmi->hdmi_data.video_mode.mdvi) {
1235                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1236         } else {
1237                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1238
1239                 /* HDMI Initialization Step E - Configure audio */
1240                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1241                 hdmi_enable_audio_clk(hdmi);
1242
1243                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1244                 hdmi_config_AVI(hdmi, mode);
1245         }
1246
1247         hdmi_video_packetize(hdmi);
1248         hdmi_video_csc(hdmi);
1249         hdmi_video_sample(hdmi);
1250         hdmi_tx_hdcp_config(hdmi);
1251
1252         dw_hdmi_clear_overflow(hdmi);
1253         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1254                 hdmi_enable_overflow_interrupts(hdmi);
1255
1256         return 0;
1257 }
1258
1259 /* Wait until we are registered to enable interrupts */
1260 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1261 {
1262         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1263                     HDMI_PHY_I2CM_INT_ADDR);
1264
1265         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1266                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1267                     HDMI_PHY_I2CM_CTLINT_ADDR);
1268
1269         /* enable cable hot plug irq */
1270         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1271
1272         /* Clear Hotplug interrupts */
1273         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1274
1275         return 0;
1276 }
1277
1278 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1279 {
1280         u8 ih_mute;
1281
1282         /*
1283          * Boot up defaults are:
1284          * HDMI_IH_MUTE   = 0x03 (disabled)
1285          * HDMI_IH_MUTE_* = 0x00 (enabled)
1286          *
1287          * Disable top level interrupt bits in HDMI block
1288          */
1289         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1290                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1291                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1292
1293         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1294
1295         /* by default mask all interrupts */
1296         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1297         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1298         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1299         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1300         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1301         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1302         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1303         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1304         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1305         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1306         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1307         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1308         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1309         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1310         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1311
1312         /* Disable interrupts in the IH_MUTE_* registers */
1313         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1314         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1315         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1316         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1317         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1318         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1319         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1320         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1321         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1322         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1323
1324         /* Enable top level interrupt bits in HDMI block */
1325         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1326                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1327         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1328 }
1329
1330 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1331 {
1332         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1333 }
1334
1335 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1336 {
1337         dw_hdmi_phy_disable(hdmi);
1338 }
1339
1340 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1341                                     struct drm_display_mode *orig_mode,
1342                                     struct drm_display_mode *mode)
1343 {
1344         struct dw_hdmi *hdmi = bridge->driver_private;
1345
1346         dw_hdmi_setup(hdmi, mode);
1347
1348         /* Store the display mode for plugin/DKMS poweron events */
1349         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1350 }
1351
1352 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1353                                       const struct drm_display_mode *mode,
1354                                       struct drm_display_mode *adjusted_mode)
1355 {
1356         return true;
1357 }
1358
1359 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1360 {
1361         struct dw_hdmi *hdmi = bridge->driver_private;
1362
1363         dw_hdmi_poweroff(hdmi);
1364 }
1365
1366 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1367 {
1368         struct dw_hdmi *hdmi = bridge->driver_private;
1369
1370         dw_hdmi_poweron(hdmi);
1371 }
1372
1373 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1374 {
1375         /* do nothing */
1376 }
1377
1378 static enum drm_connector_status
1379 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1380 {
1381         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1382                                              connector);
1383
1384         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1385                 connector_status_connected : connector_status_disconnected;
1386 }
1387
1388 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1389 {
1390         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1391                                              connector);
1392         struct edid *edid;
1393         int ret;
1394
1395         if (!hdmi->ddc)
1396                 return 0;
1397
1398         edid = drm_get_edid(connector, hdmi->ddc);
1399         if (edid) {
1400                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1401                         edid->width_cm, edid->height_cm);
1402
1403                 drm_mode_connector_update_edid_property(connector, edid);
1404                 ret = drm_add_edid_modes(connector, edid);
1405                 kfree(edid);
1406         } else {
1407                 dev_dbg(hdmi->dev, "failed to get edid\n");
1408         }
1409
1410         return 0;
1411 }
1412
1413 static enum drm_mode_status
1414 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1415                              struct drm_display_mode *mode)
1416 {
1417         struct dw_hdmi *hdmi = container_of(connector,
1418                                            struct dw_hdmi, connector);
1419         enum drm_mode_status mode_status = MODE_OK;
1420
1421         if (hdmi->plat_data->mode_valid)
1422                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1423
1424         return mode_status;
1425 }
1426
1427 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1428                                                            *connector)
1429 {
1430         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1431                                              connector);
1432
1433         return hdmi->encoder;
1434 }
1435
1436 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1437 {
1438         drm_connector_unregister(connector);
1439         drm_connector_cleanup(connector);
1440 }
1441
1442 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1443         .dpms = drm_helper_connector_dpms,
1444         .fill_modes = drm_helper_probe_single_connector_modes,
1445         .detect = dw_hdmi_connector_detect,
1446         .destroy = dw_hdmi_connector_destroy,
1447 };
1448
1449 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1450         .get_modes = dw_hdmi_connector_get_modes,
1451         .mode_valid = dw_hdmi_connector_mode_valid,
1452         .best_encoder = dw_hdmi_connector_best_encoder,
1453 };
1454
1455 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1456         .enable = dw_hdmi_bridge_enable,
1457         .disable = dw_hdmi_bridge_disable,
1458         .pre_enable = dw_hdmi_bridge_nop,
1459         .post_disable = dw_hdmi_bridge_nop,
1460         .mode_set = dw_hdmi_bridge_mode_set,
1461         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1462 };
1463
1464 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1465 {
1466         struct dw_hdmi *hdmi = dev_id;
1467         u8 intr_stat;
1468
1469         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1470         if (intr_stat)
1471                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1472
1473         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1474 }
1475
1476 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1477 {
1478         struct dw_hdmi *hdmi = dev_id;
1479         u8 intr_stat;
1480         u8 phy_int_pol;
1481
1482         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1483
1484         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1485
1486         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1487                 if (phy_int_pol & HDMI_PHY_HPD) {
1488                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1489
1490                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1491
1492                         dw_hdmi_poweron(hdmi);
1493                 } else {
1494                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1495
1496                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1497                                   HDMI_PHY_POL0);
1498
1499                         dw_hdmi_poweroff(hdmi);
1500                 }
1501                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1502         }
1503
1504         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1505         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1506
1507         return IRQ_HANDLED;
1508 }
1509
1510 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1511 {
1512         struct drm_encoder *encoder = hdmi->encoder;
1513         struct drm_bridge *bridge;
1514         int ret;
1515
1516         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1517         if (!bridge) {
1518                 DRM_ERROR("Failed to allocate drm bridge\n");
1519                 return -ENOMEM;
1520         }
1521
1522         hdmi->bridge = bridge;
1523         bridge->driver_private = hdmi;
1524         bridge->funcs = &dw_hdmi_bridge_funcs;
1525         ret = drm_bridge_attach(drm, bridge);
1526         if (ret) {
1527                 DRM_ERROR("Failed to initialize bridge with drm\n");
1528                 return -EINVAL;
1529         }
1530
1531         encoder->bridge = bridge;
1532         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1533
1534         drm_connector_helper_add(&hdmi->connector,
1535                                  &dw_hdmi_connector_helper_funcs);
1536         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1537                            DRM_MODE_CONNECTOR_HDMIA);
1538
1539         hdmi->connector.encoder = encoder;
1540
1541         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1542
1543         return 0;
1544 }
1545
1546 int dw_hdmi_bind(struct device *dev, struct device *master,
1547                  void *data, struct drm_encoder *encoder,
1548                  struct resource *iores, int irq,
1549                  const struct dw_hdmi_plat_data *plat_data)
1550 {
1551         struct drm_device *drm = data;
1552         struct device_node *np = dev->of_node;
1553         struct device_node *ddc_node;
1554         struct dw_hdmi *hdmi;
1555         int ret;
1556         u32 val = 1;
1557
1558         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1559         if (!hdmi)
1560                 return -ENOMEM;
1561
1562         hdmi->plat_data = plat_data;
1563         hdmi->dev = dev;
1564         hdmi->dev_type = plat_data->dev_type;
1565         hdmi->sample_rate = 48000;
1566         hdmi->ratio = 100;
1567         hdmi->encoder = encoder;
1568
1569         mutex_init(&hdmi->audio_mutex);
1570
1571         of_property_read_u32(np, "reg-io-width", &val);
1572
1573         switch (val) {
1574         case 4:
1575                 hdmi->write = dw_hdmi_writel;
1576                 hdmi->read = dw_hdmi_readl;
1577                 break;
1578         case 1:
1579                 hdmi->write = dw_hdmi_writeb;
1580                 hdmi->read = dw_hdmi_readb;
1581                 break;
1582         default:
1583                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1584                 return -EINVAL;
1585         }
1586
1587         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1588         if (ddc_node) {
1589                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1590                 of_node_put(ddc_node);
1591                 if (!hdmi->ddc) {
1592                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1593                         return -EPROBE_DEFER;
1594                 }
1595
1596         } else {
1597                 dev_dbg(hdmi->dev, "no ddc property found\n");
1598         }
1599
1600         hdmi->regs = devm_ioremap_resource(dev, iores);
1601         if (IS_ERR(hdmi->regs))
1602                 return PTR_ERR(hdmi->regs);
1603
1604         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1605         if (IS_ERR(hdmi->isfr_clk)) {
1606                 ret = PTR_ERR(hdmi->isfr_clk);
1607                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1608                 return ret;
1609         }
1610
1611         ret = clk_prepare_enable(hdmi->isfr_clk);
1612         if (ret) {
1613                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1614                 return ret;
1615         }
1616
1617         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1618         if (IS_ERR(hdmi->iahb_clk)) {
1619                 ret = PTR_ERR(hdmi->iahb_clk);
1620                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1621                 goto err_isfr;
1622         }
1623
1624         ret = clk_prepare_enable(hdmi->iahb_clk);
1625         if (ret) {
1626                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1627                 goto err_isfr;
1628         }
1629
1630         /* Product and revision IDs */
1631         dev_info(dev,
1632                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1633                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1634                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1635                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1636                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1637
1638         initialize_hdmi_ih_mutes(hdmi);
1639
1640         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1641                                         dw_hdmi_irq, IRQF_SHARED,
1642                                         dev_name(dev), hdmi);
1643         if (ret)
1644                 goto err_iahb;
1645
1646         /*
1647          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1648          * N and cts values before enabling phy
1649          */
1650         hdmi_init_clk_regenerator(hdmi);
1651
1652         /*
1653          * Configure registers related to HDMI interrupt
1654          * generation before registering IRQ.
1655          */
1656         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1657
1658         /* Clear Hotplug interrupts */
1659         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1660
1661         ret = dw_hdmi_fb_registered(hdmi);
1662         if (ret)
1663                 goto err_iahb;
1664
1665         ret = dw_hdmi_register(drm, hdmi);
1666         if (ret)
1667                 goto err_iahb;
1668
1669         /* Unmute interrupts */
1670         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1671
1672         dev_set_drvdata(dev, hdmi);
1673
1674         return 0;
1675
1676 err_iahb:
1677         clk_disable_unprepare(hdmi->iahb_clk);
1678 err_isfr:
1679         clk_disable_unprepare(hdmi->isfr_clk);
1680
1681         return ret;
1682 }
1683 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1684
1685 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1686 {
1687         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1688
1689         /* Disable all interrupts */
1690         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1691
1692         hdmi->connector.funcs->destroy(&hdmi->connector);
1693         hdmi->encoder->funcs->destroy(hdmi->encoder);
1694
1695         clk_disable_unprepare(hdmi->iahb_clk);
1696         clk_disable_unprepare(hdmi->isfr_clk);
1697         i2c_put_adapter(hdmi->ddc);
1698 }
1699 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1700
1701 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1702 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1703 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1704 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1705 MODULE_LICENSE("GPL");
1706 MODULE_ALIAS("platform:dw-hdmi");