2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/pci.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
24 #define IOH_EDGE_FALLING 0
25 #define IOH_EDGE_RISING BIT(0)
26 #define IOH_LEVEL_L BIT(1)
27 #define IOH_LEVEL_H (BIT(0) | BIT(1))
28 #define IOH_EDGE_BOTH BIT(2)
29 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31 #define IOH_IRQ_BASE 0
33 #define PCI_VENDOR_ID_ROHM 0x10DB
51 struct ioh_reg_comn regs[8];
59 * struct ioh_gpio_reg_data - The register store data.
60 * @ien_reg To store contents of interrupt enable register.
61 * @imask_reg: To store contents of interrupt mask regist
62 * @po_reg: To store contents of PO register.
63 * @pm_reg: To store contents of PM register.
64 * @im0_reg: To store contents of interrupt mode regist0
65 * @im1_reg: To store contents of interrupt mode regist1
67 struct ioh_gpio_reg_data {
77 * struct ioh_gpio - GPIO private data structure.
78 * @base: PCI base address of Memory mapped I/O register.
79 * @reg: Memory mapped IOH GPIO register list.
80 * @dev: Pointer to device structure.
81 * @gpio: Data for GPIO infrastructure.
82 * @ioh_gpio_reg: Memory mapped Register data is saved here
84 * @ch: Indicate GPIO channel
85 * @irq_base: Save base of IRQ number for interrupt
86 * @spinlock: Used for register access protection in
87 * interrupt context ioh_irq_type and PM;
91 struct ioh_regs __iomem *reg;
93 struct gpio_chip gpio;
94 struct ioh_gpio_reg_data ioh_gpio_reg;
101 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
103 static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
106 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
108 mutex_lock(&chip->lock);
109 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
111 reg_val |= (1 << nr);
113 reg_val &= ~(1 << nr);
115 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
116 mutex_unlock(&chip->lock);
119 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
121 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
123 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
126 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
129 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
133 mutex_lock(&chip->lock);
134 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
135 ((1 << num_ports[chip->ch]) - 1);
137 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
139 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
141 reg_val |= (1 << nr);
143 reg_val &= ~(1 << nr);
144 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
146 mutex_unlock(&chip->lock);
151 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
153 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
156 mutex_lock(&chip->lock);
157 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
158 ((1 << num_ports[chip->ch]) - 1);
160 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
161 mutex_unlock(&chip->lock);
168 * Save register configuration and disable interrupts.
170 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
172 chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
173 chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
174 chip->ioh_gpio_reg.ien_reg = ioread32(&chip->reg->regs[chip->ch].ien);
175 chip->ioh_gpio_reg.imask_reg = ioread32(&chip->reg->regs[chip->ch].imask);
176 chip->ioh_gpio_reg.im0_reg = ioread32(&chip->reg->regs[chip->ch].im_0);
177 chip->ioh_gpio_reg.im1_reg = ioread32(&chip->reg->regs[chip->ch].im_1);
181 * This function restores the register configuration of the GPIO device.
183 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
185 iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
186 iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
187 iowrite32(chip->ioh_gpio_reg.ien_reg, &chip->reg->regs[chip->ch].ien);
188 iowrite32(chip->ioh_gpio_reg.imask_reg, &chip->reg->regs[chip->ch].imask);
189 iowrite32(chip->ioh_gpio_reg.im0_reg, &chip->reg->regs[chip->ch].im_0);
190 iowrite32(chip->ioh_gpio_reg.im1_reg, &chip->reg->regs[chip->ch].im_1);
194 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
196 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
197 return chip->irq_base + offset;
200 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
202 struct gpio_chip *gpio = &chip->gpio;
204 gpio->label = dev_name(chip->dev);
205 gpio->owner = THIS_MODULE;
206 gpio->direction_input = ioh_gpio_direction_input;
207 gpio->get = ioh_gpio_get;
208 gpio->direction_output = ioh_gpio_direction_output;
209 gpio->set = ioh_gpio_set;
210 gpio->dbg_show = NULL;
212 gpio->ngpio = num_port;
214 gpio->to_irq = ioh_gpio_to_irq;
217 static int ioh_irq_type(struct irq_data *d, unsigned int type)
227 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
228 struct ioh_gpio *chip = gc->private;
230 ch = irq - chip->irq_base;
231 if (irq <= chip->irq_base + 7) {
232 im_reg = &chip->reg->regs[chip->ch].im_0;
235 im_reg = &chip->reg->regs[chip->ch].im_1;
238 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
239 __func__, irq, type, ch, im_pos, type);
241 spin_lock_irqsave(&chip->spinlock, flags);
244 case IRQ_TYPE_EDGE_RISING:
245 val = IOH_EDGE_RISING;
247 case IRQ_TYPE_EDGE_FALLING:
248 val = IOH_EDGE_FALLING;
250 case IRQ_TYPE_EDGE_BOTH:
253 case IRQ_TYPE_LEVEL_HIGH:
256 case IRQ_TYPE_LEVEL_LOW:
262 dev_warn(chip->dev, "%s: unknown type(%dd)",
267 /* Set interrupt mode */
268 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
269 iowrite32(im | (val << (im_pos * 4)), im_reg);
272 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
275 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
277 /* Enable interrupt */
278 ien = ioread32(&chip->reg->regs[chip->ch].ien);
279 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
281 spin_unlock_irqrestore(&chip->spinlock, flags);
286 static void ioh_irq_unmask(struct irq_data *d)
288 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
289 struct ioh_gpio *chip = gc->private;
291 iowrite32(1 << (d->irq - chip->irq_base),
292 &chip->reg->regs[chip->ch].imaskclr);
295 static void ioh_irq_mask(struct irq_data *d)
297 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
298 struct ioh_gpio *chip = gc->private;
300 iowrite32(1 << (d->irq - chip->irq_base),
301 &chip->reg->regs[chip->ch].imask);
304 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
306 struct ioh_gpio *chip = dev_id;
311 for (i = 0; i < 8; i++) {
312 reg_val = ioread32(&chip->reg->regs[i].istatus);
313 for (j = 0; j < num_ports[i]; j++) {
314 if (reg_val & BIT(j)) {
316 "%s:[%d]:irq=%d status=0x%x\n",
317 __func__, j, irq, reg_val);
319 &chip->reg->regs[chip->ch].iclr);
320 generic_handle_irq(chip->irq_base + j);
328 static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
329 unsigned int irq_start, unsigned int num)
331 struct irq_chip_generic *gc;
332 struct irq_chip_type *ct;
334 gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
339 ct->chip.irq_mask = ioh_irq_mask;
340 ct->chip.irq_unmask = ioh_irq_unmask;
341 ct->chip.irq_set_type = ioh_irq_type;
343 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
344 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
347 static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
348 const struct pci_device_id *id)
352 struct ioh_gpio *chip;
354 void __iomem *chip_save;
357 ret = pci_enable_device(pdev);
359 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
363 ret = pci_request_regions(pdev, KBUILD_MODNAME);
365 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
366 goto err_request_regions;
369 base = pci_iomap(pdev, 1, 0);
371 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
376 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
377 if (chip_save == NULL) {
378 dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
384 for (i = 0; i < 8; i++, chip++) {
385 chip->dev = &pdev->dev;
387 chip->reg = chip->base;
389 mutex_init(&chip->lock);
390 ioh_gpio_setup(chip, num_ports[i]);
391 ret = gpiochip_add(&chip->gpio);
393 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
394 goto err_gpiochip_add;
399 for (j = 0; j < 8; j++, chip++) {
400 irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
404 "ml_ioh_gpio: Failed to get IRQ base num\n");
406 goto err_irq_alloc_descs;
408 chip->irq_base = irq_base;
409 ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
413 ret = request_irq(pdev->irq, ioh_gpio_handler,
414 IRQF_SHARED, KBUILD_MODNAME, chip);
417 "%s request_irq failed\n", __func__);
418 goto err_request_irq;
421 pci_set_drvdata(pdev, chip);
430 irq_free_descs(chip->irq_base, num_ports[j]);
437 ret = gpiochip_remove(&chip->gpio);
439 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
444 pci_iounmap(pdev, base);
447 pci_release_regions(pdev);
450 pci_disable_device(pdev);
454 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
458 static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
462 struct ioh_gpio *chip = pci_get_drvdata(pdev);
463 void __iomem *chip_save;
467 free_irq(pdev->irq, chip);
469 for (i = 0; i < 8; i++, chip++) {
470 irq_free_descs(chip->irq_base, num_ports[i]);
471 err = gpiochip_remove(&chip->gpio);
473 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
477 pci_iounmap(pdev, chip->base);
478 pci_release_regions(pdev);
479 pci_disable_device(pdev);
484 static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
487 struct ioh_gpio *chip = pci_get_drvdata(pdev);
489 ioh_gpio_save_reg_conf(chip);
491 ret = pci_save_state(pdev);
493 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
496 pci_disable_device(pdev);
497 pci_set_power_state(pdev, PCI_D0);
498 ret = pci_enable_wake(pdev, PCI_D0, 1);
500 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
505 static int ioh_gpio_resume(struct pci_dev *pdev)
508 struct ioh_gpio *chip = pci_get_drvdata(pdev);
510 ret = pci_enable_wake(pdev, PCI_D0, 0);
512 pci_set_power_state(pdev, PCI_D0);
513 ret = pci_enable_device(pdev);
515 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
518 pci_restore_state(pdev);
520 iowrite32(0x01, &chip->reg->srst);
521 iowrite32(0x00, &chip->reg->srst);
522 ioh_gpio_restore_reg_conf(chip);
527 #define ioh_gpio_suspend NULL
528 #define ioh_gpio_resume NULL
531 static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
532 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
535 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
537 static struct pci_driver ioh_gpio_driver = {
538 .name = "ml_ioh_gpio",
539 .id_table = ioh_gpio_pcidev_id,
540 .probe = ioh_gpio_probe,
541 .remove = __devexit_p(ioh_gpio_remove),
542 .suspend = ioh_gpio_suspend,
543 .resume = ioh_gpio_resume
546 static int __init ioh_gpio_pci_init(void)
548 return pci_register_driver(&ioh_gpio_driver);
550 module_init(ioh_gpio_pci_init);
552 static void __exit ioh_gpio_pci_exit(void)
554 pci_unregister_driver(&ioh_gpio_driver);
556 module_exit(ioh_gpio_pci_exit);
558 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
559 MODULE_LICENSE("GPL");