drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bug.h>
  22 #include <linux/compiler.h>
  23 #include <linux/delay.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/firewire.h>
  27 #include <linux/firewire-constants.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/mutex.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/slab.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/string.h>
  42 #include <linux/time.h>
  43 #include <linux/vmalloc.h>
  44
  45 #include <asm/byteorder.h>
  46 #include <asm/page.h>
  47 #include <asm/system.h>
  48
  49 #ifdef CONFIG_PPC_PMAC
  50 #include <asm/pmac_feature.h>
  51 #endif
  52
  53 #include "core.h"
  54 #include "ohci.h"
  55
  56 #define DESCRIPTOR_OUTPUT_MORE          0
  57 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  58 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  59 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  60 #define DESCRIPTOR_STATUS               (1 << 11)
  61 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  62 #define DESCRIPTOR_PING                 (1 << 7)
  63 #define DESCRIPTOR_YY                   (1 << 6)
  64 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  65 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  66 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  67 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  68 #define DESCRIPTOR_WAIT                 (3 << 0)
  69
  70 struct descriptor {
  71         __le16 req_count;
  72         __le16 control;
  73         __le32 data_address;
  74         __le32 branch_address;
  75         __le16 res_count;
  76         __le16 transfer_status;
  77 } __attribute__((aligned(16)));
  78
  79 #define CONTROL_SET(regs)       (regs)
  80 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  81 #define COMMAND_PTR(regs)       ((regs) + 12)
  82 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  83
  84 #define AR_BUFFER_SIZE  (32*1024)
  85 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  86 /* we need at least two pages for proper list management */
  87 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  88
  89 #define MAX_ASYNC_PAYLOAD       4096
  90 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  91 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  92
  93 struct ar_context {
  94         struct fw_ohci *ohci;
  95         struct page *pages[AR_BUFFERS];
  96         void *buffer;
  97         struct descriptor *descriptors;
  98         dma_addr_t descriptors_bus;
  99         void *pointer;
 100         unsigned int last_buffer_index;
 101         u32 regs;
 102         struct tasklet_struct tasklet;
 103 };
 104
 105 struct context;
 106
 107 typedef int (*descriptor_callback_t)(struct context *ctx,
 108                                      struct descriptor *d,
 109                                      struct descriptor *last);
 110
 111 /*
 112  * A buffer that contains a block of DMA-able coherent memory used for
 113  * storing a portion of a DMA descriptor program.
 114  */
 115 struct descriptor_buffer {
 116         struct list_head list;
 117         dma_addr_t buffer_bus;
 118         size_t buffer_size;
 119         size_t used;
 120         struct descriptor buffer[0];
 121 };
 122
 123 struct context {
 124         struct fw_ohci *ohci;
 125         u32 regs;
 126         int total_allocation;
 127
 128         /*
 129          * List of page-sized buffers for storing DMA descriptors.
 130          * Head of list contains buffers in use and tail of list contains
 131          * free buffers.
 132          */
 133         struct list_head buffer_list;
 134
 135         /*
 136          * Pointer to a buffer inside buffer_list that contains the tail
 137          * end of the current DMA program.
 138          */
 139         struct descriptor_buffer *buffer_tail;
 140
 141         /*
 142          * The descriptor containing the branch address of the first
 143          * descriptor that has not yet been filled by the device.
 144          */
 145         struct descriptor *last;
 146
 147         /*
 148          * The last descriptor in the DMA program.  It contains the branch
 149          * address that must be updated upon appending a new descriptor.
 150          */
 151         struct descriptor *prev;
 152
 153         descriptor_callback_t callback;
 154
 155         struct tasklet_struct tasklet;
 156 };
 157
 158 #define IT_HEADER_SY(v)          ((v) <<  0)
 159 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 160 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 161 #define IT_HEADER_TAG(v)         ((v) << 14)
 162 #define IT_HEADER_SPEED(v)       ((v) << 16)
 163 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 164
 165 struct iso_context {
 166         struct fw_iso_context base;
 167         struct context context;
 168         int excess_bytes;
 169         void *header;
 170         size_t header_length;
 171 };
 172
 173 #define CONFIG_ROM_SIZE 1024
 174
 175 struct fw_ohci {
 176         struct fw_card card;
 177
 178         __iomem char *registers;
 179         int node_id;
 180         int generation;
 181         int request_generation; /* for timestamping incoming requests */
 182         unsigned quirks;
 183         unsigned int pri_req_max;
 184         u32 bus_time;
 185         bool is_root;
 186         bool csr_state_setclear_abdicate;
 187
 188         /*
 189          * Spinlock for accessing fw_ohci data.  Never call out of
 190          * this driver with this lock held.
 191          */
 192         spinlock_t lock;
 193
 194         struct mutex phy_reg_mutex;
 195
 196         void *misc_buffer;
 197         dma_addr_t misc_buffer_bus;
 198
 199         struct ar_context ar_request_ctx;
 200         struct ar_context ar_response_ctx;
 201         struct context at_request_ctx;
 202         struct context at_response_ctx;
 203
 204         u32 it_context_mask;     /* unoccupied IT contexts */
 205         struct iso_context *it_context_list;
 206         u64 ir_context_channels; /* unoccupied channels */
 207         u32 ir_context_mask;     /* unoccupied IR contexts */
 208         struct iso_context *ir_context_list;
 209         u64 mc_channels; /* channels in use by the multichannel IR context */
 210         bool mc_allocated;
 211
 212         __be32    *config_rom;
 213         dma_addr_t config_rom_bus;
 214         __be32    *next_config_rom;
 215         dma_addr_t next_config_rom_bus;
 216         __be32     next_header;
 217
 218         __le32    *self_id_cpu;
 219         dma_addr_t self_id_bus;
 220         struct tasklet_struct bus_reset_tasklet;
 221
 222         u32 self_id_buffer[512];
 223 };
 224
 225 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 226 {
 227         return container_of(card, struct fw_ohci, card);
 228 }
 229
 230 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 231 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 232 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 233 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 234 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 235 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 236
 237 #define CONTEXT_RUN     0x8000
 238 #define CONTEXT_WAKE    0x1000
 239 #define CONTEXT_DEAD    0x0800
 240 #define CONTEXT_ACTIVE  0x0400
 241
 242 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 243 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 244 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 245
 246 #define OHCI1394_REGISTER_SIZE          0x800
 247 #define OHCI_LOOP_COUNT                 500
 248 #define OHCI1394_PCI_HCI_Control        0x40
 249 #define SELF_ID_BUF_SIZE                0x800
 250 #define OHCI_TCODE_PHY_PACKET           0x0e
 251 #define OHCI_VERSION_1_1                0x010010
 252
 253 static char ohci_driver_name[] = KBUILD_MODNAME;
 254
 255 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 256 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 257 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 258
 259 #define QUIRK_CYCLE_TIMER               1
 260 #define QUIRK_RESET_PACKET              2
 261 #define QUIRK_BE_HEADERS                4
 262 #define QUIRK_NO_1394A                  8
 263 #define QUIRK_NO_MSI                    16
 264
 265 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 266 static const struct {
 267         unsigned short vendor, device, revision, flags;
 268 } ohci_quirks[] = {
 269         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 270                 QUIRK_CYCLE_TIMER},
 271
 272         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 273                 QUIRK_BE_HEADERS},
 274
 275         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 276                 QUIRK_NO_MSI},
 277
 278         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 279                 QUIRK_NO_MSI},
 280
 281         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 282                 QUIRK_CYCLE_TIMER},
 283
 284         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 285                 QUIRK_CYCLE_TIMER},
 286
 287         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 288                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 289
 290         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 291                 QUIRK_RESET_PACKET},
 292
 293         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 294                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 295 };
 296
 297 /* This overrides anything that was found in ohci_quirks[]. */
 298 static int param_quirks;
 299 module_param_named(quirks, param_quirks, int, 0644);
 300 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 301         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 302         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 303         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 304         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 305         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 306         ")");
 307
 308 #define OHCI_PARAM_DEBUG_AT_AR          1
 309 #define OHCI_PARAM_DEBUG_SELFIDS        2
 310 #define OHCI_PARAM_DEBUG_IRQS           4
 311 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 312
 313 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 314
 315 static int param_debug;
 316 module_param_named(debug, param_debug, int, 0644);
 317 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 318         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 319         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 320         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 321         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 322         ", or a combination, or all = -1)");
 323
 324 static void log_irqs(u32 evt)
 325 {
 326         if (likely(!(param_debug &
 327                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 328                 return;
 329
 330         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 331             !(evt & OHCI1394_busReset))
 332                 return;
 333
 334         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 335             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 336             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 337             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 338             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 339             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 340             evt & OHCI1394_isochRx              ? " IR"                 : "",
 341             evt & OHCI1394_isochTx              ? " IT"                 : "",
 342             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 343             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 344             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 345             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 346             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 347             evt & OHCI1394_busReset             ? " busReset"           : "",
 348             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 349                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 350                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 351                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 352                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 353                     OHCI1394_cycleInconsistent |
 354                     OHCI1394_regAccessFail | OHCI1394_busReset)
 355                                                 ? " ?"                  : "");
 356 }
 357
 358 static const char *speed[] = {
 359         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 360 };
 361 static const char *power[] = {
 362         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 363         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 364 };
 365 static const char port[] = { '.', '-', 'p', 'c', };
 366
 367 static char _p(u32 *s, int shift)
 368 {
 369         return port[*s >> shift & 3];
 370 }
 371
 372 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 373 {
 374         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 375                 return;
 376
 377         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 378                   self_id_count, generation, node_id);
 379
 380         for (; self_id_count--; ++s)
 381                 if ((*s & 1 << 23) == 0)
 382                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 383                             "%s gc=%d %s %s%s%s\n",
 384                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 385                             speed[*s >> 14 & 3], *s >> 16 & 63,
 386                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 387                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 388                 else
 389                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 390                             *s, *s >> 24 & 63,
 391                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 392                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 393 }
 394
 395 static const char *evts[] = {
 396         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 397         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 398         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 399         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 400         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 401         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 402         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 403         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 404         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 405         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 406         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 407         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 408         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 409         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 410         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 411         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 412         [0x20] = "pending/cancelled",
 413 };
 414 static const char *tcodes[] = {
 415         [0x0] = "QW req",               [0x1] = "BW req",
 416         [0x2] = "W resp",               [0x3] = "-reserved-",
 417         [0x4] = "QR req",               [0x5] = "BR req",
 418         [0x6] = "QR resp",              [0x7] = "BR resp",
 419         [0x8] = "cycle start",          [0x9] = "Lk req",
 420         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 421         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 422         [0xe] = "link internal",        [0xf] = "-reserved-",
 423 };
 424
 425 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 426 {
 427         int tcode = header[0] >> 4 & 0xf;
 428         char specific[12];
 429
 430         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 431                 return;
 432
 433         if (unlikely(evt >= ARRAY_SIZE(evts)))
 434                         evt = 0x1f;
 435
 436         if (evt == OHCI1394_evt_bus_reset) {
 437                 fw_notify("A%c evt_bus_reset, generation %d\n",
 438                     dir, (header[2] >> 16) & 0xff);
 439                 return;
 440         }
 441
 442         switch (tcode) {
 443         case 0x0: case 0x6: case 0x8:
 444                 snprintf(specific, sizeof(specific), " = %08x",
 445                          be32_to_cpu((__force __be32)header[3]));
 446                 break;
 447         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 448                 snprintf(specific, sizeof(specific), " %x,%x",
 449                          header[3] >> 16, header[3] & 0xffff);
 450                 break;
 451         default:
 452                 specific[0] = '\0';
 453         }
 454
 455         switch (tcode) {
 456         case 0xa:
 457                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 458                 break;
 459         case 0xe:
 460                 fw_notify("A%c %s, PHY %08x %08x\n",
 461                           dir, evts[evt], header[1], header[2]);
 462                 break;
 463         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 464                 fw_notify("A%c spd %x tl %02x, "
 465                     "%04x -> %04x, %s, "
 466                     "%s, %04x%08x%s\n",
 467                     dir, speed, header[0] >> 10 & 0x3f,
 468                     header[1] >> 16, header[0] >> 16, evts[evt],
 469                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 470                 break;
 471         default:
 472                 fw_notify("A%c spd %x tl %02x, "
 473                     "%04x -> %04x, %s, "
 474                     "%s%s\n",
 475                     dir, speed, header[0] >> 10 & 0x3f,
 476                     header[1] >> 16, header[0] >> 16, evts[evt],
 477                     tcodes[tcode], specific);
 478         }
 479 }
 480
 481 #else
 482
 483 #define param_debug 0
 484 static inline void log_irqs(u32 evt) {}
 485 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 486 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 487
 488 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 489
 490 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 491 {
 492         writel(data, ohci->registers + offset);
 493 }
 494
 495 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 496 {
 497         return readl(ohci->registers + offset);
 498 }
 499
 500 static inline void flush_writes(const struct fw_ohci *ohci)
 501 {
 502         /* Do a dummy read to flush writes. */
 503         reg_read(ohci, OHCI1394_Version);
 504 }
 505
 506 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 507 {
 508         u32 val;
 509         int i;
 510
 511         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 512         for (i = 0; i < 3 + 100; i++) {
 513                 val = reg_read(ohci, OHCI1394_PhyControl);
 514                 if (val & OHCI1394_PhyControl_ReadDone)
 515                         return OHCI1394_PhyControl_ReadData(val);
 516
 517                 /*
 518                  * Try a few times without waiting.  Sleeping is necessary
 519                  * only when the link/PHY interface is busy.
 520                  */
 521                 if (i >= 3)
 522                         msleep(1);
 523         }
 524         fw_error("failed to read phy reg\n");
 525
 526         return -EBUSY;
 527 }
 528
 529 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 530 {
 531         int i;
 532
 533         reg_write(ohci, OHCI1394_PhyControl,
 534                   OHCI1394_PhyControl_Write(addr, val));
 535         for (i = 0; i < 3 + 100; i++) {
 536                 val = reg_read(ohci, OHCI1394_PhyControl);
 537                 if (!(val & OHCI1394_PhyControl_WritePending))
 538                         return 0;
 539
 540                 if (i >= 3)
 541                         msleep(1);
 542         }
 543         fw_error("failed to write phy reg\n");
 544
 545         return -EBUSY;
 546 }
 547
 548 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 549                           int clear_bits, int set_bits)
 550 {
 551         int ret = read_phy_reg(ohci, addr);
 552         if (ret < 0)
 553                 return ret;
 554
 555         /*
 556          * The interrupt status bits are cleared by writing a one bit.
 557          * Avoid clearing them unless explicitly requested in set_bits.
 558          */
 559         if (addr == 5)
 560                 clear_bits |= PHY_INT_STATUS_BITS;
 561
 562         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 563 }
 564
 565 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 566 {
 567         int ret;
 568
 569         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 570         if (ret < 0)
 571                 return ret;
 572
 573         return read_phy_reg(ohci, addr);
 574 }
 575
 576 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 577 {
 578         struct fw_ohci *ohci = fw_ohci(card);
 579         int ret;
 580
 581         mutex_lock(&ohci->phy_reg_mutex);
 582         ret = read_phy_reg(ohci, addr);
 583         mutex_unlock(&ohci->phy_reg_mutex);
 584
 585         return ret;
 586 }
 587
 588 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 589                                int clear_bits, int set_bits)
 590 {
 591         struct fw_ohci *ohci = fw_ohci(card);
 592         int ret;
 593
 594         mutex_lock(&ohci->phy_reg_mutex);
 595         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 596         mutex_unlock(&ohci->phy_reg_mutex);
 597
 598         return ret;
 599 }
 600
 601 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 602 {
 603         return page_private(ctx->pages[i]);
 604 }
 605
 606 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 607 {
 608         struct descriptor *d;
 609
 610         d = &ctx->descriptors[index];
 611         d->branch_address  &= cpu_to_le32(~0xf);
 612         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 613         d->transfer_status =  0;
 614
 615         wmb(); /* finish init of new descriptors before branch_address update */
 616         d = &ctx->descriptors[ctx->last_buffer_index];
 617         d->branch_address  |= cpu_to_le32(1);
 618
 619         ctx->last_buffer_index = index;
 620
 621         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 622         flush_writes(ctx->ohci);
 623 }
 624
 625 static void ar_context_release(struct ar_context *ctx)
 626 {
 627         unsigned int i;
 628
 629         if (ctx->buffer)
 630                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 631
 632         for (i = 0; i < AR_BUFFERS; i++)
 633                 if (ctx->pages[i]) {
 634                         dma_unmap_page(ctx->ohci->card.device,
 635                                        ar_buffer_bus(ctx, i),
 636                                        PAGE_SIZE, DMA_FROM_DEVICE);
 637                         __free_page(ctx->pages[i]);
 638                 }
 639 }
 640
 641 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 642 {
 643         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 644                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 645                 flush_writes(ctx->ohci);
 646
 647                 fw_error("AR error: %s; DMA stopped\n", error_msg);
 648         }
 649         /* FIXME: restart? */
 650 }
 651
 652 static inline unsigned int ar_next_buffer_index(unsigned int index)
 653 {
 654         return (index + 1) % AR_BUFFERS;
 655 }
 656
 657 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 658 {
 659         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 660 }
 661
 662 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 663 {
 664         return ar_next_buffer_index(ctx->last_buffer_index);
 665 }
 666
 667 /*
 668  * We search for the buffer that contains the last AR packet DMA data written
 669  * by the controller.
 670  */
 671 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 672                                                  unsigned int *buffer_offset)
 673 {
 674         unsigned int i, next_i, last = ctx->last_buffer_index;
 675         __le16 res_count, next_res_count;
 676
 677         i = ar_first_buffer_index(ctx);
 678         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 679
 680         /* A buffer that is not yet completely filled must be the last one. */
 681         while (i != last && res_count == 0) {
 682
 683                 /* Peek at the next descriptor. */
 684                 next_i = ar_next_buffer_index(i);
 685                 rmb(); /* read descriptors in order */
 686                 next_res_count = ACCESS_ONCE(
 687                                 ctx->descriptors[next_i].res_count);
 688                 /*
 689                  * If the next descriptor is still empty, we must stop at this
 690                  * descriptor.
 691                  */
 692                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 693                         /*
 694                          * The exception is when the DMA data for one packet is
 695                          * split over three buffers; in this case, the middle
 696                          * buffer's descriptor might be never updated by the
 697                          * controller and look still empty, and we have to peek
 698                          * at the third one.
 699                          */
 700                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 701                                 next_i = ar_next_buffer_index(next_i);
 702                                 rmb();
 703                                 next_res_count = ACCESS_ONCE(
 704                                         ctx->descriptors[next_i].res_count);
 705                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 706                                         goto next_buffer_is_active;
 707                         }
 708
 709                         break;
 710                 }
 711
 712 next_buffer_is_active:
 713                 i = next_i;
 714                 res_count = next_res_count;
 715         }
 716
 717         rmb(); /* read res_count before the DMA data */
 718
 719         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 720         if (*buffer_offset > PAGE_SIZE) {
 721                 *buffer_offset = 0;
 722                 ar_context_abort(ctx, "corrupted descriptor");
 723         }
 724
 725         return i;
 726 }
 727
 728 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 729                                     unsigned int end_buffer_index,
 730                                     unsigned int end_buffer_offset)
 731 {
 732         unsigned int i;
 733
 734         i = ar_first_buffer_index(ctx);
 735         while (i != end_buffer_index) {
 736                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 737                                         ar_buffer_bus(ctx, i),
 738                                         PAGE_SIZE, DMA_FROM_DEVICE);
 739                 i = ar_next_buffer_index(i);
 740         }
 741         if (end_buffer_offset > 0)
 742                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 743                                         ar_buffer_bus(ctx, i),
 744                                         end_buffer_offset, DMA_FROM_DEVICE);
 745 }
 746
 747 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 748 #define cond_le32_to_cpu(v) \
 749         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 750 #else
 751 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 752 #endif
 753
 754 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 755 {
 756         struct fw_ohci *ohci = ctx->ohci;
 757         struct fw_packet p;
 758         u32 status, length, tcode;
 759         int evt;
 760
 761         p.header[0] = cond_le32_to_cpu(buffer[0]);
 762         p.header[1] = cond_le32_to_cpu(buffer[1]);
 763         p.header[2] = cond_le32_to_cpu(buffer[2]);
 764
 765         tcode = (p.header[0] >> 4) & 0x0f;
 766         switch (tcode) {
 767         case TCODE_WRITE_QUADLET_REQUEST:
 768         case TCODE_READ_QUADLET_RESPONSE:
 769                 p.header[3] = (__force __u32) buffer[3];
 770                 p.header_length = 16;
 771                 p.payload_length = 0;
 772                 break;
 773
 774         case TCODE_READ_BLOCK_REQUEST :
 775                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 776                 p.header_length = 16;
 777                 p.payload_length = 0;
 778                 break;
 779
 780         case TCODE_WRITE_BLOCK_REQUEST:
 781         case TCODE_READ_BLOCK_RESPONSE:
 782         case TCODE_LOCK_REQUEST:
 783         case TCODE_LOCK_RESPONSE:
 784                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 785                 p.header_length = 16;
 786                 p.payload_length = p.header[3] >> 16;
 787                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 788                         ar_context_abort(ctx, "invalid packet length");
 789                         return NULL;
 790                 }
 791                 break;
 792
 793         case TCODE_WRITE_RESPONSE:
 794         case TCODE_READ_QUADLET_REQUEST:
 795         case OHCI_TCODE_PHY_PACKET:
 796                 p.header_length = 12;
 797                 p.payload_length = 0;
 798                 break;
 799
 800         default:
 801                 ar_context_abort(ctx, "invalid tcode");
 802                 return NULL;
 803         }
 804
 805         p.payload = (void *) buffer + p.header_length;
 806
 807         /* FIXME: What to do about evt_* errors? */
 808         length = (p.header_length + p.payload_length + 3) / 4;
 809         status = cond_le32_to_cpu(buffer[length]);
 810         evt    = (status >> 16) & 0x1f;
 811
 812         p.ack        = evt - 16;
 813         p.speed      = (status >> 21) & 0x7;
 814         p.timestamp  = status & 0xffff;
 815         p.generation = ohci->request_generation;
 816
 817         log_ar_at_event('R', p.speed, p.header, evt);
 818
 819         /*
 820          * Several controllers, notably from NEC and VIA, forget to
 821          * write ack_complete status at PHY packet reception.
 822          */
 823         if (evt == OHCI1394_evt_no_status &&
 824             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 825                 p.ack = ACK_COMPLETE;
 826
 827         /*
 828          * The OHCI bus reset handler synthesizes a PHY packet with
 829          * the new generation number when a bus reset happens (see
 830          * section 8.4.2.3).  This helps us determine when a request
 831          * was received and make sure we send the response in the same
 832          * generation.  We only need this for requests; for responses
 833          * we use the unique tlabel for finding the matching
 834          * request.
 835          *
 836          * Alas some chips sometimes emit bus reset packets with a
 837          * wrong generation.  We set the correct generation for these
 838          * at a slightly incorrect time (in bus_reset_tasklet).
 839          */
 840         if (evt == OHCI1394_evt_bus_reset) {
 841                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 842                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 843         } else if (ctx == &ohci->ar_request_ctx) {
 844                 fw_core_handle_request(&ohci->card, &p);
 845         } else {
 846                 fw_core_handle_response(&ohci->card, &p);
 847         }
 848
 849         return buffer + length + 1;
 850 }
 851
 852 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 853 {
 854         void *next;
 855
 856         while (p < end) {
 857                 next = handle_ar_packet(ctx, p);
 858                 if (!next)
 859                         return p;
 860                 p = next;
 861         }
 862
 863         return p;
 864 }
 865
 866 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 867 {
 868         unsigned int i;
 869
 870         i = ar_first_buffer_index(ctx);
 871         while (i != end_buffer) {
 872                 dma_sync_single_for_device(ctx->ohci->card.device,
 873                                            ar_buffer_bus(ctx, i),
 874                                            PAGE_SIZE, DMA_FROM_DEVICE);
 875                 ar_context_link_page(ctx, i);
 876                 i = ar_next_buffer_index(i);
 877         }
 878 }
 879
 880 static void ar_context_tasklet(unsigned long data)
 881 {
 882         struct ar_context *ctx = (struct ar_context *)data;
 883         unsigned int end_buffer_index, end_buffer_offset;
 884         void *p, *end;
 885
 886         p = ctx->pointer;
 887         if (!p)
 888                 return;
 889
 890         end_buffer_index = ar_search_last_active_buffer(ctx,
 891                                                         &end_buffer_offset);
 892         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 893         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 894
 895         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 896                 /*
 897                  * The filled part of the overall buffer wraps around; handle
 898                  * all packets up to the buffer end here.  If the last packet
 899                  * wraps around, its tail will be visible after the buffer end
 900                  * because the buffer start pages are mapped there again.
 901                  */
 902                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 903                 p = handle_ar_packets(ctx, p, buffer_end);
 904                 if (p < buffer_end)
 905                         goto error;
 906                 /* adjust p to point back into the actual buffer */
 907                 p -= AR_BUFFERS * PAGE_SIZE;
 908         }
 909
 910         p = handle_ar_packets(ctx, p, end);
 911         if (p != end) {
 912                 if (p > end)
 913                         ar_context_abort(ctx, "inconsistent descriptor");
 914                 goto error;
 915         }
 916
 917         ctx->pointer = p;
 918         ar_recycle_buffers(ctx, end_buffer_index);
 919
 920         return;
 921
 922 error:
 923         ctx->pointer = NULL;
 924 }
 925
 926 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 927                            unsigned int descriptors_offset, u32 regs)
 928 {
 929         unsigned int i;
 930         dma_addr_t dma_addr;
 931         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 932         struct descriptor *d;
 933
 934         ctx->regs        = regs;
 935         ctx->ohci        = ohci;
 936         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 937
 938         for (i = 0; i < AR_BUFFERS; i++) {
 939                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 940                 if (!ctx->pages[i])
 941                         goto out_of_memory;
 942                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 943                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 944                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 945                         __free_page(ctx->pages[i]);
 946                         ctx->pages[i] = NULL;
 947                         goto out_of_memory;
 948                 }
 949                 set_page_private(ctx->pages[i], dma_addr);
 950         }
 951
 952         for (i = 0; i < AR_BUFFERS; i++)
 953                 pages[i]              = ctx->pages[i];
 954         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 955                 pages[AR_BUFFERS + i] = ctx->pages[i];
 956         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 957                                  -1, PAGE_KERNEL_RO);
 958         if (!ctx->buffer)
 959                 goto out_of_memory;
 960
 961         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
 962         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
 963
 964         for (i = 0; i < AR_BUFFERS; i++) {
 965                 d = &ctx->descriptors[i];
 966                 d->req_count      = cpu_to_le16(PAGE_SIZE);
 967                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 968                                                 DESCRIPTOR_STATUS |
 969                                                 DESCRIPTOR_BRANCH_ALWAYS);
 970                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
 971                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
 972                         ar_next_buffer_index(i) * sizeof(struct descriptor));
 973         }
 974
 975         return 0;
 976
 977 out_of_memory:
 978         ar_context_release(ctx);
 979
 980         return -ENOMEM;
 981 }
 982
 983 static void ar_context_run(struct ar_context *ctx)
 984 {
 985         unsigned int i;
 986
 987         for (i = 0; i < AR_BUFFERS; i++)
 988                 ar_context_link_page(ctx, i);
 989
 990         ctx->pointer = ctx->buffer;
 991
 992         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
 993         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 994         flush_writes(ctx->ohci);
 995 }
 996
 997 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 998 {
 999         int b, key;
1000
1001         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1002         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1003
1004         /* figure out which descriptor the branch address goes in */
1005         if (z == 2 && (b == 3 || key == 2))
1006                 return d;
1007         else
1008                 return d + z - 1;
1009 }
1010
1011 static void context_tasklet(unsigned long data)
1012 {
1013         struct context *ctx = (struct context *) data;
1014         struct descriptor *d, *last;
1015         u32 address;
1016         int z;
1017         struct descriptor_buffer *desc;
1018
1019         desc = list_entry(ctx->buffer_list.next,
1020                         struct descriptor_buffer, list);
1021         last = ctx->last;
1022         while (last->branch_address != 0) {
1023                 struct descriptor_buffer *old_desc = desc;
1024                 address = le32_to_cpu(last->branch_address);
1025                 z = address & 0xf;
1026                 address &= ~0xf;
1027
1028                 /* If the branch address points to a buffer outside of the
1029                  * current buffer, advance to the next buffer. */
1030                 if (address < desc->buffer_bus ||
1031                                 address >= desc->buffer_bus + desc->used)
1032                         desc = list_entry(desc->list.next,
1033                                         struct descriptor_buffer, list);
1034                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1035                 last = find_branch_descriptor(d, z);
1036
1037                 if (!ctx->callback(ctx, d, last))
1038                         break;
1039
1040                 if (old_desc != desc) {
1041                         /* If we've advanced to the next buffer, move the
1042                          * previous buffer to the free list. */
1043                         unsigned long flags;
1044                         old_desc->used = 0;
1045                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1046                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1047                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1048                 }
1049                 ctx->last = last;
1050         }
1051 }
1052
1053 /*
1054  * Allocate a new buffer and add it to the list of free buffers for this
1055  * context.  Must be called with ohci->lock held.
1056  */
1057 static int context_add_buffer(struct context *ctx)
1058 {
1059         struct descriptor_buffer *desc;
1060         dma_addr_t uninitialized_var(bus_addr);
1061         int offset;
1062
1063         /*
1064          * 16MB of descriptors should be far more than enough for any DMA
1065          * program.  This will catch run-away userspace or DoS attacks.
1066          */
1067         if (ctx->total_allocation >= 16*1024*1024)
1068                 return -ENOMEM;
1069
1070         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1071                         &bus_addr, GFP_ATOMIC);
1072         if (!desc)
1073                 return -ENOMEM;
1074
1075         offset = (void *)&desc->buffer - (void *)desc;
1076         desc->buffer_size = PAGE_SIZE - offset;
1077         desc->buffer_bus = bus_addr + offset;
1078         desc->used = 0;
1079
1080         list_add_tail(&desc->list, &ctx->buffer_list);
1081         ctx->total_allocation += PAGE_SIZE;
1082
1083         return 0;
1084 }
1085
1086 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1087                         u32 regs, descriptor_callback_t callback)
1088 {
1089         ctx->ohci = ohci;
1090         ctx->regs = regs;
1091         ctx->total_allocation = 0;
1092
1093         INIT_LIST_HEAD(&ctx->buffer_list);
1094         if (context_add_buffer(ctx) < 0)
1095                 return -ENOMEM;
1096
1097         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1098                         struct descriptor_buffer, list);
1099
1100         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1101         ctx->callback = callback;
1102
1103         /*
1104          * We put a dummy descriptor in the buffer that has a NULL
1105          * branch address and looks like it's been sent.  That way we
1106          * have a descriptor to append DMA programs to.
1107          */
1108         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1109         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1110         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1111         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1112         ctx->last = ctx->buffer_tail->buffer;
1113         ctx->prev = ctx->buffer_tail->buffer;
1114
1115         return 0;
1116 }
1117
1118 static void context_release(struct context *ctx)
1119 {
1120         struct fw_card *card = &ctx->ohci->card;
1121         struct descriptor_buffer *desc, *tmp;
1122
1123         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1124                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1125                         desc->buffer_bus -
1126                         ((void *)&desc->buffer - (void *)desc));
1127 }
1128
1129 /* Must be called with ohci->lock held */
1130 static struct descriptor *context_get_descriptors(struct context *ctx,
1131                                                   int z, dma_addr_t *d_bus)
1132 {
1133         struct descriptor *d = NULL;
1134         struct descriptor_buffer *desc = ctx->buffer_tail;
1135
1136         if (z * sizeof(*d) > desc->buffer_size)
1137                 return NULL;
1138
1139         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1140                 /* No room for the descriptor in this buffer, so advance to the
1141                  * next one. */
1142
1143                 if (desc->list.next == &ctx->buffer_list) {
1144                         /* If there is no free buffer next in the list,
1145                          * allocate one. */
1146                         if (context_add_buffer(ctx) < 0)
1147                                 return NULL;
1148                 }
1149                 desc = list_entry(desc->list.next,
1150                                 struct descriptor_buffer, list);
1151                 ctx->buffer_tail = desc;
1152         }
1153
1154         d = desc->buffer + desc->used / sizeof(*d);
1155         memset(d, 0, z * sizeof(*d));
1156         *d_bus = desc->buffer_bus + desc->used;
1157
1158         return d;
1159 }
1160
1161 static void context_run(struct context *ctx, u32 extra)
1162 {
1163         struct fw_ohci *ohci = ctx->ohci;
1164
1165         reg_write(ohci, COMMAND_PTR(ctx->regs),
1166                   le32_to_cpu(ctx->last->branch_address));
1167         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1168         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1169         flush_writes(ohci);
1170 }
1171
1172 static void context_append(struct context *ctx,
1173                            struct descriptor *d, int z, int extra)
1174 {
1175         dma_addr_t d_bus;
1176         struct descriptor_buffer *desc = ctx->buffer_tail;
1177
1178         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1179
1180         desc->used += (z + extra) * sizeof(*d);
1181
1182         wmb(); /* finish init of new descriptors before branch_address update */
1183         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1184         ctx->prev = find_branch_descriptor(d, z);
1185
1186         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1187         flush_writes(ctx->ohci);
1188 }
1189
1190 static void context_stop(struct context *ctx)
1191 {
1192         u32 reg;
1193         int i;
1194
1195         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1196         flush_writes(ctx->ohci);
1197
1198         for (i = 0; i < 10; i++) {
1199                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1200                 if ((reg & CONTEXT_ACTIVE) == 0)
1201                         return;
1202
1203                 mdelay(1);
1204         }
1205         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1206 }
1207
1208 struct driver_data {
1209         struct fw_packet *packet;
1210 };
1211
1212 /*
1213  * This function apppends a packet to the DMA queue for transmission.
1214  * Must always be called with the ochi->lock held to ensure proper
1215  * generation handling and locking around packet queue manipulation.
1216  */
1217 static int at_context_queue_packet(struct context *ctx,
1218                                    struct fw_packet *packet)
1219 {
1220         struct fw_ohci *ohci = ctx->ohci;
1221         dma_addr_t d_bus, uninitialized_var(payload_bus);
1222         struct driver_data *driver_data;
1223         struct descriptor *d, *last;
1224         __le32 *header;
1225         int z, tcode;
1226         u32 reg;
1227
1228         d = context_get_descriptors(ctx, 4, &d_bus);
1229         if (d == NULL) {
1230                 packet->ack = RCODE_SEND_ERROR;
1231                 return -1;
1232         }
1233
1234         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1235         d[0].res_count = cpu_to_le16(packet->timestamp);
1236
1237         /*
1238          * The DMA format for asyncronous link packets is different
1239          * from the IEEE1394 layout, so shift the fields around
1240          * accordingly.
1241          */
1242
1243         tcode = (packet->header[0] >> 4) & 0x0f;
1244         header = (__le32 *) &d[1];
1245         switch (tcode) {
1246         case TCODE_WRITE_QUADLET_REQUEST:
1247         case TCODE_WRITE_BLOCK_REQUEST:
1248         case TCODE_WRITE_RESPONSE:
1249         case TCODE_READ_QUADLET_REQUEST:
1250         case TCODE_READ_BLOCK_REQUEST:
1251         case TCODE_READ_QUADLET_RESPONSE:
1252         case TCODE_READ_BLOCK_RESPONSE:
1253         case TCODE_LOCK_REQUEST:
1254         case TCODE_LOCK_RESPONSE:
1255                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1256                                         (packet->speed << 16));
1257                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1258                                         (packet->header[0] & 0xffff0000));
1259                 header[2] = cpu_to_le32(packet->header[2]);
1260
1261                 if (TCODE_IS_BLOCK_PACKET(tcode))
1262                         header[3] = cpu_to_le32(packet->header[3]);
1263                 else
1264                         header[3] = (__force __le32) packet->header[3];
1265
1266                 d[0].req_count = cpu_to_le16(packet->header_length);
1267                 break;
1268
1269         case TCODE_LINK_INTERNAL:
1270                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1271                                         (packet->speed << 16));
1272                 header[1] = cpu_to_le32(packet->header[1]);
1273                 header[2] = cpu_to_le32(packet->header[2]);
1274                 d[0].req_count = cpu_to_le16(12);
1275
1276                 if (is_ping_packet(&packet->header[1]))
1277                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1278                 break;
1279
1280         case TCODE_STREAM_DATA:
1281                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1282                                         (packet->speed << 16));
1283                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1284                 d[0].req_count = cpu_to_le16(8);
1285                 break;
1286
1287         default:
1288                 /* BUG(); */
1289                 packet->ack = RCODE_SEND_ERROR;
1290                 return -1;
1291         }
1292
1293         driver_data = (struct driver_data *) &d[3];
1294         driver_data->packet = packet;
1295         packet->driver_data = driver_data;
1296
1297         if (packet->payload_length > 0) {
1298                 payload_bus =
1299                         dma_map_single(ohci->card.device, packet->payload,
1300                                        packet->payload_length, DMA_TO_DEVICE);
1301                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1302                         packet->ack = RCODE_SEND_ERROR;
1303                         return -1;
1304                 }
1305                 packet->payload_bus     = payload_bus;
1306                 packet->payload_mapped  = true;
1307
1308                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1309                 d[2].data_address = cpu_to_le32(payload_bus);
1310                 last = &d[2];
1311                 z = 3;
1312         } else {
1313                 last = &d[0];
1314                 z = 2;
1315         }
1316
1317         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1318                                      DESCRIPTOR_IRQ_ALWAYS |
1319                                      DESCRIPTOR_BRANCH_ALWAYS);
1320
1321         /*
1322          * If the controller and packet generations don't match, we need to
1323          * bail out and try again.  If IntEvent.busReset is set, the AT context
1324          * is halted, so appending to the context and trying to run it is
1325          * futile.  Most controllers do the right thing and just flush the AT
1326          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1327          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1328          * up stalling out.  So we just bail out in software and try again
1329          * later, and everyone is happy.
1330          * FIXME: Document how the locking works.
1331          */
1332         if (ohci->generation != packet->generation ||
1333             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1334                 if (packet->payload_mapped)
1335                         dma_unmap_single(ohci->card.device, payload_bus,
1336                                          packet->payload_length, DMA_TO_DEVICE);
1337                 packet->ack = RCODE_GENERATION;
1338                 return -1;
1339         }
1340
1341         context_append(ctx, d, z, 4 - z);
1342
1343         /* If the context isn't already running, start it up. */
1344         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1345         if ((reg & CONTEXT_RUN) == 0)
1346                 context_run(ctx, 0);
1347
1348         return 0;
1349 }
1350
1351 static int handle_at_packet(struct context *context,
1352                             struct descriptor *d,
1353                             struct descriptor *last)
1354 {
1355         struct driver_data *driver_data;
1356         struct fw_packet *packet;
1357         struct fw_ohci *ohci = context->ohci;
1358         int evt;
1359
1360         if (last->transfer_status == 0)
1361                 /* This descriptor isn't done yet, stop iteration. */
1362                 return 0;
1363
1364         driver_data = (struct driver_data *) &d[3];
1365         packet = driver_data->packet;
1366         if (packet == NULL)
1367                 /* This packet was cancelled, just continue. */
1368                 return 1;
1369
1370         if (packet->payload_mapped)
1371                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1372                                  packet->payload_length, DMA_TO_DEVICE);
1373
1374         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1375         packet->timestamp = le16_to_cpu(last->res_count);
1376
1377         log_ar_at_event('T', packet->speed, packet->header, evt);
1378
1379         switch (evt) {
1380         case OHCI1394_evt_timeout:
1381                 /* Async response transmit timed out. */
1382                 packet->ack = RCODE_CANCELLED;
1383                 break;
1384
1385         case OHCI1394_evt_flushed:
1386                 /*
1387                  * The packet was flushed should give same error as
1388                  * when we try to use a stale generation count.
1389                  */
1390                 packet->ack = RCODE_GENERATION;
1391                 break;
1392
1393         case OHCI1394_evt_missing_ack:
1394                 /*
1395                  * Using a valid (current) generation count, but the
1396                  * node is not on the bus or not sending acks.
1397                  */
1398                 packet->ack = RCODE_NO_ACK;
1399                 break;
1400
1401         case ACK_COMPLETE + 0x10:
1402         case ACK_PENDING + 0x10:
1403         case ACK_BUSY_X + 0x10:
1404         case ACK_BUSY_A + 0x10:
1405         case ACK_BUSY_B + 0x10:
1406         case ACK_DATA_ERROR + 0x10:
1407         case ACK_TYPE_ERROR + 0x10:
1408                 packet->ack = evt - 0x10;
1409                 break;
1410
1411         default:
1412                 packet->ack = RCODE_SEND_ERROR;
1413                 break;
1414         }
1415
1416         packet->callback(packet, &ohci->card, packet->ack);
1417
1418         return 1;
1419 }
1420
1421 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1422 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1423 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1424 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1425 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1426
1427 static void handle_local_rom(struct fw_ohci *ohci,
1428                              struct fw_packet *packet, u32 csr)
1429 {
1430         struct fw_packet response;
1431         int tcode, length, i;
1432
1433         tcode = HEADER_GET_TCODE(packet->header[0]);
1434         if (TCODE_IS_BLOCK_PACKET(tcode))
1435                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1436         else
1437                 length = 4;
1438
1439         i = csr - CSR_CONFIG_ROM;
1440         if (i + length > CONFIG_ROM_SIZE) {
1441                 fw_fill_response(&response, packet->header,
1442                                  RCODE_ADDRESS_ERROR, NULL, 0);
1443         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1444                 fw_fill_response(&response, packet->header,
1445                                  RCODE_TYPE_ERROR, NULL, 0);
1446         } else {
1447                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1448                                  (void *) ohci->config_rom + i, length);
1449         }
1450
1451         fw_core_handle_response(&ohci->card, &response);
1452 }
1453
1454 static void handle_local_lock(struct fw_ohci *ohci,
1455                               struct fw_packet *packet, u32 csr)
1456 {
1457         struct fw_packet response;
1458         int tcode, length, ext_tcode, sel, try;
1459         __be32 *payload, lock_old;
1460         u32 lock_arg, lock_data;
1461
1462         tcode = HEADER_GET_TCODE(packet->header[0]);
1463         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1464         payload = packet->payload;
1465         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1466
1467         if (tcode == TCODE_LOCK_REQUEST &&
1468             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1469                 lock_arg = be32_to_cpu(payload[0]);
1470                 lock_data = be32_to_cpu(payload[1]);
1471         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1472                 lock_arg = 0;
1473                 lock_data = 0;
1474         } else {
1475                 fw_fill_response(&response, packet->header,
1476                                  RCODE_TYPE_ERROR, NULL, 0);
1477                 goto out;
1478         }
1479
1480         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1481         reg_write(ohci, OHCI1394_CSRData, lock_data);
1482         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1483         reg_write(ohci, OHCI1394_CSRControl, sel);
1484
1485         for (try = 0; try < 20; try++)
1486                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1487                         lock_old = cpu_to_be32(reg_read(ohci,
1488                                                         OHCI1394_CSRData));
1489                         fw_fill_response(&response, packet->header,
1490                                          RCODE_COMPLETE,
1491                                          &lock_old, sizeof(lock_old));
1492                         goto out;
1493                 }
1494
1495         fw_error("swap not done (CSR lock timeout)\n");
1496         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1497
1498  out:
1499         fw_core_handle_response(&ohci->card, &response);
1500 }
1501
1502 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1503 {
1504         u64 offset, csr;
1505
1506         if (ctx == &ctx->ohci->at_request_ctx) {
1507                 packet->ack = ACK_PENDING;
1508                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1509         }
1510
1511         offset =
1512                 ((unsigned long long)
1513                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1514                 packet->header[2];
1515         csr = offset - CSR_REGISTER_BASE;
1516
1517         /* Handle config rom reads. */
1518         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1519                 handle_local_rom(ctx->ohci, packet, csr);
1520         else switch (csr) {
1521         case CSR_BUS_MANAGER_ID:
1522         case CSR_BANDWIDTH_AVAILABLE:
1523         case CSR_CHANNELS_AVAILABLE_HI:
1524         case CSR_CHANNELS_AVAILABLE_LO:
1525                 handle_local_lock(ctx->ohci, packet, csr);
1526                 break;
1527         default:
1528                 if (ctx == &ctx->ohci->at_request_ctx)
1529                         fw_core_handle_request(&ctx->ohci->card, packet);
1530                 else
1531                         fw_core_handle_response(&ctx->ohci->card, packet);
1532                 break;
1533         }
1534
1535         if (ctx == &ctx->ohci->at_response_ctx) {
1536                 packet->ack = ACK_COMPLETE;
1537                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1538         }
1539 }
1540
1541 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1542 {
1543         unsigned long flags;
1544         int ret;
1545
1546         spin_lock_irqsave(&ctx->ohci->lock, flags);
1547
1548         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1549             ctx->ohci->generation == packet->generation) {
1550                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1551                 handle_local_request(ctx, packet);
1552                 return;
1553         }
1554
1555         ret = at_context_queue_packet(ctx, packet);
1556         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1557
1558         if (ret < 0)
1559                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1560
1561 }
1562
1563 static u32 cycle_timer_ticks(u32 cycle_timer)
1564 {
1565         u32 ticks;
1566
1567         ticks = cycle_timer & 0xfff;
1568         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1569         ticks += (3072 * 8000) * (cycle_timer >> 25);
1570
1571         return ticks;
1572 }
1573
1574 /*
1575  * Some controllers exhibit one or more of the following bugs when updating the
1576  * iso cycle timer register:
1577  *  - When the lowest six bits are wrapping around to zero, a read that happens
1578  *    at the same time will return garbage in the lowest ten bits.
1579  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1580  *    not incremented for about 60 ns.
1581  *  - Occasionally, the entire register reads zero.
1582  *
1583  * To catch these, we read the register three times and ensure that the
1584  * difference between each two consecutive reads is approximately the same, i.e.
1585  * less than twice the other.  Furthermore, any negative difference indicates an
1586  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1587  * execute, so we have enough precision to compute the ratio of the differences.)
1588  */
1589 static u32 get_cycle_time(struct fw_ohci *ohci)
1590 {
1591         u32 c0, c1, c2;
1592         u32 t0, t1, t2;
1593         s32 diff01, diff12;
1594         int i;
1595
1596         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1597
1598         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1599                 i = 0;
1600                 c1 = c2;
1601                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1602                 do {
1603                         c0 = c1;
1604                         c1 = c2;
1605                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1606                         t0 = cycle_timer_ticks(c0);
1607                         t1 = cycle_timer_ticks(c1);
1608                         t2 = cycle_timer_ticks(c2);
1609                         diff01 = t1 - t0;
1610                         diff12 = t2 - t1;
1611                 } while ((diff01 <= 0 || diff12 <= 0 ||
1612                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1613                          && i++ < 20);
1614         }
1615
1616         return c2;
1617 }
1618
1619 /*
1620  * This function has to be called at least every 64 seconds.  The bus_time
1621  * field stores not only the upper 25 bits of the BUS_TIME register but also
1622  * the most significant bit of the cycle timer in bit 6 so that we can detect
1623  * changes in this bit.
1624  */
1625 static u32 update_bus_time(struct fw_ohci *ohci)
1626 {
1627         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1628
1629         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1630                 ohci->bus_time += 0x40;
1631
1632         return ohci->bus_time | cycle_time_seconds;
1633 }
1634
1635 static void bus_reset_tasklet(unsigned long data)
1636 {
1637         struct fw_ohci *ohci = (struct fw_ohci *)data;
1638         int self_id_count, i, j, reg;
1639         int generation, new_generation;
1640         unsigned long flags;
1641         void *free_rom = NULL;
1642         dma_addr_t free_rom_bus = 0;
1643         bool is_new_root;
1644
1645         reg = reg_read(ohci, OHCI1394_NodeID);
1646         if (!(reg & OHCI1394_NodeID_idValid)) {
1647                 fw_notify("node ID not valid, new bus reset in progress\n");
1648                 return;
1649         }
1650         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1651                 fw_notify("malconfigured bus\n");
1652                 return;
1653         }
1654         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1655                                OHCI1394_NodeID_nodeNumber);
1656
1657         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1658         if (!(ohci->is_root && is_new_root))
1659                 reg_write(ohci, OHCI1394_LinkControlSet,
1660                           OHCI1394_LinkControl_cycleMaster);
1661         ohci->is_root = is_new_root;
1662
1663         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1664         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1665                 fw_notify("inconsistent self IDs\n");
1666                 return;
1667         }
1668         /*
1669          * The count in the SelfIDCount register is the number of
1670          * bytes in the self ID receive buffer.  Since we also receive
1671          * the inverted quadlets and a header quadlet, we shift one
1672          * bit extra to get the actual number of self IDs.
1673          */
1674         self_id_count = (reg >> 3) & 0xff;
1675         if (self_id_count == 0 || self_id_count > 252) {
1676                 fw_notify("inconsistent self IDs\n");
1677                 return;
1678         }
1679         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1680         rmb();
1681
1682         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1683                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1684                         fw_notify("inconsistent self IDs\n");
1685                         return;
1686                 }
1687                 ohci->self_id_buffer[j] =
1688                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1689         }
1690         rmb();
1691
1692         /*
1693          * Check the consistency of the self IDs we just read.  The
1694          * problem we face is that a new bus reset can start while we
1695          * read out the self IDs from the DMA buffer. If this happens,
1696          * the DMA buffer will be overwritten with new self IDs and we
1697          * will read out inconsistent data.  The OHCI specification
1698          * (section 11.2) recommends a technique similar to
1699          * linux/seqlock.h, where we remember the generation of the
1700          * self IDs in the buffer before reading them out and compare
1701          * it to the current generation after reading them out.  If
1702          * the two generations match we know we have a consistent set
1703          * of self IDs.
1704          */
1705
1706         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1707         if (new_generation != generation) {
1708                 fw_notify("recursive bus reset detected, "
1709                           "discarding self ids\n");
1710                 return;
1711         }
1712
1713         /* FIXME: Document how the locking works. */
1714         spin_lock_irqsave(&ohci->lock, flags);
1715
1716         ohci->generation = generation;
1717         context_stop(&ohci->at_request_ctx);
1718         context_stop(&ohci->at_response_ctx);
1719         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1720
1721         if (ohci->quirks & QUIRK_RESET_PACKET)
1722                 ohci->request_generation = generation;
1723
1724         /*
1725          * This next bit is unrelated to the AT context stuff but we
1726          * have to do it under the spinlock also.  If a new config rom
1727          * was set up before this reset, the old one is now no longer
1728          * in use and we can free it. Update the config rom pointers
1729          * to point to the current config rom and clear the
1730          * next_config_rom pointer so a new update can take place.
1731          */
1732
1733         if (ohci->next_config_rom != NULL) {
1734                 if (ohci->next_config_rom != ohci->config_rom) {
1735                         free_rom      = ohci->config_rom;
1736                         free_rom_bus  = ohci->config_rom_bus;
1737                 }
1738                 ohci->config_rom      = ohci->next_config_rom;
1739                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1740                 ohci->next_config_rom = NULL;
1741
1742                 /*
1743                  * Restore config_rom image and manually update
1744                  * config_rom registers.  Writing the header quadlet
1745                  * will indicate that the config rom is ready, so we
1746                  * do that last.
1747                  */
1748                 reg_write(ohci, OHCI1394_BusOptions,
1749                           be32_to_cpu(ohci->config_rom[2]));
1750                 ohci->config_rom[0] = ohci->next_header;
1751                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1752                           be32_to_cpu(ohci->next_header));
1753         }
1754
1755 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1756         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1757         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1758 #endif
1759
1760         spin_unlock_irqrestore(&ohci->lock, flags);
1761
1762         if (free_rom)
1763                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1764                                   free_rom, free_rom_bus);
1765
1766         log_selfids(ohci->node_id, generation,
1767                     self_id_count, ohci->self_id_buffer);
1768
1769         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1770                                  self_id_count, ohci->self_id_buffer,
1771                                  ohci->csr_state_setclear_abdicate);
1772         ohci->csr_state_setclear_abdicate = false;
1773 }
1774
1775 static irqreturn_t irq_handler(int irq, void *data)
1776 {
1777         struct fw_ohci *ohci = data;
1778         u32 event, iso_event;
1779         int i;
1780
1781         event = reg_read(ohci, OHCI1394_IntEventClear);
1782
1783         if (!event || !~event)
1784                 return IRQ_NONE;
1785
1786         /*
1787          * busReset and postedWriteErr must not be cleared yet
1788          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1789          */
1790         reg_write(ohci, OHCI1394_IntEventClear,
1791                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1792         log_irqs(event);
1793
1794         if (event & OHCI1394_selfIDComplete)
1795                 tasklet_schedule(&ohci->bus_reset_tasklet);
1796
1797         if (event & OHCI1394_RQPkt)
1798                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1799
1800         if (event & OHCI1394_RSPkt)
1801                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1802
1803         if (event & OHCI1394_reqTxComplete)
1804                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1805
1806         if (event & OHCI1394_respTxComplete)
1807                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1808
1809         if (event & OHCI1394_isochRx) {
1810                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1811                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1812
1813                 while (iso_event) {
1814                         i = ffs(iso_event) - 1;
1815                         tasklet_schedule(
1816                                 &ohci->ir_context_list[i].context.tasklet);
1817                         iso_event &= ~(1 << i);
1818                 }
1819         }
1820
1821         if (event & OHCI1394_isochTx) {
1822                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1823                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1824
1825                 while (iso_event) {
1826                         i = ffs(iso_event) - 1;
1827                         tasklet_schedule(
1828                                 &ohci->it_context_list[i].context.tasklet);
1829                         iso_event &= ~(1 << i);
1830                 }
1831         }
1832
1833         if (unlikely(event & OHCI1394_regAccessFail))
1834                 fw_error("Register access failure - "
1835                          "please notify linux1394-devel@lists.sf.net\n");
1836
1837         if (unlikely(event & OHCI1394_postedWriteErr)) {
1838                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1839                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1840                 reg_write(ohci, OHCI1394_IntEventClear,
1841                           OHCI1394_postedWriteErr);
1842                 fw_error("PCI posted write error\n");
1843         }
1844
1845         if (unlikely(event & OHCI1394_cycleTooLong)) {
1846                 if (printk_ratelimit())
1847                         fw_notify("isochronous cycle too long\n");
1848                 reg_write(ohci, OHCI1394_LinkControlSet,
1849                           OHCI1394_LinkControl_cycleMaster);
1850         }
1851
1852         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1853                 /*
1854                  * We need to clear this event bit in order to make
1855                  * cycleMatch isochronous I/O work.  In theory we should
1856                  * stop active cycleMatch iso contexts now and restart
1857                  * them at least two cycles later.  (FIXME?)
1858                  */
1859                 if (printk_ratelimit())
1860                         fw_notify("isochronous cycle inconsistent\n");
1861         }
1862
1863         if (event & OHCI1394_cycle64Seconds) {
1864                 spin_lock(&ohci->lock);
1865                 update_bus_time(ohci);
1866                 spin_unlock(&ohci->lock);
1867         } else
1868                 flush_writes(ohci);
1869
1870         return IRQ_HANDLED;
1871 }
1872
1873 static int software_reset(struct fw_ohci *ohci)
1874 {
1875         int i;
1876
1877         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1878
1879         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1880                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1881                      OHCI1394_HCControl_softReset) == 0)
1882                         return 0;
1883                 msleep(1);
1884         }
1885
1886         return -EBUSY;
1887 }
1888
1889 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1890 {
1891         size_t size = length * 4;
1892
1893         memcpy(dest, src, size);
1894         if (size < CONFIG_ROM_SIZE)
1895                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1896 }
1897
1898 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1899 {
1900         bool enable_1394a;
1901         int ret, clear, set, offset;
1902
1903         /* Check if the driver should configure link and PHY. */
1904         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1905               OHCI1394_HCControl_programPhyEnable))
1906                 return 0;
1907
1908         /* Paranoia: check whether the PHY supports 1394a, too. */
1909         enable_1394a = false;
1910         ret = read_phy_reg(ohci, 2);
1911         if (ret < 0)
1912                 return ret;
1913         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1914                 ret = read_paged_phy_reg(ohci, 1, 8);
1915                 if (ret < 0)
1916                         return ret;
1917                 if (ret >= 1)
1918                         enable_1394a = true;
1919         }
1920
1921         if (ohci->quirks & QUIRK_NO_1394A)
1922                 enable_1394a = false;
1923
1924         /* Configure PHY and link consistently. */
1925         if (enable_1394a) {
1926                 clear = 0;
1927                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1928         } else {
1929                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1930                 set = 0;
1931         }
1932         ret = update_phy_reg(ohci, 5, clear, set);
1933         if (ret < 0)
1934                 return ret;
1935
1936         if (enable_1394a)
1937                 offset = OHCI1394_HCControlSet;
1938         else
1939                 offset = OHCI1394_HCControlClear;
1940         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1941
1942         /* Clean up: configuration has been taken care of. */
1943         reg_write(ohci, OHCI1394_HCControlClear,
1944                   OHCI1394_HCControl_programPhyEnable);
1945
1946         return 0;
1947 }
1948
1949 static int ohci_enable(struct fw_card *card,
1950                        const __be32 *config_rom, size_t length)
1951 {
1952         struct fw_ohci *ohci = fw_ohci(card);
1953         struct pci_dev *dev = to_pci_dev(card->device);
1954         u32 lps, seconds, version, irqs;
1955         int i, ret;
1956
1957         if (software_reset(ohci)) {
1958                 fw_error("Failed to reset ohci card.\n");
1959                 return -EBUSY;
1960         }
1961
1962         /*
1963          * Now enable LPS, which we need in order to start accessing
1964          * most of the registers.  In fact, on some cards (ALI M5251),
1965          * accessing registers in the SClk domain without LPS enabled
1966          * will lock up the machine.  Wait 50msec to make sure we have
1967          * full link enabled.  However, with some cards (well, at least
1968          * a JMicron PCIe card), we have to try again sometimes.
1969          */
1970         reg_write(ohci, OHCI1394_HCControlSet,
1971                   OHCI1394_HCControl_LPS |
1972                   OHCI1394_HCControl_postedWriteEnable);
1973         flush_writes(ohci);
1974
1975         for (lps = 0, i = 0; !lps && i < 3; i++) {
1976                 msleep(50);
1977                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1978                       OHCI1394_HCControl_LPS;
1979         }
1980
1981         if (!lps) {
1982                 fw_error("Failed to set Link Power Status\n");
1983                 return -EIO;
1984         }
1985
1986         reg_write(ohci, OHCI1394_HCControlClear,
1987                   OHCI1394_HCControl_noByteSwapData);
1988
1989         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1990         reg_write(ohci, OHCI1394_LinkControlSet,
1991                   OHCI1394_LinkControl_rcvSelfID |
1992                   OHCI1394_LinkControl_rcvPhyPkt |
1993                   OHCI1394_LinkControl_cycleTimerEnable |
1994                   OHCI1394_LinkControl_cycleMaster);
1995
1996         reg_write(ohci, OHCI1394_ATRetries,
1997                   OHCI1394_MAX_AT_REQ_RETRIES |
1998                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1999                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2000                   (200 << 16));
2001
2002         seconds = lower_32_bits(get_seconds());
2003         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2004         ohci->bus_time = seconds & ~0x3f;
2005
2006         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2007         if (version >= OHCI_VERSION_1_1) {
2008                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2009                           0xfffffffe);
2010                 card->broadcast_channel_auto_allocated = true;
2011         }
2012
2013         /* Get implemented bits of the priority arbitration request counter. */
2014         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2015         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2016         reg_write(ohci, OHCI1394_FairnessControl, 0);
2017         card->priority_budget_implemented = ohci->pri_req_max != 0;
2018
2019         ar_context_run(&ohci->ar_request_ctx);
2020         ar_context_run(&ohci->ar_response_ctx);
2021
2022         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2023         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2024         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2025
2026         ret = configure_1394a_enhancements(ohci);
2027         if (ret < 0)
2028                 return ret;
2029
2030         /* Activate link_on bit and contender bit in our self ID packets.*/
2031         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2032         if (ret < 0)
2033                 return ret;
2034
2035         /*
2036          * When the link is not yet enabled, the atomic config rom
2037          * update mechanism described below in ohci_set_config_rom()
2038          * is not active.  We have to update ConfigRomHeader and
2039          * BusOptions manually, and the write to ConfigROMmap takes
2040          * effect immediately.  We tie this to the enabling of the
2041          * link, so we have a valid config rom before enabling - the
2042          * OHCI requires that ConfigROMhdr and BusOptions have valid
2043          * values before enabling.
2044          *
2045          * However, when the ConfigROMmap is written, some controllers
2046          * always read back quadlets 0 and 2 from the config rom to
2047          * the ConfigRomHeader and BusOptions registers on bus reset.
2048          * They shouldn't do that in this initial case where the link
2049          * isn't enabled.  This means we have to use the same
2050          * workaround here, setting the bus header to 0 and then write
2051          * the right values in the bus reset tasklet.
2052          */
2053
2054         if (config_rom) {
2055                 ohci->next_config_rom =
2056                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2057                                            &ohci->next_config_rom_bus,
2058                                            GFP_KERNEL);
2059                 if (ohci->next_config_rom == NULL)
2060                         return -ENOMEM;
2061
2062                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2063         } else {
2064                 /*
2065                  * In the suspend case, config_rom is NULL, which
2066                  * means that we just reuse the old config rom.
2067                  */
2068                 ohci->next_config_rom = ohci->config_rom;
2069                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2070         }
2071
2072         ohci->next_header = ohci->next_config_rom[0];
2073         ohci->next_config_rom[0] = 0;
2074         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2075         reg_write(ohci, OHCI1394_BusOptions,
2076                   be32_to_cpu(ohci->next_config_rom[2]));
2077         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2078
2079         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2080
2081         if (!(ohci->quirks & QUIRK_NO_MSI))
2082                 pci_enable_msi(dev);
2083         if (request_irq(dev->irq, irq_handler,
2084                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2085                         ohci_driver_name, ohci)) {
2086                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2087                 pci_disable_msi(dev);
2088                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2089                                   ohci->config_rom, ohci->config_rom_bus);
2090                 return -EIO;
2091         }
2092
2093         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2094                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2095                 OHCI1394_isochTx | OHCI1394_isochRx |
2096                 OHCI1394_postedWriteErr |
2097                 OHCI1394_selfIDComplete |
2098                 OHCI1394_regAccessFail |
2099                 OHCI1394_cycle64Seconds |
2100                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2101                 OHCI1394_masterIntEnable;
2102         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2103                 irqs |= OHCI1394_busReset;
2104         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2105
2106         reg_write(ohci, OHCI1394_HCControlSet,
2107                   OHCI1394_HCControl_linkEnable |
2108                   OHCI1394_HCControl_BIBimageValid);
2109         flush_writes(ohci);
2110
2111         /* We are ready to go, reset bus to finish initialization. */
2112         fw_schedule_bus_reset(&ohci->card, false, true);
2113
2114         return 0;
2115 }
2116
2117 static int ohci_set_config_rom(struct fw_card *card,
2118                                const __be32 *config_rom, size_t length)
2119 {
2120         struct fw_ohci *ohci;
2121         unsigned long flags;
2122         int ret = -EBUSY;
2123         __be32 *next_config_rom;
2124         dma_addr_t uninitialized_var(next_config_rom_bus);
2125
2126         ohci = fw_ohci(card);
2127
2128         /*
2129          * When the OHCI controller is enabled, the config rom update
2130          * mechanism is a bit tricky, but easy enough to use.  See
2131          * section 5.5.6 in the OHCI specification.
2132          *
2133          * The OHCI controller caches the new config rom address in a
2134          * shadow register (ConfigROMmapNext) and needs a bus reset
2135          * for the changes to take place.  When the bus reset is
2136          * detected, the controller loads the new values for the
2137          * ConfigRomHeader and BusOptions registers from the specified
2138          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2139          * shadow register. All automatically and atomically.
2140          *
2141          * Now, there's a twist to this story.  The automatic load of
2142          * ConfigRomHeader and BusOptions doesn't honor the
2143          * noByteSwapData bit, so with a be32 config rom, the
2144          * controller will load be32 values in to these registers
2145          * during the atomic update, even on litte endian
2146          * architectures.  The workaround we use is to put a 0 in the
2147          * header quadlet; 0 is endian agnostic and means that the
2148          * config rom isn't ready yet.  In the bus reset tasklet we
2149          * then set up the real values for the two registers.
2150          *
2151          * We use ohci->lock to avoid racing with the code that sets
2152          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2153          */
2154
2155         next_config_rom =
2156                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2157                                    &next_config_rom_bus, GFP_KERNEL);
2158         if (next_config_rom == NULL)
2159                 return -ENOMEM;
2160
2161         spin_lock_irqsave(&ohci->lock, flags);
2162
2163         if (ohci->next_config_rom == NULL) {
2164                 ohci->next_config_rom = next_config_rom;
2165                 ohci->next_config_rom_bus = next_config_rom_bus;
2166
2167                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2168
2169                 ohci->next_header = config_rom[0];
2170                 ohci->next_config_rom[0] = 0;
2171
2172                 reg_write(ohci, OHCI1394_ConfigROMmap,
2173                           ohci->next_config_rom_bus);
2174                 ret = 0;
2175         }
2176
2177         spin_unlock_irqrestore(&ohci->lock, flags);
2178
2179         /*
2180          * Now initiate a bus reset to have the changes take
2181          * effect. We clean up the old config rom memory and DMA
2182          * mappings in the bus reset tasklet, since the OHCI
2183          * controller could need to access it before the bus reset
2184          * takes effect.
2185          */
2186         if (ret == 0)
2187                 fw_schedule_bus_reset(&ohci->card, true, true);
2188         else
2189                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2190                                   next_config_rom, next_config_rom_bus);
2191
2192         return ret;
2193 }
2194
2195 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2196 {
2197         struct fw_ohci *ohci = fw_ohci(card);
2198
2199         at_context_transmit(&ohci->at_request_ctx, packet);
2200 }
2201
2202 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2203 {
2204         struct fw_ohci *ohci = fw_ohci(card);
2205
2206         at_context_transmit(&ohci->at_response_ctx, packet);
2207 }
2208
2209 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2210 {
2211         struct fw_ohci *ohci = fw_ohci(card);
2212         struct context *ctx = &ohci->at_request_ctx;
2213         struct driver_data *driver_data = packet->driver_data;
2214         int ret = -ENOENT;
2215
2216         tasklet_disable(&ctx->tasklet);
2217
2218         if (packet->ack != 0)
2219                 goto out;
2220
2221         if (packet->payload_mapped)
2222                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2223                                  packet->payload_length, DMA_TO_DEVICE);
2224
2225         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2226         driver_data->packet = NULL;
2227         packet->ack = RCODE_CANCELLED;
2228         packet->callback(packet, &ohci->card, packet->ack);
2229         ret = 0;
2230  out:
2231         tasklet_enable(&ctx->tasklet);
2232
2233         return ret;
2234 }
2235
2236 static int ohci_enable_phys_dma(struct fw_card *card,
2237                                 int node_id, int generation)
2238 {
2239 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2240         return 0;
2241 #else
2242         struct fw_ohci *ohci = fw_ohci(card);
2243         unsigned long flags;
2244         int n, ret = 0;
2245
2246         /*
2247          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2248          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2249          */
2250
2251         spin_lock_irqsave(&ohci->lock, flags);
2252
2253         if (ohci->generation != generation) {
2254                 ret = -ESTALE;
2255                 goto out;
2256         }
2257
2258         /*
2259          * Note, if the node ID contains a non-local bus ID, physical DMA is
2260          * enabled for _all_ nodes on remote buses.
2261          */
2262
2263         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2264         if (n < 32)
2265                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2266         else
2267                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2268
2269         flush_writes(ohci);
2270  out:
2271         spin_unlock_irqrestore(&ohci->lock, flags);
2272
2273         return ret;
2274 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2275 }
2276
2277 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2278 {
2279         struct fw_ohci *ohci = fw_ohci(card);
2280         unsigned long flags;
2281         u32 value;
2282
2283         switch (csr_offset) {
2284         case CSR_STATE_CLEAR:
2285         case CSR_STATE_SET:
2286                 if (ohci->is_root &&
2287                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2288                      OHCI1394_LinkControl_cycleMaster))
2289                         value = CSR_STATE_BIT_CMSTR;
2290                 else
2291                         value = 0;
2292                 if (ohci->csr_state_setclear_abdicate)
2293                         value |= CSR_STATE_BIT_ABDICATE;
2294
2295                 return value;
2296
2297         case CSR_NODE_IDS:
2298                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2299
2300         case CSR_CYCLE_TIME:
2301                 return get_cycle_time(ohci);
2302
2303         case CSR_BUS_TIME:
2304                 /*
2305                  * We might be called just after the cycle timer has wrapped
2306                  * around but just before the cycle64Seconds handler, so we
2307                  * better check here, too, if the bus time needs to be updated.
2308                  */
2309                 spin_lock_irqsave(&ohci->lock, flags);
2310                 value = update_bus_time(ohci);
2311                 spin_unlock_irqrestore(&ohci->lock, flags);
2312                 return value;
2313
2314         case CSR_BUSY_TIMEOUT:
2315                 value = reg_read(ohci, OHCI1394_ATRetries);
2316                 return (value >> 4) & 0x0ffff00f;
2317
2318         case CSR_PRIORITY_BUDGET:
2319                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2320                         (ohci->pri_req_max << 8);
2321
2322         default:
2323                 WARN_ON(1);
2324                 return 0;
2325         }
2326 }
2327
2328 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2329 {
2330         struct fw_ohci *ohci = fw_ohci(card);
2331         unsigned long flags;
2332
2333         switch (csr_offset) {
2334         case CSR_STATE_CLEAR:
2335                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2336                         reg_write(ohci, OHCI1394_LinkControlClear,
2337                                   OHCI1394_LinkControl_cycleMaster);
2338                         flush_writes(ohci);
2339                 }
2340                 if (value & CSR_STATE_BIT_ABDICATE)
2341                         ohci->csr_state_setclear_abdicate = false;
2342                 break;
2343
2344         case CSR_STATE_SET:
2345                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2346                         reg_write(ohci, OHCI1394_LinkControlSet,
2347                                   OHCI1394_LinkControl_cycleMaster);
2348                         flush_writes(ohci);
2349                 }
2350                 if (value & CSR_STATE_BIT_ABDICATE)
2351                         ohci->csr_state_setclear_abdicate = true;
2352                 break;
2353
2354         case CSR_NODE_IDS:
2355                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2356                 flush_writes(ohci);
2357                 break;
2358
2359         case CSR_CYCLE_TIME:
2360                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2361                 reg_write(ohci, OHCI1394_IntEventSet,
2362                           OHCI1394_cycleInconsistent);
2363                 flush_writes(ohci);
2364                 break;
2365
2366         case CSR_BUS_TIME:
2367                 spin_lock_irqsave(&ohci->lock, flags);
2368                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2369                 spin_unlock_irqrestore(&ohci->lock, flags);
2370                 break;
2371
2372         case CSR_BUSY_TIMEOUT:
2373                 value = (value & 0xf) | ((value & 0xf) << 4) |
2374                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2375                 reg_write(ohci, OHCI1394_ATRetries, value);
2376                 flush_writes(ohci);
2377                 break;
2378
2379         case CSR_PRIORITY_BUDGET:
2380                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2381                 flush_writes(ohci);
2382                 break;
2383
2384         default:
2385                 WARN_ON(1);
2386                 break;
2387         }
2388 }
2389
2390 static void copy_iso_headers(struct iso_context *ctx, void *p)
2391 {
2392         int i = ctx->header_length;
2393
2394         if (i + ctx->base.header_size > PAGE_SIZE)
2395                 return;
2396
2397         /*
2398          * The iso header is byteswapped to little endian by
2399          * the controller, but the remaining header quadlets
2400          * are big endian.  We want to present all the headers
2401          * as big endian, so we have to swap the first quadlet.
2402          */
2403         if (ctx->base.header_size > 0)
2404                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2405         if (ctx->base.header_size > 4)
2406                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2407         if (ctx->base.header_size > 8)
2408                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2409         ctx->header_length += ctx->base.header_size;
2410 }
2411
2412 static int handle_ir_packet_per_buffer(struct context *context,
2413                                        struct descriptor *d,
2414                                        struct descriptor *last)
2415 {
2416         struct iso_context *ctx =
2417                 container_of(context, struct iso_context, context);
2418         struct descriptor *pd;
2419         __le32 *ir_header;
2420         void *p;
2421
2422         for (pd = d; pd <= last; pd++)
2423                 if (pd->transfer_status)
2424                         break;
2425         if (pd > last)
2426                 /* Descriptor(s) not done yet, stop iteration */
2427                 return 0;
2428
2429         p = last + 1;
2430         copy_iso_headers(ctx, p);
2431
2432         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2433                 ir_header = (__le32 *) p;
2434                 ctx->base.callback.sc(&ctx->base,
2435                                       le32_to_cpu(ir_header[0]) & 0xffff,
2436                                       ctx->header_length, ctx->header,
2437                                       ctx->base.callback_data);
2438                 ctx->header_length = 0;
2439         }
2440
2441         return 1;
2442 }
2443
2444 /* d == last because each descriptor block is only a single descriptor. */
2445 static int handle_ir_buffer_fill(struct context *context,
2446                                  struct descriptor *d,
2447                                  struct descriptor *last)
2448 {
2449         struct iso_context *ctx =
2450                 container_of(context, struct iso_context, context);
2451
2452         if (!last->transfer_status)
2453                 /* Descriptor(s) not done yet, stop iteration */
2454                 return 0;
2455
2456         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2457                 ctx->base.callback.mc(&ctx->base,
2458                                       le32_to_cpu(last->data_address) +
2459                                       le16_to_cpu(last->req_count) -
2460                                       le16_to_cpu(last->res_count),
2461                                       ctx->base.callback_data);
2462
2463         return 1;
2464 }
2465
2466 static int handle_it_packet(struct context *context,
2467                             struct descriptor *d,
2468                             struct descriptor *last)
2469 {
2470         struct iso_context *ctx =
2471                 container_of(context, struct iso_context, context);
2472         int i;
2473         struct descriptor *pd;
2474
2475         for (pd = d; pd <= last; pd++)
2476                 if (pd->transfer_status)
2477                         break;
2478         if (pd > last)
2479                 /* Descriptor(s) not done yet, stop iteration */
2480                 return 0;
2481
2482         i = ctx->header_length;
2483         if (i + 4 < PAGE_SIZE) {
2484                 /* Present this value as big-endian to match the receive code */
2485                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2486                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2487                                 le16_to_cpu(pd->res_count));
2488                 ctx->header_length += 4;
2489         }
2490         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2491                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2492                                       ctx->header_length, ctx->header,
2493                                       ctx->base.callback_data);
2494                 ctx->header_length = 0;
2495         }
2496         return 1;
2497 }
2498
2499 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2500 {
2501         u32 hi = channels >> 32, lo = channels;
2502
2503         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2504         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2505         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2506         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2507         mmiowb();
2508         ohci->mc_channels = channels;
2509 }
2510
2511 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2512                                 int type, int channel, size_t header_size)
2513 {
2514         struct fw_ohci *ohci = fw_ohci(card);
2515         struct iso_context *uninitialized_var(ctx);
2516         descriptor_callback_t uninitialized_var(callback);
2517         u64 *uninitialized_var(channels);
2518         u32 *uninitialized_var(mask), uninitialized_var(regs);
2519         unsigned long flags;
2520         int index, ret = -EBUSY;
2521
2522         spin_lock_irqsave(&ohci->lock, flags);
2523
2524         switch (type) {
2525         case FW_ISO_CONTEXT_TRANSMIT:
2526                 mask     = &ohci->it_context_mask;
2527                 callback = handle_it_packet;
2528                 index    = ffs(*mask) - 1;
2529                 if (index >= 0) {
2530                         *mask &= ~(1 << index);
2531                         regs = OHCI1394_IsoXmitContextBase(index);
2532                         ctx  = &ohci->it_context_list[index];
2533                 }
2534                 break;
2535
2536         case FW_ISO_CONTEXT_RECEIVE:
2537                 channels = &ohci->ir_context_channels;
2538                 mask     = &ohci->ir_context_mask;
2539                 callback = handle_ir_packet_per_buffer;
2540                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2541                 if (index >= 0) {
2542                         *channels &= ~(1ULL << channel);
2543                         *mask     &= ~(1 << index);
2544                         regs = OHCI1394_IsoRcvContextBase(index);
2545                         ctx  = &ohci->ir_context_list[index];
2546                 }
2547                 break;
2548
2549         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2550                 mask     = &ohci->ir_context_mask;
2551                 callback = handle_ir_buffer_fill;
2552                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2553                 if (index >= 0) {
2554                         ohci->mc_allocated = true;
2555                         *mask &= ~(1 << index);
2556                         regs = OHCI1394_IsoRcvContextBase(index);
2557                         ctx  = &ohci->ir_context_list[index];
2558                 }
2559                 break;
2560
2561         default:
2562                 index = -1;
2563                 ret = -ENOSYS;
2564         }
2565
2566         spin_unlock_irqrestore(&ohci->lock, flags);
2567
2568         if (index < 0)
2569                 return ERR_PTR(ret);
2570
2571         memset(ctx, 0, sizeof(*ctx));
2572         ctx->header_length = 0;
2573         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2574         if (ctx->header == NULL) {
2575                 ret = -ENOMEM;
2576                 goto out;
2577         }
2578         ret = context_init(&ctx->context, ohci, regs, callback);
2579         if (ret < 0)
2580                 goto out_with_header;
2581
2582         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2583                 set_multichannel_mask(ohci, 0);
2584
2585         return &ctx->base;
2586
2587  out_with_header:
2588         free_page((unsigned long)ctx->header);
2589  out:
2590         spin_lock_irqsave(&ohci->lock, flags);
2591
2592         switch (type) {
2593         case FW_ISO_CONTEXT_RECEIVE:
2594                 *channels |= 1ULL << channel;
2595                 break;
2596
2597         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2598                 ohci->mc_allocated = false;
2599                 break;
2600         }
2601         *mask |= 1 << index;
2602
2603         spin_unlock_irqrestore(&ohci->lock, flags);
2604
2605         return ERR_PTR(ret);
2606 }
2607
2608 static int ohci_start_iso(struct fw_iso_context *base,
2609                           s32 cycle, u32 sync, u32 tags)
2610 {
2611         struct iso_context *ctx = container_of(base, struct iso_context, base);
2612         struct fw_ohci *ohci = ctx->context.ohci;
2613         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2614         int index;
2615
2616         switch (ctx->base.type) {
2617         case FW_ISO_CONTEXT_TRANSMIT:
2618                 index = ctx - ohci->it_context_list;
2619                 match = 0;
2620                 if (cycle >= 0)
2621                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2622                                 (cycle & 0x7fff) << 16;
2623
2624                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2625                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2626                 context_run(&ctx->context, match);
2627                 break;
2628
2629         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2630                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2631                 /* fall through */
2632         case FW_ISO_CONTEXT_RECEIVE:
2633                 index = ctx - ohci->ir_context_list;
2634                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2635                 if (cycle >= 0) {
2636                         match |= (cycle & 0x07fff) << 12;
2637                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2638                 }
2639
2640                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2641                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2642                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2643                 context_run(&ctx->context, control);
2644                 break;
2645         }
2646
2647         return 0;
2648 }
2649
2650 static int ohci_stop_iso(struct fw_iso_context *base)
2651 {
2652         struct fw_ohci *ohci = fw_ohci(base->card);
2653         struct iso_context *ctx = container_of(base, struct iso_context, base);
2654         int index;
2655
2656         switch (ctx->base.type) {
2657         case FW_ISO_CONTEXT_TRANSMIT:
2658                 index = ctx - ohci->it_context_list;
2659                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2660                 break;
2661
2662         case FW_ISO_CONTEXT_RECEIVE:
2663         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2664                 index = ctx - ohci->ir_context_list;
2665                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2666                 break;
2667         }
2668         flush_writes(ohci);
2669         context_stop(&ctx->context);
2670
2671         return 0;
2672 }
2673
2674 static void ohci_free_iso_context(struct fw_iso_context *base)
2675 {
2676         struct fw_ohci *ohci = fw_ohci(base->card);
2677         struct iso_context *ctx = container_of(base, struct iso_context, base);
2678         unsigned long flags;
2679         int index;
2680
2681         ohci_stop_iso(base);
2682         context_release(&ctx->context);
2683         free_page((unsigned long)ctx->header);
2684
2685         spin_lock_irqsave(&ohci->lock, flags);
2686
2687         switch (base->type) {
2688         case FW_ISO_CONTEXT_TRANSMIT:
2689                 index = ctx - ohci->it_context_list;
2690                 ohci->it_context_mask |= 1 << index;
2691                 break;
2692
2693         case FW_ISO_CONTEXT_RECEIVE:
2694                 index = ctx - ohci->ir_context_list;
2695                 ohci->ir_context_mask |= 1 << index;
2696                 ohci->ir_context_channels |= 1ULL << base->channel;
2697                 break;
2698
2699         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2700                 index = ctx - ohci->ir_context_list;
2701                 ohci->ir_context_mask |= 1 << index;
2702                 ohci->ir_context_channels |= ohci->mc_channels;
2703                 ohci->mc_channels = 0;
2704                 ohci->mc_allocated = false;
2705                 break;
2706         }
2707
2708         spin_unlock_irqrestore(&ohci->lock, flags);
2709 }
2710
2711 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2712 {
2713         struct fw_ohci *ohci = fw_ohci(base->card);
2714         unsigned long flags;
2715         int ret;
2716
2717         switch (base->type) {
2718         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2719
2720                 spin_lock_irqsave(&ohci->lock, flags);
2721
2722                 /* Don't allow multichannel to grab other contexts' channels. */
2723                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2724                         *channels = ohci->ir_context_channels;
2725                         ret = -EBUSY;
2726                 } else {
2727                         set_multichannel_mask(ohci, *channels);
2728                         ret = 0;
2729                 }
2730
2731                 spin_unlock_irqrestore(&ohci->lock, flags);
2732
2733                 break;
2734         default:
2735                 ret = -EINVAL;
2736         }
2737
2738         return ret;
2739 }
2740
2741 static int queue_iso_transmit(struct iso_context *ctx,
2742                               struct fw_iso_packet *packet,
2743                               struct fw_iso_buffer *buffer,
2744                               unsigned long payload)
2745 {
2746         struct descriptor *d, *last, *pd;
2747         struct fw_iso_packet *p;
2748         __le32 *header;
2749         dma_addr_t d_bus, page_bus;
2750         u32 z, header_z, payload_z, irq;
2751         u32 payload_index, payload_end_index, next_page_index;
2752         int page, end_page, i, length, offset;
2753
2754         p = packet;
2755         payload_index = payload;
2756
2757         if (p->skip)
2758                 z = 1;
2759         else
2760                 z = 2;
2761         if (p->header_length > 0)
2762                 z++;
2763
2764         /* Determine the first page the payload isn't contained in. */
2765         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2766         if (p->payload_length > 0)
2767                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2768         else
2769                 payload_z = 0;
2770
2771         z += payload_z;
2772
2773         /* Get header size in number of descriptors. */
2774         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2775
2776         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2777         if (d == NULL)
2778                 return -ENOMEM;
2779
2780         if (!p->skip) {
2781                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2782                 d[0].req_count = cpu_to_le16(8);
2783                 /*
2784                  * Link the skip address to this descriptor itself.  This causes
2785                  * a context to skip a cycle whenever lost cycles or FIFO
2786                  * overruns occur, without dropping the data.  The application
2787                  * should then decide whether this is an error condition or not.
2788                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2789                  */
2790                 d[0].branch_address = cpu_to_le32(d_bus | z);
2791
2792                 header = (__le32 *) &d[1];
2793                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2794                                         IT_HEADER_TAG(p->tag) |
2795                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2796                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2797                                         IT_HEADER_SPEED(ctx->base.speed));
2798                 header[1] =
2799                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2800                                                           p->payload_length));
2801         }
2802
2803         if (p->header_length > 0) {
2804                 d[2].req_count    = cpu_to_le16(p->header_length);
2805                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2806                 memcpy(&d[z], p->header, p->header_length);
2807         }
2808
2809         pd = d + z - payload_z;
2810         payload_end_index = payload_index + p->payload_length;
2811         for (i = 0; i < payload_z; i++) {
2812                 page               = payload_index >> PAGE_SHIFT;
2813                 offset             = payload_index & ~PAGE_MASK;
2814                 next_page_index    = (page + 1) << PAGE_SHIFT;
2815                 length             =
2816                         min(next_page_index, payload_end_index) - payload_index;
2817                 pd[i].req_count    = cpu_to_le16(length);
2818
2819                 page_bus = page_private(buffer->pages[page]);
2820                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2821
2822                 payload_index += length;
2823         }
2824
2825         if (p->interrupt)
2826                 irq = DESCRIPTOR_IRQ_ALWAYS;
2827         else
2828                 irq = DESCRIPTOR_NO_IRQ;
2829
2830         last = z == 2 ? d : d + z - 1;
2831         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2832                                      DESCRIPTOR_STATUS |
2833                                      DESCRIPTOR_BRANCH_ALWAYS |
2834                                      irq);
2835
2836         context_append(&ctx->context, d, z, header_z);
2837
2838         return 0;
2839 }
2840
2841 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2842                                        struct fw_iso_packet *packet,
2843                                        struct fw_iso_buffer *buffer,
2844                                        unsigned long payload)
2845 {
2846         struct descriptor *d, *pd;
2847         dma_addr_t d_bus, page_bus;
2848         u32 z, header_z, rest;
2849         int i, j, length;
2850         int page, offset, packet_count, header_size, payload_per_buffer;
2851
2852         /*
2853          * The OHCI controller puts the isochronous header and trailer in the
2854          * buffer, so we need at least 8 bytes.
2855          */
2856         packet_count = packet->header_length / ctx->base.header_size;
2857         header_size  = max(ctx->base.header_size, (size_t)8);
2858
2859         /* Get header size in number of descriptors. */
2860         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2861         page     = payload >> PAGE_SHIFT;
2862         offset   = payload & ~PAGE_MASK;
2863         payload_per_buffer = packet->payload_length / packet_count;
2864
2865         for (i = 0; i < packet_count; i++) {
2866                 /* d points to the header descriptor */
2867                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2868                 d = context_get_descriptors(&ctx->context,
2869                                 z + header_z, &d_bus);
2870                 if (d == NULL)
2871                         return -ENOMEM;
2872
2873                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2874                                               DESCRIPTOR_INPUT_MORE);
2875                 if (packet->skip && i == 0)
2876                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2877                 d->req_count    = cpu_to_le16(header_size);
2878                 d->res_count    = d->req_count;
2879                 d->transfer_status = 0;
2880                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2881
2882                 rest = payload_per_buffer;
2883                 pd = d;
2884                 for (j = 1; j < z; j++) {
2885                         pd++;
2886                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2887                                                   DESCRIPTOR_INPUT_MORE);
2888
2889                         if (offset + rest < PAGE_SIZE)
2890                                 length = rest;
2891                         else
2892                                 length = PAGE_SIZE - offset;
2893                         pd->req_count = cpu_to_le16(length);
2894                         pd->res_count = pd->req_count;
2895                         pd->transfer_status = 0;
2896
2897                         page_bus = page_private(buffer->pages[page]);
2898                         pd->data_address = cpu_to_le32(page_bus + offset);
2899
2900                         offset = (offset + length) & ~PAGE_MASK;
2901                         rest -= length;
2902                         if (offset == 0)
2903                                 page++;
2904                 }
2905                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2906                                           DESCRIPTOR_INPUT_LAST |
2907                                           DESCRIPTOR_BRANCH_ALWAYS);
2908                 if (packet->interrupt && i == packet_count - 1)
2909                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2910
2911                 context_append(&ctx->context, d, z, header_z);
2912         }
2913
2914         return 0;
2915 }
2916
2917 static int queue_iso_buffer_fill(struct iso_context *ctx,
2918                                  struct fw_iso_packet *packet,
2919                                  struct fw_iso_buffer *buffer,
2920                                  unsigned long payload)
2921 {
2922         struct descriptor *d;
2923         dma_addr_t d_bus, page_bus;
2924         int page, offset, rest, z, i, length;
2925
2926         page   = payload >> PAGE_SHIFT;
2927         offset = payload & ~PAGE_MASK;
2928         rest   = packet->payload_length;
2929
2930         /* We need one descriptor for each page in the buffer. */
2931         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2932
2933         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2934                 return -EFAULT;
2935
2936         for (i = 0; i < z; i++) {
2937                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2938                 if (d == NULL)
2939                         return -ENOMEM;
2940
2941                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2942                                          DESCRIPTOR_BRANCH_ALWAYS);
2943                 if (packet->skip && i == 0)
2944                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2945                 if (packet->interrupt && i == z - 1)
2946                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2947
2948                 if (offset + rest < PAGE_SIZE)
2949                         length = rest;
2950                 else
2951                         length = PAGE_SIZE - offset;
2952                 d->req_count = cpu_to_le16(length);
2953                 d->res_count = d->req_count;
2954                 d->transfer_status = 0;
2955
2956                 page_bus = page_private(buffer->pages[page]);
2957                 d->data_address = cpu_to_le32(page_bus + offset);
2958
2959                 rest -= length;
2960                 offset = 0;
2961                 page++;
2962
2963                 context_append(&ctx->context, d, 1, 0);
2964         }
2965
2966         return 0;
2967 }
2968
2969 static int ohci_queue_iso(struct fw_iso_context *base,
2970                           struct fw_iso_packet *packet,
2971                           struct fw_iso_buffer *buffer,
2972                           unsigned long payload)
2973 {
2974         struct iso_context *ctx = container_of(base, struct iso_context, base);
2975         unsigned long flags;
2976         int ret = -ENOSYS;
2977
2978         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2979         switch (base->type) {
2980         case FW_ISO_CONTEXT_TRANSMIT:
2981                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2982                 break;
2983         case FW_ISO_CONTEXT_RECEIVE:
2984                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2985                 break;
2986         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2987                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2988                 break;
2989         }
2990         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2991
2992         return ret;
2993 }
2994
2995 static const struct fw_card_driver ohci_driver = {
2996         .enable                 = ohci_enable,
2997         .read_phy_reg           = ohci_read_phy_reg,
2998         .update_phy_reg         = ohci_update_phy_reg,
2999         .set_config_rom         = ohci_set_config_rom,
3000         .send_request           = ohci_send_request,
3001         .send_response          = ohci_send_response,
3002         .cancel_packet          = ohci_cancel_packet,
3003         .enable_phys_dma        = ohci_enable_phys_dma,
3004         .read_csr               = ohci_read_csr,
3005         .write_csr              = ohci_write_csr,
3006
3007         .allocate_iso_context   = ohci_allocate_iso_context,
3008         .free_iso_context       = ohci_free_iso_context,
3009         .set_iso_channels       = ohci_set_iso_channels,
3010         .queue_iso              = ohci_queue_iso,
3011         .start_iso              = ohci_start_iso,
3012         .stop_iso               = ohci_stop_iso,
3013 };
3014
3015 #ifdef CONFIG_PPC_PMAC
3016 static void pmac_ohci_on(struct pci_dev *dev)
3017 {
3018         if (machine_is(powermac)) {
3019                 struct device_node *ofn = pci_device_to_OF_node(dev);
3020
3021                 if (ofn) {
3022                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3023                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3024                 }
3025         }
3026 }
3027
3028 static void pmac_ohci_off(struct pci_dev *dev)
3029 {
3030         if (machine_is(powermac)) {
3031                 struct device_node *ofn = pci_device_to_OF_node(dev);
3032
3033                 if (ofn) {
3034                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3035                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3036                 }
3037         }
3038 }
3039 #else
3040 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3041 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3042 #endif /* CONFIG_PPC_PMAC */
3043
3044 static int __devinit pci_probe(struct pci_dev *dev,
3045                                const struct pci_device_id *ent)
3046 {
3047         struct fw_ohci *ohci;
3048         u32 bus_options, max_receive, link_speed, version;
3049         u64 guid;
3050         int i, err, n_ir, n_it;
3051         size_t size;
3052
3053         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3054         if (ohci == NULL) {
3055                 err = -ENOMEM;
3056                 goto fail;
3057         }
3058
3059         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3060
3061         pmac_ohci_on(dev);
3062
3063         err = pci_enable_device(dev);
3064         if (err) {
3065                 fw_error("Failed to enable OHCI hardware\n");
3066                 goto fail_free;
3067         }
3068
3069         pci_set_master(dev);
3070         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3071         pci_set_drvdata(dev, ohci);
3072
3073         spin_lock_init(&ohci->lock);
3074         mutex_init(&ohci->phy_reg_mutex);
3075
3076         tasklet_init(&ohci->bus_reset_tasklet,
3077                      bus_reset_tasklet, (unsigned long)ohci);
3078
3079         err = pci_request_region(dev, 0, ohci_driver_name);
3080         if (err) {
3081                 fw_error("MMIO resource unavailable\n");
3082                 goto fail_disable;
3083         }
3084
3085         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3086         if (ohci->registers == NULL) {
3087                 fw_error("Failed to remap registers\n");
3088                 err = -ENXIO;
3089                 goto fail_iomem;
3090         }
3091
3092         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3093                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3094                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3095                      ohci_quirks[i].device == dev->device) &&
3096                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3097                      ohci_quirks[i].revision >= dev->revision)) {
3098                         ohci->quirks = ohci_quirks[i].flags;
3099                         break;
3100                 }
3101         if (param_quirks)
3102                 ohci->quirks = param_quirks;
3103
3104         /*
3105          * Because dma_alloc_coherent() allocates at least one page,
3106          * we save space by using a common buffer for the AR request/
3107          * response descriptors and the self IDs buffer.
3108          */
3109         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3110         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3111         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3112                                                PAGE_SIZE,
3113                                                &ohci->misc_buffer_bus,
3114                                                GFP_KERNEL);
3115         if (!ohci->misc_buffer) {
3116                 err = -ENOMEM;
3117                 goto fail_iounmap;
3118         }
3119
3120         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3121                               OHCI1394_AsReqRcvContextControlSet);
3122         if (err < 0)
3123                 goto fail_misc_buf;
3124
3125         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3126                               OHCI1394_AsRspRcvContextControlSet);
3127         if (err < 0)
3128                 goto fail_arreq_ctx;
3129
3130         err = context_init(&ohci->at_request_ctx, ohci,
3131                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3132         if (err < 0)
3133                 goto fail_arrsp_ctx;
3134
3135         err = context_init(&ohci->at_response_ctx, ohci,
3136                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3137         if (err < 0)
3138                 goto fail_atreq_ctx;
3139
3140         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3141         ohci->ir_context_channels = ~0ULL;
3142         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3143         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3144         n_ir = hweight32(ohci->ir_context_mask);
3145         size = sizeof(struct iso_context) * n_ir;
3146         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3147
3148         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3149         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3150         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3151         n_it = hweight32(ohci->it_context_mask);
3152         size = sizeof(struct iso_context) * n_it;
3153         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3154
3155         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3156                 err = -ENOMEM;
3157                 goto fail_contexts;
3158         }
3159
3160         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3161         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3162
3163         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3164         max_receive = (bus_options >> 12) & 0xf;
3165         link_speed = bus_options & 0x7;
3166         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3167                 reg_read(ohci, OHCI1394_GUIDLo);
3168
3169         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3170         if (err)
3171                 goto fail_contexts;
3172
3173         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3174         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3175                   "%d IR + %d IT contexts, quirks 0x%x\n",
3176                   dev_name(&dev->dev), version >> 16, version & 0xff,
3177                   n_ir, n_it, ohci->quirks);
3178
3179         return 0;
3180
3181  fail_contexts:
3182         kfree(ohci->ir_context_list);
3183         kfree(ohci->it_context_list);
3184         context_release(&ohci->at_response_ctx);
3185  fail_atreq_ctx:
3186         context_release(&ohci->at_request_ctx);
3187  fail_arrsp_ctx:
3188         ar_context_release(&ohci->ar_response_ctx);
3189  fail_arreq_ctx:
3190         ar_context_release(&ohci->ar_request_ctx);
3191  fail_misc_buf:
3192         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3193                           ohci->misc_buffer, ohci->misc_buffer_bus);
3194  fail_iounmap:
3195         pci_iounmap(dev, ohci->registers);
3196  fail_iomem:
3197         pci_release_region(dev, 0);
3198  fail_disable:
3199         pci_disable_device(dev);
3200  fail_free:
3201         kfree(&ohci->card);
3202         pmac_ohci_off(dev);
3203  fail:
3204         if (err == -ENOMEM)
3205                 fw_error("Out of memory\n");
3206
3207         return err;
3208 }
3209
3210 static void pci_remove(struct pci_dev *dev)
3211 {
3212         struct fw_ohci *ohci;
3213
3214         ohci = pci_get_drvdata(dev);
3215         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3216         flush_writes(ohci);
3217         fw_core_remove_card(&ohci->card);
3218
3219         /*
3220          * FIXME: Fail all pending packets here, now that the upper
3221          * layers can't queue any more.
3222          */
3223
3224         software_reset(ohci);
3225         free_irq(dev->irq, ohci);
3226
3227         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3228                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3229                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3230         if (ohci->config_rom)
3231                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3232                                   ohci->config_rom, ohci->config_rom_bus);
3233         ar_context_release(&ohci->ar_request_ctx);
3234         ar_context_release(&ohci->ar_response_ctx);
3235         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3236                           ohci->misc_buffer, ohci->misc_buffer_bus);
3237         context_release(&ohci->at_request_ctx);
3238         context_release(&ohci->at_response_ctx);
3239         kfree(ohci->it_context_list);
3240         kfree(ohci->ir_context_list);
3241         pci_disable_msi(dev);
3242         pci_iounmap(dev, ohci->registers);
3243         pci_release_region(dev, 0);
3244         pci_disable_device(dev);
3245         kfree(&ohci->card);
3246         pmac_ohci_off(dev);
3247
3248         fw_notify("Removed fw-ohci device.\n");
3249 }
3250
3251 #ifdef CONFIG_PM
3252 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3253 {
3254         struct fw_ohci *ohci = pci_get_drvdata(dev);
3255         int err;
3256
3257         software_reset(ohci);
3258         free_irq(dev->irq, ohci);
3259         pci_disable_msi(dev);
3260         err = pci_save_state(dev);
3261         if (err) {
3262                 fw_error("pci_save_state failed\n");
3263                 return err;
3264         }
3265         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3266         if (err)
3267                 fw_error("pci_set_power_state failed with %d\n", err);
3268         pmac_ohci_off(dev);
3269
3270         return 0;
3271 }
3272
3273 static int pci_resume(struct pci_dev *dev)
3274 {
3275         struct fw_ohci *ohci = pci_get_drvdata(dev);
3276         int err;
3277
3278         pmac_ohci_on(dev);
3279         pci_set_power_state(dev, PCI_D0);
3280         pci_restore_state(dev);
3281         err = pci_enable_device(dev);
3282         if (err) {
3283                 fw_error("pci_enable_device failed\n");
3284                 return err;
3285         }
3286
3287         return ohci_enable(&ohci->card, NULL, 0);
3288 }
3289 #endif
3290
3291 static const struct pci_device_id pci_table[] = {
3292         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3293         { }
3294 };
3295
3296 MODULE_DEVICE_TABLE(pci, pci_table);
3297
3298 static struct pci_driver fw_ohci_pci_driver = {
3299         .name           = ohci_driver_name,
3300         .id_table       = pci_table,
3301         .probe          = pci_probe,
3302         .remove         = pci_remove,
3303 #ifdef CONFIG_PM
3304         .resume         = pci_resume,
3305         .suspend        = pci_suspend,
3306 #endif
3307 };
3308
3309 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3310 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3311 MODULE_LICENSE("GPL");
3312
3313 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3314 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3315 MODULE_ALIAS("ohci1394");
3316 #endif
3317
3318 static int __init fw_ohci_init(void)
3319 {
3320         return pci_register_driver(&fw_ohci_pci_driver);
3321 }
3322
3323 static void __exit fw_ohci_cleanup(void)
3324 {
3325         pci_unregister_driver(&fw_ohci_pci_driver);
3326 }
3327
3328 module_init(fw_ohci_init);
3329 module_exit(fw_ohci_cleanup);