drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45
  46 #include <asm/byteorder.h>
  47 #include <asm/page.h>
  48 #include <asm/system.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define DESCRIPTOR_OUTPUT_MORE          0
  58 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  59 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  60 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  61 #define DESCRIPTOR_STATUS               (1 << 11)
  62 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  63 #define DESCRIPTOR_PING                 (1 << 7)
  64 #define DESCRIPTOR_YY                   (1 << 6)
  65 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  66 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  67 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  68 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  69 #define DESCRIPTOR_WAIT                 (3 << 0)
  70
  71 struct descriptor {
  72         __le16 req_count;
  73         __le16 control;
  74         __le32 data_address;
  75         __le32 branch_address;
  76         __le16 res_count;
  77         __le16 transfer_status;
  78 } __attribute__((aligned(16)));
  79
  80 #define CONTROL_SET(regs)       (regs)
  81 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  82 #define COMMAND_PTR(regs)       ((regs) + 12)
  83 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  84
  85 #define AR_BUFFER_SIZE  (32*1024)
  86 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  87 /* we need at least two pages for proper list management */
  88 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  89
  90 #define MAX_ASYNC_PAYLOAD       4096
  91 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  92 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  93
  94 struct ar_context {
  95         struct fw_ohci *ohci;
  96         struct page *pages[AR_BUFFERS];
  97         void *buffer;
  98         struct descriptor *descriptors;
  99         dma_addr_t descriptors_bus;
 100         void *pointer;
 101         unsigned int last_buffer_index;
 102         u32 regs;
 103         struct tasklet_struct tasklet;
 104 };
 105
 106 struct context;
 107
 108 typedef int (*descriptor_callback_t)(struct context *ctx,
 109                                      struct descriptor *d,
 110                                      struct descriptor *last);
 111
 112 /*
 113  * A buffer that contains a block of DMA-able coherent memory used for
 114  * storing a portion of a DMA descriptor program.
 115  */
 116 struct descriptor_buffer {
 117         struct list_head list;
 118         dma_addr_t buffer_bus;
 119         size_t buffer_size;
 120         size_t used;
 121         struct descriptor buffer[0];
 122 };
 123
 124 struct context {
 125         struct fw_ohci *ohci;
 126         u32 regs;
 127         int total_allocation;
 128         bool flushing;
 129
 130         /*
 131          * List of page-sized buffers for storing DMA descriptors.
 132          * Head of list contains buffers in use and tail of list contains
 133          * free buffers.
 134          */
 135         struct list_head buffer_list;
 136
 137         /*
 138          * Pointer to a buffer inside buffer_list that contains the tail
 139          * end of the current DMA program.
 140          */
 141         struct descriptor_buffer *buffer_tail;
 142
 143         /*
 144          * The descriptor containing the branch address of the first
 145          * descriptor that has not yet been filled by the device.
 146          */
 147         struct descriptor *last;
 148
 149         /*
 150          * The last descriptor in the DMA program.  It contains the branch
 151          * address that must be updated upon appending a new descriptor.
 152          */
 153         struct descriptor *prev;
 154
 155         descriptor_callback_t callback;
 156
 157         struct tasklet_struct tasklet;
 158         bool active;
 159 };
 160
 161 #define IT_HEADER_SY(v)          ((v) <<  0)
 162 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 163 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 164 #define IT_HEADER_TAG(v)         ((v) << 14)
 165 #define IT_HEADER_SPEED(v)       ((v) << 16)
 166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 167
 168 struct iso_context {
 169         struct fw_iso_context base;
 170         struct context context;
 171         int excess_bytes;
 172         void *header;
 173         size_t header_length;
 174
 175         u8 sync;
 176         u8 tags;
 177 };
 178
 179 #define CONFIG_ROM_SIZE 1024
 180
 181 struct fw_ohci {
 182         struct fw_card card;
 183
 184         __iomem char *registers;
 185         int node_id;
 186         int generation;
 187         int request_generation; /* for timestamping incoming requests */
 188         unsigned quirks;
 189         unsigned int pri_req_max;
 190         u32 bus_time;
 191         bool is_root;
 192         bool csr_state_setclear_abdicate;
 193         int n_ir;
 194         int n_it;
 195         /*
 196          * Spinlock for accessing fw_ohci data.  Never call out of
 197          * this driver with this lock held.
 198          */
 199         spinlock_t lock;
 200
 201         struct mutex phy_reg_mutex;
 202
 203         void *misc_buffer;
 204         dma_addr_t misc_buffer_bus;
 205
 206         struct ar_context ar_request_ctx;
 207         struct ar_context ar_response_ctx;
 208         struct context at_request_ctx;
 209         struct context at_response_ctx;
 210
 211         u32 it_context_mask;     /* unoccupied IT contexts */
 212         struct iso_context *it_context_list;
 213         u64 ir_context_channels; /* unoccupied channels */
 214         u32 ir_context_mask;     /* unoccupied IR contexts */
 215         struct iso_context *ir_context_list;
 216         u64 mc_channels; /* channels in use by the multichannel IR context */
 217         bool mc_allocated;
 218
 219         __be32    *config_rom;
 220         dma_addr_t config_rom_bus;
 221         __be32    *next_config_rom;
 222         dma_addr_t next_config_rom_bus;
 223         __be32     next_header;
 224
 225         __le32    *self_id_cpu;
 226         dma_addr_t self_id_bus;
 227         struct tasklet_struct bus_reset_tasklet;
 228
 229         u32 self_id_buffer[512];
 230 };
 231
 232 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 233 {
 234         return container_of(card, struct fw_ohci, card);
 235 }
 236
 237 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 238 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 239 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 240 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 241 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 242 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 243
 244 #define CONTEXT_RUN     0x8000
 245 #define CONTEXT_WAKE    0x1000
 246 #define CONTEXT_DEAD    0x0800
 247 #define CONTEXT_ACTIVE  0x0400
 248
 249 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 250 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 251 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 252
 253 #define OHCI1394_REGISTER_SIZE          0x800
 254 #define OHCI_LOOP_COUNT                 500
 255 #define OHCI1394_PCI_HCI_Control        0x40
 256 #define SELF_ID_BUF_SIZE                0x800
 257 #define OHCI_TCODE_PHY_PACKET           0x0e
 258 #define OHCI_VERSION_1_1                0x010010
 259
 260 static char ohci_driver_name[] = KBUILD_MODNAME;
 261
 262 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 263 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 264 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 265
 266 #define QUIRK_CYCLE_TIMER               1
 267 #define QUIRK_RESET_PACKET              2
 268 #define QUIRK_BE_HEADERS                4
 269 #define QUIRK_NO_1394A                  8
 270 #define QUIRK_NO_MSI                    16
 271
 272 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 273 static const struct {
 274         unsigned short vendor, device, revision, flags;
 275 } ohci_quirks[] = {
 276         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 277                 QUIRK_CYCLE_TIMER},
 278
 279         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 280                 QUIRK_BE_HEADERS},
 281
 282         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 283                 QUIRK_NO_MSI},
 284
 285         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 286                 QUIRK_NO_MSI},
 287
 288         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 289                 QUIRK_CYCLE_TIMER},
 290
 291         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 292                 QUIRK_CYCLE_TIMER},
 293
 294         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 295                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 296
 297         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 298                 QUIRK_RESET_PACKET},
 299
 300         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 301                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 302 };
 303
 304 /* This overrides anything that was found in ohci_quirks[]. */
 305 static int param_quirks;
 306 module_param_named(quirks, param_quirks, int, 0644);
 307 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 308         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 309         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 310         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 311         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 312         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 313         ")");
 314
 315 #define OHCI_PARAM_DEBUG_AT_AR          1
 316 #define OHCI_PARAM_DEBUG_SELFIDS        2
 317 #define OHCI_PARAM_DEBUG_IRQS           4
 318 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 319
 320 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 321
 322 static int param_debug;
 323 module_param_named(debug, param_debug, int, 0644);
 324 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 325         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 326         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 327         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 328         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 329         ", or a combination, or all = -1)");
 330
 331 static void log_irqs(u32 evt)
 332 {
 333         if (likely(!(param_debug &
 334                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 335                 return;
 336
 337         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 338             !(evt & OHCI1394_busReset))
 339                 return;
 340
 341         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 342             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 343             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 344             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 345             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 346             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 347             evt & OHCI1394_isochRx              ? " IR"                 : "",
 348             evt & OHCI1394_isochTx              ? " IT"                 : "",
 349             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 350             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 351             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 352             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 353             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 354             evt & OHCI1394_busReset             ? " busReset"           : "",
 355             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 356                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 357                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 358                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 359                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 360                     OHCI1394_cycleInconsistent |
 361                     OHCI1394_regAccessFail | OHCI1394_busReset)
 362                                                 ? " ?"                  : "");
 363 }
 364
 365 static const char *speed[] = {
 366         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 367 };
 368 static const char *power[] = {
 369         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 370         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 371 };
 372 static const char port[] = { '.', '-', 'p', 'c', };
 373
 374 static char _p(u32 *s, int shift)
 375 {
 376         return port[*s >> shift & 3];
 377 }
 378
 379 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 380 {
 381         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 382                 return;
 383
 384         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 385                   self_id_count, generation, node_id);
 386
 387         for (; self_id_count--; ++s)
 388                 if ((*s & 1 << 23) == 0)
 389                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 390                             "%s gc=%d %s %s%s%s\n",
 391                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 392                             speed[*s >> 14 & 3], *s >> 16 & 63,
 393                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 394                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 395                 else
 396                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 397                             *s, *s >> 24 & 63,
 398                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 399                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 400 }
 401
 402 static const char *evts[] = {
 403         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 404         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 405         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 406         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 407         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 408         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 409         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 410         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 411         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 412         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 413         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 414         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 415         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 416         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 417         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 418         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 419         [0x20] = "pending/cancelled",
 420 };
 421 static const char *tcodes[] = {
 422         [0x0] = "QW req",               [0x1] = "BW req",
 423         [0x2] = "W resp",               [0x3] = "-reserved-",
 424         [0x4] = "QR req",               [0x5] = "BR req",
 425         [0x6] = "QR resp",              [0x7] = "BR resp",
 426         [0x8] = "cycle start",          [0x9] = "Lk req",
 427         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 428         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 429         [0xe] = "link internal",        [0xf] = "-reserved-",
 430 };
 431
 432 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 433 {
 434         int tcode = header[0] >> 4 & 0xf;
 435         char specific[12];
 436
 437         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 438                 return;
 439
 440         if (unlikely(evt >= ARRAY_SIZE(evts)))
 441                         evt = 0x1f;
 442
 443         if (evt == OHCI1394_evt_bus_reset) {
 444                 fw_notify("A%c evt_bus_reset, generation %d\n",
 445                     dir, (header[2] >> 16) & 0xff);
 446                 return;
 447         }
 448
 449         switch (tcode) {
 450         case 0x0: case 0x6: case 0x8:
 451                 snprintf(specific, sizeof(specific), " = %08x",
 452                          be32_to_cpu((__force __be32)header[3]));
 453                 break;
 454         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 455                 snprintf(specific, sizeof(specific), " %x,%x",
 456                          header[3] >> 16, header[3] & 0xffff);
 457                 break;
 458         default:
 459                 specific[0] = '\0';
 460         }
 461
 462         switch (tcode) {
 463         case 0xa:
 464                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 465                 break;
 466         case 0xe:
 467                 fw_notify("A%c %s, PHY %08x %08x\n",
 468                           dir, evts[evt], header[1], header[2]);
 469                 break;
 470         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 471                 fw_notify("A%c spd %x tl %02x, "
 472                     "%04x -> %04x, %s, "
 473                     "%s, %04x%08x%s\n",
 474                     dir, speed, header[0] >> 10 & 0x3f,
 475                     header[1] >> 16, header[0] >> 16, evts[evt],
 476                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 477                 break;
 478         default:
 479                 fw_notify("A%c spd %x tl %02x, "
 480                     "%04x -> %04x, %s, "
 481                     "%s%s\n",
 482                     dir, speed, header[0] >> 10 & 0x3f,
 483                     header[1] >> 16, header[0] >> 16, evts[evt],
 484                     tcodes[tcode], specific);
 485         }
 486 }
 487
 488 #else
 489
 490 #define param_debug 0
 491 static inline void log_irqs(u32 evt) {}
 492 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 493 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 494
 495 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 496
 497 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 498 {
 499         writel(data, ohci->registers + offset);
 500 }
 501
 502 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 503 {
 504         return readl(ohci->registers + offset);
 505 }
 506
 507 static inline void flush_writes(const struct fw_ohci *ohci)
 508 {
 509         /* Do a dummy read to flush writes. */
 510         reg_read(ohci, OHCI1394_Version);
 511 }
 512
 513 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 514 {
 515         u32 val;
 516         int i;
 517
 518         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 519         for (i = 0; i < 3 + 100; i++) {
 520                 val = reg_read(ohci, OHCI1394_PhyControl);
 521                 if (val & OHCI1394_PhyControl_ReadDone)
 522                         return OHCI1394_PhyControl_ReadData(val);
 523
 524                 /*
 525                  * Try a few times without waiting.  Sleeping is necessary
 526                  * only when the link/PHY interface is busy.
 527                  */
 528                 if (i >= 3)
 529                         msleep(1);
 530         }
 531         fw_error("failed to read phy reg\n");
 532
 533         return -EBUSY;
 534 }
 535
 536 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 537 {
 538         int i;
 539
 540         reg_write(ohci, OHCI1394_PhyControl,
 541                   OHCI1394_PhyControl_Write(addr, val));
 542         for (i = 0; i < 3 + 100; i++) {
 543                 val = reg_read(ohci, OHCI1394_PhyControl);
 544                 if (!(val & OHCI1394_PhyControl_WritePending))
 545                         return 0;
 546
 547                 if (i >= 3)
 548                         msleep(1);
 549         }
 550         fw_error("failed to write phy reg\n");
 551
 552         return -EBUSY;
 553 }
 554
 555 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 556                           int clear_bits, int set_bits)
 557 {
 558         int ret = read_phy_reg(ohci, addr);
 559         if (ret < 0)
 560                 return ret;
 561
 562         /*
 563          * The interrupt status bits are cleared by writing a one bit.
 564          * Avoid clearing them unless explicitly requested in set_bits.
 565          */
 566         if (addr == 5)
 567                 clear_bits |= PHY_INT_STATUS_BITS;
 568
 569         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 570 }
 571
 572 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 573 {
 574         int ret;
 575
 576         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 577         if (ret < 0)
 578                 return ret;
 579
 580         return read_phy_reg(ohci, addr);
 581 }
 582
 583 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 584 {
 585         struct fw_ohci *ohci = fw_ohci(card);
 586         int ret;
 587
 588         mutex_lock(&ohci->phy_reg_mutex);
 589         ret = read_phy_reg(ohci, addr);
 590         mutex_unlock(&ohci->phy_reg_mutex);
 591
 592         return ret;
 593 }
 594
 595 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 596                                int clear_bits, int set_bits)
 597 {
 598         struct fw_ohci *ohci = fw_ohci(card);
 599         int ret;
 600
 601         mutex_lock(&ohci->phy_reg_mutex);
 602         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 603         mutex_unlock(&ohci->phy_reg_mutex);
 604
 605         return ret;
 606 }
 607
 608 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 609 {
 610         return page_private(ctx->pages[i]);
 611 }
 612
 613 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 614 {
 615         struct descriptor *d;
 616
 617         d = &ctx->descriptors[index];
 618         d->branch_address  &= cpu_to_le32(~0xf);
 619         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 620         d->transfer_status =  0;
 621
 622         wmb(); /* finish init of new descriptors before branch_address update */
 623         d = &ctx->descriptors[ctx->last_buffer_index];
 624         d->branch_address  |= cpu_to_le32(1);
 625
 626         ctx->last_buffer_index = index;
 627
 628         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 629         flush_writes(ctx->ohci);
 630 }
 631
 632 static void ar_context_release(struct ar_context *ctx)
 633 {
 634         unsigned int i;
 635
 636         if (ctx->buffer)
 637                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 638
 639         for (i = 0; i < AR_BUFFERS; i++)
 640                 if (ctx->pages[i]) {
 641                         dma_unmap_page(ctx->ohci->card.device,
 642                                        ar_buffer_bus(ctx, i),
 643                                        PAGE_SIZE, DMA_FROM_DEVICE);
 644                         __free_page(ctx->pages[i]);
 645                 }
 646 }
 647
 648 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 649 {
 650         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 651                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 652                 flush_writes(ctx->ohci);
 653
 654                 fw_error("AR error: %s; DMA stopped\n", error_msg);
 655         }
 656         /* FIXME: restart? */
 657 }
 658
 659 static inline unsigned int ar_next_buffer_index(unsigned int index)
 660 {
 661         return (index + 1) % AR_BUFFERS;
 662 }
 663
 664 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 665 {
 666         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 667 }
 668
 669 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 670 {
 671         return ar_next_buffer_index(ctx->last_buffer_index);
 672 }
 673
 674 /*
 675  * We search for the buffer that contains the last AR packet DMA data written
 676  * by the controller.
 677  */
 678 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 679                                                  unsigned int *buffer_offset)
 680 {
 681         unsigned int i, next_i, last = ctx->last_buffer_index;
 682         __le16 res_count, next_res_count;
 683
 684         i = ar_first_buffer_index(ctx);
 685         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 686
 687         /* A buffer that is not yet completely filled must be the last one. */
 688         while (i != last && res_count == 0) {
 689
 690                 /* Peek at the next descriptor. */
 691                 next_i = ar_next_buffer_index(i);
 692                 rmb(); /* read descriptors in order */
 693                 next_res_count = ACCESS_ONCE(
 694                                 ctx->descriptors[next_i].res_count);
 695                 /*
 696                  * If the next descriptor is still empty, we must stop at this
 697                  * descriptor.
 698                  */
 699                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 700                         /*
 701                          * The exception is when the DMA data for one packet is
 702                          * split over three buffers; in this case, the middle
 703                          * buffer's descriptor might be never updated by the
 704                          * controller and look still empty, and we have to peek
 705                          * at the third one.
 706                          */
 707                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 708                                 next_i = ar_next_buffer_index(next_i);
 709                                 rmb();
 710                                 next_res_count = ACCESS_ONCE(
 711                                         ctx->descriptors[next_i].res_count);
 712                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 713                                         goto next_buffer_is_active;
 714                         }
 715
 716                         break;
 717                 }
 718
 719 next_buffer_is_active:
 720                 i = next_i;
 721                 res_count = next_res_count;
 722         }
 723
 724         rmb(); /* read res_count before the DMA data */
 725
 726         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 727         if (*buffer_offset > PAGE_SIZE) {
 728                 *buffer_offset = 0;
 729                 ar_context_abort(ctx, "corrupted descriptor");
 730         }
 731
 732         return i;
 733 }
 734
 735 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 736                                     unsigned int end_buffer_index,
 737                                     unsigned int end_buffer_offset)
 738 {
 739         unsigned int i;
 740
 741         i = ar_first_buffer_index(ctx);
 742         while (i != end_buffer_index) {
 743                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 744                                         ar_buffer_bus(ctx, i),
 745                                         PAGE_SIZE, DMA_FROM_DEVICE);
 746                 i = ar_next_buffer_index(i);
 747         }
 748         if (end_buffer_offset > 0)
 749                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 750                                         ar_buffer_bus(ctx, i),
 751                                         end_buffer_offset, DMA_FROM_DEVICE);
 752 }
 753
 754 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 755 #define cond_le32_to_cpu(v) \
 756         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 757 #else
 758 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 759 #endif
 760
 761 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 762 {
 763         struct fw_ohci *ohci = ctx->ohci;
 764         struct fw_packet p;
 765         u32 status, length, tcode;
 766         int evt;
 767
 768         p.header[0] = cond_le32_to_cpu(buffer[0]);
 769         p.header[1] = cond_le32_to_cpu(buffer[1]);
 770         p.header[2] = cond_le32_to_cpu(buffer[2]);
 771
 772         tcode = (p.header[0] >> 4) & 0x0f;
 773         switch (tcode) {
 774         case TCODE_WRITE_QUADLET_REQUEST:
 775         case TCODE_READ_QUADLET_RESPONSE:
 776                 p.header[3] = (__force __u32) buffer[3];
 777                 p.header_length = 16;
 778                 p.payload_length = 0;
 779                 break;
 780
 781         case TCODE_READ_BLOCK_REQUEST :
 782                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 783                 p.header_length = 16;
 784                 p.payload_length = 0;
 785                 break;
 786
 787         case TCODE_WRITE_BLOCK_REQUEST:
 788         case TCODE_READ_BLOCK_RESPONSE:
 789         case TCODE_LOCK_REQUEST:
 790         case TCODE_LOCK_RESPONSE:
 791                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 792                 p.header_length = 16;
 793                 p.payload_length = p.header[3] >> 16;
 794                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 795                         ar_context_abort(ctx, "invalid packet length");
 796                         return NULL;
 797                 }
 798                 break;
 799
 800         case TCODE_WRITE_RESPONSE:
 801         case TCODE_READ_QUADLET_REQUEST:
 802         case OHCI_TCODE_PHY_PACKET:
 803                 p.header_length = 12;
 804                 p.payload_length = 0;
 805                 break;
 806
 807         default:
 808                 ar_context_abort(ctx, "invalid tcode");
 809                 return NULL;
 810         }
 811
 812         p.payload = (void *) buffer + p.header_length;
 813
 814         /* FIXME: What to do about evt_* errors? */
 815         length = (p.header_length + p.payload_length + 3) / 4;
 816         status = cond_le32_to_cpu(buffer[length]);
 817         evt    = (status >> 16) & 0x1f;
 818
 819         p.ack        = evt - 16;
 820         p.speed      = (status >> 21) & 0x7;
 821         p.timestamp  = status & 0xffff;
 822         p.generation = ohci->request_generation;
 823
 824         log_ar_at_event('R', p.speed, p.header, evt);
 825
 826         /*
 827          * Several controllers, notably from NEC and VIA, forget to
 828          * write ack_complete status at PHY packet reception.
 829          */
 830         if (evt == OHCI1394_evt_no_status &&
 831             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 832                 p.ack = ACK_COMPLETE;
 833
 834         /*
 835          * The OHCI bus reset handler synthesizes a PHY packet with
 836          * the new generation number when a bus reset happens (see
 837          * section 8.4.2.3).  This helps us determine when a request
 838          * was received and make sure we send the response in the same
 839          * generation.  We only need this for requests; for responses
 840          * we use the unique tlabel for finding the matching
 841          * request.
 842          *
 843          * Alas some chips sometimes emit bus reset packets with a
 844          * wrong generation.  We set the correct generation for these
 845          * at a slightly incorrect time (in bus_reset_tasklet).
 846          */
 847         if (evt == OHCI1394_evt_bus_reset) {
 848                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 849                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 850         } else if (ctx == &ohci->ar_request_ctx) {
 851                 fw_core_handle_request(&ohci->card, &p);
 852         } else {
 853                 fw_core_handle_response(&ohci->card, &p);
 854         }
 855
 856         return buffer + length + 1;
 857 }
 858
 859 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 860 {
 861         void *next;
 862
 863         while (p < end) {
 864                 next = handle_ar_packet(ctx, p);
 865                 if (!next)
 866                         return p;
 867                 p = next;
 868         }
 869
 870         return p;
 871 }
 872
 873 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 874 {
 875         unsigned int i;
 876
 877         i = ar_first_buffer_index(ctx);
 878         while (i != end_buffer) {
 879                 dma_sync_single_for_device(ctx->ohci->card.device,
 880                                            ar_buffer_bus(ctx, i),
 881                                            PAGE_SIZE, DMA_FROM_DEVICE);
 882                 ar_context_link_page(ctx, i);
 883                 i = ar_next_buffer_index(i);
 884         }
 885 }
 886
 887 static void ar_context_tasklet(unsigned long data)
 888 {
 889         struct ar_context *ctx = (struct ar_context *)data;
 890         unsigned int end_buffer_index, end_buffer_offset;
 891         void *p, *end;
 892
 893         p = ctx->pointer;
 894         if (!p)
 895                 return;
 896
 897         end_buffer_index = ar_search_last_active_buffer(ctx,
 898                                                         &end_buffer_offset);
 899         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 900         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 901
 902         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 903                 /*
 904                  * The filled part of the overall buffer wraps around; handle
 905                  * all packets up to the buffer end here.  If the last packet
 906                  * wraps around, its tail will be visible after the buffer end
 907                  * because the buffer start pages are mapped there again.
 908                  */
 909                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 910                 p = handle_ar_packets(ctx, p, buffer_end);
 911                 if (p < buffer_end)
 912                         goto error;
 913                 /* adjust p to point back into the actual buffer */
 914                 p -= AR_BUFFERS * PAGE_SIZE;
 915         }
 916
 917         p = handle_ar_packets(ctx, p, end);
 918         if (p != end) {
 919                 if (p > end)
 920                         ar_context_abort(ctx, "inconsistent descriptor");
 921                 goto error;
 922         }
 923
 924         ctx->pointer = p;
 925         ar_recycle_buffers(ctx, end_buffer_index);
 926
 927         return;
 928
 929 error:
 930         ctx->pointer = NULL;
 931 }
 932
 933 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 934                            unsigned int descriptors_offset, u32 regs)
 935 {
 936         unsigned int i;
 937         dma_addr_t dma_addr;
 938         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 939         struct descriptor *d;
 940
 941         ctx->regs        = regs;
 942         ctx->ohci        = ohci;
 943         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 944
 945         for (i = 0; i < AR_BUFFERS; i++) {
 946                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 947                 if (!ctx->pages[i])
 948                         goto out_of_memory;
 949                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 950                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 951                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 952                         __free_page(ctx->pages[i]);
 953                         ctx->pages[i] = NULL;
 954                         goto out_of_memory;
 955                 }
 956                 set_page_private(ctx->pages[i], dma_addr);
 957         }
 958
 959         for (i = 0; i < AR_BUFFERS; i++)
 960                 pages[i]              = ctx->pages[i];
 961         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 962                 pages[AR_BUFFERS + i] = ctx->pages[i];
 963         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 964                                  -1, PAGE_KERNEL_RO);
 965         if (!ctx->buffer)
 966                 goto out_of_memory;
 967
 968         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
 969         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
 970
 971         for (i = 0; i < AR_BUFFERS; i++) {
 972                 d = &ctx->descriptors[i];
 973                 d->req_count      = cpu_to_le16(PAGE_SIZE);
 974                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 975                                                 DESCRIPTOR_STATUS |
 976                                                 DESCRIPTOR_BRANCH_ALWAYS);
 977                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
 978                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
 979                         ar_next_buffer_index(i) * sizeof(struct descriptor));
 980         }
 981
 982         return 0;
 983
 984 out_of_memory:
 985         ar_context_release(ctx);
 986
 987         return -ENOMEM;
 988 }
 989
 990 static void ar_context_run(struct ar_context *ctx)
 991 {
 992         unsigned int i;
 993
 994         for (i = 0; i < AR_BUFFERS; i++)
 995                 ar_context_link_page(ctx, i);
 996
 997         ctx->pointer = ctx->buffer;
 998
 999         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1000         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1001         flush_writes(ctx->ohci);
1002 }
1003
1004 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1005 {
1006         int b, key;
1007
1008         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1009         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1010
1011         /* figure out which descriptor the branch address goes in */
1012         if (z == 2 && (b == 3 || key == 2))
1013                 return d;
1014         else
1015                 return d + z - 1;
1016 }
1017
1018 static void context_tasklet(unsigned long data)
1019 {
1020         struct context *ctx = (struct context *) data;
1021         struct descriptor *d, *last;
1022         u32 address;
1023         int z;
1024         struct descriptor_buffer *desc;
1025
1026         desc = list_entry(ctx->buffer_list.next,
1027                         struct descriptor_buffer, list);
1028         last = ctx->last;
1029         while (last->branch_address != 0) {
1030                 struct descriptor_buffer *old_desc = desc;
1031                 address = le32_to_cpu(last->branch_address);
1032                 z = address & 0xf;
1033                 address &= ~0xf;
1034
1035                 /* If the branch address points to a buffer outside of the
1036                  * current buffer, advance to the next buffer. */
1037                 if (address < desc->buffer_bus ||
1038                                 address >= desc->buffer_bus + desc->used)
1039                         desc = list_entry(desc->list.next,
1040                                         struct descriptor_buffer, list);
1041                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1042                 last = find_branch_descriptor(d, z);
1043
1044                 if (!ctx->callback(ctx, d, last))
1045                         break;
1046
1047                 if (old_desc != desc) {
1048                         /* If we've advanced to the next buffer, move the
1049                          * previous buffer to the free list. */
1050                         unsigned long flags;
1051                         old_desc->used = 0;
1052                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1053                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1054                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1055                 }
1056                 ctx->last = last;
1057         }
1058 }
1059
1060 /*
1061  * Allocate a new buffer and add it to the list of free buffers for this
1062  * context.  Must be called with ohci->lock held.
1063  */
1064 static int context_add_buffer(struct context *ctx)
1065 {
1066         struct descriptor_buffer *desc;
1067         dma_addr_t uninitialized_var(bus_addr);
1068         int offset;
1069
1070         /*
1071          * 16MB of descriptors should be far more than enough for any DMA
1072          * program.  This will catch run-away userspace or DoS attacks.
1073          */
1074         if (ctx->total_allocation >= 16*1024*1024)
1075                 return -ENOMEM;
1076
1077         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1078                         &bus_addr, GFP_ATOMIC);
1079         if (!desc)
1080                 return -ENOMEM;
1081
1082         offset = (void *)&desc->buffer - (void *)desc;
1083         desc->buffer_size = PAGE_SIZE - offset;
1084         desc->buffer_bus = bus_addr + offset;
1085         desc->used = 0;
1086
1087         list_add_tail(&desc->list, &ctx->buffer_list);
1088         ctx->total_allocation += PAGE_SIZE;
1089
1090         return 0;
1091 }
1092
1093 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1094                         u32 regs, descriptor_callback_t callback)
1095 {
1096         ctx->ohci = ohci;
1097         ctx->regs = regs;
1098         ctx->total_allocation = 0;
1099
1100         INIT_LIST_HEAD(&ctx->buffer_list);
1101         if (context_add_buffer(ctx) < 0)
1102                 return -ENOMEM;
1103
1104         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1105                         struct descriptor_buffer, list);
1106
1107         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1108         ctx->callback = callback;
1109
1110         /*
1111          * We put a dummy descriptor in the buffer that has a NULL
1112          * branch address and looks like it's been sent.  That way we
1113          * have a descriptor to append DMA programs to.
1114          */
1115         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1116         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1117         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1118         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1119         ctx->last = ctx->buffer_tail->buffer;
1120         ctx->prev = ctx->buffer_tail->buffer;
1121
1122         return 0;
1123 }
1124
1125 static void context_release(struct context *ctx)
1126 {
1127         struct fw_card *card = &ctx->ohci->card;
1128         struct descriptor_buffer *desc, *tmp;
1129
1130         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1131                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1132                         desc->buffer_bus -
1133                         ((void *)&desc->buffer - (void *)desc));
1134 }
1135
1136 /* Must be called with ohci->lock held */
1137 static struct descriptor *context_get_descriptors(struct context *ctx,
1138                                                   int z, dma_addr_t *d_bus)
1139 {
1140         struct descriptor *d = NULL;
1141         struct descriptor_buffer *desc = ctx->buffer_tail;
1142
1143         if (z * sizeof(*d) > desc->buffer_size)
1144                 return NULL;
1145
1146         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1147                 /* No room for the descriptor in this buffer, so advance to the
1148                  * next one. */
1149
1150                 if (desc->list.next == &ctx->buffer_list) {
1151                         /* If there is no free buffer next in the list,
1152                          * allocate one. */
1153                         if (context_add_buffer(ctx) < 0)
1154                                 return NULL;
1155                 }
1156                 desc = list_entry(desc->list.next,
1157                                 struct descriptor_buffer, list);
1158                 ctx->buffer_tail = desc;
1159         }
1160
1161         d = desc->buffer + desc->used / sizeof(*d);
1162         memset(d, 0, z * sizeof(*d));
1163         *d_bus = desc->buffer_bus + desc->used;
1164
1165         return d;
1166 }
1167
1168 static void context_run(struct context *ctx, u32 extra)
1169 {
1170         struct fw_ohci *ohci = ctx->ohci;
1171         ctx->active = true;
1172
1173         reg_write(ohci, COMMAND_PTR(ctx->regs),
1174                   le32_to_cpu(ctx->last->branch_address));
1175         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1176         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1177         flush_writes(ohci);
1178 }
1179
1180 static void context_append(struct context *ctx,
1181                            struct descriptor *d, int z, int extra)
1182 {
1183         dma_addr_t d_bus;
1184         struct descriptor_buffer *desc = ctx->buffer_tail;
1185
1186         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1187
1188         desc->used += (z + extra) * sizeof(*d);
1189
1190         wmb(); /* finish init of new descriptors before branch_address update */
1191         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1192         ctx->prev = find_branch_descriptor(d, z);
1193
1194         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1195         flush_writes(ctx->ohci);
1196 }
1197
1198 static void context_stop(struct context *ctx)
1199 {
1200         u32 reg;
1201         int i;
1202
1203         ctx->active = false;
1204         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1205         flush_writes(ctx->ohci);
1206
1207         for (i = 0; i < 10; i++) {
1208                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1209                 if ((reg & CONTEXT_ACTIVE) == 0)
1210                         return;
1211
1212                 mdelay(1);
1213         }
1214         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1215 }
1216
1217 struct driver_data {
1218         struct fw_packet *packet;
1219 };
1220
1221 /*
1222  * This function apppends a packet to the DMA queue for transmission.
1223  * Must always be called with the ochi->lock held to ensure proper
1224  * generation handling and locking around packet queue manipulation.
1225  */
1226 static int at_context_queue_packet(struct context *ctx,
1227                                    struct fw_packet *packet)
1228 {
1229         struct fw_ohci *ohci = ctx->ohci;
1230         dma_addr_t d_bus, uninitialized_var(payload_bus);
1231         struct driver_data *driver_data;
1232         struct descriptor *d, *last;
1233         __le32 *header;
1234         int z, tcode;
1235         u32 reg;
1236
1237         d = context_get_descriptors(ctx, 4, &d_bus);
1238         if (d == NULL) {
1239                 packet->ack = RCODE_SEND_ERROR;
1240                 return -1;
1241         }
1242
1243         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1244         d[0].res_count = cpu_to_le16(packet->timestamp);
1245
1246         /*
1247          * The DMA format for asyncronous link packets is different
1248          * from the IEEE1394 layout, so shift the fields around
1249          * accordingly.
1250          */
1251
1252         tcode = (packet->header[0] >> 4) & 0x0f;
1253         header = (__le32 *) &d[1];
1254         switch (tcode) {
1255         case TCODE_WRITE_QUADLET_REQUEST:
1256         case TCODE_WRITE_BLOCK_REQUEST:
1257         case TCODE_WRITE_RESPONSE:
1258         case TCODE_READ_QUADLET_REQUEST:
1259         case TCODE_READ_BLOCK_REQUEST:
1260         case TCODE_READ_QUADLET_RESPONSE:
1261         case TCODE_READ_BLOCK_RESPONSE:
1262         case TCODE_LOCK_REQUEST:
1263         case TCODE_LOCK_RESPONSE:
1264                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1265                                         (packet->speed << 16));
1266                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1267                                         (packet->header[0] & 0xffff0000));
1268                 header[2] = cpu_to_le32(packet->header[2]);
1269
1270                 if (TCODE_IS_BLOCK_PACKET(tcode))
1271                         header[3] = cpu_to_le32(packet->header[3]);
1272                 else
1273                         header[3] = (__force __le32) packet->header[3];
1274
1275                 d[0].req_count = cpu_to_le16(packet->header_length);
1276                 break;
1277
1278         case TCODE_LINK_INTERNAL:
1279                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1280                                         (packet->speed << 16));
1281                 header[1] = cpu_to_le32(packet->header[1]);
1282                 header[2] = cpu_to_le32(packet->header[2]);
1283                 d[0].req_count = cpu_to_le16(12);
1284
1285                 if (is_ping_packet(&packet->header[1]))
1286                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1287                 break;
1288
1289         case TCODE_STREAM_DATA:
1290                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1291                                         (packet->speed << 16));
1292                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1293                 d[0].req_count = cpu_to_le16(8);
1294                 break;
1295
1296         default:
1297                 /* BUG(); */
1298                 packet->ack = RCODE_SEND_ERROR;
1299                 return -1;
1300         }
1301
1302         driver_data = (struct driver_data *) &d[3];
1303         driver_data->packet = packet;
1304         packet->driver_data = driver_data;
1305
1306         if (packet->payload_length > 0) {
1307                 payload_bus =
1308                         dma_map_single(ohci->card.device, packet->payload,
1309                                        packet->payload_length, DMA_TO_DEVICE);
1310                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1311                         packet->ack = RCODE_SEND_ERROR;
1312                         return -1;
1313                 }
1314                 packet->payload_bus     = payload_bus;
1315                 packet->payload_mapped  = true;
1316
1317                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1318                 d[2].data_address = cpu_to_le32(payload_bus);
1319                 last = &d[2];
1320                 z = 3;
1321         } else {
1322                 last = &d[0];
1323                 z = 2;
1324         }
1325
1326         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1327                                      DESCRIPTOR_IRQ_ALWAYS |
1328                                      DESCRIPTOR_BRANCH_ALWAYS);
1329
1330         /*
1331          * If the controller and packet generations don't match, we need to
1332          * bail out and try again.  If IntEvent.busReset is set, the AT context
1333          * is halted, so appending to the context and trying to run it is
1334          * futile.  Most controllers do the right thing and just flush the AT
1335          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1336          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1337          * up stalling out.  So we just bail out in software and try again
1338          * later, and everyone is happy.
1339          * FIXME: Document how the locking works.
1340          */
1341         if (ohci->generation != packet->generation ||
1342             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1343                 if (packet->payload_mapped)
1344                         dma_unmap_single(ohci->card.device, payload_bus,
1345                                          packet->payload_length, DMA_TO_DEVICE);
1346                 packet->ack = RCODE_GENERATION;
1347                 return -1;
1348         }
1349
1350         context_append(ctx, d, z, 4 - z);
1351
1352         /* If the context isn't already running, start it up. */
1353         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1354         if ((reg & CONTEXT_RUN) == 0)
1355                 context_run(ctx, 0);
1356
1357         return 0;
1358 }
1359
1360 static void at_context_flush(struct context *ctx)
1361 {
1362         tasklet_disable(&ctx->tasklet);
1363
1364         ctx->flushing = true;
1365         context_tasklet((unsigned long)ctx);
1366         ctx->flushing = false;
1367
1368         tasklet_enable(&ctx->tasklet);
1369 }
1370
1371 static int handle_at_packet(struct context *context,
1372                             struct descriptor *d,
1373                             struct descriptor *last)
1374 {
1375         struct driver_data *driver_data;
1376         struct fw_packet *packet;
1377         struct fw_ohci *ohci = context->ohci;
1378         int evt;
1379
1380         if (last->transfer_status == 0 && !context->flushing)
1381                 /* This descriptor isn't done yet, stop iteration. */
1382                 return 0;
1383
1384         driver_data = (struct driver_data *) &d[3];
1385         packet = driver_data->packet;
1386         if (packet == NULL)
1387                 /* This packet was cancelled, just continue. */
1388                 return 1;
1389
1390         if (packet->payload_mapped)
1391                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1392                                  packet->payload_length, DMA_TO_DEVICE);
1393
1394         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1395         packet->timestamp = le16_to_cpu(last->res_count);
1396
1397         log_ar_at_event('T', packet->speed, packet->header, evt);
1398
1399         switch (evt) {
1400         case OHCI1394_evt_timeout:
1401                 /* Async response transmit timed out. */
1402                 packet->ack = RCODE_CANCELLED;
1403                 break;
1404
1405         case OHCI1394_evt_flushed:
1406                 /*
1407                  * The packet was flushed should give same error as
1408                  * when we try to use a stale generation count.
1409                  */
1410                 packet->ack = RCODE_GENERATION;
1411                 break;
1412
1413         case OHCI1394_evt_missing_ack:
1414                 if (context->flushing)
1415                         packet->ack = RCODE_GENERATION;
1416                 else {
1417                         /*
1418                          * Using a valid (current) generation count, but the
1419                          * node is not on the bus or not sending acks.
1420                          */
1421                         packet->ack = RCODE_NO_ACK;
1422                 }
1423                 break;
1424
1425         case ACK_COMPLETE + 0x10:
1426         case ACK_PENDING + 0x10:
1427         case ACK_BUSY_X + 0x10:
1428         case ACK_BUSY_A + 0x10:
1429         case ACK_BUSY_B + 0x10:
1430         case ACK_DATA_ERROR + 0x10:
1431         case ACK_TYPE_ERROR + 0x10:
1432                 packet->ack = evt - 0x10;
1433                 break;
1434
1435         case OHCI1394_evt_no_status:
1436                 if (context->flushing) {
1437                         packet->ack = RCODE_GENERATION;
1438                         break;
1439                 }
1440                 /* fall through */
1441
1442         default:
1443                 packet->ack = RCODE_SEND_ERROR;
1444                 break;
1445         }
1446
1447         packet->callback(packet, &ohci->card, packet->ack);
1448
1449         return 1;
1450 }
1451
1452 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1453 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1454 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1455 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1456 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1457
1458 static void handle_local_rom(struct fw_ohci *ohci,
1459                              struct fw_packet *packet, u32 csr)
1460 {
1461         struct fw_packet response;
1462         int tcode, length, i;
1463
1464         tcode = HEADER_GET_TCODE(packet->header[0]);
1465         if (TCODE_IS_BLOCK_PACKET(tcode))
1466                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1467         else
1468                 length = 4;
1469
1470         i = csr - CSR_CONFIG_ROM;
1471         if (i + length > CONFIG_ROM_SIZE) {
1472                 fw_fill_response(&response, packet->header,
1473                                  RCODE_ADDRESS_ERROR, NULL, 0);
1474         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1475                 fw_fill_response(&response, packet->header,
1476                                  RCODE_TYPE_ERROR, NULL, 0);
1477         } else {
1478                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1479                                  (void *) ohci->config_rom + i, length);
1480         }
1481
1482         fw_core_handle_response(&ohci->card, &response);
1483 }
1484
1485 static void handle_local_lock(struct fw_ohci *ohci,
1486                               struct fw_packet *packet, u32 csr)
1487 {
1488         struct fw_packet response;
1489         int tcode, length, ext_tcode, sel, try;
1490         __be32 *payload, lock_old;
1491         u32 lock_arg, lock_data;
1492
1493         tcode = HEADER_GET_TCODE(packet->header[0]);
1494         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1495         payload = packet->payload;
1496         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1497
1498         if (tcode == TCODE_LOCK_REQUEST &&
1499             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1500                 lock_arg = be32_to_cpu(payload[0]);
1501                 lock_data = be32_to_cpu(payload[1]);
1502         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1503                 lock_arg = 0;
1504                 lock_data = 0;
1505         } else {
1506                 fw_fill_response(&response, packet->header,
1507                                  RCODE_TYPE_ERROR, NULL, 0);
1508                 goto out;
1509         }
1510
1511         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1512         reg_write(ohci, OHCI1394_CSRData, lock_data);
1513         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1514         reg_write(ohci, OHCI1394_CSRControl, sel);
1515
1516         for (try = 0; try < 20; try++)
1517                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1518                         lock_old = cpu_to_be32(reg_read(ohci,
1519                                                         OHCI1394_CSRData));
1520                         fw_fill_response(&response, packet->header,
1521                                          RCODE_COMPLETE,
1522                                          &lock_old, sizeof(lock_old));
1523                         goto out;
1524                 }
1525
1526         fw_error("swap not done (CSR lock timeout)\n");
1527         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1528
1529  out:
1530         fw_core_handle_response(&ohci->card, &response);
1531 }
1532
1533 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1534 {
1535         u64 offset, csr;
1536
1537         if (ctx == &ctx->ohci->at_request_ctx) {
1538                 packet->ack = ACK_PENDING;
1539                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1540         }
1541
1542         offset =
1543                 ((unsigned long long)
1544                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1545                 packet->header[2];
1546         csr = offset - CSR_REGISTER_BASE;
1547
1548         /* Handle config rom reads. */
1549         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1550                 handle_local_rom(ctx->ohci, packet, csr);
1551         else switch (csr) {
1552         case CSR_BUS_MANAGER_ID:
1553         case CSR_BANDWIDTH_AVAILABLE:
1554         case CSR_CHANNELS_AVAILABLE_HI:
1555         case CSR_CHANNELS_AVAILABLE_LO:
1556                 handle_local_lock(ctx->ohci, packet, csr);
1557                 break;
1558         default:
1559                 if (ctx == &ctx->ohci->at_request_ctx)
1560                         fw_core_handle_request(&ctx->ohci->card, packet);
1561                 else
1562                         fw_core_handle_response(&ctx->ohci->card, packet);
1563                 break;
1564         }
1565
1566         if (ctx == &ctx->ohci->at_response_ctx) {
1567                 packet->ack = ACK_COMPLETE;
1568                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1569         }
1570 }
1571
1572 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1573 {
1574         unsigned long flags;
1575         int ret;
1576
1577         spin_lock_irqsave(&ctx->ohci->lock, flags);
1578
1579         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1580             ctx->ohci->generation == packet->generation) {
1581                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1582                 handle_local_request(ctx, packet);
1583                 return;
1584         }
1585
1586         ret = at_context_queue_packet(ctx, packet);
1587         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1588
1589         if (ret < 0)
1590                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1591
1592 }
1593
1594 static u32 cycle_timer_ticks(u32 cycle_timer)
1595 {
1596         u32 ticks;
1597
1598         ticks = cycle_timer & 0xfff;
1599         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1600         ticks += (3072 * 8000) * (cycle_timer >> 25);
1601
1602         return ticks;
1603 }
1604
1605 /*
1606  * Some controllers exhibit one or more of the following bugs when updating the
1607  * iso cycle timer register:
1608  *  - When the lowest six bits are wrapping around to zero, a read that happens
1609  *    at the same time will return garbage in the lowest ten bits.
1610  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1611  *    not incremented for about 60 ns.
1612  *  - Occasionally, the entire register reads zero.
1613  *
1614  * To catch these, we read the register three times and ensure that the
1615  * difference between each two consecutive reads is approximately the same, i.e.
1616  * less than twice the other.  Furthermore, any negative difference indicates an
1617  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1618  * execute, so we have enough precision to compute the ratio of the differences.)
1619  */
1620 static u32 get_cycle_time(struct fw_ohci *ohci)
1621 {
1622         u32 c0, c1, c2;
1623         u32 t0, t1, t2;
1624         s32 diff01, diff12;
1625         int i;
1626
1627         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1628
1629         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1630                 i = 0;
1631                 c1 = c2;
1632                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1633                 do {
1634                         c0 = c1;
1635                         c1 = c2;
1636                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1637                         t0 = cycle_timer_ticks(c0);
1638                         t1 = cycle_timer_ticks(c1);
1639                         t2 = cycle_timer_ticks(c2);
1640                         diff01 = t1 - t0;
1641                         diff12 = t2 - t1;
1642                 } while ((diff01 <= 0 || diff12 <= 0 ||
1643                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1644                          && i++ < 20);
1645         }
1646
1647         return c2;
1648 }
1649
1650 /*
1651  * This function has to be called at least every 64 seconds.  The bus_time
1652  * field stores not only the upper 25 bits of the BUS_TIME register but also
1653  * the most significant bit of the cycle timer in bit 6 so that we can detect
1654  * changes in this bit.
1655  */
1656 static u32 update_bus_time(struct fw_ohci *ohci)
1657 {
1658         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1659
1660         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1661                 ohci->bus_time += 0x40;
1662
1663         return ohci->bus_time | cycle_time_seconds;
1664 }
1665
1666 static void bus_reset_tasklet(unsigned long data)
1667 {
1668         struct fw_ohci *ohci = (struct fw_ohci *)data;
1669         int self_id_count, i, j, reg;
1670         int generation, new_generation;
1671         unsigned long flags;
1672         void *free_rom = NULL;
1673         dma_addr_t free_rom_bus = 0;
1674         bool is_new_root;
1675
1676         reg = reg_read(ohci, OHCI1394_NodeID);
1677         if (!(reg & OHCI1394_NodeID_idValid)) {
1678                 fw_notify("node ID not valid, new bus reset in progress\n");
1679                 return;
1680         }
1681         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1682                 fw_notify("malconfigured bus\n");
1683                 return;
1684         }
1685         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1686                                OHCI1394_NodeID_nodeNumber);
1687
1688         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1689         if (!(ohci->is_root && is_new_root))
1690                 reg_write(ohci, OHCI1394_LinkControlSet,
1691                           OHCI1394_LinkControl_cycleMaster);
1692         ohci->is_root = is_new_root;
1693
1694         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1695         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1696                 fw_notify("inconsistent self IDs\n");
1697                 return;
1698         }
1699         /*
1700          * The count in the SelfIDCount register is the number of
1701          * bytes in the self ID receive buffer.  Since we also receive
1702          * the inverted quadlets and a header quadlet, we shift one
1703          * bit extra to get the actual number of self IDs.
1704          */
1705         self_id_count = (reg >> 3) & 0xff;
1706         if (self_id_count == 0 || self_id_count > 252) {
1707                 fw_notify("inconsistent self IDs\n");
1708                 return;
1709         }
1710         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1711         rmb();
1712
1713         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1714                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1715                         fw_notify("inconsistent self IDs\n");
1716                         return;
1717                 }
1718                 ohci->self_id_buffer[j] =
1719                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1720         }
1721         rmb();
1722
1723         /*
1724          * Check the consistency of the self IDs we just read.  The
1725          * problem we face is that a new bus reset can start while we
1726          * read out the self IDs from the DMA buffer. If this happens,
1727          * the DMA buffer will be overwritten with new self IDs and we
1728          * will read out inconsistent data.  The OHCI specification
1729          * (section 11.2) recommends a technique similar to
1730          * linux/seqlock.h, where we remember the generation of the
1731          * self IDs in the buffer before reading them out and compare
1732          * it to the current generation after reading them out.  If
1733          * the two generations match we know we have a consistent set
1734          * of self IDs.
1735          */
1736
1737         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1738         if (new_generation != generation) {
1739                 fw_notify("recursive bus reset detected, "
1740                           "discarding self ids\n");
1741                 return;
1742         }
1743
1744         /* FIXME: Document how the locking works. */
1745         spin_lock_irqsave(&ohci->lock, flags);
1746
1747         ohci->generation = -1; /* prevent AT packet queueing */
1748         context_stop(&ohci->at_request_ctx);
1749         context_stop(&ohci->at_response_ctx);
1750
1751         spin_unlock_irqrestore(&ohci->lock, flags);
1752
1753         at_context_flush(&ohci->at_request_ctx);
1754         at_context_flush(&ohci->at_response_ctx);
1755
1756         spin_lock_irqsave(&ohci->lock, flags);
1757
1758         ohci->generation = generation;
1759         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1760
1761         if (ohci->quirks & QUIRK_RESET_PACKET)
1762                 ohci->request_generation = generation;
1763
1764         /*
1765          * This next bit is unrelated to the AT context stuff but we
1766          * have to do it under the spinlock also.  If a new config rom
1767          * was set up before this reset, the old one is now no longer
1768          * in use and we can free it. Update the config rom pointers
1769          * to point to the current config rom and clear the
1770          * next_config_rom pointer so a new update can take place.
1771          */
1772
1773         if (ohci->next_config_rom != NULL) {
1774                 if (ohci->next_config_rom != ohci->config_rom) {
1775                         free_rom      = ohci->config_rom;
1776                         free_rom_bus  = ohci->config_rom_bus;
1777                 }
1778                 ohci->config_rom      = ohci->next_config_rom;
1779                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1780                 ohci->next_config_rom = NULL;
1781
1782                 /*
1783                  * Restore config_rom image and manually update
1784                  * config_rom registers.  Writing the header quadlet
1785                  * will indicate that the config rom is ready, so we
1786                  * do that last.
1787                  */
1788                 reg_write(ohci, OHCI1394_BusOptions,
1789                           be32_to_cpu(ohci->config_rom[2]));
1790                 ohci->config_rom[0] = ohci->next_header;
1791                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1792                           be32_to_cpu(ohci->next_header));
1793         }
1794
1795 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1796         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1797         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1798 #endif
1799
1800         spin_unlock_irqrestore(&ohci->lock, flags);
1801
1802         if (free_rom)
1803                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1804                                   free_rom, free_rom_bus);
1805
1806         log_selfids(ohci->node_id, generation,
1807                     self_id_count, ohci->self_id_buffer);
1808
1809         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1810                                  self_id_count, ohci->self_id_buffer,
1811                                  ohci->csr_state_setclear_abdicate);
1812         ohci->csr_state_setclear_abdicate = false;
1813 }
1814
1815 static irqreturn_t irq_handler(int irq, void *data)
1816 {
1817         struct fw_ohci *ohci = data;
1818         u32 event, iso_event;
1819         int i;
1820
1821         event = reg_read(ohci, OHCI1394_IntEventClear);
1822
1823         if (!event || !~event)
1824                 return IRQ_NONE;
1825
1826         /*
1827          * busReset and postedWriteErr must not be cleared yet
1828          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1829          */
1830         reg_write(ohci, OHCI1394_IntEventClear,
1831                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1832         log_irqs(event);
1833
1834         if (event & OHCI1394_selfIDComplete)
1835                 tasklet_schedule(&ohci->bus_reset_tasklet);
1836
1837         if (event & OHCI1394_RQPkt)
1838                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1839
1840         if (event & OHCI1394_RSPkt)
1841                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1842
1843         if (event & OHCI1394_reqTxComplete)
1844                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1845
1846         if (event & OHCI1394_respTxComplete)
1847                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1848
1849         if (event & OHCI1394_isochRx) {
1850                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1851                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1852
1853                 while (iso_event) {
1854                         i = ffs(iso_event) - 1;
1855                         tasklet_schedule(
1856                                 &ohci->ir_context_list[i].context.tasklet);
1857                         iso_event &= ~(1 << i);
1858                 }
1859         }
1860
1861         if (event & OHCI1394_isochTx) {
1862                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1863                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1864
1865                 while (iso_event) {
1866                         i = ffs(iso_event) - 1;
1867                         tasklet_schedule(
1868                                 &ohci->it_context_list[i].context.tasklet);
1869                         iso_event &= ~(1 << i);
1870                 }
1871         }
1872
1873         if (unlikely(event & OHCI1394_regAccessFail))
1874                 fw_error("Register access failure - "
1875                          "please notify linux1394-devel@lists.sf.net\n");
1876
1877         if (unlikely(event & OHCI1394_postedWriteErr)) {
1878                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1879                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1880                 reg_write(ohci, OHCI1394_IntEventClear,
1881                           OHCI1394_postedWriteErr);
1882                 fw_error("PCI posted write error\n");
1883         }
1884
1885         if (unlikely(event & OHCI1394_cycleTooLong)) {
1886                 if (printk_ratelimit())
1887                         fw_notify("isochronous cycle too long\n");
1888                 reg_write(ohci, OHCI1394_LinkControlSet,
1889                           OHCI1394_LinkControl_cycleMaster);
1890         }
1891
1892         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1893                 /*
1894                  * We need to clear this event bit in order to make
1895                  * cycleMatch isochronous I/O work.  In theory we should
1896                  * stop active cycleMatch iso contexts now and restart
1897                  * them at least two cycles later.  (FIXME?)
1898                  */
1899                 if (printk_ratelimit())
1900                         fw_notify("isochronous cycle inconsistent\n");
1901         }
1902
1903         if (event & OHCI1394_cycle64Seconds) {
1904                 spin_lock(&ohci->lock);
1905                 update_bus_time(ohci);
1906                 spin_unlock(&ohci->lock);
1907         } else
1908                 flush_writes(ohci);
1909
1910         return IRQ_HANDLED;
1911 }
1912
1913 static int software_reset(struct fw_ohci *ohci)
1914 {
1915         int i;
1916
1917         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1918
1919         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1920                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1921                      OHCI1394_HCControl_softReset) == 0)
1922                         return 0;
1923                 msleep(1);
1924         }
1925
1926         return -EBUSY;
1927 }
1928
1929 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1930 {
1931         size_t size = length * 4;
1932
1933         memcpy(dest, src, size);
1934         if (size < CONFIG_ROM_SIZE)
1935                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1936 }
1937
1938 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1939 {
1940         bool enable_1394a;
1941         int ret, clear, set, offset;
1942
1943         /* Check if the driver should configure link and PHY. */
1944         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1945               OHCI1394_HCControl_programPhyEnable))
1946                 return 0;
1947
1948         /* Paranoia: check whether the PHY supports 1394a, too. */
1949         enable_1394a = false;
1950         ret = read_phy_reg(ohci, 2);
1951         if (ret < 0)
1952                 return ret;
1953         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1954                 ret = read_paged_phy_reg(ohci, 1, 8);
1955                 if (ret < 0)
1956                         return ret;
1957                 if (ret >= 1)
1958                         enable_1394a = true;
1959         }
1960
1961         if (ohci->quirks & QUIRK_NO_1394A)
1962                 enable_1394a = false;
1963
1964         /* Configure PHY and link consistently. */
1965         if (enable_1394a) {
1966                 clear = 0;
1967                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1968         } else {
1969                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1970                 set = 0;
1971         }
1972         ret = update_phy_reg(ohci, 5, clear, set);
1973         if (ret < 0)
1974                 return ret;
1975
1976         if (enable_1394a)
1977                 offset = OHCI1394_HCControlSet;
1978         else
1979                 offset = OHCI1394_HCControlClear;
1980         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1981
1982         /* Clean up: configuration has been taken care of. */
1983         reg_write(ohci, OHCI1394_HCControlClear,
1984                   OHCI1394_HCControl_programPhyEnable);
1985
1986         return 0;
1987 }
1988
1989 static int ohci_enable(struct fw_card *card,
1990                        const __be32 *config_rom, size_t length)
1991 {
1992         struct fw_ohci *ohci = fw_ohci(card);
1993         struct pci_dev *dev = to_pci_dev(card->device);
1994         u32 lps, seconds, version, irqs;
1995         int i, ret;
1996
1997         if (software_reset(ohci)) {
1998                 fw_error("Failed to reset ohci card.\n");
1999                 return -EBUSY;
2000         }
2001
2002         /*
2003          * Now enable LPS, which we need in order to start accessing
2004          * most of the registers.  In fact, on some cards (ALI M5251),
2005          * accessing registers in the SClk domain without LPS enabled
2006          * will lock up the machine.  Wait 50msec to make sure we have
2007          * full link enabled.  However, with some cards (well, at least
2008          * a JMicron PCIe card), we have to try again sometimes.
2009          */
2010         reg_write(ohci, OHCI1394_HCControlSet,
2011                   OHCI1394_HCControl_LPS |
2012                   OHCI1394_HCControl_postedWriteEnable);
2013         flush_writes(ohci);
2014
2015         for (lps = 0, i = 0; !lps && i < 3; i++) {
2016                 msleep(50);
2017                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2018                       OHCI1394_HCControl_LPS;
2019         }
2020
2021         if (!lps) {
2022                 fw_error("Failed to set Link Power Status\n");
2023                 return -EIO;
2024         }
2025
2026         reg_write(ohci, OHCI1394_HCControlClear,
2027                   OHCI1394_HCControl_noByteSwapData);
2028
2029         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2030         reg_write(ohci, OHCI1394_LinkControlSet,
2031                   OHCI1394_LinkControl_rcvSelfID |
2032                   OHCI1394_LinkControl_rcvPhyPkt |
2033                   OHCI1394_LinkControl_cycleTimerEnable |
2034                   OHCI1394_LinkControl_cycleMaster);
2035
2036         reg_write(ohci, OHCI1394_ATRetries,
2037                   OHCI1394_MAX_AT_REQ_RETRIES |
2038                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2039                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2040                   (200 << 16));
2041
2042         seconds = lower_32_bits(get_seconds());
2043         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2044         ohci->bus_time = seconds & ~0x3f;
2045
2046         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2047         if (version >= OHCI_VERSION_1_1) {
2048                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2049                           0xfffffffe);
2050                 card->broadcast_channel_auto_allocated = true;
2051         }
2052
2053         /* Get implemented bits of the priority arbitration request counter. */
2054         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2055         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2056         reg_write(ohci, OHCI1394_FairnessControl, 0);
2057         card->priority_budget_implemented = ohci->pri_req_max != 0;
2058
2059         ar_context_run(&ohci->ar_request_ctx);
2060         ar_context_run(&ohci->ar_response_ctx);
2061
2062         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2063         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2064         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2065
2066         ret = configure_1394a_enhancements(ohci);
2067         if (ret < 0)
2068                 return ret;
2069
2070         /* Activate link_on bit and contender bit in our self ID packets.*/
2071         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2072         if (ret < 0)
2073                 return ret;
2074
2075         /*
2076          * When the link is not yet enabled, the atomic config rom
2077          * update mechanism described below in ohci_set_config_rom()
2078          * is not active.  We have to update ConfigRomHeader and
2079          * BusOptions manually, and the write to ConfigROMmap takes
2080          * effect immediately.  We tie this to the enabling of the
2081          * link, so we have a valid config rom before enabling - the
2082          * OHCI requires that ConfigROMhdr and BusOptions have valid
2083          * values before enabling.
2084          *
2085          * However, when the ConfigROMmap is written, some controllers
2086          * always read back quadlets 0 and 2 from the config rom to
2087          * the ConfigRomHeader and BusOptions registers on bus reset.
2088          * They shouldn't do that in this initial case where the link
2089          * isn't enabled.  This means we have to use the same
2090          * workaround here, setting the bus header to 0 and then write
2091          * the right values in the bus reset tasklet.
2092          */
2093
2094         if (config_rom) {
2095                 ohci->next_config_rom =
2096                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2097                                            &ohci->next_config_rom_bus,
2098                                            GFP_KERNEL);
2099                 if (ohci->next_config_rom == NULL)
2100                         return -ENOMEM;
2101
2102                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2103         } else {
2104                 /*
2105                  * In the suspend case, config_rom is NULL, which
2106                  * means that we just reuse the old config rom.
2107                  */
2108                 ohci->next_config_rom = ohci->config_rom;
2109                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2110         }
2111
2112         ohci->next_header = ohci->next_config_rom[0];
2113         ohci->next_config_rom[0] = 0;
2114         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2115         reg_write(ohci, OHCI1394_BusOptions,
2116                   be32_to_cpu(ohci->next_config_rom[2]));
2117         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2118
2119         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2120
2121         if (!(ohci->quirks & QUIRK_NO_MSI))
2122                 pci_enable_msi(dev);
2123         if (request_irq(dev->irq, irq_handler,
2124                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2125                         ohci_driver_name, ohci)) {
2126                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2127                 pci_disable_msi(dev);
2128                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2129                                   ohci->config_rom, ohci->config_rom_bus);
2130                 return -EIO;
2131         }
2132
2133         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2134                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2135                 OHCI1394_isochTx | OHCI1394_isochRx |
2136                 OHCI1394_postedWriteErr |
2137                 OHCI1394_selfIDComplete |
2138                 OHCI1394_regAccessFail |
2139                 OHCI1394_cycle64Seconds |
2140                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2141                 OHCI1394_masterIntEnable;
2142         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2143                 irqs |= OHCI1394_busReset;
2144         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2145
2146         reg_write(ohci, OHCI1394_HCControlSet,
2147                   OHCI1394_HCControl_linkEnable |
2148                   OHCI1394_HCControl_BIBimageValid);
2149         flush_writes(ohci);
2150
2151         /* We are ready to go, reset bus to finish initialization. */
2152         fw_schedule_bus_reset(&ohci->card, false, true);
2153
2154         return 0;
2155 }
2156
2157 static int ohci_set_config_rom(struct fw_card *card,
2158                                const __be32 *config_rom, size_t length)
2159 {
2160         struct fw_ohci *ohci;
2161         unsigned long flags;
2162         int ret = -EBUSY;
2163         __be32 *next_config_rom;
2164         dma_addr_t uninitialized_var(next_config_rom_bus);
2165
2166         ohci = fw_ohci(card);
2167
2168         /*
2169          * When the OHCI controller is enabled, the config rom update
2170          * mechanism is a bit tricky, but easy enough to use.  See
2171          * section 5.5.6 in the OHCI specification.
2172          *
2173          * The OHCI controller caches the new config rom address in a
2174          * shadow register (ConfigROMmapNext) and needs a bus reset
2175          * for the changes to take place.  When the bus reset is
2176          * detected, the controller loads the new values for the
2177          * ConfigRomHeader and BusOptions registers from the specified
2178          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2179          * shadow register. All automatically and atomically.
2180          *
2181          * Now, there's a twist to this story.  The automatic load of
2182          * ConfigRomHeader and BusOptions doesn't honor the
2183          * noByteSwapData bit, so with a be32 config rom, the
2184          * controller will load be32 values in to these registers
2185          * during the atomic update, even on litte endian
2186          * architectures.  The workaround we use is to put a 0 in the
2187          * header quadlet; 0 is endian agnostic and means that the
2188          * config rom isn't ready yet.  In the bus reset tasklet we
2189          * then set up the real values for the two registers.
2190          *
2191          * We use ohci->lock to avoid racing with the code that sets
2192          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2193          */
2194
2195         next_config_rom =
2196                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2197                                    &next_config_rom_bus, GFP_KERNEL);
2198         if (next_config_rom == NULL)
2199                 return -ENOMEM;
2200
2201         spin_lock_irqsave(&ohci->lock, flags);
2202
2203         if (ohci->next_config_rom == NULL) {
2204                 ohci->next_config_rom = next_config_rom;
2205                 ohci->next_config_rom_bus = next_config_rom_bus;
2206
2207                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2208
2209                 ohci->next_header = config_rom[0];
2210                 ohci->next_config_rom[0] = 0;
2211
2212                 reg_write(ohci, OHCI1394_ConfigROMmap,
2213                           ohci->next_config_rom_bus);
2214                 ret = 0;
2215         }
2216
2217         spin_unlock_irqrestore(&ohci->lock, flags);
2218
2219         /*
2220          * Now initiate a bus reset to have the changes take
2221          * effect. We clean up the old config rom memory and DMA
2222          * mappings in the bus reset tasklet, since the OHCI
2223          * controller could need to access it before the bus reset
2224          * takes effect.
2225          */
2226         if (ret == 0)
2227                 fw_schedule_bus_reset(&ohci->card, true, true);
2228         else
2229                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2230                                   next_config_rom, next_config_rom_bus);
2231
2232         return ret;
2233 }
2234
2235 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2236 {
2237         struct fw_ohci *ohci = fw_ohci(card);
2238
2239         at_context_transmit(&ohci->at_request_ctx, packet);
2240 }
2241
2242 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2243 {
2244         struct fw_ohci *ohci = fw_ohci(card);
2245
2246         at_context_transmit(&ohci->at_response_ctx, packet);
2247 }
2248
2249 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2250 {
2251         struct fw_ohci *ohci = fw_ohci(card);
2252         struct context *ctx = &ohci->at_request_ctx;
2253         struct driver_data *driver_data = packet->driver_data;
2254         int ret = -ENOENT;
2255
2256         tasklet_disable(&ctx->tasklet);
2257
2258         if (packet->ack != 0)
2259                 goto out;
2260
2261         if (packet->payload_mapped)
2262                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2263                                  packet->payload_length, DMA_TO_DEVICE);
2264
2265         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2266         driver_data->packet = NULL;
2267         packet->ack = RCODE_CANCELLED;
2268         packet->callback(packet, &ohci->card, packet->ack);
2269         ret = 0;
2270  out:
2271         tasklet_enable(&ctx->tasklet);
2272
2273         return ret;
2274 }
2275
2276 static int ohci_enable_phys_dma(struct fw_card *card,
2277                                 int node_id, int generation)
2278 {
2279 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2280         return 0;
2281 #else
2282         struct fw_ohci *ohci = fw_ohci(card);
2283         unsigned long flags;
2284         int n, ret = 0;
2285
2286         /*
2287          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2288          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2289          */
2290
2291         spin_lock_irqsave(&ohci->lock, flags);
2292
2293         if (ohci->generation != generation) {
2294                 ret = -ESTALE;
2295                 goto out;
2296         }
2297
2298         /*
2299          * Note, if the node ID contains a non-local bus ID, physical DMA is
2300          * enabled for _all_ nodes on remote buses.
2301          */
2302
2303         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2304         if (n < 32)
2305                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2306         else
2307                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2308
2309         flush_writes(ohci);
2310  out:
2311         spin_unlock_irqrestore(&ohci->lock, flags);
2312
2313         return ret;
2314 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2315 }
2316
2317 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2318 {
2319         struct fw_ohci *ohci = fw_ohci(card);
2320         unsigned long flags;
2321         u32 value;
2322
2323         switch (csr_offset) {
2324         case CSR_STATE_CLEAR:
2325         case CSR_STATE_SET:
2326                 if (ohci->is_root &&
2327                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2328                      OHCI1394_LinkControl_cycleMaster))
2329                         value = CSR_STATE_BIT_CMSTR;
2330                 else
2331                         value = 0;
2332                 if (ohci->csr_state_setclear_abdicate)
2333                         value |= CSR_STATE_BIT_ABDICATE;
2334
2335                 return value;
2336
2337         case CSR_NODE_IDS:
2338                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2339
2340         case CSR_CYCLE_TIME:
2341                 return get_cycle_time(ohci);
2342
2343         case CSR_BUS_TIME:
2344                 /*
2345                  * We might be called just after the cycle timer has wrapped
2346                  * around but just before the cycle64Seconds handler, so we
2347                  * better check here, too, if the bus time needs to be updated.
2348                  */
2349                 spin_lock_irqsave(&ohci->lock, flags);
2350                 value = update_bus_time(ohci);
2351                 spin_unlock_irqrestore(&ohci->lock, flags);
2352                 return value;
2353
2354         case CSR_BUSY_TIMEOUT:
2355                 value = reg_read(ohci, OHCI1394_ATRetries);
2356                 return (value >> 4) & 0x0ffff00f;
2357
2358         case CSR_PRIORITY_BUDGET:
2359                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2360                         (ohci->pri_req_max << 8);
2361
2362         default:
2363                 WARN_ON(1);
2364                 return 0;
2365         }
2366 }
2367
2368 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2369 {
2370         struct fw_ohci *ohci = fw_ohci(card);
2371         unsigned long flags;
2372
2373         switch (csr_offset) {
2374         case CSR_STATE_CLEAR:
2375                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2376                         reg_write(ohci, OHCI1394_LinkControlClear,
2377                                   OHCI1394_LinkControl_cycleMaster);
2378                         flush_writes(ohci);
2379                 }
2380                 if (value & CSR_STATE_BIT_ABDICATE)
2381                         ohci->csr_state_setclear_abdicate = false;
2382                 break;
2383
2384         case CSR_STATE_SET:
2385                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2386                         reg_write(ohci, OHCI1394_LinkControlSet,
2387                                   OHCI1394_LinkControl_cycleMaster);
2388                         flush_writes(ohci);
2389                 }
2390                 if (value & CSR_STATE_BIT_ABDICATE)
2391                         ohci->csr_state_setclear_abdicate = true;
2392                 break;
2393
2394         case CSR_NODE_IDS:
2395                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2396                 flush_writes(ohci);
2397                 break;
2398
2399         case CSR_CYCLE_TIME:
2400                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2401                 reg_write(ohci, OHCI1394_IntEventSet,
2402                           OHCI1394_cycleInconsistent);
2403                 flush_writes(ohci);
2404                 break;
2405
2406         case CSR_BUS_TIME:
2407                 spin_lock_irqsave(&ohci->lock, flags);
2408                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2409                 spin_unlock_irqrestore(&ohci->lock, flags);
2410                 break;
2411
2412         case CSR_BUSY_TIMEOUT:
2413                 value = (value & 0xf) | ((value & 0xf) << 4) |
2414                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2415                 reg_write(ohci, OHCI1394_ATRetries, value);
2416                 flush_writes(ohci);
2417                 break;
2418
2419         case CSR_PRIORITY_BUDGET:
2420                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2421                 flush_writes(ohci);
2422                 break;
2423
2424         default:
2425                 WARN_ON(1);
2426                 break;
2427         }
2428 }
2429
2430 static void copy_iso_headers(struct iso_context *ctx, void *p)
2431 {
2432         int i = ctx->header_length;
2433
2434         if (i + ctx->base.header_size > PAGE_SIZE)
2435                 return;
2436
2437         /*
2438          * The iso header is byteswapped to little endian by
2439          * the controller, but the remaining header quadlets
2440          * are big endian.  We want to present all the headers
2441          * as big endian, so we have to swap the first quadlet.
2442          */
2443         if (ctx->base.header_size > 0)
2444                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2445         if (ctx->base.header_size > 4)
2446                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2447         if (ctx->base.header_size > 8)
2448                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2449         ctx->header_length += ctx->base.header_size;
2450 }
2451
2452 static int handle_ir_packet_per_buffer(struct context *context,
2453                                        struct descriptor *d,
2454                                        struct descriptor *last)
2455 {
2456         struct iso_context *ctx =
2457                 container_of(context, struct iso_context, context);
2458         struct descriptor *pd;
2459         __le32 *ir_header;
2460         void *p;
2461
2462         for (pd = d; pd <= last; pd++)
2463                 if (pd->transfer_status)
2464                         break;
2465         if (pd > last)
2466                 /* Descriptor(s) not done yet, stop iteration */
2467                 return 0;
2468
2469         p = last + 1;
2470         copy_iso_headers(ctx, p);
2471
2472         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2473                 ir_header = (__le32 *) p;
2474                 ctx->base.callback.sc(&ctx->base,
2475                                       le32_to_cpu(ir_header[0]) & 0xffff,
2476                                       ctx->header_length, ctx->header,
2477                                       ctx->base.callback_data);
2478                 ctx->header_length = 0;
2479         }
2480
2481         return 1;
2482 }
2483
2484 /* d == last because each descriptor block is only a single descriptor. */
2485 static int handle_ir_buffer_fill(struct context *context,
2486                                  struct descriptor *d,
2487                                  struct descriptor *last)
2488 {
2489         struct iso_context *ctx =
2490                 container_of(context, struct iso_context, context);
2491
2492         if (!last->transfer_status)
2493                 /* Descriptor(s) not done yet, stop iteration */
2494                 return 0;
2495
2496         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2497                 ctx->base.callback.mc(&ctx->base,
2498                                       le32_to_cpu(last->data_address) +
2499                                       le16_to_cpu(last->req_count) -
2500                                       le16_to_cpu(last->res_count),
2501                                       ctx->base.callback_data);
2502
2503         return 1;
2504 }
2505
2506 static int handle_it_packet(struct context *context,
2507                             struct descriptor *d,
2508                             struct descriptor *last)
2509 {
2510         struct iso_context *ctx =
2511                 container_of(context, struct iso_context, context);
2512         int i;
2513         struct descriptor *pd;
2514
2515         for (pd = d; pd <= last; pd++)
2516                 if (pd->transfer_status)
2517                         break;
2518         if (pd > last)
2519                 /* Descriptor(s) not done yet, stop iteration */
2520                 return 0;
2521
2522         i = ctx->header_length;
2523         if (i + 4 < PAGE_SIZE) {
2524                 /* Present this value as big-endian to match the receive code */
2525                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2526                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2527                                 le16_to_cpu(pd->res_count));
2528                 ctx->header_length += 4;
2529         }
2530         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2531                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2532                                       ctx->header_length, ctx->header,
2533                                       ctx->base.callback_data);
2534                 ctx->header_length = 0;
2535         }
2536         return 1;
2537 }
2538
2539 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2540 {
2541         u32 hi = channels >> 32, lo = channels;
2542
2543         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2544         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2545         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2546         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2547         mmiowb();
2548         ohci->mc_channels = channels;
2549 }
2550
2551 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2552                                 int type, int channel, size_t header_size)
2553 {
2554         struct fw_ohci *ohci = fw_ohci(card);
2555         struct iso_context *uninitialized_var(ctx);
2556         descriptor_callback_t uninitialized_var(callback);
2557         u64 *uninitialized_var(channels);
2558         u32 *uninitialized_var(mask), uninitialized_var(regs);
2559         unsigned long flags;
2560         int index, ret = -EBUSY;
2561
2562         spin_lock_irqsave(&ohci->lock, flags);
2563
2564         switch (type) {
2565         case FW_ISO_CONTEXT_TRANSMIT:
2566                 mask     = &ohci->it_context_mask;
2567                 callback = handle_it_packet;
2568                 index    = ffs(*mask) - 1;
2569                 if (index >= 0) {
2570                         *mask &= ~(1 << index);
2571                         regs = OHCI1394_IsoXmitContextBase(index);
2572                         ctx  = &ohci->it_context_list[index];
2573                 }
2574                 break;
2575
2576         case FW_ISO_CONTEXT_RECEIVE:
2577                 channels = &ohci->ir_context_channels;
2578                 mask     = &ohci->ir_context_mask;
2579                 callback = handle_ir_packet_per_buffer;
2580                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2581                 if (index >= 0) {
2582                         *channels &= ~(1ULL << channel);
2583                         *mask     &= ~(1 << index);
2584                         regs = OHCI1394_IsoRcvContextBase(index);
2585                         ctx  = &ohci->ir_context_list[index];
2586                 }
2587                 break;
2588
2589         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2590                 mask     = &ohci->ir_context_mask;
2591                 callback = handle_ir_buffer_fill;
2592                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2593                 if (index >= 0) {
2594                         ohci->mc_allocated = true;
2595                         *mask &= ~(1 << index);
2596                         regs = OHCI1394_IsoRcvContextBase(index);
2597                         ctx  = &ohci->ir_context_list[index];
2598                 }
2599                 break;
2600
2601         default:
2602                 index = -1;
2603                 ret = -ENOSYS;
2604         }
2605
2606         spin_unlock_irqrestore(&ohci->lock, flags);
2607
2608         if (index < 0)
2609                 return ERR_PTR(ret);
2610
2611         memset(ctx, 0, sizeof(*ctx));
2612         ctx->header_length = 0;
2613         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2614         if (ctx->header == NULL) {
2615                 ret = -ENOMEM;
2616                 goto out;
2617         }
2618         ret = context_init(&ctx->context, ohci, regs, callback);
2619         if (ret < 0)
2620                 goto out_with_header;
2621
2622         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2623                 set_multichannel_mask(ohci, 0);
2624
2625         return &ctx->base;
2626
2627  out_with_header:
2628         free_page((unsigned long)ctx->header);
2629  out:
2630         spin_lock_irqsave(&ohci->lock, flags);
2631
2632         switch (type) {
2633         case FW_ISO_CONTEXT_RECEIVE:
2634                 *channels |= 1ULL << channel;
2635                 break;
2636
2637         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2638                 ohci->mc_allocated = false;
2639                 break;
2640         }
2641         *mask |= 1 << index;
2642
2643         spin_unlock_irqrestore(&ohci->lock, flags);
2644
2645         return ERR_PTR(ret);
2646 }
2647
2648 static int ohci_start_iso(struct fw_iso_context *base,
2649                           s32 cycle, u32 sync, u32 tags)
2650 {
2651         struct iso_context *ctx = container_of(base, struct iso_context, base);
2652         struct fw_ohci *ohci = ctx->context.ohci;
2653         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2654         int index;
2655
2656         switch (ctx->base.type) {
2657         case FW_ISO_CONTEXT_TRANSMIT:
2658                 index = ctx - ohci->it_context_list;
2659                 match = 0;
2660                 if (cycle >= 0)
2661                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2662                                 (cycle & 0x7fff) << 16;
2663
2664                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2665                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2666                 context_run(&ctx->context, match);
2667                 break;
2668
2669         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2670                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2671                 /* fall through */
2672         case FW_ISO_CONTEXT_RECEIVE:
2673                 index = ctx - ohci->ir_context_list;
2674                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2675                 if (cycle >= 0) {
2676                         match |= (cycle & 0x07fff) << 12;
2677                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2678                 }
2679
2680                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2681                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2682                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2683                 context_run(&ctx->context, control);
2684
2685                 ctx->sync = sync;
2686                 ctx->tags = tags;
2687
2688                 break;
2689         }
2690
2691         return 0;
2692 }
2693
2694 static int ohci_stop_iso(struct fw_iso_context *base)
2695 {
2696         struct fw_ohci *ohci = fw_ohci(base->card);
2697         struct iso_context *ctx = container_of(base, struct iso_context, base);
2698         int index;
2699
2700         switch (ctx->base.type) {
2701         case FW_ISO_CONTEXT_TRANSMIT:
2702                 index = ctx - ohci->it_context_list;
2703                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2704                 break;
2705
2706         case FW_ISO_CONTEXT_RECEIVE:
2707         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2708                 index = ctx - ohci->ir_context_list;
2709                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2710                 break;
2711         }
2712         flush_writes(ohci);
2713         context_stop(&ctx->context);
2714
2715         return 0;
2716 }
2717
2718 static void ohci_free_iso_context(struct fw_iso_context *base)
2719 {
2720         struct fw_ohci *ohci = fw_ohci(base->card);
2721         struct iso_context *ctx = container_of(base, struct iso_context, base);
2722         unsigned long flags;
2723         int index;
2724
2725         ohci_stop_iso(base);
2726         context_release(&ctx->context);
2727         free_page((unsigned long)ctx->header);
2728
2729         spin_lock_irqsave(&ohci->lock, flags);
2730
2731         switch (base->type) {
2732         case FW_ISO_CONTEXT_TRANSMIT:
2733                 index = ctx - ohci->it_context_list;
2734                 ohci->it_context_mask |= 1 << index;
2735                 break;
2736
2737         case FW_ISO_CONTEXT_RECEIVE:
2738                 index = ctx - ohci->ir_context_list;
2739                 ohci->ir_context_mask |= 1 << index;
2740                 ohci->ir_context_channels |= 1ULL << base->channel;
2741                 break;
2742
2743         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2744                 index = ctx - ohci->ir_context_list;
2745                 ohci->ir_context_mask |= 1 << index;
2746                 ohci->ir_context_channels |= ohci->mc_channels;
2747                 ohci->mc_channels = 0;
2748                 ohci->mc_allocated = false;
2749                 break;
2750         }
2751
2752         spin_unlock_irqrestore(&ohci->lock, flags);
2753 }
2754
2755 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2756 {
2757         struct fw_ohci *ohci = fw_ohci(base->card);
2758         unsigned long flags;
2759         int ret;
2760
2761         switch (base->type) {
2762         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2763
2764                 spin_lock_irqsave(&ohci->lock, flags);
2765
2766                 /* Don't allow multichannel to grab other contexts' channels. */
2767                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2768                         *channels = ohci->ir_context_channels;
2769                         ret = -EBUSY;
2770                 } else {
2771                         set_multichannel_mask(ohci, *channels);
2772                         ret = 0;
2773                 }
2774
2775                 spin_unlock_irqrestore(&ohci->lock, flags);
2776
2777                 break;
2778         default:
2779                 ret = -EINVAL;
2780         }
2781
2782         return ret;
2783 }
2784
2785 #ifdef CONFIG_PM
2786 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2787 {
2788         int i;
2789         struct iso_context *ctx;
2790
2791         for (i = 0 ; i < ohci->n_ir ; i++) {
2792                 ctx = &ohci->ir_context_list[i];
2793                 if (ctx->context.active)
2794                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2795         }
2796
2797         for (i = 0 ; i < ohci->n_it ; i++) {
2798                 ctx = &ohci->it_context_list[i];
2799                 if (ctx->context.active)
2800                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2801         }
2802 }
2803 #endif
2804
2805 static int queue_iso_transmit(struct iso_context *ctx,
2806                               struct fw_iso_packet *packet,
2807                               struct fw_iso_buffer *buffer,
2808                               unsigned long payload)
2809 {
2810         struct descriptor *d, *last, *pd;
2811         struct fw_iso_packet *p;
2812         __le32 *header;
2813         dma_addr_t d_bus, page_bus;
2814         u32 z, header_z, payload_z, irq;
2815         u32 payload_index, payload_end_index, next_page_index;
2816         int page, end_page, i, length, offset;
2817
2818         p = packet;
2819         payload_index = payload;
2820
2821         if (p->skip)
2822                 z = 1;
2823         else
2824                 z = 2;
2825         if (p->header_length > 0)
2826                 z++;
2827
2828         /* Determine the first page the payload isn't contained in. */
2829         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2830         if (p->payload_length > 0)
2831                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2832         else
2833                 payload_z = 0;
2834
2835         z += payload_z;
2836
2837         /* Get header size in number of descriptors. */
2838         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2839
2840         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2841         if (d == NULL)
2842                 return -ENOMEM;
2843
2844         if (!p->skip) {
2845                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2846                 d[0].req_count = cpu_to_le16(8);
2847                 /*
2848                  * Link the skip address to this descriptor itself.  This causes
2849                  * a context to skip a cycle whenever lost cycles or FIFO
2850                  * overruns occur, without dropping the data.  The application
2851                  * should then decide whether this is an error condition or not.
2852                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2853                  */
2854                 d[0].branch_address = cpu_to_le32(d_bus | z);
2855
2856                 header = (__le32 *) &d[1];
2857                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2858                                         IT_HEADER_TAG(p->tag) |
2859                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2860                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2861                                         IT_HEADER_SPEED(ctx->base.speed));
2862                 header[1] =
2863                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2864                                                           p->payload_length));
2865         }
2866
2867         if (p->header_length > 0) {
2868                 d[2].req_count    = cpu_to_le16(p->header_length);
2869                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2870                 memcpy(&d[z], p->header, p->header_length);
2871         }
2872
2873         pd = d + z - payload_z;
2874         payload_end_index = payload_index + p->payload_length;
2875         for (i = 0; i < payload_z; i++) {
2876                 page               = payload_index >> PAGE_SHIFT;
2877                 offset             = payload_index & ~PAGE_MASK;
2878                 next_page_index    = (page + 1) << PAGE_SHIFT;
2879                 length             =
2880                         min(next_page_index, payload_end_index) - payload_index;
2881                 pd[i].req_count    = cpu_to_le16(length);
2882
2883                 page_bus = page_private(buffer->pages[page]);
2884                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2885
2886                 payload_index += length;
2887         }
2888
2889         if (p->interrupt)
2890                 irq = DESCRIPTOR_IRQ_ALWAYS;
2891         else
2892                 irq = DESCRIPTOR_NO_IRQ;
2893
2894         last = z == 2 ? d : d + z - 1;
2895         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2896                                      DESCRIPTOR_STATUS |
2897                                      DESCRIPTOR_BRANCH_ALWAYS |
2898                                      irq);
2899
2900         context_append(&ctx->context, d, z, header_z);
2901
2902         return 0;
2903 }
2904
2905 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2906                                        struct fw_iso_packet *packet,
2907                                        struct fw_iso_buffer *buffer,
2908                                        unsigned long payload)
2909 {
2910         struct descriptor *d, *pd;
2911         dma_addr_t d_bus, page_bus;
2912         u32 z, header_z, rest;
2913         int i, j, length;
2914         int page, offset, packet_count, header_size, payload_per_buffer;
2915
2916         /*
2917          * The OHCI controller puts the isochronous header and trailer in the
2918          * buffer, so we need at least 8 bytes.
2919          */
2920         packet_count = packet->header_length / ctx->base.header_size;
2921         header_size  = max(ctx->base.header_size, (size_t)8);
2922
2923         /* Get header size in number of descriptors. */
2924         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2925         page     = payload >> PAGE_SHIFT;
2926         offset   = payload & ~PAGE_MASK;
2927         payload_per_buffer = packet->payload_length / packet_count;
2928
2929         for (i = 0; i < packet_count; i++) {
2930                 /* d points to the header descriptor */
2931                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2932                 d = context_get_descriptors(&ctx->context,
2933                                 z + header_z, &d_bus);
2934                 if (d == NULL)
2935                         return -ENOMEM;
2936
2937                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2938                                               DESCRIPTOR_INPUT_MORE);
2939                 if (packet->skip && i == 0)
2940                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2941                 d->req_count    = cpu_to_le16(header_size);
2942                 d->res_count    = d->req_count;
2943                 d->transfer_status = 0;
2944                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2945
2946                 rest = payload_per_buffer;
2947                 pd = d;
2948                 for (j = 1; j < z; j++) {
2949                         pd++;
2950                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2951                                                   DESCRIPTOR_INPUT_MORE);
2952
2953                         if (offset + rest < PAGE_SIZE)
2954                                 length = rest;
2955                         else
2956                                 length = PAGE_SIZE - offset;
2957                         pd->req_count = cpu_to_le16(length);
2958                         pd->res_count = pd->req_count;
2959                         pd->transfer_status = 0;
2960
2961                         page_bus = page_private(buffer->pages[page]);
2962                         pd->data_address = cpu_to_le32(page_bus + offset);
2963
2964                         offset = (offset + length) & ~PAGE_MASK;
2965                         rest -= length;
2966                         if (offset == 0)
2967                                 page++;
2968                 }
2969                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2970                                           DESCRIPTOR_INPUT_LAST |
2971                                           DESCRIPTOR_BRANCH_ALWAYS);
2972                 if (packet->interrupt && i == packet_count - 1)
2973                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2974
2975                 context_append(&ctx->context, d, z, header_z);
2976         }
2977
2978         return 0;
2979 }
2980
2981 static int queue_iso_buffer_fill(struct iso_context *ctx,
2982                                  struct fw_iso_packet *packet,
2983                                  struct fw_iso_buffer *buffer,
2984                                  unsigned long payload)
2985 {
2986         struct descriptor *d;
2987         dma_addr_t d_bus, page_bus;
2988         int page, offset, rest, z, i, length;
2989
2990         page   = payload >> PAGE_SHIFT;
2991         offset = payload & ~PAGE_MASK;
2992         rest   = packet->payload_length;
2993
2994         /* We need one descriptor for each page in the buffer. */
2995         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2996
2997         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2998                 return -EFAULT;
2999
3000         for (i = 0; i < z; i++) {
3001                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3002                 if (d == NULL)
3003                         return -ENOMEM;
3004
3005                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3006                                          DESCRIPTOR_BRANCH_ALWAYS);
3007                 if (packet->skip && i == 0)
3008                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3009                 if (packet->interrupt && i == z - 1)
3010                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3011
3012                 if (offset + rest < PAGE_SIZE)
3013                         length = rest;
3014                 else
3015                         length = PAGE_SIZE - offset;
3016                 d->req_count = cpu_to_le16(length);
3017                 d->res_count = d->req_count;
3018                 d->transfer_status = 0;
3019
3020                 page_bus = page_private(buffer->pages[page]);
3021                 d->data_address = cpu_to_le32(page_bus + offset);
3022
3023                 rest -= length;
3024                 offset = 0;
3025                 page++;
3026
3027                 context_append(&ctx->context, d, 1, 0);
3028         }
3029
3030         return 0;
3031 }
3032
3033 static int ohci_queue_iso(struct fw_iso_context *base,
3034                           struct fw_iso_packet *packet,
3035                           struct fw_iso_buffer *buffer,
3036                           unsigned long payload)
3037 {
3038         struct iso_context *ctx = container_of(base, struct iso_context, base);
3039         unsigned long flags;
3040         int ret = -ENOSYS;
3041
3042         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3043         switch (base->type) {
3044         case FW_ISO_CONTEXT_TRANSMIT:
3045                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3046                 break;
3047         case FW_ISO_CONTEXT_RECEIVE:
3048                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3049                 break;
3050         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3051                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3052                 break;
3053         }
3054         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3055
3056         return ret;
3057 }
3058
3059 static const struct fw_card_driver ohci_driver = {
3060         .enable                 = ohci_enable,
3061         .read_phy_reg           = ohci_read_phy_reg,
3062         .update_phy_reg         = ohci_update_phy_reg,
3063         .set_config_rom         = ohci_set_config_rom,
3064         .send_request           = ohci_send_request,
3065         .send_response          = ohci_send_response,
3066         .cancel_packet          = ohci_cancel_packet,
3067         .enable_phys_dma        = ohci_enable_phys_dma,
3068         .read_csr               = ohci_read_csr,
3069         .write_csr              = ohci_write_csr,
3070
3071         .allocate_iso_context   = ohci_allocate_iso_context,
3072         .free_iso_context       = ohci_free_iso_context,
3073         .set_iso_channels       = ohci_set_iso_channels,
3074         .queue_iso              = ohci_queue_iso,
3075         .start_iso              = ohci_start_iso,
3076         .stop_iso               = ohci_stop_iso,
3077 };
3078
3079 #ifdef CONFIG_PPC_PMAC
3080 static void pmac_ohci_on(struct pci_dev *dev)
3081 {
3082         if (machine_is(powermac)) {
3083                 struct device_node *ofn = pci_device_to_OF_node(dev);
3084
3085                 if (ofn) {
3086                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3087                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3088                 }
3089         }
3090 }
3091
3092 static void pmac_ohci_off(struct pci_dev *dev)
3093 {
3094         if (machine_is(powermac)) {
3095                 struct device_node *ofn = pci_device_to_OF_node(dev);
3096
3097                 if (ofn) {
3098                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3099                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3100                 }
3101         }
3102 }
3103 #else
3104 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3105 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3106 #endif /* CONFIG_PPC_PMAC */
3107
3108 static int __devinit pci_probe(struct pci_dev *dev,
3109                                const struct pci_device_id *ent)
3110 {
3111         struct fw_ohci *ohci;
3112         u32 bus_options, max_receive, link_speed, version;
3113         u64 guid;
3114         int i, err;
3115         size_t size;
3116
3117         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3118         if (ohci == NULL) {
3119                 err = -ENOMEM;
3120                 goto fail;
3121         }
3122
3123         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3124
3125         pmac_ohci_on(dev);
3126
3127         err = pci_enable_device(dev);
3128         if (err) {
3129                 fw_error("Failed to enable OHCI hardware\n");
3130                 goto fail_free;
3131         }
3132
3133         pci_set_master(dev);
3134         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3135         pci_set_drvdata(dev, ohci);
3136
3137         spin_lock_init(&ohci->lock);
3138         mutex_init(&ohci->phy_reg_mutex);
3139
3140         tasklet_init(&ohci->bus_reset_tasklet,
3141                      bus_reset_tasklet, (unsigned long)ohci);
3142
3143         err = pci_request_region(dev, 0, ohci_driver_name);
3144         if (err) {
3145                 fw_error("MMIO resource unavailable\n");
3146                 goto fail_disable;
3147         }
3148
3149         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3150         if (ohci->registers == NULL) {
3151                 fw_error("Failed to remap registers\n");
3152                 err = -ENXIO;
3153                 goto fail_iomem;
3154         }
3155
3156         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3157                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3158                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3159                      ohci_quirks[i].device == dev->device) &&
3160                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3161                      ohci_quirks[i].revision >= dev->revision)) {
3162                         ohci->quirks = ohci_quirks[i].flags;
3163                         break;
3164                 }
3165         if (param_quirks)
3166                 ohci->quirks = param_quirks;
3167
3168         /*
3169          * Because dma_alloc_coherent() allocates at least one page,
3170          * we save space by using a common buffer for the AR request/
3171          * response descriptors and the self IDs buffer.
3172          */
3173         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3174         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3175         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3176                                                PAGE_SIZE,
3177                                                &ohci->misc_buffer_bus,
3178                                                GFP_KERNEL);
3179         if (!ohci->misc_buffer) {
3180                 err = -ENOMEM;
3181                 goto fail_iounmap;
3182         }
3183
3184         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3185                               OHCI1394_AsReqRcvContextControlSet);
3186         if (err < 0)
3187                 goto fail_misc_buf;
3188
3189         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3190                               OHCI1394_AsRspRcvContextControlSet);
3191         if (err < 0)
3192                 goto fail_arreq_ctx;
3193
3194         err = context_init(&ohci->at_request_ctx, ohci,
3195                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3196         if (err < 0)
3197                 goto fail_arrsp_ctx;
3198
3199         err = context_init(&ohci->at_response_ctx, ohci,
3200                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3201         if (err < 0)
3202                 goto fail_atreq_ctx;
3203
3204         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3205         ohci->ir_context_channels = ~0ULL;
3206         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3207         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3208         ohci->n_ir = hweight32(ohci->ir_context_mask);
3209         size = sizeof(struct iso_context) * ohci->n_ir;
3210         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3211
3212         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3213         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3214         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3215         ohci->n_it = hweight32(ohci->it_context_mask);
3216         size = sizeof(struct iso_context) * ohci->n_it;
3217         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3218
3219         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3220                 err = -ENOMEM;
3221                 goto fail_contexts;
3222         }
3223
3224         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3225         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3226
3227         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3228         max_receive = (bus_options >> 12) & 0xf;
3229         link_speed = bus_options & 0x7;
3230         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3231                 reg_read(ohci, OHCI1394_GUIDLo);
3232
3233         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3234         if (err)
3235                 goto fail_contexts;
3236
3237         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3238         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3239                   "%d IR + %d IT contexts, quirks 0x%x\n",
3240                   dev_name(&dev->dev), version >> 16, version & 0xff,
3241                   ohci->n_ir, ohci->n_it, ohci->quirks);
3242
3243         return 0;
3244
3245  fail_contexts:
3246         kfree(ohci->ir_context_list);
3247         kfree(ohci->it_context_list);
3248         context_release(&ohci->at_response_ctx);
3249  fail_atreq_ctx:
3250         context_release(&ohci->at_request_ctx);
3251  fail_arrsp_ctx:
3252         ar_context_release(&ohci->ar_response_ctx);
3253  fail_arreq_ctx:
3254         ar_context_release(&ohci->ar_request_ctx);
3255  fail_misc_buf:
3256         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3257                           ohci->misc_buffer, ohci->misc_buffer_bus);
3258  fail_iounmap:
3259         pci_iounmap(dev, ohci->registers);
3260  fail_iomem:
3261         pci_release_region(dev, 0);
3262  fail_disable:
3263         pci_disable_device(dev);
3264  fail_free:
3265         kfree(&ohci->card);
3266         pmac_ohci_off(dev);
3267  fail:
3268         if (err == -ENOMEM)
3269                 fw_error("Out of memory\n");
3270
3271         return err;
3272 }
3273
3274 static void pci_remove(struct pci_dev *dev)
3275 {
3276         struct fw_ohci *ohci;
3277
3278         ohci = pci_get_drvdata(dev);
3279         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3280         flush_writes(ohci);
3281         fw_core_remove_card(&ohci->card);
3282
3283         /*
3284          * FIXME: Fail all pending packets here, now that the upper
3285          * layers can't queue any more.
3286          */
3287
3288         software_reset(ohci);
3289         free_irq(dev->irq, ohci);
3290
3291         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3292                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3293                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3294         if (ohci->config_rom)
3295                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3296                                   ohci->config_rom, ohci->config_rom_bus);
3297         ar_context_release(&ohci->ar_request_ctx);
3298         ar_context_release(&ohci->ar_response_ctx);
3299         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3300                           ohci->misc_buffer, ohci->misc_buffer_bus);
3301         context_release(&ohci->at_request_ctx);
3302         context_release(&ohci->at_response_ctx);
3303         kfree(ohci->it_context_list);
3304         kfree(ohci->ir_context_list);
3305         pci_disable_msi(dev);
3306         pci_iounmap(dev, ohci->registers);
3307         pci_release_region(dev, 0);
3308         pci_disable_device(dev);
3309         kfree(&ohci->card);
3310         pmac_ohci_off(dev);
3311
3312         fw_notify("Removed fw-ohci device.\n");
3313 }
3314
3315 #ifdef CONFIG_PM
3316 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3317 {
3318         struct fw_ohci *ohci = pci_get_drvdata(dev);
3319         int err;
3320
3321         software_reset(ohci);
3322         free_irq(dev->irq, ohci);
3323         pci_disable_msi(dev);
3324         err = pci_save_state(dev);
3325         if (err) {
3326                 fw_error("pci_save_state failed\n");
3327                 return err;
3328         }
3329         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3330         if (err)
3331                 fw_error("pci_set_power_state failed with %d\n", err);
3332         pmac_ohci_off(dev);
3333
3334         return 0;
3335 }
3336
3337 static int pci_resume(struct pci_dev *dev)
3338 {
3339         struct fw_ohci *ohci = pci_get_drvdata(dev);
3340         int err;
3341
3342         pmac_ohci_on(dev);
3343         pci_set_power_state(dev, PCI_D0);
3344         pci_restore_state(dev);
3345         err = pci_enable_device(dev);
3346         if (err) {
3347                 fw_error("pci_enable_device failed\n");
3348                 return err;
3349         }
3350
3351         /* Some systems don't setup GUID register on resume from ram  */
3352         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3353                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3354                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3355                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3356         }
3357
3358         err = ohci_enable(&ohci->card, NULL, 0);
3359
3360         if (err)
3361                 return err;
3362
3363         ohci_resume_iso_dma(ohci);
3364         return 0;
3365 }
3366 #endif
3367
3368 static const struct pci_device_id pci_table[] = {
3369         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3370         { }
3371 };
3372
3373 MODULE_DEVICE_TABLE(pci, pci_table);
3374
3375 static struct pci_driver fw_ohci_pci_driver = {
3376         .name           = ohci_driver_name,
3377         .id_table       = pci_table,
3378         .probe          = pci_probe,
3379         .remove         = pci_remove,
3380 #ifdef CONFIG_PM
3381         .resume         = pci_resume,
3382         .suspend        = pci_suspend,
3383 #endif
3384 };
3385
3386 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3387 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3388 MODULE_LICENSE("GPL");
3389
3390 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3391 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3392 MODULE_ALIAS("ohci1394");
3393 #endif
3394
3395 static int __init fw_ohci_init(void)
3396 {
3397         return pci_register_driver(&fw_ohci_pci_driver);
3398 }
3399
3400 static void __exit fw_ohci_cleanup(void)
3401 {
3402         pci_unregister_driver(&fw_ohci_pci_driver);
3403 }
3404
3405 module_init(fw_ohci_init);
3406 module_exit(fw_ohci_cleanup);