drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bug.h>
  22 #include <linux/compiler.h>
  23 #include <linux/delay.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/firewire.h>
  27 #include <linux/firewire-constants.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/mutex.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/slab.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/string.h>
  42 #include <linux/time.h>
  43 #include <linux/vmalloc.h>
  44
  45 #include <asm/byteorder.h>
  46 #include <asm/page.h>
  47 #include <asm/system.h>
  48
  49 #ifdef CONFIG_PPC_PMAC
  50 #include <asm/pmac_feature.h>
  51 #endif
  52
  53 #include "core.h"
  54 #include "ohci.h"
  55
  56 #define DESCRIPTOR_OUTPUT_MORE          0
  57 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  58 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  59 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  60 #define DESCRIPTOR_STATUS               (1 << 11)
  61 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  62 #define DESCRIPTOR_PING                 (1 << 7)
  63 #define DESCRIPTOR_YY                   (1 << 6)
  64 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  65 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  66 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  67 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  68 #define DESCRIPTOR_WAIT                 (3 << 0)
  69
  70 struct descriptor {
  71         __le16 req_count;
  72         __le16 control;
  73         __le32 data_address;
  74         __le32 branch_address;
  75         __le16 res_count;
  76         __le16 transfer_status;
  77 } __attribute__((aligned(16)));
  78
  79 #define CONTROL_SET(regs)       (regs)
  80 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  81 #define COMMAND_PTR(regs)       ((regs) + 12)
  82 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  83
  84 #define AR_BUFFER_SIZE  (32*1024)
  85 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  86 /* we need at least two pages for proper list management */
  87 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  88
  89 #define MAX_ASYNC_PAYLOAD       4096
  90 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  91 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  92
  93 struct ar_context {
  94         struct fw_ohci *ohci;
  95         struct page *pages[AR_BUFFERS];
  96         void *buffer;
  97         struct descriptor *descriptors;
  98         dma_addr_t descriptors_bus;
  99         void *pointer;
 100         unsigned int last_buffer_index;
 101         u32 regs;
 102         struct tasklet_struct tasklet;
 103 };
 104
 105 struct context;
 106
 107 typedef int (*descriptor_callback_t)(struct context *ctx,
 108                                      struct descriptor *d,
 109                                      struct descriptor *last);
 110
 111 /*
 112  * A buffer that contains a block of DMA-able coherent memory used for
 113  * storing a portion of a DMA descriptor program.
 114  */
 115 struct descriptor_buffer {
 116         struct list_head list;
 117         dma_addr_t buffer_bus;
 118         size_t buffer_size;
 119         size_t used;
 120         struct descriptor buffer[0];
 121 };
 122
 123 struct context {
 124         struct fw_ohci *ohci;
 125         u32 regs;
 126         int total_allocation;
 127
 128         /*
 129          * List of page-sized buffers for storing DMA descriptors.
 130          * Head of list contains buffers in use and tail of list contains
 131          * free buffers.
 132          */
 133         struct list_head buffer_list;
 134
 135         /*
 136          * Pointer to a buffer inside buffer_list that contains the tail
 137          * end of the current DMA program.
 138          */
 139         struct descriptor_buffer *buffer_tail;
 140
 141         /*
 142          * The descriptor containing the branch address of the first
 143          * descriptor that has not yet been filled by the device.
 144          */
 145         struct descriptor *last;
 146
 147         /*
 148          * The last descriptor in the DMA program.  It contains the branch
 149          * address that must be updated upon appending a new descriptor.
 150          */
 151         struct descriptor *prev;
 152
 153         descriptor_callback_t callback;
 154
 155         struct tasklet_struct tasklet;
 156 };
 157
 158 #define IT_HEADER_SY(v)          ((v) <<  0)
 159 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 160 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 161 #define IT_HEADER_TAG(v)         ((v) << 14)
 162 #define IT_HEADER_SPEED(v)       ((v) << 16)
 163 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 164
 165 struct iso_context {
 166         struct fw_iso_context base;
 167         struct context context;
 168         int excess_bytes;
 169         void *header;
 170         size_t header_length;
 171 };
 172
 173 #define CONFIG_ROM_SIZE 1024
 174
 175 struct fw_ohci {
 176         struct fw_card card;
 177
 178         __iomem char *registers;
 179         int node_id;
 180         int generation;
 181         int request_generation; /* for timestamping incoming requests */
 182         unsigned quirks;
 183         unsigned int pri_req_max;
 184         u32 bus_time;
 185         bool is_root;
 186         bool csr_state_setclear_abdicate;
 187
 188         /*
 189          * Spinlock for accessing fw_ohci data.  Never call out of
 190          * this driver with this lock held.
 191          */
 192         spinlock_t lock;
 193
 194         struct mutex phy_reg_mutex;
 195
 196         struct ar_context ar_request_ctx;
 197         struct ar_context ar_response_ctx;
 198         struct context at_request_ctx;
 199         struct context at_response_ctx;
 200
 201         u32 it_context_mask;     /* unoccupied IT contexts */
 202         struct iso_context *it_context_list;
 203         u64 ir_context_channels; /* unoccupied channels */
 204         u32 ir_context_mask;     /* unoccupied IR contexts */
 205         struct iso_context *ir_context_list;
 206         u64 mc_channels; /* channels in use by the multichannel IR context */
 207         bool mc_allocated;
 208
 209         __be32    *config_rom;
 210         dma_addr_t config_rom_bus;
 211         __be32    *next_config_rom;
 212         dma_addr_t next_config_rom_bus;
 213         __be32     next_header;
 214
 215         __le32    *self_id_cpu;
 216         dma_addr_t self_id_bus;
 217         struct tasklet_struct bus_reset_tasklet;
 218
 219         u32 self_id_buffer[512];
 220 };
 221
 222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 223 {
 224         return container_of(card, struct fw_ohci, card);
 225 }
 226
 227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 228 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 229 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 231 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 232 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 233
 234 #define CONTEXT_RUN     0x8000
 235 #define CONTEXT_WAKE    0x1000
 236 #define CONTEXT_DEAD    0x0800
 237 #define CONTEXT_ACTIVE  0x0400
 238
 239 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 240 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 241 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 242
 243 #define OHCI1394_REGISTER_SIZE          0x800
 244 #define OHCI_LOOP_COUNT                 500
 245 #define OHCI1394_PCI_HCI_Control        0x40
 246 #define SELF_ID_BUF_SIZE                0x800
 247 #define OHCI_TCODE_PHY_PACKET           0x0e
 248 #define OHCI_VERSION_1_1                0x010010
 249
 250 static char ohci_driver_name[] = KBUILD_MODNAME;
 251
 252 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 253 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 254 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 255
 256 #define QUIRK_CYCLE_TIMER               1
 257 #define QUIRK_RESET_PACKET              2
 258 #define QUIRK_BE_HEADERS                4
 259 #define QUIRK_NO_1394A                  8
 260 #define QUIRK_NO_MSI                    16
 261
 262 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 263 static const struct {
 264         unsigned short vendor, device, revision, flags;
 265 } ohci_quirks[] = {
 266         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 267                 QUIRK_CYCLE_TIMER},
 268
 269         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 270                 QUIRK_BE_HEADERS},
 271
 272         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 273                 QUIRK_NO_MSI},
 274
 275         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 276                 QUIRK_NO_MSI},
 277
 278         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 279                 QUIRK_CYCLE_TIMER},
 280
 281         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 282                 QUIRK_CYCLE_TIMER},
 283
 284         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 285                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 286
 287         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 288                 QUIRK_RESET_PACKET},
 289
 290         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 291                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 292 };
 293
 294 /* This overrides anything that was found in ohci_quirks[]. */
 295 static int param_quirks;
 296 module_param_named(quirks, param_quirks, int, 0644);
 297 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 298         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 299         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 300         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 301         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 302         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 303         ")");
 304
 305 #define OHCI_PARAM_DEBUG_AT_AR          1
 306 #define OHCI_PARAM_DEBUG_SELFIDS        2
 307 #define OHCI_PARAM_DEBUG_IRQS           4
 308 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 309
 310 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 311
 312 static int param_debug;
 313 module_param_named(debug, param_debug, int, 0644);
 314 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 315         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 316         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 317         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 318         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 319         ", or a combination, or all = -1)");
 320
 321 static void log_irqs(u32 evt)
 322 {
 323         if (likely(!(param_debug &
 324                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 325                 return;
 326
 327         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 328             !(evt & OHCI1394_busReset))
 329                 return;
 330
 331         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 332             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 333             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 334             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 335             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 336             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 337             evt & OHCI1394_isochRx              ? " IR"                 : "",
 338             evt & OHCI1394_isochTx              ? " IT"                 : "",
 339             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 340             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 341             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 342             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 343             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 344             evt & OHCI1394_busReset             ? " busReset"           : "",
 345             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 346                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 347                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 348                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 349                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 350                     OHCI1394_cycleInconsistent |
 351                     OHCI1394_regAccessFail | OHCI1394_busReset)
 352                                                 ? " ?"                  : "");
 353 }
 354
 355 static const char *speed[] = {
 356         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 357 };
 358 static const char *power[] = {
 359         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 360         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 361 };
 362 static const char port[] = { '.', '-', 'p', 'c', };
 363
 364 static char _p(u32 *s, int shift)
 365 {
 366         return port[*s >> shift & 3];
 367 }
 368
 369 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 370 {
 371         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 372                 return;
 373
 374         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 375                   self_id_count, generation, node_id);
 376
 377         for (; self_id_count--; ++s)
 378                 if ((*s & 1 << 23) == 0)
 379                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 380                             "%s gc=%d %s %s%s%s\n",
 381                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 382                             speed[*s >> 14 & 3], *s >> 16 & 63,
 383                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 384                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 385                 else
 386                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 387                             *s, *s >> 24 & 63,
 388                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 389                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 390 }
 391
 392 static const char *evts[] = {
 393         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 394         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 395         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 396         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 397         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 398         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 399         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 400         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 401         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 402         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 403         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 404         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 405         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 406         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 407         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 408         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 409         [0x20] = "pending/cancelled",
 410 };
 411 static const char *tcodes[] = {
 412         [0x0] = "QW req",               [0x1] = "BW req",
 413         [0x2] = "W resp",               [0x3] = "-reserved-",
 414         [0x4] = "QR req",               [0x5] = "BR req",
 415         [0x6] = "QR resp",              [0x7] = "BR resp",
 416         [0x8] = "cycle start",          [0x9] = "Lk req",
 417         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 418         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 419         [0xe] = "link internal",        [0xf] = "-reserved-",
 420 };
 421 static const char *phys[] = {
 422         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 423         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 424 };
 425
 426 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 427 {
 428         int tcode = header[0] >> 4 & 0xf;
 429         char specific[12];
 430
 431         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 432                 return;
 433
 434         if (unlikely(evt >= ARRAY_SIZE(evts)))
 435                         evt = 0x1f;
 436
 437         if (evt == OHCI1394_evt_bus_reset) {
 438                 fw_notify("A%c evt_bus_reset, generation %d\n",
 439                     dir, (header[2] >> 16) & 0xff);
 440                 return;
 441         }
 442
 443         if (header[0] == ~header[1]) {
 444                 fw_notify("A%c %s, %s, %08x\n",
 445                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 446                 return;
 447         }
 448
 449         switch (tcode) {
 450         case 0x0: case 0x6: case 0x8:
 451                 snprintf(specific, sizeof(specific), " = %08x",
 452                          be32_to_cpu((__force __be32)header[3]));
 453                 break;
 454         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 455                 snprintf(specific, sizeof(specific), " %x,%x",
 456                          header[3] >> 16, header[3] & 0xffff);
 457                 break;
 458         default:
 459                 specific[0] = '\0';
 460         }
 461
 462         switch (tcode) {
 463         case 0xe: case 0xa:
 464                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 465                 break;
 466         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 467                 fw_notify("A%c spd %x tl %02x, "
 468                     "%04x -> %04x, %s, "
 469                     "%s, %04x%08x%s\n",
 470                     dir, speed, header[0] >> 10 & 0x3f,
 471                     header[1] >> 16, header[0] >> 16, evts[evt],
 472                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 473                 break;
 474         default:
 475                 fw_notify("A%c spd %x tl %02x, "
 476                     "%04x -> %04x, %s, "
 477                     "%s%s\n",
 478                     dir, speed, header[0] >> 10 & 0x3f,
 479                     header[1] >> 16, header[0] >> 16, evts[evt],
 480                     tcodes[tcode], specific);
 481         }
 482 }
 483
 484 #else
 485
 486 #define param_debug 0
 487 static inline void log_irqs(u32 evt) {}
 488 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 489 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 490
 491 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 492
 493 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 494 {
 495         writel(data, ohci->registers + offset);
 496 }
 497
 498 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 499 {
 500         return readl(ohci->registers + offset);
 501 }
 502
 503 static inline void flush_writes(const struct fw_ohci *ohci)
 504 {
 505         /* Do a dummy read to flush writes. */
 506         reg_read(ohci, OHCI1394_Version);
 507 }
 508
 509 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 510 {
 511         u32 val;
 512         int i;
 513
 514         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 515         for (i = 0; i < 3 + 100; i++) {
 516                 val = reg_read(ohci, OHCI1394_PhyControl);
 517                 if (val & OHCI1394_PhyControl_ReadDone)
 518                         return OHCI1394_PhyControl_ReadData(val);
 519
 520                 /*
 521                  * Try a few times without waiting.  Sleeping is necessary
 522                  * only when the link/PHY interface is busy.
 523                  */
 524                 if (i >= 3)
 525                         msleep(1);
 526         }
 527         fw_error("failed to read phy reg\n");
 528
 529         return -EBUSY;
 530 }
 531
 532 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 533 {
 534         int i;
 535
 536         reg_write(ohci, OHCI1394_PhyControl,
 537                   OHCI1394_PhyControl_Write(addr, val));
 538         for (i = 0; i < 3 + 100; i++) {
 539                 val = reg_read(ohci, OHCI1394_PhyControl);
 540                 if (!(val & OHCI1394_PhyControl_WritePending))
 541                         return 0;
 542
 543                 if (i >= 3)
 544                         msleep(1);
 545         }
 546         fw_error("failed to write phy reg\n");
 547
 548         return -EBUSY;
 549 }
 550
 551 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 552                           int clear_bits, int set_bits)
 553 {
 554         int ret = read_phy_reg(ohci, addr);
 555         if (ret < 0)
 556                 return ret;
 557
 558         /*
 559          * The interrupt status bits are cleared by writing a one bit.
 560          * Avoid clearing them unless explicitly requested in set_bits.
 561          */
 562         if (addr == 5)
 563                 clear_bits |= PHY_INT_STATUS_BITS;
 564
 565         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 566 }
 567
 568 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 569 {
 570         int ret;
 571
 572         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 573         if (ret < 0)
 574                 return ret;
 575
 576         return read_phy_reg(ohci, addr);
 577 }
 578
 579 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 580 {
 581         struct fw_ohci *ohci = fw_ohci(card);
 582         int ret;
 583
 584         mutex_lock(&ohci->phy_reg_mutex);
 585         ret = read_phy_reg(ohci, addr);
 586         mutex_unlock(&ohci->phy_reg_mutex);
 587
 588         return ret;
 589 }
 590
 591 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 592                                int clear_bits, int set_bits)
 593 {
 594         struct fw_ohci *ohci = fw_ohci(card);
 595         int ret;
 596
 597         mutex_lock(&ohci->phy_reg_mutex);
 598         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 599         mutex_unlock(&ohci->phy_reg_mutex);
 600
 601         return ret;
 602 }
 603
 604 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 605 {
 606         return page_private(ctx->pages[i]);
 607 }
 608
 609 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 610 {
 611         struct descriptor *d;
 612
 613         d = &ctx->descriptors[index];
 614         d->branch_address  &= cpu_to_le32(~0xf);
 615         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 616         d->transfer_status =  0;
 617
 618         wmb(); /* finish init of new descriptors before branch_address update */
 619         d = &ctx->descriptors[ctx->last_buffer_index];
 620         d->branch_address  |= cpu_to_le32(1);
 621
 622         ctx->last_buffer_index = index;
 623
 624         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 625         flush_writes(ctx->ohci);
 626 }
 627
 628 static void ar_context_release(struct ar_context *ctx)
 629 {
 630         unsigned int i;
 631
 632         if (ctx->descriptors)
 633                 dma_free_coherent(ctx->ohci->card.device,
 634                                   AR_BUFFERS * sizeof(struct descriptor),
 635                                   ctx->descriptors, ctx->descriptors_bus);
 636
 637         if (ctx->buffer)
 638                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 639
 640         for (i = 0; i < AR_BUFFERS; i++)
 641                 if (ctx->pages[i]) {
 642                         dma_unmap_page(ctx->ohci->card.device,
 643                                        ar_buffer_bus(ctx, i),
 644                                        PAGE_SIZE, DMA_FROM_DEVICE);
 645                         __free_page(ctx->pages[i]);
 646                 }
 647 }
 648
 649 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 650 {
 651         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 652                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 653                 flush_writes(ctx->ohci);
 654
 655                 fw_error("AR error: %s; DMA stopped\n", error_msg);
 656         }
 657         /* FIXME: restart? */
 658 }
 659
 660 static inline unsigned int ar_next_buffer_index(unsigned int index)
 661 {
 662         return (index + 1) % AR_BUFFERS;
 663 }
 664
 665 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 666 {
 667         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 668 }
 669
 670 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 671 {
 672         return ar_next_buffer_index(ctx->last_buffer_index);
 673 }
 674
 675 /*
 676  * We search for the buffer that contains the last AR packet DMA data written
 677  * by the controller.
 678  */
 679 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 680                                                  unsigned int *buffer_offset)
 681 {
 682         unsigned int i, next_i, last = ctx->last_buffer_index;
 683         __le16 res_count, next_res_count;
 684
 685         i = ar_first_buffer_index(ctx);
 686         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 687
 688         /* A buffer that is not yet completely filled must be the last one. */
 689         while (i != last && res_count == 0) {
 690
 691                 /* Peek at the next descriptor. */
 692                 next_i = ar_next_buffer_index(i);
 693                 rmb(); /* read descriptors in order */
 694                 next_res_count = ACCESS_ONCE(
 695                                 ctx->descriptors[next_i].res_count);
 696                 /*
 697                  * If the next descriptor is still empty, we must stop at this
 698                  * descriptor.
 699                  */
 700                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 701                         /*
 702                          * The exception is when the DMA data for one packet is
 703                          * split over three buffers; in this case, the middle
 704                          * buffer's descriptor might be never updated by the
 705                          * controller and look still empty, and we have to peek
 706                          * at the third one.
 707                          */
 708                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 709                                 next_i = ar_next_buffer_index(next_i);
 710                                 rmb();
 711                                 next_res_count = ACCESS_ONCE(
 712                                         ctx->descriptors[next_i].res_count);
 713                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 714                                         goto next_buffer_is_active;
 715                         }
 716
 717                         break;
 718                 }
 719
 720 next_buffer_is_active:
 721                 i = next_i;
 722                 res_count = next_res_count;
 723         }
 724
 725         rmb(); /* read res_count before the DMA data */
 726
 727         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 728         if (*buffer_offset > PAGE_SIZE) {
 729                 *buffer_offset = 0;
 730                 ar_context_abort(ctx, "corrupted descriptor");
 731         }
 732
 733         return i;
 734 }
 735
 736 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 737                                     unsigned int end_buffer_index,
 738                                     unsigned int end_buffer_offset)
 739 {
 740         unsigned int i;
 741
 742         i = ar_first_buffer_index(ctx);
 743         while (i != end_buffer_index) {
 744                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 745                                         ar_buffer_bus(ctx, i),
 746                                         PAGE_SIZE, DMA_FROM_DEVICE);
 747                 i = ar_next_buffer_index(i);
 748         }
 749         if (end_buffer_offset > 0)
 750                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 751                                         ar_buffer_bus(ctx, i),
 752                                         end_buffer_offset, DMA_FROM_DEVICE);
 753 }
 754
 755 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 756 #define cond_le32_to_cpu(v) \
 757         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 758 #else
 759 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 760 #endif
 761
 762 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 763 {
 764         struct fw_ohci *ohci = ctx->ohci;
 765         struct fw_packet p;
 766         u32 status, length, tcode;
 767         int evt;
 768
 769         p.header[0] = cond_le32_to_cpu(buffer[0]);
 770         p.header[1] = cond_le32_to_cpu(buffer[1]);
 771         p.header[2] = cond_le32_to_cpu(buffer[2]);
 772
 773         tcode = (p.header[0] >> 4) & 0x0f;
 774         switch (tcode) {
 775         case TCODE_WRITE_QUADLET_REQUEST:
 776         case TCODE_READ_QUADLET_RESPONSE:
 777                 p.header[3] = (__force __u32) buffer[3];
 778                 p.header_length = 16;
 779                 p.payload_length = 0;
 780                 break;
 781
 782         case TCODE_READ_BLOCK_REQUEST :
 783                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 784                 p.header_length = 16;
 785                 p.payload_length = 0;
 786                 break;
 787
 788         case TCODE_WRITE_BLOCK_REQUEST:
 789         case TCODE_READ_BLOCK_RESPONSE:
 790         case TCODE_LOCK_REQUEST:
 791         case TCODE_LOCK_RESPONSE:
 792                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 793                 p.header_length = 16;
 794                 p.payload_length = p.header[3] >> 16;
 795                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 796                         ar_context_abort(ctx, "invalid packet length");
 797                         return NULL;
 798                 }
 799                 break;
 800
 801         case TCODE_WRITE_RESPONSE:
 802         case TCODE_READ_QUADLET_REQUEST:
 803         case OHCI_TCODE_PHY_PACKET:
 804                 p.header_length = 12;
 805                 p.payload_length = 0;
 806                 break;
 807
 808         default:
 809                 ar_context_abort(ctx, "invalid tcode");
 810                 return NULL;
 811         }
 812
 813         p.payload = (void *) buffer + p.header_length;
 814
 815         /* FIXME: What to do about evt_* errors? */
 816         length = (p.header_length + p.payload_length + 3) / 4;
 817         status = cond_le32_to_cpu(buffer[length]);
 818         evt    = (status >> 16) & 0x1f;
 819
 820         p.ack        = evt - 16;
 821         p.speed      = (status >> 21) & 0x7;
 822         p.timestamp  = status & 0xffff;
 823         p.generation = ohci->request_generation;
 824
 825         log_ar_at_event('R', p.speed, p.header, evt);
 826
 827         /*
 828          * Several controllers, notably from NEC and VIA, forget to
 829          * write ack_complete status at PHY packet reception.
 830          */
 831         if (evt == OHCI1394_evt_no_status &&
 832             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 833                 p.ack = ACK_COMPLETE;
 834
 835         /*
 836          * The OHCI bus reset handler synthesizes a PHY packet with
 837          * the new generation number when a bus reset happens (see
 838          * section 8.4.2.3).  This helps us determine when a request
 839          * was received and make sure we send the response in the same
 840          * generation.  We only need this for requests; for responses
 841          * we use the unique tlabel for finding the matching
 842          * request.
 843          *
 844          * Alas some chips sometimes emit bus reset packets with a
 845          * wrong generation.  We set the correct generation for these
 846          * at a slightly incorrect time (in bus_reset_tasklet).
 847          */
 848         if (evt == OHCI1394_evt_bus_reset) {
 849                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 850                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 851         } else if (ctx == &ohci->ar_request_ctx) {
 852                 fw_core_handle_request(&ohci->card, &p);
 853         } else {
 854                 fw_core_handle_response(&ohci->card, &p);
 855         }
 856
 857         return buffer + length + 1;
 858 }
 859
 860 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 861 {
 862         void *next;
 863
 864         while (p < end) {
 865                 next = handle_ar_packet(ctx, p);
 866                 if (!next)
 867                         return p;
 868                 p = next;
 869         }
 870
 871         return p;
 872 }
 873
 874 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 875 {
 876         unsigned int i;
 877
 878         i = ar_first_buffer_index(ctx);
 879         while (i != end_buffer) {
 880                 dma_sync_single_for_device(ctx->ohci->card.device,
 881                                            ar_buffer_bus(ctx, i),
 882                                            PAGE_SIZE, DMA_FROM_DEVICE);
 883                 ar_context_link_page(ctx, i);
 884                 i = ar_next_buffer_index(i);
 885         }
 886 }
 887
 888 static void ar_context_tasklet(unsigned long data)
 889 {
 890         struct ar_context *ctx = (struct ar_context *)data;
 891         unsigned int end_buffer_index, end_buffer_offset;
 892         void *p, *end;
 893
 894         p = ctx->pointer;
 895         if (!p)
 896                 return;
 897
 898         end_buffer_index = ar_search_last_active_buffer(ctx,
 899                                                         &end_buffer_offset);
 900         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 901         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 902
 903         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 904                 /*
 905                  * The filled part of the overall buffer wraps around; handle
 906                  * all packets up to the buffer end here.  If the last packet
 907                  * wraps around, its tail will be visible after the buffer end
 908                  * because the buffer start pages are mapped there again.
 909                  */
 910                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 911                 p = handle_ar_packets(ctx, p, buffer_end);
 912                 if (p < buffer_end)
 913                         goto error;
 914                 /* adjust p to point back into the actual buffer */
 915                 p -= AR_BUFFERS * PAGE_SIZE;
 916         }
 917
 918         p = handle_ar_packets(ctx, p, end);
 919         if (p != end) {
 920                 if (p > end)
 921                         ar_context_abort(ctx, "inconsistent descriptor");
 922                 goto error;
 923         }
 924
 925         ctx->pointer = p;
 926         ar_recycle_buffers(ctx, end_buffer_index);
 927
 928         return;
 929
 930 error:
 931         ctx->pointer = NULL;
 932 }
 933
 934 static int ar_context_init(struct ar_context *ctx,
 935                            struct fw_ohci *ohci, u32 regs)
 936 {
 937         unsigned int i;
 938         dma_addr_t dma_addr;
 939         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 940         struct descriptor *d;
 941
 942         ctx->regs        = regs;
 943         ctx->ohci        = ohci;
 944         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 945
 946         for (i = 0; i < AR_BUFFERS; i++) {
 947                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 948                 if (!ctx->pages[i])
 949                         goto out_of_memory;
 950                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 951                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 952                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 953                         __free_page(ctx->pages[i]);
 954                         ctx->pages[i] = NULL;
 955                         goto out_of_memory;
 956                 }
 957                 set_page_private(ctx->pages[i], dma_addr);
 958         }
 959
 960         for (i = 0; i < AR_BUFFERS; i++)
 961                 pages[i]              = ctx->pages[i];
 962         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 963                 pages[AR_BUFFERS + i] = ctx->pages[i];
 964         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 965                                  -1, PAGE_KERNEL_RO);
 966         if (!ctx->buffer)
 967                 goto out_of_memory;
 968
 969         ctx->descriptors =
 970                 dma_alloc_coherent(ohci->card.device,
 971                                    AR_BUFFERS * sizeof(struct descriptor),
 972                                    &ctx->descriptors_bus,
 973                                    GFP_KERNEL);
 974         if (!ctx->descriptors)
 975                 goto out_of_memory;
 976
 977         for (i = 0; i < AR_BUFFERS; i++) {
 978                 d = &ctx->descriptors[i];
 979                 d->req_count      = cpu_to_le16(PAGE_SIZE);
 980                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 981                                                 DESCRIPTOR_STATUS |
 982                                                 DESCRIPTOR_BRANCH_ALWAYS);
 983                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
 984                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
 985                         ar_next_buffer_index(i) * sizeof(struct descriptor));
 986         }
 987
 988         return 0;
 989
 990 out_of_memory:
 991         ar_context_release(ctx);
 992
 993         return -ENOMEM;
 994 }
 995
 996 static void ar_context_run(struct ar_context *ctx)
 997 {
 998         unsigned int i;
 999
1000         for (i = 0; i < AR_BUFFERS; i++)
1001                 ar_context_link_page(ctx, i);
1002
1003         ctx->pointer = ctx->buffer;
1004
1005         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1006         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1007         flush_writes(ctx->ohci);
1008 }
1009
1010 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1011 {
1012         int b, key;
1013
1014         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1015         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1016
1017         /* figure out which descriptor the branch address goes in */
1018         if (z == 2 && (b == 3 || key == 2))
1019                 return d;
1020         else
1021                 return d + z - 1;
1022 }
1023
1024 static void context_tasklet(unsigned long data)
1025 {
1026         struct context *ctx = (struct context *) data;
1027         struct descriptor *d, *last;
1028         u32 address;
1029         int z;
1030         struct descriptor_buffer *desc;
1031
1032         desc = list_entry(ctx->buffer_list.next,
1033                         struct descriptor_buffer, list);
1034         last = ctx->last;
1035         while (last->branch_address != 0) {
1036                 struct descriptor_buffer *old_desc = desc;
1037                 address = le32_to_cpu(last->branch_address);
1038                 z = address & 0xf;
1039                 address &= ~0xf;
1040
1041                 /* If the branch address points to a buffer outside of the
1042                  * current buffer, advance to the next buffer. */
1043                 if (address < desc->buffer_bus ||
1044                                 address >= desc->buffer_bus + desc->used)
1045                         desc = list_entry(desc->list.next,
1046                                         struct descriptor_buffer, list);
1047                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1048                 last = find_branch_descriptor(d, z);
1049
1050                 if (!ctx->callback(ctx, d, last))
1051                         break;
1052
1053                 if (old_desc != desc) {
1054                         /* If we've advanced to the next buffer, move the
1055                          * previous buffer to the free list. */
1056                         unsigned long flags;
1057                         old_desc->used = 0;
1058                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1059                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1060                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1061                 }
1062                 ctx->last = last;
1063         }
1064 }
1065
1066 /*
1067  * Allocate a new buffer and add it to the list of free buffers for this
1068  * context.  Must be called with ohci->lock held.
1069  */
1070 static int context_add_buffer(struct context *ctx)
1071 {
1072         struct descriptor_buffer *desc;
1073         dma_addr_t uninitialized_var(bus_addr);
1074         int offset;
1075
1076         /*
1077          * 16MB of descriptors should be far more than enough for any DMA
1078          * program.  This will catch run-away userspace or DoS attacks.
1079          */
1080         if (ctx->total_allocation >= 16*1024*1024)
1081                 return -ENOMEM;
1082
1083         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1084                         &bus_addr, GFP_ATOMIC);
1085         if (!desc)
1086                 return -ENOMEM;
1087
1088         offset = (void *)&desc->buffer - (void *)desc;
1089         desc->buffer_size = PAGE_SIZE - offset;
1090         desc->buffer_bus = bus_addr + offset;
1091         desc->used = 0;
1092
1093         list_add_tail(&desc->list, &ctx->buffer_list);
1094         ctx->total_allocation += PAGE_SIZE;
1095
1096         return 0;
1097 }
1098
1099 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1100                         u32 regs, descriptor_callback_t callback)
1101 {
1102         ctx->ohci = ohci;
1103         ctx->regs = regs;
1104         ctx->total_allocation = 0;
1105
1106         INIT_LIST_HEAD(&ctx->buffer_list);
1107         if (context_add_buffer(ctx) < 0)
1108                 return -ENOMEM;
1109
1110         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1111                         struct descriptor_buffer, list);
1112
1113         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1114         ctx->callback = callback;
1115
1116         /*
1117          * We put a dummy descriptor in the buffer that has a NULL
1118          * branch address and looks like it's been sent.  That way we
1119          * have a descriptor to append DMA programs to.
1120          */
1121         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1122         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1123         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1124         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1125         ctx->last = ctx->buffer_tail->buffer;
1126         ctx->prev = ctx->buffer_tail->buffer;
1127
1128         return 0;
1129 }
1130
1131 static void context_release(struct context *ctx)
1132 {
1133         struct fw_card *card = &ctx->ohci->card;
1134         struct descriptor_buffer *desc, *tmp;
1135
1136         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1137                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1138                         desc->buffer_bus -
1139                         ((void *)&desc->buffer - (void *)desc));
1140 }
1141
1142 /* Must be called with ohci->lock held */
1143 static struct descriptor *context_get_descriptors(struct context *ctx,
1144                                                   int z, dma_addr_t *d_bus)
1145 {
1146         struct descriptor *d = NULL;
1147         struct descriptor_buffer *desc = ctx->buffer_tail;
1148
1149         if (z * sizeof(*d) > desc->buffer_size)
1150                 return NULL;
1151
1152         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1153                 /* No room for the descriptor in this buffer, so advance to the
1154                  * next one. */
1155
1156                 if (desc->list.next == &ctx->buffer_list) {
1157                         /* If there is no free buffer next in the list,
1158                          * allocate one. */
1159                         if (context_add_buffer(ctx) < 0)
1160                                 return NULL;
1161                 }
1162                 desc = list_entry(desc->list.next,
1163                                 struct descriptor_buffer, list);
1164                 ctx->buffer_tail = desc;
1165         }
1166
1167         d = desc->buffer + desc->used / sizeof(*d);
1168         memset(d, 0, z * sizeof(*d));
1169         *d_bus = desc->buffer_bus + desc->used;
1170
1171         return d;
1172 }
1173
1174 static void context_run(struct context *ctx, u32 extra)
1175 {
1176         struct fw_ohci *ohci = ctx->ohci;
1177
1178         reg_write(ohci, COMMAND_PTR(ctx->regs),
1179                   le32_to_cpu(ctx->last->branch_address));
1180         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1181         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1182         flush_writes(ohci);
1183 }
1184
1185 static void context_append(struct context *ctx,
1186                            struct descriptor *d, int z, int extra)
1187 {
1188         dma_addr_t d_bus;
1189         struct descriptor_buffer *desc = ctx->buffer_tail;
1190
1191         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1192
1193         desc->used += (z + extra) * sizeof(*d);
1194
1195         wmb(); /* finish init of new descriptors before branch_address update */
1196         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1197         ctx->prev = find_branch_descriptor(d, z);
1198
1199         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1200         flush_writes(ctx->ohci);
1201 }
1202
1203 static void context_stop(struct context *ctx)
1204 {
1205         u32 reg;
1206         int i;
1207
1208         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1209         flush_writes(ctx->ohci);
1210
1211         for (i = 0; i < 10; i++) {
1212                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1213                 if ((reg & CONTEXT_ACTIVE) == 0)
1214                         return;
1215
1216                 mdelay(1);
1217         }
1218         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1219 }
1220
1221 struct driver_data {
1222         struct fw_packet *packet;
1223 };
1224
1225 /*
1226  * This function apppends a packet to the DMA queue for transmission.
1227  * Must always be called with the ochi->lock held to ensure proper
1228  * generation handling and locking around packet queue manipulation.
1229  */
1230 static int at_context_queue_packet(struct context *ctx,
1231                                    struct fw_packet *packet)
1232 {
1233         struct fw_ohci *ohci = ctx->ohci;
1234         dma_addr_t d_bus, uninitialized_var(payload_bus);
1235         struct driver_data *driver_data;
1236         struct descriptor *d, *last;
1237         __le32 *header;
1238         int z, tcode;
1239         u32 reg;
1240
1241         d = context_get_descriptors(ctx, 4, &d_bus);
1242         if (d == NULL) {
1243                 packet->ack = RCODE_SEND_ERROR;
1244                 return -1;
1245         }
1246
1247         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1248         d[0].res_count = cpu_to_le16(packet->timestamp);
1249
1250         /*
1251          * The DMA format for asyncronous link packets is different
1252          * from the IEEE1394 layout, so shift the fields around
1253          * accordingly.  If header_length is 8, it's a PHY packet, to
1254          * which we need to prepend an extra quadlet.
1255          */
1256
1257         header = (__le32 *) &d[1];
1258         switch (packet->header_length) {
1259         case 16:
1260         case 12:
1261                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1262                                         (packet->speed << 16));
1263                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1264                                         (packet->header[0] & 0xffff0000));
1265                 header[2] = cpu_to_le32(packet->header[2]);
1266
1267                 tcode = (packet->header[0] >> 4) & 0x0f;
1268                 if (TCODE_IS_BLOCK_PACKET(tcode))
1269                         header[3] = cpu_to_le32(packet->header[3]);
1270                 else
1271                         header[3] = (__force __le32) packet->header[3];
1272
1273                 d[0].req_count = cpu_to_le16(packet->header_length);
1274                 break;
1275
1276         case 8:
1277                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1278                                         (packet->speed << 16));
1279                 header[1] = cpu_to_le32(packet->header[0]);
1280                 header[2] = cpu_to_le32(packet->header[1]);
1281                 d[0].req_count = cpu_to_le16(12);
1282
1283                 if (is_ping_packet(packet->header))
1284                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1285                 break;
1286
1287         case 4:
1288                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1289                                         (packet->speed << 16));
1290                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1291                 d[0].req_count = cpu_to_le16(8);
1292                 break;
1293
1294         default:
1295                 /* BUG(); */
1296                 packet->ack = RCODE_SEND_ERROR;
1297                 return -1;
1298         }
1299
1300         driver_data = (struct driver_data *) &d[3];
1301         driver_data->packet = packet;
1302         packet->driver_data = driver_data;
1303
1304         if (packet->payload_length > 0) {
1305                 payload_bus =
1306                         dma_map_single(ohci->card.device, packet->payload,
1307                                        packet->payload_length, DMA_TO_DEVICE);
1308                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1309                         packet->ack = RCODE_SEND_ERROR;
1310                         return -1;
1311                 }
1312                 packet->payload_bus     = payload_bus;
1313                 packet->payload_mapped  = true;
1314
1315                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1316                 d[2].data_address = cpu_to_le32(payload_bus);
1317                 last = &d[2];
1318                 z = 3;
1319         } else {
1320                 last = &d[0];
1321                 z = 2;
1322         }
1323
1324         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1325                                      DESCRIPTOR_IRQ_ALWAYS |
1326                                      DESCRIPTOR_BRANCH_ALWAYS);
1327
1328         /*
1329          * If the controller and packet generations don't match, we need to
1330          * bail out and try again.  If IntEvent.busReset is set, the AT context
1331          * is halted, so appending to the context and trying to run it is
1332          * futile.  Most controllers do the right thing and just flush the AT
1333          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1334          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1335          * up stalling out.  So we just bail out in software and try again
1336          * later, and everyone is happy.
1337          * FIXME: Document how the locking works.
1338          */
1339         if (ohci->generation != packet->generation ||
1340             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1341                 if (packet->payload_mapped)
1342                         dma_unmap_single(ohci->card.device, payload_bus,
1343                                          packet->payload_length, DMA_TO_DEVICE);
1344                 packet->ack = RCODE_GENERATION;
1345                 return -1;
1346         }
1347
1348         context_append(ctx, d, z, 4 - z);
1349
1350         /* If the context isn't already running, start it up. */
1351         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1352         if ((reg & CONTEXT_RUN) == 0)
1353                 context_run(ctx, 0);
1354
1355         return 0;
1356 }
1357
1358 static int handle_at_packet(struct context *context,
1359                             struct descriptor *d,
1360                             struct descriptor *last)
1361 {
1362         struct driver_data *driver_data;
1363         struct fw_packet *packet;
1364         struct fw_ohci *ohci = context->ohci;
1365         int evt;
1366
1367         if (last->transfer_status == 0)
1368                 /* This descriptor isn't done yet, stop iteration. */
1369                 return 0;
1370
1371         driver_data = (struct driver_data *) &d[3];
1372         packet = driver_data->packet;
1373         if (packet == NULL)
1374                 /* This packet was cancelled, just continue. */
1375                 return 1;
1376
1377         if (packet->payload_mapped)
1378                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1379                                  packet->payload_length, DMA_TO_DEVICE);
1380
1381         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1382         packet->timestamp = le16_to_cpu(last->res_count);
1383
1384         log_ar_at_event('T', packet->speed, packet->header, evt);
1385
1386         switch (evt) {
1387         case OHCI1394_evt_timeout:
1388                 /* Async response transmit timed out. */
1389                 packet->ack = RCODE_CANCELLED;
1390                 break;
1391
1392         case OHCI1394_evt_flushed:
1393                 /*
1394                  * The packet was flushed should give same error as
1395                  * when we try to use a stale generation count.
1396                  */
1397                 packet->ack = RCODE_GENERATION;
1398                 break;
1399
1400         case OHCI1394_evt_missing_ack:
1401                 /*
1402                  * Using a valid (current) generation count, but the
1403                  * node is not on the bus or not sending acks.
1404                  */
1405                 packet->ack = RCODE_NO_ACK;
1406                 break;
1407
1408         case ACK_COMPLETE + 0x10:
1409         case ACK_PENDING + 0x10:
1410         case ACK_BUSY_X + 0x10:
1411         case ACK_BUSY_A + 0x10:
1412         case ACK_BUSY_B + 0x10:
1413         case ACK_DATA_ERROR + 0x10:
1414         case ACK_TYPE_ERROR + 0x10:
1415                 packet->ack = evt - 0x10;
1416                 break;
1417
1418         default:
1419                 packet->ack = RCODE_SEND_ERROR;
1420                 break;
1421         }
1422
1423         packet->callback(packet, &ohci->card, packet->ack);
1424
1425         return 1;
1426 }
1427
1428 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1429 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1430 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1431 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1432 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1433
1434 static void handle_local_rom(struct fw_ohci *ohci,
1435                              struct fw_packet *packet, u32 csr)
1436 {
1437         struct fw_packet response;
1438         int tcode, length, i;
1439
1440         tcode = HEADER_GET_TCODE(packet->header[0]);
1441         if (TCODE_IS_BLOCK_PACKET(tcode))
1442                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1443         else
1444                 length = 4;
1445
1446         i = csr - CSR_CONFIG_ROM;
1447         if (i + length > CONFIG_ROM_SIZE) {
1448                 fw_fill_response(&response, packet->header,
1449                                  RCODE_ADDRESS_ERROR, NULL, 0);
1450         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1451                 fw_fill_response(&response, packet->header,
1452                                  RCODE_TYPE_ERROR, NULL, 0);
1453         } else {
1454                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1455                                  (void *) ohci->config_rom + i, length);
1456         }
1457
1458         fw_core_handle_response(&ohci->card, &response);
1459 }
1460
1461 static void handle_local_lock(struct fw_ohci *ohci,
1462                               struct fw_packet *packet, u32 csr)
1463 {
1464         struct fw_packet response;
1465         int tcode, length, ext_tcode, sel, try;
1466         __be32 *payload, lock_old;
1467         u32 lock_arg, lock_data;
1468
1469         tcode = HEADER_GET_TCODE(packet->header[0]);
1470         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1471         payload = packet->payload;
1472         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1473
1474         if (tcode == TCODE_LOCK_REQUEST &&
1475             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1476                 lock_arg = be32_to_cpu(payload[0]);
1477                 lock_data = be32_to_cpu(payload[1]);
1478         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1479                 lock_arg = 0;
1480                 lock_data = 0;
1481         } else {
1482                 fw_fill_response(&response, packet->header,
1483                                  RCODE_TYPE_ERROR, NULL, 0);
1484                 goto out;
1485         }
1486
1487         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1488         reg_write(ohci, OHCI1394_CSRData, lock_data);
1489         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1490         reg_write(ohci, OHCI1394_CSRControl, sel);
1491
1492         for (try = 0; try < 20; try++)
1493                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1494                         lock_old = cpu_to_be32(reg_read(ohci,
1495                                                         OHCI1394_CSRData));
1496                         fw_fill_response(&response, packet->header,
1497                                          RCODE_COMPLETE,
1498                                          &lock_old, sizeof(lock_old));
1499                         goto out;
1500                 }
1501
1502         fw_error("swap not done (CSR lock timeout)\n");
1503         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1504
1505  out:
1506         fw_core_handle_response(&ohci->card, &response);
1507 }
1508
1509 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1510 {
1511         u64 offset, csr;
1512
1513         if (ctx == &ctx->ohci->at_request_ctx) {
1514                 packet->ack = ACK_PENDING;
1515                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1516         }
1517
1518         offset =
1519                 ((unsigned long long)
1520                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1521                 packet->header[2];
1522         csr = offset - CSR_REGISTER_BASE;
1523
1524         /* Handle config rom reads. */
1525         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1526                 handle_local_rom(ctx->ohci, packet, csr);
1527         else switch (csr) {
1528         case CSR_BUS_MANAGER_ID:
1529         case CSR_BANDWIDTH_AVAILABLE:
1530         case CSR_CHANNELS_AVAILABLE_HI:
1531         case CSR_CHANNELS_AVAILABLE_LO:
1532                 handle_local_lock(ctx->ohci, packet, csr);
1533                 break;
1534         default:
1535                 if (ctx == &ctx->ohci->at_request_ctx)
1536                         fw_core_handle_request(&ctx->ohci->card, packet);
1537                 else
1538                         fw_core_handle_response(&ctx->ohci->card, packet);
1539                 break;
1540         }
1541
1542         if (ctx == &ctx->ohci->at_response_ctx) {
1543                 packet->ack = ACK_COMPLETE;
1544                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1545         }
1546 }
1547
1548 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1549 {
1550         unsigned long flags;
1551         int ret;
1552
1553         spin_lock_irqsave(&ctx->ohci->lock, flags);
1554
1555         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1556             ctx->ohci->generation == packet->generation) {
1557                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1558                 handle_local_request(ctx, packet);
1559                 return;
1560         }
1561
1562         ret = at_context_queue_packet(ctx, packet);
1563         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1564
1565         if (ret < 0)
1566                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1567
1568 }
1569
1570 static u32 cycle_timer_ticks(u32 cycle_timer)
1571 {
1572         u32 ticks;
1573
1574         ticks = cycle_timer & 0xfff;
1575         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1576         ticks += (3072 * 8000) * (cycle_timer >> 25);
1577
1578         return ticks;
1579 }
1580
1581 /*
1582  * Some controllers exhibit one or more of the following bugs when updating the
1583  * iso cycle timer register:
1584  *  - When the lowest six bits are wrapping around to zero, a read that happens
1585  *    at the same time will return garbage in the lowest ten bits.
1586  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1587  *    not incremented for about 60 ns.
1588  *  - Occasionally, the entire register reads zero.
1589  *
1590  * To catch these, we read the register three times and ensure that the
1591  * difference between each two consecutive reads is approximately the same, i.e.
1592  * less than twice the other.  Furthermore, any negative difference indicates an
1593  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1594  * execute, so we have enough precision to compute the ratio of the differences.)
1595  */
1596 static u32 get_cycle_time(struct fw_ohci *ohci)
1597 {
1598         u32 c0, c1, c2;
1599         u32 t0, t1, t2;
1600         s32 diff01, diff12;
1601         int i;
1602
1603         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1604
1605         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1606                 i = 0;
1607                 c1 = c2;
1608                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1609                 do {
1610                         c0 = c1;
1611                         c1 = c2;
1612                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1613                         t0 = cycle_timer_ticks(c0);
1614                         t1 = cycle_timer_ticks(c1);
1615                         t2 = cycle_timer_ticks(c2);
1616                         diff01 = t1 - t0;
1617                         diff12 = t2 - t1;
1618                 } while ((diff01 <= 0 || diff12 <= 0 ||
1619                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1620                          && i++ < 20);
1621         }
1622
1623         return c2;
1624 }
1625
1626 /*
1627  * This function has to be called at least every 64 seconds.  The bus_time
1628  * field stores not only the upper 25 bits of the BUS_TIME register but also
1629  * the most significant bit of the cycle timer in bit 6 so that we can detect
1630  * changes in this bit.
1631  */
1632 static u32 update_bus_time(struct fw_ohci *ohci)
1633 {
1634         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1635
1636         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1637                 ohci->bus_time += 0x40;
1638
1639         return ohci->bus_time | cycle_time_seconds;
1640 }
1641
1642 static void bus_reset_tasklet(unsigned long data)
1643 {
1644         struct fw_ohci *ohci = (struct fw_ohci *)data;
1645         int self_id_count, i, j, reg;
1646         int generation, new_generation;
1647         unsigned long flags;
1648         void *free_rom = NULL;
1649         dma_addr_t free_rom_bus = 0;
1650         bool is_new_root;
1651
1652         reg = reg_read(ohci, OHCI1394_NodeID);
1653         if (!(reg & OHCI1394_NodeID_idValid)) {
1654                 fw_notify("node ID not valid, new bus reset in progress\n");
1655                 return;
1656         }
1657         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1658                 fw_notify("malconfigured bus\n");
1659                 return;
1660         }
1661         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1662                                OHCI1394_NodeID_nodeNumber);
1663
1664         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1665         if (!(ohci->is_root && is_new_root))
1666                 reg_write(ohci, OHCI1394_LinkControlSet,
1667                           OHCI1394_LinkControl_cycleMaster);
1668         ohci->is_root = is_new_root;
1669
1670         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1671         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1672                 fw_notify("inconsistent self IDs\n");
1673                 return;
1674         }
1675         /*
1676          * The count in the SelfIDCount register is the number of
1677          * bytes in the self ID receive buffer.  Since we also receive
1678          * the inverted quadlets and a header quadlet, we shift one
1679          * bit extra to get the actual number of self IDs.
1680          */
1681         self_id_count = (reg >> 3) & 0xff;
1682         if (self_id_count == 0 || self_id_count > 252) {
1683                 fw_notify("inconsistent self IDs\n");
1684                 return;
1685         }
1686         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1687         rmb();
1688
1689         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1690                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1691                         fw_notify("inconsistent self IDs\n");
1692                         return;
1693                 }
1694                 ohci->self_id_buffer[j] =
1695                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1696         }
1697         rmb();
1698
1699         /*
1700          * Check the consistency of the self IDs we just read.  The
1701          * problem we face is that a new bus reset can start while we
1702          * read out the self IDs from the DMA buffer. If this happens,
1703          * the DMA buffer will be overwritten with new self IDs and we
1704          * will read out inconsistent data.  The OHCI specification
1705          * (section 11.2) recommends a technique similar to
1706          * linux/seqlock.h, where we remember the generation of the
1707          * self IDs in the buffer before reading them out and compare
1708          * it to the current generation after reading them out.  If
1709          * the two generations match we know we have a consistent set
1710          * of self IDs.
1711          */
1712
1713         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1714         if (new_generation != generation) {
1715                 fw_notify("recursive bus reset detected, "
1716                           "discarding self ids\n");
1717                 return;
1718         }
1719
1720         /* FIXME: Document how the locking works. */
1721         spin_lock_irqsave(&ohci->lock, flags);
1722
1723         ohci->generation = generation;
1724         context_stop(&ohci->at_request_ctx);
1725         context_stop(&ohci->at_response_ctx);
1726         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1727
1728         if (ohci->quirks & QUIRK_RESET_PACKET)
1729                 ohci->request_generation = generation;
1730
1731         /*
1732          * This next bit is unrelated to the AT context stuff but we
1733          * have to do it under the spinlock also.  If a new config rom
1734          * was set up before this reset, the old one is now no longer
1735          * in use and we can free it. Update the config rom pointers
1736          * to point to the current config rom and clear the
1737          * next_config_rom pointer so a new update can take place.
1738          */
1739
1740         if (ohci->next_config_rom != NULL) {
1741                 if (ohci->next_config_rom != ohci->config_rom) {
1742                         free_rom      = ohci->config_rom;
1743                         free_rom_bus  = ohci->config_rom_bus;
1744                 }
1745                 ohci->config_rom      = ohci->next_config_rom;
1746                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1747                 ohci->next_config_rom = NULL;
1748
1749                 /*
1750                  * Restore config_rom image and manually update
1751                  * config_rom registers.  Writing the header quadlet
1752                  * will indicate that the config rom is ready, so we
1753                  * do that last.
1754                  */
1755                 reg_write(ohci, OHCI1394_BusOptions,
1756                           be32_to_cpu(ohci->config_rom[2]));
1757                 ohci->config_rom[0] = ohci->next_header;
1758                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1759                           be32_to_cpu(ohci->next_header));
1760         }
1761
1762 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1763         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1764         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1765 #endif
1766
1767         spin_unlock_irqrestore(&ohci->lock, flags);
1768
1769         if (free_rom)
1770                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1771                                   free_rom, free_rom_bus);
1772
1773         log_selfids(ohci->node_id, generation,
1774                     self_id_count, ohci->self_id_buffer);
1775
1776         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1777                                  self_id_count, ohci->self_id_buffer,
1778                                  ohci->csr_state_setclear_abdicate);
1779         ohci->csr_state_setclear_abdicate = false;
1780 }
1781
1782 static irqreturn_t irq_handler(int irq, void *data)
1783 {
1784         struct fw_ohci *ohci = data;
1785         u32 event, iso_event;
1786         int i;
1787
1788         event = reg_read(ohci, OHCI1394_IntEventClear);
1789
1790         if (!event || !~event)
1791                 return IRQ_NONE;
1792
1793         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1794         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1795         log_irqs(event);
1796
1797         if (event & OHCI1394_selfIDComplete)
1798                 tasklet_schedule(&ohci->bus_reset_tasklet);
1799
1800         if (event & OHCI1394_RQPkt)
1801                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1802
1803         if (event & OHCI1394_RSPkt)
1804                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1805
1806         if (event & OHCI1394_reqTxComplete)
1807                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1808
1809         if (event & OHCI1394_respTxComplete)
1810                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1811
1812         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1813         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1814
1815         while (iso_event) {
1816                 i = ffs(iso_event) - 1;
1817                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1818                 iso_event &= ~(1 << i);
1819         }
1820
1821         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1822         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1823
1824         while (iso_event) {
1825                 i = ffs(iso_event) - 1;
1826                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1827                 iso_event &= ~(1 << i);
1828         }
1829
1830         if (unlikely(event & OHCI1394_regAccessFail))
1831                 fw_error("Register access failure - "
1832                          "please notify linux1394-devel@lists.sf.net\n");
1833
1834         if (unlikely(event & OHCI1394_postedWriteErr))
1835                 fw_error("PCI posted write error\n");
1836
1837         if (unlikely(event & OHCI1394_cycleTooLong)) {
1838                 if (printk_ratelimit())
1839                         fw_notify("isochronous cycle too long\n");
1840                 reg_write(ohci, OHCI1394_LinkControlSet,
1841                           OHCI1394_LinkControl_cycleMaster);
1842         }
1843
1844         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1845                 /*
1846                  * We need to clear this event bit in order to make
1847                  * cycleMatch isochronous I/O work.  In theory we should
1848                  * stop active cycleMatch iso contexts now and restart
1849                  * them at least two cycles later.  (FIXME?)
1850                  */
1851                 if (printk_ratelimit())
1852                         fw_notify("isochronous cycle inconsistent\n");
1853         }
1854
1855         if (event & OHCI1394_cycle64Seconds) {
1856                 spin_lock(&ohci->lock);
1857                 update_bus_time(ohci);
1858                 spin_unlock(&ohci->lock);
1859         }
1860
1861         return IRQ_HANDLED;
1862 }
1863
1864 static int software_reset(struct fw_ohci *ohci)
1865 {
1866         int i;
1867
1868         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1869
1870         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1871                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1872                      OHCI1394_HCControl_softReset) == 0)
1873                         return 0;
1874                 msleep(1);
1875         }
1876
1877         return -EBUSY;
1878 }
1879
1880 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1881 {
1882         size_t size = length * 4;
1883
1884         memcpy(dest, src, size);
1885         if (size < CONFIG_ROM_SIZE)
1886                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1887 }
1888
1889 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1890 {
1891         bool enable_1394a;
1892         int ret, clear, set, offset;
1893
1894         /* Check if the driver should configure link and PHY. */
1895         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1896               OHCI1394_HCControl_programPhyEnable))
1897                 return 0;
1898
1899         /* Paranoia: check whether the PHY supports 1394a, too. */
1900         enable_1394a = false;
1901         ret = read_phy_reg(ohci, 2);
1902         if (ret < 0)
1903                 return ret;
1904         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1905                 ret = read_paged_phy_reg(ohci, 1, 8);
1906                 if (ret < 0)
1907                         return ret;
1908                 if (ret >= 1)
1909                         enable_1394a = true;
1910         }
1911
1912         if (ohci->quirks & QUIRK_NO_1394A)
1913                 enable_1394a = false;
1914
1915         /* Configure PHY and link consistently. */
1916         if (enable_1394a) {
1917                 clear = 0;
1918                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1919         } else {
1920                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1921                 set = 0;
1922         }
1923         ret = update_phy_reg(ohci, 5, clear, set);
1924         if (ret < 0)
1925                 return ret;
1926
1927         if (enable_1394a)
1928                 offset = OHCI1394_HCControlSet;
1929         else
1930                 offset = OHCI1394_HCControlClear;
1931         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1932
1933         /* Clean up: configuration has been taken care of. */
1934         reg_write(ohci, OHCI1394_HCControlClear,
1935                   OHCI1394_HCControl_programPhyEnable);
1936
1937         return 0;
1938 }
1939
1940 static int ohci_enable(struct fw_card *card,
1941                        const __be32 *config_rom, size_t length)
1942 {
1943         struct fw_ohci *ohci = fw_ohci(card);
1944         struct pci_dev *dev = to_pci_dev(card->device);
1945         u32 lps, seconds, version, irqs;
1946         int i, ret;
1947
1948         if (software_reset(ohci)) {
1949                 fw_error("Failed to reset ohci card.\n");
1950                 return -EBUSY;
1951         }
1952
1953         /*
1954          * Now enable LPS, which we need in order to start accessing
1955          * most of the registers.  In fact, on some cards (ALI M5251),
1956          * accessing registers in the SClk domain without LPS enabled
1957          * will lock up the machine.  Wait 50msec to make sure we have
1958          * full link enabled.  However, with some cards (well, at least
1959          * a JMicron PCIe card), we have to try again sometimes.
1960          */
1961         reg_write(ohci, OHCI1394_HCControlSet,
1962                   OHCI1394_HCControl_LPS |
1963                   OHCI1394_HCControl_postedWriteEnable);
1964         flush_writes(ohci);
1965
1966         for (lps = 0, i = 0; !lps && i < 3; i++) {
1967                 msleep(50);
1968                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1969                       OHCI1394_HCControl_LPS;
1970         }
1971
1972         if (!lps) {
1973                 fw_error("Failed to set Link Power Status\n");
1974                 return -EIO;
1975         }
1976
1977         reg_write(ohci, OHCI1394_HCControlClear,
1978                   OHCI1394_HCControl_noByteSwapData);
1979
1980         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1981         reg_write(ohci, OHCI1394_LinkControlSet,
1982                   OHCI1394_LinkControl_rcvSelfID |
1983                   OHCI1394_LinkControl_rcvPhyPkt |
1984                   OHCI1394_LinkControl_cycleTimerEnable |
1985                   OHCI1394_LinkControl_cycleMaster);
1986
1987         reg_write(ohci, OHCI1394_ATRetries,
1988                   OHCI1394_MAX_AT_REQ_RETRIES |
1989                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1990                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1991                   (200 << 16));
1992
1993         seconds = lower_32_bits(get_seconds());
1994         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1995         ohci->bus_time = seconds & ~0x3f;
1996
1997         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1998         if (version >= OHCI_VERSION_1_1) {
1999                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2000                           0xfffffffe);
2001                 card->broadcast_channel_auto_allocated = true;
2002         }
2003
2004         /* Get implemented bits of the priority arbitration request counter. */
2005         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2006         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2007         reg_write(ohci, OHCI1394_FairnessControl, 0);
2008         card->priority_budget_implemented = ohci->pri_req_max != 0;
2009
2010         ar_context_run(&ohci->ar_request_ctx);
2011         ar_context_run(&ohci->ar_response_ctx);
2012
2013         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2014         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2015         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2016
2017         ret = configure_1394a_enhancements(ohci);
2018         if (ret < 0)
2019                 return ret;
2020
2021         /* Activate link_on bit and contender bit in our self ID packets.*/
2022         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2023         if (ret < 0)
2024                 return ret;
2025
2026         /*
2027          * When the link is not yet enabled, the atomic config rom
2028          * update mechanism described below in ohci_set_config_rom()
2029          * is not active.  We have to update ConfigRomHeader and
2030          * BusOptions manually, and the write to ConfigROMmap takes
2031          * effect immediately.  We tie this to the enabling of the
2032          * link, so we have a valid config rom before enabling - the
2033          * OHCI requires that ConfigROMhdr and BusOptions have valid
2034          * values before enabling.
2035          *
2036          * However, when the ConfigROMmap is written, some controllers
2037          * always read back quadlets 0 and 2 from the config rom to
2038          * the ConfigRomHeader and BusOptions registers on bus reset.
2039          * They shouldn't do that in this initial case where the link
2040          * isn't enabled.  This means we have to use the same
2041          * workaround here, setting the bus header to 0 and then write
2042          * the right values in the bus reset tasklet.
2043          */
2044
2045         if (config_rom) {
2046                 ohci->next_config_rom =
2047                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2048                                            &ohci->next_config_rom_bus,
2049                                            GFP_KERNEL);
2050                 if (ohci->next_config_rom == NULL)
2051                         return -ENOMEM;
2052
2053                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2054         } else {
2055                 /*
2056                  * In the suspend case, config_rom is NULL, which
2057                  * means that we just reuse the old config rom.
2058                  */
2059                 ohci->next_config_rom = ohci->config_rom;
2060                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2061         }
2062
2063         ohci->next_header = ohci->next_config_rom[0];
2064         ohci->next_config_rom[0] = 0;
2065         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2066         reg_write(ohci, OHCI1394_BusOptions,
2067                   be32_to_cpu(ohci->next_config_rom[2]));
2068         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2069
2070         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2071
2072         if (!(ohci->quirks & QUIRK_NO_MSI))
2073                 pci_enable_msi(dev);
2074         if (request_irq(dev->irq, irq_handler,
2075                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2076                         ohci_driver_name, ohci)) {
2077                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2078                 pci_disable_msi(dev);
2079                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2080                                   ohci->config_rom, ohci->config_rom_bus);
2081                 return -EIO;
2082         }
2083
2084         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2085                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2086                 OHCI1394_isochTx | OHCI1394_isochRx |
2087                 OHCI1394_postedWriteErr |
2088                 OHCI1394_selfIDComplete |
2089                 OHCI1394_regAccessFail |
2090                 OHCI1394_cycle64Seconds |
2091                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2092                 OHCI1394_masterIntEnable;
2093         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2094                 irqs |= OHCI1394_busReset;
2095         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2096
2097         reg_write(ohci, OHCI1394_HCControlSet,
2098                   OHCI1394_HCControl_linkEnable |
2099                   OHCI1394_HCControl_BIBimageValid);
2100         flush_writes(ohci);
2101
2102         /* We are ready to go, reset bus to finish initialization. */
2103         fw_schedule_bus_reset(&ohci->card, false, true);
2104
2105         return 0;
2106 }
2107
2108 static int ohci_set_config_rom(struct fw_card *card,
2109                                const __be32 *config_rom, size_t length)
2110 {
2111         struct fw_ohci *ohci;
2112         unsigned long flags;
2113         int ret = -EBUSY;
2114         __be32 *next_config_rom;
2115         dma_addr_t uninitialized_var(next_config_rom_bus);
2116
2117         ohci = fw_ohci(card);
2118
2119         /*
2120          * When the OHCI controller is enabled, the config rom update
2121          * mechanism is a bit tricky, but easy enough to use.  See
2122          * section 5.5.6 in the OHCI specification.
2123          *
2124          * The OHCI controller caches the new config rom address in a
2125          * shadow register (ConfigROMmapNext) and needs a bus reset
2126          * for the changes to take place.  When the bus reset is
2127          * detected, the controller loads the new values for the
2128          * ConfigRomHeader and BusOptions registers from the specified
2129          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2130          * shadow register. All automatically and atomically.
2131          *
2132          * Now, there's a twist to this story.  The automatic load of
2133          * ConfigRomHeader and BusOptions doesn't honor the
2134          * noByteSwapData bit, so with a be32 config rom, the
2135          * controller will load be32 values in to these registers
2136          * during the atomic update, even on litte endian
2137          * architectures.  The workaround we use is to put a 0 in the
2138          * header quadlet; 0 is endian agnostic and means that the
2139          * config rom isn't ready yet.  In the bus reset tasklet we
2140          * then set up the real values for the two registers.
2141          *
2142          * We use ohci->lock to avoid racing with the code that sets
2143          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2144          */
2145
2146         next_config_rom =
2147                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2148                                    &next_config_rom_bus, GFP_KERNEL);
2149         if (next_config_rom == NULL)
2150                 return -ENOMEM;
2151
2152         spin_lock_irqsave(&ohci->lock, flags);
2153
2154         if (ohci->next_config_rom == NULL) {
2155                 ohci->next_config_rom = next_config_rom;
2156                 ohci->next_config_rom_bus = next_config_rom_bus;
2157
2158                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2159
2160                 ohci->next_header = config_rom[0];
2161                 ohci->next_config_rom[0] = 0;
2162
2163                 reg_write(ohci, OHCI1394_ConfigROMmap,
2164                           ohci->next_config_rom_bus);
2165                 ret = 0;
2166         }
2167
2168         spin_unlock_irqrestore(&ohci->lock, flags);
2169
2170         /*
2171          * Now initiate a bus reset to have the changes take
2172          * effect. We clean up the old config rom memory and DMA
2173          * mappings in the bus reset tasklet, since the OHCI
2174          * controller could need to access it before the bus reset
2175          * takes effect.
2176          */
2177         if (ret == 0)
2178                 fw_schedule_bus_reset(&ohci->card, true, true);
2179         else
2180                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2181                                   next_config_rom, next_config_rom_bus);
2182
2183         return ret;
2184 }
2185
2186 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2187 {
2188         struct fw_ohci *ohci = fw_ohci(card);
2189
2190         at_context_transmit(&ohci->at_request_ctx, packet);
2191 }
2192
2193 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2194 {
2195         struct fw_ohci *ohci = fw_ohci(card);
2196
2197         at_context_transmit(&ohci->at_response_ctx, packet);
2198 }
2199
2200 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2201 {
2202         struct fw_ohci *ohci = fw_ohci(card);
2203         struct context *ctx = &ohci->at_request_ctx;
2204         struct driver_data *driver_data = packet->driver_data;
2205         int ret = -ENOENT;
2206
2207         tasklet_disable(&ctx->tasklet);
2208
2209         if (packet->ack != 0)
2210                 goto out;
2211
2212         if (packet->payload_mapped)
2213                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2214                                  packet->payload_length, DMA_TO_DEVICE);
2215
2216         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2217         driver_data->packet = NULL;
2218         packet->ack = RCODE_CANCELLED;
2219         packet->callback(packet, &ohci->card, packet->ack);
2220         ret = 0;
2221  out:
2222         tasklet_enable(&ctx->tasklet);
2223
2224         return ret;
2225 }
2226
2227 static int ohci_enable_phys_dma(struct fw_card *card,
2228                                 int node_id, int generation)
2229 {
2230 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2231         return 0;
2232 #else
2233         struct fw_ohci *ohci = fw_ohci(card);
2234         unsigned long flags;
2235         int n, ret = 0;
2236
2237         /*
2238          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2239          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2240          */
2241
2242         spin_lock_irqsave(&ohci->lock, flags);
2243
2244         if (ohci->generation != generation) {
2245                 ret = -ESTALE;
2246                 goto out;
2247         }
2248
2249         /*
2250          * Note, if the node ID contains a non-local bus ID, physical DMA is
2251          * enabled for _all_ nodes on remote buses.
2252          */
2253
2254         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2255         if (n < 32)
2256                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2257         else
2258                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2259
2260         flush_writes(ohci);
2261  out:
2262         spin_unlock_irqrestore(&ohci->lock, flags);
2263
2264         return ret;
2265 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2266 }
2267
2268 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2269 {
2270         struct fw_ohci *ohci = fw_ohci(card);
2271         unsigned long flags;
2272         u32 value;
2273
2274         switch (csr_offset) {
2275         case CSR_STATE_CLEAR:
2276         case CSR_STATE_SET:
2277                 if (ohci->is_root &&
2278                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2279                      OHCI1394_LinkControl_cycleMaster))
2280                         value = CSR_STATE_BIT_CMSTR;
2281                 else
2282                         value = 0;
2283                 if (ohci->csr_state_setclear_abdicate)
2284                         value |= CSR_STATE_BIT_ABDICATE;
2285
2286                 return value;
2287
2288         case CSR_NODE_IDS:
2289                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2290
2291         case CSR_CYCLE_TIME:
2292                 return get_cycle_time(ohci);
2293
2294         case CSR_BUS_TIME:
2295                 /*
2296                  * We might be called just after the cycle timer has wrapped
2297                  * around but just before the cycle64Seconds handler, so we
2298                  * better check here, too, if the bus time needs to be updated.
2299                  */
2300                 spin_lock_irqsave(&ohci->lock, flags);
2301                 value = update_bus_time(ohci);
2302                 spin_unlock_irqrestore(&ohci->lock, flags);
2303                 return value;
2304
2305         case CSR_BUSY_TIMEOUT:
2306                 value = reg_read(ohci, OHCI1394_ATRetries);
2307                 return (value >> 4) & 0x0ffff00f;
2308
2309         case CSR_PRIORITY_BUDGET:
2310                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2311                         (ohci->pri_req_max << 8);
2312
2313         default:
2314                 WARN_ON(1);
2315                 return 0;
2316         }
2317 }
2318
2319 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2320 {
2321         struct fw_ohci *ohci = fw_ohci(card);
2322         unsigned long flags;
2323
2324         switch (csr_offset) {
2325         case CSR_STATE_CLEAR:
2326                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2327                         reg_write(ohci, OHCI1394_LinkControlClear,
2328                                   OHCI1394_LinkControl_cycleMaster);
2329                         flush_writes(ohci);
2330                 }
2331                 if (value & CSR_STATE_BIT_ABDICATE)
2332                         ohci->csr_state_setclear_abdicate = false;
2333                 break;
2334
2335         case CSR_STATE_SET:
2336                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2337                         reg_write(ohci, OHCI1394_LinkControlSet,
2338                                   OHCI1394_LinkControl_cycleMaster);
2339                         flush_writes(ohci);
2340                 }
2341                 if (value & CSR_STATE_BIT_ABDICATE)
2342                         ohci->csr_state_setclear_abdicate = true;
2343                 break;
2344
2345         case CSR_NODE_IDS:
2346                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2347                 flush_writes(ohci);
2348                 break;
2349
2350         case CSR_CYCLE_TIME:
2351                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2352                 reg_write(ohci, OHCI1394_IntEventSet,
2353                           OHCI1394_cycleInconsistent);
2354                 flush_writes(ohci);
2355                 break;
2356
2357         case CSR_BUS_TIME:
2358                 spin_lock_irqsave(&ohci->lock, flags);
2359                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2360                 spin_unlock_irqrestore(&ohci->lock, flags);
2361                 break;
2362
2363         case CSR_BUSY_TIMEOUT:
2364                 value = (value & 0xf) | ((value & 0xf) << 4) |
2365                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2366                 reg_write(ohci, OHCI1394_ATRetries, value);
2367                 flush_writes(ohci);
2368                 break;
2369
2370         case CSR_PRIORITY_BUDGET:
2371                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2372                 flush_writes(ohci);
2373                 break;
2374
2375         default:
2376                 WARN_ON(1);
2377                 break;
2378         }
2379 }
2380
2381 static void copy_iso_headers(struct iso_context *ctx, void *p)
2382 {
2383         int i = ctx->header_length;
2384
2385         if (i + ctx->base.header_size > PAGE_SIZE)
2386                 return;
2387
2388         /*
2389          * The iso header is byteswapped to little endian by
2390          * the controller, but the remaining header quadlets
2391          * are big endian.  We want to present all the headers
2392          * as big endian, so we have to swap the first quadlet.
2393          */
2394         if (ctx->base.header_size > 0)
2395                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2396         if (ctx->base.header_size > 4)
2397                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2398         if (ctx->base.header_size > 8)
2399                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2400         ctx->header_length += ctx->base.header_size;
2401 }
2402
2403 static int handle_ir_packet_per_buffer(struct context *context,
2404                                        struct descriptor *d,
2405                                        struct descriptor *last)
2406 {
2407         struct iso_context *ctx =
2408                 container_of(context, struct iso_context, context);
2409         struct descriptor *pd;
2410         __le32 *ir_header;
2411         void *p;
2412
2413         for (pd = d; pd <= last; pd++)
2414                 if (pd->transfer_status)
2415                         break;
2416         if (pd > last)
2417                 /* Descriptor(s) not done yet, stop iteration */
2418                 return 0;
2419
2420         p = last + 1;
2421         copy_iso_headers(ctx, p);
2422
2423         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2424                 ir_header = (__le32 *) p;
2425                 ctx->base.callback.sc(&ctx->base,
2426                                       le32_to_cpu(ir_header[0]) & 0xffff,
2427                                       ctx->header_length, ctx->header,
2428                                       ctx->base.callback_data);
2429                 ctx->header_length = 0;
2430         }
2431
2432         return 1;
2433 }
2434
2435 /* d == last because each descriptor block is only a single descriptor. */
2436 static int handle_ir_buffer_fill(struct context *context,
2437                                  struct descriptor *d,
2438                                  struct descriptor *last)
2439 {
2440         struct iso_context *ctx =
2441                 container_of(context, struct iso_context, context);
2442
2443         if (!last->transfer_status)
2444                 /* Descriptor(s) not done yet, stop iteration */
2445                 return 0;
2446
2447         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2448                 ctx->base.callback.mc(&ctx->base,
2449                                       le32_to_cpu(last->data_address) +
2450                                       le16_to_cpu(last->req_count) -
2451                                       le16_to_cpu(last->res_count),
2452                                       ctx->base.callback_data);
2453
2454         return 1;
2455 }
2456
2457 static int handle_it_packet(struct context *context,
2458                             struct descriptor *d,
2459                             struct descriptor *last)
2460 {
2461         struct iso_context *ctx =
2462                 container_of(context, struct iso_context, context);
2463         int i;
2464         struct descriptor *pd;
2465
2466         for (pd = d; pd <= last; pd++)
2467                 if (pd->transfer_status)
2468                         break;
2469         if (pd > last)
2470                 /* Descriptor(s) not done yet, stop iteration */
2471                 return 0;
2472
2473         i = ctx->header_length;
2474         if (i + 4 < PAGE_SIZE) {
2475                 /* Present this value as big-endian to match the receive code */
2476                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2477                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2478                                 le16_to_cpu(pd->res_count));
2479                 ctx->header_length += 4;
2480         }
2481         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2482                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2483                                       ctx->header_length, ctx->header,
2484                                       ctx->base.callback_data);
2485                 ctx->header_length = 0;
2486         }
2487         return 1;
2488 }
2489
2490 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2491 {
2492         u32 hi = channels >> 32, lo = channels;
2493
2494         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2495         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2496         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2497         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2498         mmiowb();
2499         ohci->mc_channels = channels;
2500 }
2501
2502 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2503                                 int type, int channel, size_t header_size)
2504 {
2505         struct fw_ohci *ohci = fw_ohci(card);
2506         struct iso_context *uninitialized_var(ctx);
2507         descriptor_callback_t uninitialized_var(callback);
2508         u64 *uninitialized_var(channels);
2509         u32 *uninitialized_var(mask), uninitialized_var(regs);
2510         unsigned long flags;
2511         int index, ret = -EBUSY;
2512
2513         spin_lock_irqsave(&ohci->lock, flags);
2514
2515         switch (type) {
2516         case FW_ISO_CONTEXT_TRANSMIT:
2517                 mask     = &ohci->it_context_mask;
2518                 callback = handle_it_packet;
2519                 index    = ffs(*mask) - 1;
2520                 if (index >= 0) {
2521                         *mask &= ~(1 << index);
2522                         regs = OHCI1394_IsoXmitContextBase(index);
2523                         ctx  = &ohci->it_context_list[index];
2524                 }
2525                 break;
2526
2527         case FW_ISO_CONTEXT_RECEIVE:
2528                 channels = &ohci->ir_context_channels;
2529                 mask     = &ohci->ir_context_mask;
2530                 callback = handle_ir_packet_per_buffer;
2531                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2532                 if (index >= 0) {
2533                         *channels &= ~(1ULL << channel);
2534                         *mask     &= ~(1 << index);
2535                         regs = OHCI1394_IsoRcvContextBase(index);
2536                         ctx  = &ohci->ir_context_list[index];
2537                 }
2538                 break;
2539
2540         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2541                 mask     = &ohci->ir_context_mask;
2542                 callback = handle_ir_buffer_fill;
2543                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2544                 if (index >= 0) {
2545                         ohci->mc_allocated = true;
2546                         *mask &= ~(1 << index);
2547                         regs = OHCI1394_IsoRcvContextBase(index);
2548                         ctx  = &ohci->ir_context_list[index];
2549                 }
2550                 break;
2551
2552         default:
2553                 index = -1;
2554                 ret = -ENOSYS;
2555         }
2556
2557         spin_unlock_irqrestore(&ohci->lock, flags);
2558
2559         if (index < 0)
2560                 return ERR_PTR(ret);
2561
2562         memset(ctx, 0, sizeof(*ctx));
2563         ctx->header_length = 0;
2564         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2565         if (ctx->header == NULL) {
2566                 ret = -ENOMEM;
2567                 goto out;
2568         }
2569         ret = context_init(&ctx->context, ohci, regs, callback);
2570         if (ret < 0)
2571                 goto out_with_header;
2572
2573         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2574                 set_multichannel_mask(ohci, 0);
2575
2576         return &ctx->base;
2577
2578  out_with_header:
2579         free_page((unsigned long)ctx->header);
2580  out:
2581         spin_lock_irqsave(&ohci->lock, flags);
2582
2583         switch (type) {
2584         case FW_ISO_CONTEXT_RECEIVE:
2585                 *channels |= 1ULL << channel;
2586                 break;
2587
2588         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2589                 ohci->mc_allocated = false;
2590                 break;
2591         }
2592         *mask |= 1 << index;
2593
2594         spin_unlock_irqrestore(&ohci->lock, flags);
2595
2596         return ERR_PTR(ret);
2597 }
2598
2599 static int ohci_start_iso(struct fw_iso_context *base,
2600                           s32 cycle, u32 sync, u32 tags)
2601 {
2602         struct iso_context *ctx = container_of(base, struct iso_context, base);
2603         struct fw_ohci *ohci = ctx->context.ohci;
2604         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2605         int index;
2606
2607         switch (ctx->base.type) {
2608         case FW_ISO_CONTEXT_TRANSMIT:
2609                 index = ctx - ohci->it_context_list;
2610                 match = 0;
2611                 if (cycle >= 0)
2612                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2613                                 (cycle & 0x7fff) << 16;
2614
2615                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2616                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2617                 context_run(&ctx->context, match);
2618                 break;
2619
2620         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2621                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2622                 /* fall through */
2623         case FW_ISO_CONTEXT_RECEIVE:
2624                 index = ctx - ohci->ir_context_list;
2625                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2626                 if (cycle >= 0) {
2627                         match |= (cycle & 0x07fff) << 12;
2628                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2629                 }
2630
2631                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2632                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2633                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2634                 context_run(&ctx->context, control);
2635                 break;
2636         }
2637
2638         return 0;
2639 }
2640
2641 static int ohci_stop_iso(struct fw_iso_context *base)
2642 {
2643         struct fw_ohci *ohci = fw_ohci(base->card);
2644         struct iso_context *ctx = container_of(base, struct iso_context, base);
2645         int index;
2646
2647         switch (ctx->base.type) {
2648         case FW_ISO_CONTEXT_TRANSMIT:
2649                 index = ctx - ohci->it_context_list;
2650                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2651                 break;
2652
2653         case FW_ISO_CONTEXT_RECEIVE:
2654         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2655                 index = ctx - ohci->ir_context_list;
2656                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2657                 break;
2658         }
2659         flush_writes(ohci);
2660         context_stop(&ctx->context);
2661
2662         return 0;
2663 }
2664
2665 static void ohci_free_iso_context(struct fw_iso_context *base)
2666 {
2667         struct fw_ohci *ohci = fw_ohci(base->card);
2668         struct iso_context *ctx = container_of(base, struct iso_context, base);
2669         unsigned long flags;
2670         int index;
2671
2672         ohci_stop_iso(base);
2673         context_release(&ctx->context);
2674         free_page((unsigned long)ctx->header);
2675
2676         spin_lock_irqsave(&ohci->lock, flags);
2677
2678         switch (base->type) {
2679         case FW_ISO_CONTEXT_TRANSMIT:
2680                 index = ctx - ohci->it_context_list;
2681                 ohci->it_context_mask |= 1 << index;
2682                 break;
2683
2684         case FW_ISO_CONTEXT_RECEIVE:
2685                 index = ctx - ohci->ir_context_list;
2686                 ohci->ir_context_mask |= 1 << index;
2687                 ohci->ir_context_channels |= 1ULL << base->channel;
2688                 break;
2689
2690         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2691                 index = ctx - ohci->ir_context_list;
2692                 ohci->ir_context_mask |= 1 << index;
2693                 ohci->ir_context_channels |= ohci->mc_channels;
2694                 ohci->mc_channels = 0;
2695                 ohci->mc_allocated = false;
2696                 break;
2697         }
2698
2699         spin_unlock_irqrestore(&ohci->lock, flags);
2700 }
2701
2702 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2703 {
2704         struct fw_ohci *ohci = fw_ohci(base->card);
2705         unsigned long flags;
2706         int ret;
2707
2708         switch (base->type) {
2709         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2710
2711                 spin_lock_irqsave(&ohci->lock, flags);
2712
2713                 /* Don't allow multichannel to grab other contexts' channels. */
2714                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2715                         *channels = ohci->ir_context_channels;
2716                         ret = -EBUSY;
2717                 } else {
2718                         set_multichannel_mask(ohci, *channels);
2719                         ret = 0;
2720                 }
2721
2722                 spin_unlock_irqrestore(&ohci->lock, flags);
2723
2724                 break;
2725         default:
2726                 ret = -EINVAL;
2727         }
2728
2729         return ret;
2730 }
2731
2732 static int queue_iso_transmit(struct iso_context *ctx,
2733                               struct fw_iso_packet *packet,
2734                               struct fw_iso_buffer *buffer,
2735                               unsigned long payload)
2736 {
2737         struct descriptor *d, *last, *pd;
2738         struct fw_iso_packet *p;
2739         __le32 *header;
2740         dma_addr_t d_bus, page_bus;
2741         u32 z, header_z, payload_z, irq;
2742         u32 payload_index, payload_end_index, next_page_index;
2743         int page, end_page, i, length, offset;
2744
2745         p = packet;
2746         payload_index = payload;
2747
2748         if (p->skip)
2749                 z = 1;
2750         else
2751                 z = 2;
2752         if (p->header_length > 0)
2753                 z++;
2754
2755         /* Determine the first page the payload isn't contained in. */
2756         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2757         if (p->payload_length > 0)
2758                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2759         else
2760                 payload_z = 0;
2761
2762         z += payload_z;
2763
2764         /* Get header size in number of descriptors. */
2765         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2766
2767         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2768         if (d == NULL)
2769                 return -ENOMEM;
2770
2771         if (!p->skip) {
2772                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2773                 d[0].req_count = cpu_to_le16(8);
2774                 /*
2775                  * Link the skip address to this descriptor itself.  This causes
2776                  * a context to skip a cycle whenever lost cycles or FIFO
2777                  * overruns occur, without dropping the data.  The application
2778                  * should then decide whether this is an error condition or not.
2779                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2780                  */
2781                 d[0].branch_address = cpu_to_le32(d_bus | z);
2782
2783                 header = (__le32 *) &d[1];
2784                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2785                                         IT_HEADER_TAG(p->tag) |
2786                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2787                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2788                                         IT_HEADER_SPEED(ctx->base.speed));
2789                 header[1] =
2790                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2791                                                           p->payload_length));
2792         }
2793
2794         if (p->header_length > 0) {
2795                 d[2].req_count    = cpu_to_le16(p->header_length);
2796                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2797                 memcpy(&d[z], p->header, p->header_length);
2798         }
2799
2800         pd = d + z - payload_z;
2801         payload_end_index = payload_index + p->payload_length;
2802         for (i = 0; i < payload_z; i++) {
2803                 page               = payload_index >> PAGE_SHIFT;
2804                 offset             = payload_index & ~PAGE_MASK;
2805                 next_page_index    = (page + 1) << PAGE_SHIFT;
2806                 length             =
2807                         min(next_page_index, payload_end_index) - payload_index;
2808                 pd[i].req_count    = cpu_to_le16(length);
2809
2810                 page_bus = page_private(buffer->pages[page]);
2811                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2812
2813                 payload_index += length;
2814         }
2815
2816         if (p->interrupt)
2817                 irq = DESCRIPTOR_IRQ_ALWAYS;
2818         else
2819                 irq = DESCRIPTOR_NO_IRQ;
2820
2821         last = z == 2 ? d : d + z - 1;
2822         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2823                                      DESCRIPTOR_STATUS |
2824                                      DESCRIPTOR_BRANCH_ALWAYS |
2825                                      irq);
2826
2827         context_append(&ctx->context, d, z, header_z);
2828
2829         return 0;
2830 }
2831
2832 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2833                                        struct fw_iso_packet *packet,
2834                                        struct fw_iso_buffer *buffer,
2835                                        unsigned long payload)
2836 {
2837         struct descriptor *d, *pd;
2838         dma_addr_t d_bus, page_bus;
2839         u32 z, header_z, rest;
2840         int i, j, length;
2841         int page, offset, packet_count, header_size, payload_per_buffer;
2842
2843         /*
2844          * The OHCI controller puts the isochronous header and trailer in the
2845          * buffer, so we need at least 8 bytes.
2846          */
2847         packet_count = packet->header_length / ctx->base.header_size;
2848         header_size  = max(ctx->base.header_size, (size_t)8);
2849
2850         /* Get header size in number of descriptors. */
2851         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2852         page     = payload >> PAGE_SHIFT;
2853         offset   = payload & ~PAGE_MASK;
2854         payload_per_buffer = packet->payload_length / packet_count;
2855
2856         for (i = 0; i < packet_count; i++) {
2857                 /* d points to the header descriptor */
2858                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2859                 d = context_get_descriptors(&ctx->context,
2860                                 z + header_z, &d_bus);
2861                 if (d == NULL)
2862                         return -ENOMEM;
2863
2864                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2865                                               DESCRIPTOR_INPUT_MORE);
2866                 if (packet->skip && i == 0)
2867                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2868                 d->req_count    = cpu_to_le16(header_size);
2869                 d->res_count    = d->req_count;
2870                 d->transfer_status = 0;
2871                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2872
2873                 rest = payload_per_buffer;
2874                 pd = d;
2875                 for (j = 1; j < z; j++) {
2876                         pd++;
2877                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2878                                                   DESCRIPTOR_INPUT_MORE);
2879
2880                         if (offset + rest < PAGE_SIZE)
2881                                 length = rest;
2882                         else
2883                                 length = PAGE_SIZE - offset;
2884                         pd->req_count = cpu_to_le16(length);
2885                         pd->res_count = pd->req_count;
2886                         pd->transfer_status = 0;
2887
2888                         page_bus = page_private(buffer->pages[page]);
2889                         pd->data_address = cpu_to_le32(page_bus + offset);
2890
2891                         offset = (offset + length) & ~PAGE_MASK;
2892                         rest -= length;
2893                         if (offset == 0)
2894                                 page++;
2895                 }
2896                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2897                                           DESCRIPTOR_INPUT_LAST |
2898                                           DESCRIPTOR_BRANCH_ALWAYS);
2899                 if (packet->interrupt && i == packet_count - 1)
2900                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2901
2902                 context_append(&ctx->context, d, z, header_z);
2903         }
2904
2905         return 0;
2906 }
2907
2908 static int queue_iso_buffer_fill(struct iso_context *ctx,
2909                                  struct fw_iso_packet *packet,
2910                                  struct fw_iso_buffer *buffer,
2911                                  unsigned long payload)
2912 {
2913         struct descriptor *d;
2914         dma_addr_t d_bus, page_bus;
2915         int page, offset, rest, z, i, length;
2916
2917         page   = payload >> PAGE_SHIFT;
2918         offset = payload & ~PAGE_MASK;
2919         rest   = packet->payload_length;
2920
2921         /* We need one descriptor for each page in the buffer. */
2922         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2923
2924         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2925                 return -EFAULT;
2926
2927         for (i = 0; i < z; i++) {
2928                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2929                 if (d == NULL)
2930                         return -ENOMEM;
2931
2932                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2933                                          DESCRIPTOR_BRANCH_ALWAYS);
2934                 if (packet->skip && i == 0)
2935                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2936                 if (packet->interrupt && i == z - 1)
2937                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2938
2939                 if (offset + rest < PAGE_SIZE)
2940                         length = rest;
2941                 else
2942                         length = PAGE_SIZE - offset;
2943                 d->req_count = cpu_to_le16(length);
2944                 d->res_count = d->req_count;
2945                 d->transfer_status = 0;
2946
2947                 page_bus = page_private(buffer->pages[page]);
2948                 d->data_address = cpu_to_le32(page_bus + offset);
2949
2950                 rest -= length;
2951                 offset = 0;
2952                 page++;
2953
2954                 context_append(&ctx->context, d, 1, 0);
2955         }
2956
2957         return 0;
2958 }
2959
2960 static int ohci_queue_iso(struct fw_iso_context *base,
2961                           struct fw_iso_packet *packet,
2962                           struct fw_iso_buffer *buffer,
2963                           unsigned long payload)
2964 {
2965         struct iso_context *ctx = container_of(base, struct iso_context, base);
2966         unsigned long flags;
2967         int ret = -ENOSYS;
2968
2969         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2970         switch (base->type) {
2971         case FW_ISO_CONTEXT_TRANSMIT:
2972                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2973                 break;
2974         case FW_ISO_CONTEXT_RECEIVE:
2975                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2976                 break;
2977         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2978                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2979                 break;
2980         }
2981         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2982
2983         return ret;
2984 }
2985
2986 static const struct fw_card_driver ohci_driver = {
2987         .enable                 = ohci_enable,
2988         .read_phy_reg           = ohci_read_phy_reg,
2989         .update_phy_reg         = ohci_update_phy_reg,
2990         .set_config_rom         = ohci_set_config_rom,
2991         .send_request           = ohci_send_request,
2992         .send_response          = ohci_send_response,
2993         .cancel_packet          = ohci_cancel_packet,
2994         .enable_phys_dma        = ohci_enable_phys_dma,
2995         .read_csr               = ohci_read_csr,
2996         .write_csr              = ohci_write_csr,
2997
2998         .allocate_iso_context   = ohci_allocate_iso_context,
2999         .free_iso_context       = ohci_free_iso_context,
3000         .set_iso_channels       = ohci_set_iso_channels,
3001         .queue_iso              = ohci_queue_iso,
3002         .start_iso              = ohci_start_iso,
3003         .stop_iso               = ohci_stop_iso,
3004 };
3005
3006 #ifdef CONFIG_PPC_PMAC
3007 static void pmac_ohci_on(struct pci_dev *dev)
3008 {
3009         if (machine_is(powermac)) {
3010                 struct device_node *ofn = pci_device_to_OF_node(dev);
3011
3012                 if (ofn) {
3013                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3014                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3015                 }
3016         }
3017 }
3018
3019 static void pmac_ohci_off(struct pci_dev *dev)
3020 {
3021         if (machine_is(powermac)) {
3022                 struct device_node *ofn = pci_device_to_OF_node(dev);
3023
3024                 if (ofn) {
3025                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3026                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3027                 }
3028         }
3029 }
3030 #else
3031 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3032 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3033 #endif /* CONFIG_PPC_PMAC */
3034
3035 static int __devinit pci_probe(struct pci_dev *dev,
3036                                const struct pci_device_id *ent)
3037 {
3038         struct fw_ohci *ohci;
3039         u32 bus_options, max_receive, link_speed, version;
3040         u64 guid;
3041         int i, err, n_ir, n_it;
3042         size_t size;
3043
3044         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3045         if (ohci == NULL) {
3046                 err = -ENOMEM;
3047                 goto fail;
3048         }
3049
3050         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3051
3052         pmac_ohci_on(dev);
3053
3054         err = pci_enable_device(dev);
3055         if (err) {
3056                 fw_error("Failed to enable OHCI hardware\n");
3057                 goto fail_free;
3058         }
3059
3060         pci_set_master(dev);
3061         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3062         pci_set_drvdata(dev, ohci);
3063
3064         spin_lock_init(&ohci->lock);
3065         mutex_init(&ohci->phy_reg_mutex);
3066
3067         tasklet_init(&ohci->bus_reset_tasklet,
3068                      bus_reset_tasklet, (unsigned long)ohci);
3069
3070         err = pci_request_region(dev, 0, ohci_driver_name);
3071         if (err) {
3072                 fw_error("MMIO resource unavailable\n");
3073                 goto fail_disable;
3074         }
3075
3076         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3077         if (ohci->registers == NULL) {
3078                 fw_error("Failed to remap registers\n");
3079                 err = -ENXIO;
3080                 goto fail_iomem;
3081         }
3082
3083         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3084                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3085                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3086                      ohci_quirks[i].device == dev->device) &&
3087                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3088                      ohci_quirks[i].revision >= dev->revision)) {
3089                         ohci->quirks = ohci_quirks[i].flags;
3090                         break;
3091                 }
3092         if (param_quirks)
3093                 ohci->quirks = param_quirks;
3094
3095         err = ar_context_init(&ohci->ar_request_ctx, ohci,
3096                               OHCI1394_AsReqRcvContextControlSet);
3097         if (err < 0)
3098                 goto fail_iounmap;
3099
3100         err = ar_context_init(&ohci->ar_response_ctx, ohci,
3101                               OHCI1394_AsRspRcvContextControlSet);
3102         if (err < 0)
3103                 goto fail_arreq_ctx;
3104
3105         context_init(&ohci->at_request_ctx, ohci,
3106                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3107
3108         context_init(&ohci->at_response_ctx, ohci,
3109                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3110
3111         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3112         ohci->ir_context_channels = ~0ULL;
3113         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3114         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3115         n_ir = hweight32(ohci->ir_context_mask);
3116         size = sizeof(struct iso_context) * n_ir;
3117         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3118
3119         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3120         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3121         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3122         n_it = hweight32(ohci->it_context_mask);
3123         size = sizeof(struct iso_context) * n_it;
3124         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3125
3126         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3127                 err = -ENOMEM;
3128                 goto fail_contexts;
3129         }
3130
3131         /* self-id dma buffer allocation */
3132         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
3133                                                SELF_ID_BUF_SIZE,
3134                                                &ohci->self_id_bus,
3135                                                GFP_KERNEL);
3136         if (ohci->self_id_cpu == NULL) {
3137                 err = -ENOMEM;
3138                 goto fail_contexts;
3139         }
3140
3141         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3142         max_receive = (bus_options >> 12) & 0xf;
3143         link_speed = bus_options & 0x7;
3144         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3145                 reg_read(ohci, OHCI1394_GUIDLo);
3146
3147         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3148         if (err)
3149                 goto fail_self_id;
3150
3151         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3152         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3153                   "%d IR + %d IT contexts, quirks 0x%x\n",
3154                   dev_name(&dev->dev), version >> 16, version & 0xff,
3155                   n_ir, n_it, ohci->quirks);
3156
3157         return 0;
3158
3159  fail_self_id:
3160         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3161                           ohci->self_id_cpu, ohci->self_id_bus);
3162  fail_contexts:
3163         kfree(ohci->ir_context_list);
3164         kfree(ohci->it_context_list);
3165         context_release(&ohci->at_response_ctx);
3166         context_release(&ohci->at_request_ctx);
3167         ar_context_release(&ohci->ar_response_ctx);
3168  fail_arreq_ctx:
3169         ar_context_release(&ohci->ar_request_ctx);
3170  fail_iounmap:
3171         pci_iounmap(dev, ohci->registers);
3172  fail_iomem:
3173         pci_release_region(dev, 0);
3174  fail_disable:
3175         pci_disable_device(dev);
3176  fail_free:
3177         kfree(&ohci->card);
3178         pmac_ohci_off(dev);
3179  fail:
3180         if (err == -ENOMEM)
3181                 fw_error("Out of memory\n");
3182
3183         return err;
3184 }
3185
3186 static void pci_remove(struct pci_dev *dev)
3187 {
3188         struct fw_ohci *ohci;
3189
3190         ohci = pci_get_drvdata(dev);
3191         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3192         flush_writes(ohci);
3193         fw_core_remove_card(&ohci->card);
3194
3195         /*
3196          * FIXME: Fail all pending packets here, now that the upper
3197          * layers can't queue any more.
3198          */
3199
3200         software_reset(ohci);
3201         free_irq(dev->irq, ohci);
3202
3203         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3204                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3205                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3206         if (ohci->config_rom)
3207                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3208                                   ohci->config_rom, ohci->config_rom_bus);
3209         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3210                           ohci->self_id_cpu, ohci->self_id_bus);
3211         ar_context_release(&ohci->ar_request_ctx);
3212         ar_context_release(&ohci->ar_response_ctx);
3213         context_release(&ohci->at_request_ctx);
3214         context_release(&ohci->at_response_ctx);
3215         kfree(ohci->it_context_list);
3216         kfree(ohci->ir_context_list);
3217         pci_disable_msi(dev);
3218         pci_iounmap(dev, ohci->registers);
3219         pci_release_region(dev, 0);
3220         pci_disable_device(dev);
3221         kfree(&ohci->card);
3222         pmac_ohci_off(dev);
3223
3224         fw_notify("Removed fw-ohci device.\n");
3225 }
3226
3227 #ifdef CONFIG_PM
3228 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3229 {
3230         struct fw_ohci *ohci = pci_get_drvdata(dev);
3231         int err;
3232
3233         software_reset(ohci);
3234         free_irq(dev->irq, ohci);
3235         pci_disable_msi(dev);
3236         err = pci_save_state(dev);
3237         if (err) {
3238                 fw_error("pci_save_state failed\n");
3239                 return err;
3240         }
3241         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3242         if (err)
3243                 fw_error("pci_set_power_state failed with %d\n", err);
3244         pmac_ohci_off(dev);
3245
3246         return 0;
3247 }
3248
3249 static int pci_resume(struct pci_dev *dev)
3250 {
3251         struct fw_ohci *ohci = pci_get_drvdata(dev);
3252         int err;
3253
3254         pmac_ohci_on(dev);
3255         pci_set_power_state(dev, PCI_D0);
3256         pci_restore_state(dev);
3257         err = pci_enable_device(dev);
3258         if (err) {
3259                 fw_error("pci_enable_device failed\n");
3260                 return err;
3261         }
3262
3263         return ohci_enable(&ohci->card, NULL, 0);
3264 }
3265 #endif
3266
3267 static const struct pci_device_id pci_table[] = {
3268         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3269         { }
3270 };
3271
3272 MODULE_DEVICE_TABLE(pci, pci_table);
3273
3274 static struct pci_driver fw_ohci_pci_driver = {
3275         .name           = ohci_driver_name,
3276         .id_table       = pci_table,
3277         .probe          = pci_probe,
3278         .remove         = pci_remove,
3279 #ifdef CONFIG_PM
3280         .resume         = pci_resume,
3281         .suspend        = pci_suspend,
3282 #endif
3283 };
3284
3285 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3286 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3287 MODULE_LICENSE("GPL");
3288
3289 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3290 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3291 MODULE_ALIAS("ohci1394");
3292 #endif
3293
3294 static int __init fw_ohci_init(void)
3295 {
3296         return pci_register_driver(&fw_ohci_pci_driver);
3297 }
3298
3299 static void __exit fw_ohci_cleanup(void)
3300 {
3301         pci_unregister_driver(&fw_ohci_pci_driver);
3302 }
3303
3304 module_init(fw_ohci_init);
3305 module_exit(fw_ohci_cleanup);