drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49 #include <asm/system.h>
  50
  51 #ifdef CONFIG_PPC_PMAC
  52 #include <asm/pmac_feature.h>
  53 #endif
  54
  55 #include "core.h"
  56 #include "ohci.h"
  57
  58 #define DESCRIPTOR_OUTPUT_MORE          0
  59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  62 #define DESCRIPTOR_STATUS               (1 << 11)
  63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  64 #define DESCRIPTOR_PING                 (1 << 7)
  65 #define DESCRIPTOR_YY                   (1 << 6)
  66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  70 #define DESCRIPTOR_WAIT                 (3 << 0)
  71
  72 struct descriptor {
  73         __le16 req_count;
  74         __le16 control;
  75         __le32 data_address;
  76         __le32 branch_address;
  77         __le16 res_count;
  78         __le16 transfer_status;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 #define AR_BUFFER_SIZE  (32*1024)
  87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  88 /* we need at least two pages for proper list management */
  89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  90
  91 #define MAX_ASYNC_PAYLOAD       4096
  92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  94
  95 struct ar_context {
  96         struct fw_ohci *ohci;
  97         struct page *pages[AR_BUFFERS];
  98         void *buffer;
  99         struct descriptor *descriptors;
 100         dma_addr_t descriptors_bus;
 101         void *pointer;
 102         unsigned int last_buffer_index;
 103         u32 regs;
 104         struct tasklet_struct tasklet;
 105 };
 106
 107 struct context;
 108
 109 typedef int (*descriptor_callback_t)(struct context *ctx,
 110                                      struct descriptor *d,
 111                                      struct descriptor *last);
 112
 113 /*
 114  * A buffer that contains a block of DMA-able coherent memory used for
 115  * storing a portion of a DMA descriptor program.
 116  */
 117 struct descriptor_buffer {
 118         struct list_head list;
 119         dma_addr_t buffer_bus;
 120         size_t buffer_size;
 121         size_t used;
 122         struct descriptor buffer[0];
 123 };
 124
 125 struct context {
 126         struct fw_ohci *ohci;
 127         u32 regs;
 128         int total_allocation;
 129         u32 current_bus;
 130         bool running;
 131         bool flushing;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor in the DMA program.  It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157
 158         descriptor_callback_t callback;
 159
 160         struct tasklet_struct tasklet;
 161 };
 162
 163 #define IT_HEADER_SY(v)          ((v) <<  0)
 164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 166 #define IT_HEADER_TAG(v)         ((v) << 14)
 167 #define IT_HEADER_SPEED(v)       ((v) << 16)
 168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 169
 170 struct iso_context {
 171         struct fw_iso_context base;
 172         struct context context;
 173         int excess_bytes;
 174         void *header;
 175         size_t header_length;
 176
 177         u8 sync;
 178         u8 tags;
 179 };
 180
 181 #define CONFIG_ROM_SIZE 1024
 182
 183 struct fw_ohci {
 184         struct fw_card card;
 185
 186         __iomem char *registers;
 187         int node_id;
 188         int generation;
 189         int request_generation; /* for timestamping incoming requests */
 190         unsigned quirks;
 191         unsigned int pri_req_max;
 192         u32 bus_time;
 193         bool is_root;
 194         bool csr_state_setclear_abdicate;
 195         int n_ir;
 196         int n_it;
 197         /*
 198          * Spinlock for accessing fw_ohci data.  Never call out of
 199          * this driver with this lock held.
 200          */
 201         spinlock_t lock;
 202
 203         struct mutex phy_reg_mutex;
 204
 205         void *misc_buffer;
 206         dma_addr_t misc_buffer_bus;
 207
 208         struct ar_context ar_request_ctx;
 209         struct ar_context ar_response_ctx;
 210         struct context at_request_ctx;
 211         struct context at_response_ctx;
 212
 213         u32 it_context_support;
 214         u32 it_context_mask;     /* unoccupied IT contexts */
 215         struct iso_context *it_context_list;
 216         u64 ir_context_channels; /* unoccupied channels */
 217         u32 ir_context_support;
 218         u32 ir_context_mask;     /* unoccupied IR contexts */
 219         struct iso_context *ir_context_list;
 220         u64 mc_channels; /* channels in use by the multichannel IR context */
 221         bool mc_allocated;
 222
 223         __be32    *config_rom;
 224         dma_addr_t config_rom_bus;
 225         __be32    *next_config_rom;
 226         dma_addr_t next_config_rom_bus;
 227         __be32     next_header;
 228
 229         __le32    *self_id_cpu;
 230         dma_addr_t self_id_bus;
 231         struct work_struct bus_reset_work;
 232
 233         u32 self_id_buffer[512];
 234 };
 235
 236 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 237 {
 238         return container_of(card, struct fw_ohci, card);
 239 }
 240
 241 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 242 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 243 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 244 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 245 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 246 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 247
 248 #define CONTEXT_RUN     0x8000
 249 #define CONTEXT_WAKE    0x1000
 250 #define CONTEXT_DEAD    0x0800
 251 #define CONTEXT_ACTIVE  0x0400
 252
 253 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 254 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 255 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 256
 257 #define OHCI1394_REGISTER_SIZE          0x800
 258 #define OHCI1394_PCI_HCI_Control        0x40
 259 #define SELF_ID_BUF_SIZE                0x800
 260 #define OHCI_TCODE_PHY_PACKET           0x0e
 261 #define OHCI_VERSION_1_1                0x010010
 262
 263 static char ohci_driver_name[] = KBUILD_MODNAME;
 264
 265 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 267 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 268 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 269 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 270 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 271
 272 #define QUIRK_CYCLE_TIMER               1
 273 #define QUIRK_RESET_PACKET              2
 274 #define QUIRK_BE_HEADERS                4
 275 #define QUIRK_NO_1394A                  8
 276 #define QUIRK_NO_MSI                    16
 277 #define QUIRK_TI_SLLZ059                32
 278
 279 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 280 static const struct {
 281         unsigned short vendor, device, revision, flags;
 282 } ohci_quirks[] = {
 283         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 284                 QUIRK_CYCLE_TIMER},
 285
 286         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 287                 QUIRK_BE_HEADERS},
 288
 289         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 290                 QUIRK_NO_MSI},
 291
 292         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 293                 QUIRK_NO_MSI},
 294
 295         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 296                 QUIRK_CYCLE_TIMER},
 297
 298         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 299                 QUIRK_NO_MSI},
 300
 301         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 302                 QUIRK_CYCLE_TIMER},
 303
 304         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 305                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 306
 307         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 308                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 309
 310         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 311                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 312
 313         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 314                 QUIRK_RESET_PACKET},
 315
 316         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 317                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 318 };
 319
 320 /* This overrides anything that was found in ohci_quirks[]. */
 321 static int param_quirks;
 322 module_param_named(quirks, param_quirks, int, 0644);
 323 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 324         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 325         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 326         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 327         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 328         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 329         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 330         ")");
 331
 332 #define OHCI_PARAM_DEBUG_AT_AR          1
 333 #define OHCI_PARAM_DEBUG_SELFIDS        2
 334 #define OHCI_PARAM_DEBUG_IRQS           4
 335 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 336
 337 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 338
 339 static int param_debug;
 340 module_param_named(debug, param_debug, int, 0644);
 341 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 342         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 343         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 344         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 345         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 346         ", or a combination, or all = -1)");
 347
 348 static void log_irqs(u32 evt)
 349 {
 350         if (likely(!(param_debug &
 351                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 352                 return;
 353
 354         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 355             !(evt & OHCI1394_busReset))
 356                 return;
 357
 358         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 359             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 360             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 361             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 362             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 363             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 364             evt & OHCI1394_isochRx              ? " IR"                 : "",
 365             evt & OHCI1394_isochTx              ? " IT"                 : "",
 366             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 367             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 368             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 369             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 370             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 371             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 372             evt & OHCI1394_busReset             ? " busReset"           : "",
 373             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 374                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 375                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 376                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 377                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 378                     OHCI1394_cycleInconsistent |
 379                     OHCI1394_regAccessFail | OHCI1394_busReset)
 380                                                 ? " ?"                  : "");
 381 }
 382
 383 static const char *speed[] = {
 384         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 385 };
 386 static const char *power[] = {
 387         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 388         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 389 };
 390 static const char port[] = { '.', '-', 'p', 'c', };
 391
 392 static char _p(u32 *s, int shift)
 393 {
 394         return port[*s >> shift & 3];
 395 }
 396
 397 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 398 {
 399         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 400                 return;
 401
 402         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 403                   self_id_count, generation, node_id);
 404
 405         for (; self_id_count--; ++s)
 406                 if ((*s & 1 << 23) == 0)
 407                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 408                             "%s gc=%d %s %s%s%s\n",
 409                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 410                             speed[*s >> 14 & 3], *s >> 16 & 63,
 411                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 412                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 413                 else
 414                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 415                             *s, *s >> 24 & 63,
 416                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 417                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 418 }
 419
 420 static const char *evts[] = {
 421         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 422         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 423         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 424         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 425         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 426         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 427         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 428         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 429         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 430         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 431         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 432         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 433         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 434         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 435         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 436         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 437         [0x20] = "pending/cancelled",
 438 };
 439 static const char *tcodes[] = {
 440         [0x0] = "QW req",               [0x1] = "BW req",
 441         [0x2] = "W resp",               [0x3] = "-reserved-",
 442         [0x4] = "QR req",               [0x5] = "BR req",
 443         [0x6] = "QR resp",              [0x7] = "BR resp",
 444         [0x8] = "cycle start",          [0x9] = "Lk req",
 445         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 446         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 447         [0xe] = "link internal",        [0xf] = "-reserved-",
 448 };
 449
 450 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 451 {
 452         int tcode = header[0] >> 4 & 0xf;
 453         char specific[12];
 454
 455         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 456                 return;
 457
 458         if (unlikely(evt >= ARRAY_SIZE(evts)))
 459                         evt = 0x1f;
 460
 461         if (evt == OHCI1394_evt_bus_reset) {
 462                 fw_notify("A%c evt_bus_reset, generation %d\n",
 463                     dir, (header[2] >> 16) & 0xff);
 464                 return;
 465         }
 466
 467         switch (tcode) {
 468         case 0x0: case 0x6: case 0x8:
 469                 snprintf(specific, sizeof(specific), " = %08x",
 470                          be32_to_cpu((__force __be32)header[3]));
 471                 break;
 472         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 473                 snprintf(specific, sizeof(specific), " %x,%x",
 474                          header[3] >> 16, header[3] & 0xffff);
 475                 break;
 476         default:
 477                 specific[0] = '\0';
 478         }
 479
 480         switch (tcode) {
 481         case 0xa:
 482                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 483                 break;
 484         case 0xe:
 485                 fw_notify("A%c %s, PHY %08x %08x\n",
 486                           dir, evts[evt], header[1], header[2]);
 487                 break;
 488         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 489                 fw_notify("A%c spd %x tl %02x, "
 490                     "%04x -> %04x, %s, "
 491                     "%s, %04x%08x%s\n",
 492                     dir, speed, header[0] >> 10 & 0x3f,
 493                     header[1] >> 16, header[0] >> 16, evts[evt],
 494                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 495                 break;
 496         default:
 497                 fw_notify("A%c spd %x tl %02x, "
 498                     "%04x -> %04x, %s, "
 499                     "%s%s\n",
 500                     dir, speed, header[0] >> 10 & 0x3f,
 501                     header[1] >> 16, header[0] >> 16, evts[evt],
 502                     tcodes[tcode], specific);
 503         }
 504 }
 505
 506 #else
 507
 508 #define param_debug 0
 509 static inline void log_irqs(u32 evt) {}
 510 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 511 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 512
 513 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 514
 515 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 516 {
 517         writel(data, ohci->registers + offset);
 518 }
 519
 520 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 521 {
 522         return readl(ohci->registers + offset);
 523 }
 524
 525 static inline void flush_writes(const struct fw_ohci *ohci)
 526 {
 527         /* Do a dummy read to flush writes. */
 528         reg_read(ohci, OHCI1394_Version);
 529 }
 530
 531 /*
 532  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 533  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 534  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 535  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 536  */
 537 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 538 {
 539         u32 val;
 540         int i;
 541
 542         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 543         for (i = 0; i < 3 + 100; i++) {
 544                 val = reg_read(ohci, OHCI1394_PhyControl);
 545                 if (!~val)
 546                         return -ENODEV; /* Card was ejected. */
 547
 548                 if (val & OHCI1394_PhyControl_ReadDone)
 549                         return OHCI1394_PhyControl_ReadData(val);
 550
 551                 /*
 552                  * Try a few times without waiting.  Sleeping is necessary
 553                  * only when the link/PHY interface is busy.
 554                  */
 555                 if (i >= 3)
 556                         msleep(1);
 557         }
 558         fw_error("failed to read phy reg\n");
 559
 560         return -EBUSY;
 561 }
 562
 563 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 564 {
 565         int i;
 566
 567         reg_write(ohci, OHCI1394_PhyControl,
 568                   OHCI1394_PhyControl_Write(addr, val));
 569         for (i = 0; i < 3 + 100; i++) {
 570                 val = reg_read(ohci, OHCI1394_PhyControl);
 571                 if (!~val)
 572                         return -ENODEV; /* Card was ejected. */
 573
 574                 if (!(val & OHCI1394_PhyControl_WritePending))
 575                         return 0;
 576
 577                 if (i >= 3)
 578                         msleep(1);
 579         }
 580         fw_error("failed to write phy reg\n");
 581
 582         return -EBUSY;
 583 }
 584
 585 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 586                           int clear_bits, int set_bits)
 587 {
 588         int ret = read_phy_reg(ohci, addr);
 589         if (ret < 0)
 590                 return ret;
 591
 592         /*
 593          * The interrupt status bits are cleared by writing a one bit.
 594          * Avoid clearing them unless explicitly requested in set_bits.
 595          */
 596         if (addr == 5)
 597                 clear_bits |= PHY_INT_STATUS_BITS;
 598
 599         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 600 }
 601
 602 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 603 {
 604         int ret;
 605
 606         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 607         if (ret < 0)
 608                 return ret;
 609
 610         return read_phy_reg(ohci, addr);
 611 }
 612
 613 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 614 {
 615         struct fw_ohci *ohci = fw_ohci(card);
 616         int ret;
 617
 618         mutex_lock(&ohci->phy_reg_mutex);
 619         ret = read_phy_reg(ohci, addr);
 620         mutex_unlock(&ohci->phy_reg_mutex);
 621
 622         return ret;
 623 }
 624
 625 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 626                                int clear_bits, int set_bits)
 627 {
 628         struct fw_ohci *ohci = fw_ohci(card);
 629         int ret;
 630
 631         mutex_lock(&ohci->phy_reg_mutex);
 632         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 633         mutex_unlock(&ohci->phy_reg_mutex);
 634
 635         return ret;
 636 }
 637
 638 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 639 {
 640         return page_private(ctx->pages[i]);
 641 }
 642
 643 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 644 {
 645         struct descriptor *d;
 646
 647         d = &ctx->descriptors[index];
 648         d->branch_address  &= cpu_to_le32(~0xf);
 649         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 650         d->transfer_status =  0;
 651
 652         wmb(); /* finish init of new descriptors before branch_address update */
 653         d = &ctx->descriptors[ctx->last_buffer_index];
 654         d->branch_address  |= cpu_to_le32(1);
 655
 656         ctx->last_buffer_index = index;
 657
 658         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 659 }
 660
 661 static void ar_context_release(struct ar_context *ctx)
 662 {
 663         unsigned int i;
 664
 665         if (ctx->buffer)
 666                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 667
 668         for (i = 0; i < AR_BUFFERS; i++)
 669                 if (ctx->pages[i]) {
 670                         dma_unmap_page(ctx->ohci->card.device,
 671                                        ar_buffer_bus(ctx, i),
 672                                        PAGE_SIZE, DMA_FROM_DEVICE);
 673                         __free_page(ctx->pages[i]);
 674                 }
 675 }
 676
 677 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 678 {
 679         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 680                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 681                 flush_writes(ctx->ohci);
 682
 683                 fw_error("AR error: %s; DMA stopped\n", error_msg);
 684         }
 685         /* FIXME: restart? */
 686 }
 687
 688 static inline unsigned int ar_next_buffer_index(unsigned int index)
 689 {
 690         return (index + 1) % AR_BUFFERS;
 691 }
 692
 693 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 694 {
 695         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 696 }
 697
 698 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 699 {
 700         return ar_next_buffer_index(ctx->last_buffer_index);
 701 }
 702
 703 /*
 704  * We search for the buffer that contains the last AR packet DMA data written
 705  * by the controller.
 706  */
 707 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 708                                                  unsigned int *buffer_offset)
 709 {
 710         unsigned int i, next_i, last = ctx->last_buffer_index;
 711         __le16 res_count, next_res_count;
 712
 713         i = ar_first_buffer_index(ctx);
 714         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 715
 716         /* A buffer that is not yet completely filled must be the last one. */
 717         while (i != last && res_count == 0) {
 718
 719                 /* Peek at the next descriptor. */
 720                 next_i = ar_next_buffer_index(i);
 721                 rmb(); /* read descriptors in order */
 722                 next_res_count = ACCESS_ONCE(
 723                                 ctx->descriptors[next_i].res_count);
 724                 /*
 725                  * If the next descriptor is still empty, we must stop at this
 726                  * descriptor.
 727                  */
 728                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 729                         /*
 730                          * The exception is when the DMA data for one packet is
 731                          * split over three buffers; in this case, the middle
 732                          * buffer's descriptor might be never updated by the
 733                          * controller and look still empty, and we have to peek
 734                          * at the third one.
 735                          */
 736                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 737                                 next_i = ar_next_buffer_index(next_i);
 738                                 rmb();
 739                                 next_res_count = ACCESS_ONCE(
 740                                         ctx->descriptors[next_i].res_count);
 741                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 742                                         goto next_buffer_is_active;
 743                         }
 744
 745                         break;
 746                 }
 747
 748 next_buffer_is_active:
 749                 i = next_i;
 750                 res_count = next_res_count;
 751         }
 752
 753         rmb(); /* read res_count before the DMA data */
 754
 755         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 756         if (*buffer_offset > PAGE_SIZE) {
 757                 *buffer_offset = 0;
 758                 ar_context_abort(ctx, "corrupted descriptor");
 759         }
 760
 761         return i;
 762 }
 763
 764 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 765                                     unsigned int end_buffer_index,
 766                                     unsigned int end_buffer_offset)
 767 {
 768         unsigned int i;
 769
 770         i = ar_first_buffer_index(ctx);
 771         while (i != end_buffer_index) {
 772                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 773                                         ar_buffer_bus(ctx, i),
 774                                         PAGE_SIZE, DMA_FROM_DEVICE);
 775                 i = ar_next_buffer_index(i);
 776         }
 777         if (end_buffer_offset > 0)
 778                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 779                                         ar_buffer_bus(ctx, i),
 780                                         end_buffer_offset, DMA_FROM_DEVICE);
 781 }
 782
 783 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 784 #define cond_le32_to_cpu(v) \
 785         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 786 #else
 787 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 788 #endif
 789
 790 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 791 {
 792         struct fw_ohci *ohci = ctx->ohci;
 793         struct fw_packet p;
 794         u32 status, length, tcode;
 795         int evt;
 796
 797         p.header[0] = cond_le32_to_cpu(buffer[0]);
 798         p.header[1] = cond_le32_to_cpu(buffer[1]);
 799         p.header[2] = cond_le32_to_cpu(buffer[2]);
 800
 801         tcode = (p.header[0] >> 4) & 0x0f;
 802         switch (tcode) {
 803         case TCODE_WRITE_QUADLET_REQUEST:
 804         case TCODE_READ_QUADLET_RESPONSE:
 805                 p.header[3] = (__force __u32) buffer[3];
 806                 p.header_length = 16;
 807                 p.payload_length = 0;
 808                 break;
 809
 810         case TCODE_READ_BLOCK_REQUEST :
 811                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 812                 p.header_length = 16;
 813                 p.payload_length = 0;
 814                 break;
 815
 816         case TCODE_WRITE_BLOCK_REQUEST:
 817         case TCODE_READ_BLOCK_RESPONSE:
 818         case TCODE_LOCK_REQUEST:
 819         case TCODE_LOCK_RESPONSE:
 820                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 821                 p.header_length = 16;
 822                 p.payload_length = p.header[3] >> 16;
 823                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 824                         ar_context_abort(ctx, "invalid packet length");
 825                         return NULL;
 826                 }
 827                 break;
 828
 829         case TCODE_WRITE_RESPONSE:
 830         case TCODE_READ_QUADLET_REQUEST:
 831         case OHCI_TCODE_PHY_PACKET:
 832                 p.header_length = 12;
 833                 p.payload_length = 0;
 834                 break;
 835
 836         default:
 837                 ar_context_abort(ctx, "invalid tcode");
 838                 return NULL;
 839         }
 840
 841         p.payload = (void *) buffer + p.header_length;
 842
 843         /* FIXME: What to do about evt_* errors? */
 844         length = (p.header_length + p.payload_length + 3) / 4;
 845         status = cond_le32_to_cpu(buffer[length]);
 846         evt    = (status >> 16) & 0x1f;
 847
 848         p.ack        = evt - 16;
 849         p.speed      = (status >> 21) & 0x7;
 850         p.timestamp  = status & 0xffff;
 851         p.generation = ohci->request_generation;
 852
 853         log_ar_at_event('R', p.speed, p.header, evt);
 854
 855         /*
 856          * Several controllers, notably from NEC and VIA, forget to
 857          * write ack_complete status at PHY packet reception.
 858          */
 859         if (evt == OHCI1394_evt_no_status &&
 860             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 861                 p.ack = ACK_COMPLETE;
 862
 863         /*
 864          * The OHCI bus reset handler synthesizes a PHY packet with
 865          * the new generation number when a bus reset happens (see
 866          * section 8.4.2.3).  This helps us determine when a request
 867          * was received and make sure we send the response in the same
 868          * generation.  We only need this for requests; for responses
 869          * we use the unique tlabel for finding the matching
 870          * request.
 871          *
 872          * Alas some chips sometimes emit bus reset packets with a
 873          * wrong generation.  We set the correct generation for these
 874          * at a slightly incorrect time (in bus_reset_work).
 875          */
 876         if (evt == OHCI1394_evt_bus_reset) {
 877                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 878                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 879         } else if (ctx == &ohci->ar_request_ctx) {
 880                 fw_core_handle_request(&ohci->card, &p);
 881         } else {
 882                 fw_core_handle_response(&ohci->card, &p);
 883         }
 884
 885         return buffer + length + 1;
 886 }
 887
 888 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 889 {
 890         void *next;
 891
 892         while (p < end) {
 893                 next = handle_ar_packet(ctx, p);
 894                 if (!next)
 895                         return p;
 896                 p = next;
 897         }
 898
 899         return p;
 900 }
 901
 902 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 903 {
 904         unsigned int i;
 905
 906         i = ar_first_buffer_index(ctx);
 907         while (i != end_buffer) {
 908                 dma_sync_single_for_device(ctx->ohci->card.device,
 909                                            ar_buffer_bus(ctx, i),
 910                                            PAGE_SIZE, DMA_FROM_DEVICE);
 911                 ar_context_link_page(ctx, i);
 912                 i = ar_next_buffer_index(i);
 913         }
 914 }
 915
 916 static void ar_context_tasklet(unsigned long data)
 917 {
 918         struct ar_context *ctx = (struct ar_context *)data;
 919         unsigned int end_buffer_index, end_buffer_offset;
 920         void *p, *end;
 921
 922         p = ctx->pointer;
 923         if (!p)
 924                 return;
 925
 926         end_buffer_index = ar_search_last_active_buffer(ctx,
 927                                                         &end_buffer_offset);
 928         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 929         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 930
 931         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 932                 /*
 933                  * The filled part of the overall buffer wraps around; handle
 934                  * all packets up to the buffer end here.  If the last packet
 935                  * wraps around, its tail will be visible after the buffer end
 936                  * because the buffer start pages are mapped there again.
 937                  */
 938                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 939                 p = handle_ar_packets(ctx, p, buffer_end);
 940                 if (p < buffer_end)
 941                         goto error;
 942                 /* adjust p to point back into the actual buffer */
 943                 p -= AR_BUFFERS * PAGE_SIZE;
 944         }
 945
 946         p = handle_ar_packets(ctx, p, end);
 947         if (p != end) {
 948                 if (p > end)
 949                         ar_context_abort(ctx, "inconsistent descriptor");
 950                 goto error;
 951         }
 952
 953         ctx->pointer = p;
 954         ar_recycle_buffers(ctx, end_buffer_index);
 955
 956         return;
 957
 958 error:
 959         ctx->pointer = NULL;
 960 }
 961
 962 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 963                            unsigned int descriptors_offset, u32 regs)
 964 {
 965         unsigned int i;
 966         dma_addr_t dma_addr;
 967         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 968         struct descriptor *d;
 969
 970         ctx->regs        = regs;
 971         ctx->ohci        = ohci;
 972         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 973
 974         for (i = 0; i < AR_BUFFERS; i++) {
 975                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 976                 if (!ctx->pages[i])
 977                         goto out_of_memory;
 978                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 979                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 980                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 981                         __free_page(ctx->pages[i]);
 982                         ctx->pages[i] = NULL;
 983                         goto out_of_memory;
 984                 }
 985                 set_page_private(ctx->pages[i], dma_addr);
 986         }
 987
 988         for (i = 0; i < AR_BUFFERS; i++)
 989                 pages[i]              = ctx->pages[i];
 990         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 991                 pages[AR_BUFFERS + i] = ctx->pages[i];
 992         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 993                                  -1, PAGE_KERNEL);
 994         if (!ctx->buffer)
 995                 goto out_of_memory;
 996
 997         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
 998         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
 999
1000         for (i = 0; i < AR_BUFFERS; i++) {
1001                 d = &ctx->descriptors[i];
1002                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1003                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1004                                                 DESCRIPTOR_STATUS |
1005                                                 DESCRIPTOR_BRANCH_ALWAYS);
1006                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1007                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1008                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1009         }
1010
1011         return 0;
1012
1013 out_of_memory:
1014         ar_context_release(ctx);
1015
1016         return -ENOMEM;
1017 }
1018
1019 static void ar_context_run(struct ar_context *ctx)
1020 {
1021         unsigned int i;
1022
1023         for (i = 0; i < AR_BUFFERS; i++)
1024                 ar_context_link_page(ctx, i);
1025
1026         ctx->pointer = ctx->buffer;
1027
1028         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1029         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1030 }
1031
1032 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1033 {
1034         __le16 branch;
1035
1036         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1037
1038         /* figure out which descriptor the branch address goes in */
1039         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1040                 return d;
1041         else
1042                 return d + z - 1;
1043 }
1044
1045 static void context_tasklet(unsigned long data)
1046 {
1047         struct context *ctx = (struct context *) data;
1048         struct descriptor *d, *last;
1049         u32 address;
1050         int z;
1051         struct descriptor_buffer *desc;
1052
1053         desc = list_entry(ctx->buffer_list.next,
1054                         struct descriptor_buffer, list);
1055         last = ctx->last;
1056         while (last->branch_address != 0) {
1057                 struct descriptor_buffer *old_desc = desc;
1058                 address = le32_to_cpu(last->branch_address);
1059                 z = address & 0xf;
1060                 address &= ~0xf;
1061                 ctx->current_bus = address;
1062
1063                 /* If the branch address points to a buffer outside of the
1064                  * current buffer, advance to the next buffer. */
1065                 if (address < desc->buffer_bus ||
1066                                 address >= desc->buffer_bus + desc->used)
1067                         desc = list_entry(desc->list.next,
1068                                         struct descriptor_buffer, list);
1069                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1070                 last = find_branch_descriptor(d, z);
1071
1072                 if (!ctx->callback(ctx, d, last))
1073                         break;
1074
1075                 if (old_desc != desc) {
1076                         /* If we've advanced to the next buffer, move the
1077                          * previous buffer to the free list. */
1078                         unsigned long flags;
1079                         old_desc->used = 0;
1080                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1081                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1082                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1083                 }
1084                 ctx->last = last;
1085         }
1086 }
1087
1088 /*
1089  * Allocate a new buffer and add it to the list of free buffers for this
1090  * context.  Must be called with ohci->lock held.
1091  */
1092 static int context_add_buffer(struct context *ctx)
1093 {
1094         struct descriptor_buffer *desc;
1095         dma_addr_t uninitialized_var(bus_addr);
1096         int offset;
1097
1098         /*
1099          * 16MB of descriptors should be far more than enough for any DMA
1100          * program.  This will catch run-away userspace or DoS attacks.
1101          */
1102         if (ctx->total_allocation >= 16*1024*1024)
1103                 return -ENOMEM;
1104
1105         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1106                         &bus_addr, GFP_ATOMIC);
1107         if (!desc)
1108                 return -ENOMEM;
1109
1110         offset = (void *)&desc->buffer - (void *)desc;
1111         desc->buffer_size = PAGE_SIZE - offset;
1112         desc->buffer_bus = bus_addr + offset;
1113         desc->used = 0;
1114
1115         list_add_tail(&desc->list, &ctx->buffer_list);
1116         ctx->total_allocation += PAGE_SIZE;
1117
1118         return 0;
1119 }
1120
1121 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1122                         u32 regs, descriptor_callback_t callback)
1123 {
1124         ctx->ohci = ohci;
1125         ctx->regs = regs;
1126         ctx->total_allocation = 0;
1127
1128         INIT_LIST_HEAD(&ctx->buffer_list);
1129         if (context_add_buffer(ctx) < 0)
1130                 return -ENOMEM;
1131
1132         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1133                         struct descriptor_buffer, list);
1134
1135         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1136         ctx->callback = callback;
1137
1138         /*
1139          * We put a dummy descriptor in the buffer that has a NULL
1140          * branch address and looks like it's been sent.  That way we
1141          * have a descriptor to append DMA programs to.
1142          */
1143         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1144         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1145         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1146         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1147         ctx->last = ctx->buffer_tail->buffer;
1148         ctx->prev = ctx->buffer_tail->buffer;
1149
1150         return 0;
1151 }
1152
1153 static void context_release(struct context *ctx)
1154 {
1155         struct fw_card *card = &ctx->ohci->card;
1156         struct descriptor_buffer *desc, *tmp;
1157
1158         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1159                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1160                         desc->buffer_bus -
1161                         ((void *)&desc->buffer - (void *)desc));
1162 }
1163
1164 /* Must be called with ohci->lock held */
1165 static struct descriptor *context_get_descriptors(struct context *ctx,
1166                                                   int z, dma_addr_t *d_bus)
1167 {
1168         struct descriptor *d = NULL;
1169         struct descriptor_buffer *desc = ctx->buffer_tail;
1170
1171         if (z * sizeof(*d) > desc->buffer_size)
1172                 return NULL;
1173
1174         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1175                 /* No room for the descriptor in this buffer, so advance to the
1176                  * next one. */
1177
1178                 if (desc->list.next == &ctx->buffer_list) {
1179                         /* If there is no free buffer next in the list,
1180                          * allocate one. */
1181                         if (context_add_buffer(ctx) < 0)
1182                                 return NULL;
1183                 }
1184                 desc = list_entry(desc->list.next,
1185                                 struct descriptor_buffer, list);
1186                 ctx->buffer_tail = desc;
1187         }
1188
1189         d = desc->buffer + desc->used / sizeof(*d);
1190         memset(d, 0, z * sizeof(*d));
1191         *d_bus = desc->buffer_bus + desc->used;
1192
1193         return d;
1194 }
1195
1196 static void context_run(struct context *ctx, u32 extra)
1197 {
1198         struct fw_ohci *ohci = ctx->ohci;
1199
1200         reg_write(ohci, COMMAND_PTR(ctx->regs),
1201                   le32_to_cpu(ctx->last->branch_address));
1202         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1203         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1204         ctx->running = true;
1205         flush_writes(ohci);
1206 }
1207
1208 static void context_append(struct context *ctx,
1209                            struct descriptor *d, int z, int extra)
1210 {
1211         dma_addr_t d_bus;
1212         struct descriptor_buffer *desc = ctx->buffer_tail;
1213
1214         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1215
1216         desc->used += (z + extra) * sizeof(*d);
1217
1218         wmb(); /* finish init of new descriptors before branch_address update */
1219         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1220         ctx->prev = find_branch_descriptor(d, z);
1221 }
1222
1223 static void context_stop(struct context *ctx)
1224 {
1225         u32 reg;
1226         int i;
1227
1228         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1229         ctx->running = false;
1230
1231         for (i = 0; i < 1000; i++) {
1232                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1233                 if ((reg & CONTEXT_ACTIVE) == 0)
1234                         return;
1235
1236                 if (i)
1237                         udelay(10);
1238         }
1239         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1240 }
1241
1242 struct driver_data {
1243         u8 inline_data[8];
1244         struct fw_packet *packet;
1245 };
1246
1247 /*
1248  * This function apppends a packet to the DMA queue for transmission.
1249  * Must always be called with the ochi->lock held to ensure proper
1250  * generation handling and locking around packet queue manipulation.
1251  */
1252 static int at_context_queue_packet(struct context *ctx,
1253                                    struct fw_packet *packet)
1254 {
1255         struct fw_ohci *ohci = ctx->ohci;
1256         dma_addr_t d_bus, uninitialized_var(payload_bus);
1257         struct driver_data *driver_data;
1258         struct descriptor *d, *last;
1259         __le32 *header;
1260         int z, tcode;
1261
1262         d = context_get_descriptors(ctx, 4, &d_bus);
1263         if (d == NULL) {
1264                 packet->ack = RCODE_SEND_ERROR;
1265                 return -1;
1266         }
1267
1268         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1269         d[0].res_count = cpu_to_le16(packet->timestamp);
1270
1271         /*
1272          * The DMA format for asyncronous link packets is different
1273          * from the IEEE1394 layout, so shift the fields around
1274          * accordingly.
1275          */
1276
1277         tcode = (packet->header[0] >> 4) & 0x0f;
1278         header = (__le32 *) &d[1];
1279         switch (tcode) {
1280         case TCODE_WRITE_QUADLET_REQUEST:
1281         case TCODE_WRITE_BLOCK_REQUEST:
1282         case TCODE_WRITE_RESPONSE:
1283         case TCODE_READ_QUADLET_REQUEST:
1284         case TCODE_READ_BLOCK_REQUEST:
1285         case TCODE_READ_QUADLET_RESPONSE:
1286         case TCODE_READ_BLOCK_RESPONSE:
1287         case TCODE_LOCK_REQUEST:
1288         case TCODE_LOCK_RESPONSE:
1289                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1290                                         (packet->speed << 16));
1291                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1292                                         (packet->header[0] & 0xffff0000));
1293                 header[2] = cpu_to_le32(packet->header[2]);
1294
1295                 if (TCODE_IS_BLOCK_PACKET(tcode))
1296                         header[3] = cpu_to_le32(packet->header[3]);
1297                 else
1298                         header[3] = (__force __le32) packet->header[3];
1299
1300                 d[0].req_count = cpu_to_le16(packet->header_length);
1301                 break;
1302
1303         case TCODE_LINK_INTERNAL:
1304                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1305                                         (packet->speed << 16));
1306                 header[1] = cpu_to_le32(packet->header[1]);
1307                 header[2] = cpu_to_le32(packet->header[2]);
1308                 d[0].req_count = cpu_to_le16(12);
1309
1310                 if (is_ping_packet(&packet->header[1]))
1311                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1312                 break;
1313
1314         case TCODE_STREAM_DATA:
1315                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1316                                         (packet->speed << 16));
1317                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1318                 d[0].req_count = cpu_to_le16(8);
1319                 break;
1320
1321         default:
1322                 /* BUG(); */
1323                 packet->ack = RCODE_SEND_ERROR;
1324                 return -1;
1325         }
1326
1327         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1328         driver_data = (struct driver_data *) &d[3];
1329         driver_data->packet = packet;
1330         packet->driver_data = driver_data;
1331
1332         if (packet->payload_length > 0) {
1333                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1334                         payload_bus = dma_map_single(ohci->card.device,
1335                                                      packet->payload,
1336                                                      packet->payload_length,
1337                                                      DMA_TO_DEVICE);
1338                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1339                                 packet->ack = RCODE_SEND_ERROR;
1340                                 return -1;
1341                         }
1342                         packet->payload_bus     = payload_bus;
1343                         packet->payload_mapped  = true;
1344                 } else {
1345                         memcpy(driver_data->inline_data, packet->payload,
1346                                packet->payload_length);
1347                         payload_bus = d_bus + 3 * sizeof(*d);
1348                 }
1349
1350                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1351                 d[2].data_address = cpu_to_le32(payload_bus);
1352                 last = &d[2];
1353                 z = 3;
1354         } else {
1355                 last = &d[0];
1356                 z = 2;
1357         }
1358
1359         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1360                                      DESCRIPTOR_IRQ_ALWAYS |
1361                                      DESCRIPTOR_BRANCH_ALWAYS);
1362
1363         /* FIXME: Document how the locking works. */
1364         if (ohci->generation != packet->generation) {
1365                 if (packet->payload_mapped)
1366                         dma_unmap_single(ohci->card.device, payload_bus,
1367                                          packet->payload_length, DMA_TO_DEVICE);
1368                 packet->ack = RCODE_GENERATION;
1369                 return -1;
1370         }
1371
1372         context_append(ctx, d, z, 4 - z);
1373
1374         if (ctx->running)
1375                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1376         else
1377                 context_run(ctx, 0);
1378
1379         return 0;
1380 }
1381
1382 static void at_context_flush(struct context *ctx)
1383 {
1384         tasklet_disable(&ctx->tasklet);
1385
1386         ctx->flushing = true;
1387         context_tasklet((unsigned long)ctx);
1388         ctx->flushing = false;
1389
1390         tasklet_enable(&ctx->tasklet);
1391 }
1392
1393 static int handle_at_packet(struct context *context,
1394                             struct descriptor *d,
1395                             struct descriptor *last)
1396 {
1397         struct driver_data *driver_data;
1398         struct fw_packet *packet;
1399         struct fw_ohci *ohci = context->ohci;
1400         int evt;
1401
1402         if (last->transfer_status == 0 && !context->flushing)
1403                 /* This descriptor isn't done yet, stop iteration. */
1404                 return 0;
1405
1406         driver_data = (struct driver_data *) &d[3];
1407         packet = driver_data->packet;
1408         if (packet == NULL)
1409                 /* This packet was cancelled, just continue. */
1410                 return 1;
1411
1412         if (packet->payload_mapped)
1413                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1414                                  packet->payload_length, DMA_TO_DEVICE);
1415
1416         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1417         packet->timestamp = le16_to_cpu(last->res_count);
1418
1419         log_ar_at_event('T', packet->speed, packet->header, evt);
1420
1421         switch (evt) {
1422         case OHCI1394_evt_timeout:
1423                 /* Async response transmit timed out. */
1424                 packet->ack = RCODE_CANCELLED;
1425                 break;
1426
1427         case OHCI1394_evt_flushed:
1428                 /*
1429                  * The packet was flushed should give same error as
1430                  * when we try to use a stale generation count.
1431                  */
1432                 packet->ack = RCODE_GENERATION;
1433                 break;
1434
1435         case OHCI1394_evt_missing_ack:
1436                 if (context->flushing)
1437                         packet->ack = RCODE_GENERATION;
1438                 else {
1439                         /*
1440                          * Using a valid (current) generation count, but the
1441                          * node is not on the bus or not sending acks.
1442                          */
1443                         packet->ack = RCODE_NO_ACK;
1444                 }
1445                 break;
1446
1447         case ACK_COMPLETE + 0x10:
1448         case ACK_PENDING + 0x10:
1449         case ACK_BUSY_X + 0x10:
1450         case ACK_BUSY_A + 0x10:
1451         case ACK_BUSY_B + 0x10:
1452         case ACK_DATA_ERROR + 0x10:
1453         case ACK_TYPE_ERROR + 0x10:
1454                 packet->ack = evt - 0x10;
1455                 break;
1456
1457         case OHCI1394_evt_no_status:
1458                 if (context->flushing) {
1459                         packet->ack = RCODE_GENERATION;
1460                         break;
1461                 }
1462                 /* fall through */
1463
1464         default:
1465                 packet->ack = RCODE_SEND_ERROR;
1466                 break;
1467         }
1468
1469         packet->callback(packet, &ohci->card, packet->ack);
1470
1471         return 1;
1472 }
1473
1474 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1475 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1476 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1477 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1478 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1479
1480 static void handle_local_rom(struct fw_ohci *ohci,
1481                              struct fw_packet *packet, u32 csr)
1482 {
1483         struct fw_packet response;
1484         int tcode, length, i;
1485
1486         tcode = HEADER_GET_TCODE(packet->header[0]);
1487         if (TCODE_IS_BLOCK_PACKET(tcode))
1488                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1489         else
1490                 length = 4;
1491
1492         i = csr - CSR_CONFIG_ROM;
1493         if (i + length > CONFIG_ROM_SIZE) {
1494                 fw_fill_response(&response, packet->header,
1495                                  RCODE_ADDRESS_ERROR, NULL, 0);
1496         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1497                 fw_fill_response(&response, packet->header,
1498                                  RCODE_TYPE_ERROR, NULL, 0);
1499         } else {
1500                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1501                                  (void *) ohci->config_rom + i, length);
1502         }
1503
1504         fw_core_handle_response(&ohci->card, &response);
1505 }
1506
1507 static void handle_local_lock(struct fw_ohci *ohci,
1508                               struct fw_packet *packet, u32 csr)
1509 {
1510         struct fw_packet response;
1511         int tcode, length, ext_tcode, sel, try;
1512         __be32 *payload, lock_old;
1513         u32 lock_arg, lock_data;
1514
1515         tcode = HEADER_GET_TCODE(packet->header[0]);
1516         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1517         payload = packet->payload;
1518         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1519
1520         if (tcode == TCODE_LOCK_REQUEST &&
1521             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1522                 lock_arg = be32_to_cpu(payload[0]);
1523                 lock_data = be32_to_cpu(payload[1]);
1524         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1525                 lock_arg = 0;
1526                 lock_data = 0;
1527         } else {
1528                 fw_fill_response(&response, packet->header,
1529                                  RCODE_TYPE_ERROR, NULL, 0);
1530                 goto out;
1531         }
1532
1533         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1534         reg_write(ohci, OHCI1394_CSRData, lock_data);
1535         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1536         reg_write(ohci, OHCI1394_CSRControl, sel);
1537
1538         for (try = 0; try < 20; try++)
1539                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1540                         lock_old = cpu_to_be32(reg_read(ohci,
1541                                                         OHCI1394_CSRData));
1542                         fw_fill_response(&response, packet->header,
1543                                          RCODE_COMPLETE,
1544                                          &lock_old, sizeof(lock_old));
1545                         goto out;
1546                 }
1547
1548         fw_error("swap not done (CSR lock timeout)\n");
1549         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1550
1551  out:
1552         fw_core_handle_response(&ohci->card, &response);
1553 }
1554
1555 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1556 {
1557         u64 offset, csr;
1558
1559         if (ctx == &ctx->ohci->at_request_ctx) {
1560                 packet->ack = ACK_PENDING;
1561                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1562         }
1563
1564         offset =
1565                 ((unsigned long long)
1566                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1567                 packet->header[2];
1568         csr = offset - CSR_REGISTER_BASE;
1569
1570         /* Handle config rom reads. */
1571         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1572                 handle_local_rom(ctx->ohci, packet, csr);
1573         else switch (csr) {
1574         case CSR_BUS_MANAGER_ID:
1575         case CSR_BANDWIDTH_AVAILABLE:
1576         case CSR_CHANNELS_AVAILABLE_HI:
1577         case CSR_CHANNELS_AVAILABLE_LO:
1578                 handle_local_lock(ctx->ohci, packet, csr);
1579                 break;
1580         default:
1581                 if (ctx == &ctx->ohci->at_request_ctx)
1582                         fw_core_handle_request(&ctx->ohci->card, packet);
1583                 else
1584                         fw_core_handle_response(&ctx->ohci->card, packet);
1585                 break;
1586         }
1587
1588         if (ctx == &ctx->ohci->at_response_ctx) {
1589                 packet->ack = ACK_COMPLETE;
1590                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1591         }
1592 }
1593
1594 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1595 {
1596         unsigned long flags;
1597         int ret;
1598
1599         spin_lock_irqsave(&ctx->ohci->lock, flags);
1600
1601         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1602             ctx->ohci->generation == packet->generation) {
1603                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1604                 handle_local_request(ctx, packet);
1605                 return;
1606         }
1607
1608         ret = at_context_queue_packet(ctx, packet);
1609         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1610
1611         if (ret < 0)
1612                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1613
1614 }
1615
1616 static void detect_dead_context(struct fw_ohci *ohci,
1617                                 const char *name, unsigned int regs)
1618 {
1619         u32 ctl;
1620
1621         ctl = reg_read(ohci, CONTROL_SET(regs));
1622         if (ctl & CONTEXT_DEAD) {
1623 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1624                 fw_error("DMA context %s has stopped, error code: %s\n",
1625                          name, evts[ctl & 0x1f]);
1626 #else
1627                 fw_error("DMA context %s has stopped, error code: %#x\n",
1628                          name, ctl & 0x1f);
1629 #endif
1630         }
1631 }
1632
1633 static void handle_dead_contexts(struct fw_ohci *ohci)
1634 {
1635         unsigned int i;
1636         char name[8];
1637
1638         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1639         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1640         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1641         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1642         for (i = 0; i < 32; ++i) {
1643                 if (!(ohci->it_context_support & (1 << i)))
1644                         continue;
1645                 sprintf(name, "IT%u", i);
1646                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1647         }
1648         for (i = 0; i < 32; ++i) {
1649                 if (!(ohci->ir_context_support & (1 << i)))
1650                         continue;
1651                 sprintf(name, "IR%u", i);
1652                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1653         }
1654         /* TODO: maybe try to flush and restart the dead contexts */
1655 }
1656
1657 static u32 cycle_timer_ticks(u32 cycle_timer)
1658 {
1659         u32 ticks;
1660
1661         ticks = cycle_timer & 0xfff;
1662         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1663         ticks += (3072 * 8000) * (cycle_timer >> 25);
1664
1665         return ticks;
1666 }
1667
1668 /*
1669  * Some controllers exhibit one or more of the following bugs when updating the
1670  * iso cycle timer register:
1671  *  - When the lowest six bits are wrapping around to zero, a read that happens
1672  *    at the same time will return garbage in the lowest ten bits.
1673  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1674  *    not incremented for about 60 ns.
1675  *  - Occasionally, the entire register reads zero.
1676  *
1677  * To catch these, we read the register three times and ensure that the
1678  * difference between each two consecutive reads is approximately the same, i.e.
1679  * less than twice the other.  Furthermore, any negative difference indicates an
1680  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1681  * execute, so we have enough precision to compute the ratio of the differences.)
1682  */
1683 static u32 get_cycle_time(struct fw_ohci *ohci)
1684 {
1685         u32 c0, c1, c2;
1686         u32 t0, t1, t2;
1687         s32 diff01, diff12;
1688         int i;
1689
1690         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1691
1692         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1693                 i = 0;
1694                 c1 = c2;
1695                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1696                 do {
1697                         c0 = c1;
1698                         c1 = c2;
1699                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1700                         t0 = cycle_timer_ticks(c0);
1701                         t1 = cycle_timer_ticks(c1);
1702                         t2 = cycle_timer_ticks(c2);
1703                         diff01 = t1 - t0;
1704                         diff12 = t2 - t1;
1705                 } while ((diff01 <= 0 || diff12 <= 0 ||
1706                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1707                          && i++ < 20);
1708         }
1709
1710         return c2;
1711 }
1712
1713 /*
1714  * This function has to be called at least every 64 seconds.  The bus_time
1715  * field stores not only the upper 25 bits of the BUS_TIME register but also
1716  * the most significant bit of the cycle timer in bit 6 so that we can detect
1717  * changes in this bit.
1718  */
1719 static u32 update_bus_time(struct fw_ohci *ohci)
1720 {
1721         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1722
1723         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1724                 ohci->bus_time += 0x40;
1725
1726         return ohci->bus_time | cycle_time_seconds;
1727 }
1728
1729 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1730 {
1731         int reg;
1732
1733         mutex_lock(&ohci->phy_reg_mutex);
1734         reg = write_phy_reg(ohci, 7, port_index);
1735         if (reg >= 0)
1736                 reg = read_phy_reg(ohci, 8);
1737         mutex_unlock(&ohci->phy_reg_mutex);
1738         if (reg < 0)
1739                 return reg;
1740
1741         switch (reg & 0x0f) {
1742         case 0x06:
1743                 return 2;       /* is child node (connected to parent node) */
1744         case 0x0e:
1745                 return 3;       /* is parent node (connected to child node) */
1746         }
1747         return 1;               /* not connected */
1748 }
1749
1750 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1751         int self_id_count)
1752 {
1753         int i;
1754         u32 entry;
1755
1756         for (i = 0; i < self_id_count; i++) {
1757                 entry = ohci->self_id_buffer[i];
1758                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1759                         return -1;
1760                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1761                         return i;
1762         }
1763         return i;
1764 }
1765
1766 /*
1767  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1768  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1769  * Construct the selfID from phy register contents.
1770  * FIXME:  How to determine the selfID.i flag?
1771  */
1772 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1773 {
1774         int reg, i, pos, status;
1775         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1776         u32 self_id = 0x8040c800;
1777
1778         reg = reg_read(ohci, OHCI1394_NodeID);
1779         if (!(reg & OHCI1394_NodeID_idValid)) {
1780                 fw_notify("node ID not valid, new bus reset in progress\n");
1781                 return -EBUSY;
1782         }
1783         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1784
1785         reg = ohci_read_phy_reg(&ohci->card, 4);
1786         if (reg < 0)
1787                 return reg;
1788         self_id |= ((reg & 0x07) << 8); /* power class */
1789
1790         reg = ohci_read_phy_reg(&ohci->card, 1);
1791         if (reg < 0)
1792                 return reg;
1793         self_id |= ((reg & 0x3f) << 16); /* gap count */
1794
1795         for (i = 0; i < 3; i++) {
1796                 status = get_status_for_port(ohci, i);
1797                 if (status < 0)
1798                         return status;
1799                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1800         }
1801
1802         pos = get_self_id_pos(ohci, self_id, self_id_count);
1803         if (pos >= 0) {
1804                 memmove(&(ohci->self_id_buffer[pos+1]),
1805                         &(ohci->self_id_buffer[pos]),
1806                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1807                 ohci->self_id_buffer[pos] = self_id;
1808                 self_id_count++;
1809         }
1810         return self_id_count;
1811 }
1812
1813 static void bus_reset_work(struct work_struct *work)
1814 {
1815         struct fw_ohci *ohci =
1816                 container_of(work, struct fw_ohci, bus_reset_work);
1817         int self_id_count, i, j, reg;
1818         int generation, new_generation;
1819         unsigned long flags;
1820         void *free_rom = NULL;
1821         dma_addr_t free_rom_bus = 0;
1822         bool is_new_root;
1823
1824         reg = reg_read(ohci, OHCI1394_NodeID);
1825         if (!(reg & OHCI1394_NodeID_idValid)) {
1826                 fw_notify("node ID not valid, new bus reset in progress\n");
1827                 return;
1828         }
1829         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1830                 fw_notify("malconfigured bus\n");
1831                 return;
1832         }
1833         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1834                                OHCI1394_NodeID_nodeNumber);
1835
1836         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1837         if (!(ohci->is_root && is_new_root))
1838                 reg_write(ohci, OHCI1394_LinkControlSet,
1839                           OHCI1394_LinkControl_cycleMaster);
1840         ohci->is_root = is_new_root;
1841
1842         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1843         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1844                 fw_notify("inconsistent self IDs\n");
1845                 return;
1846         }
1847         /*
1848          * The count in the SelfIDCount register is the number of
1849          * bytes in the self ID receive buffer.  Since we also receive
1850          * the inverted quadlets and a header quadlet, we shift one
1851          * bit extra to get the actual number of self IDs.
1852          */
1853         self_id_count = (reg >> 3) & 0xff;
1854
1855         if (self_id_count > 252) {
1856                 fw_notify("inconsistent self IDs\n");
1857                 return;
1858         }
1859
1860         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1861         rmb();
1862
1863         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1864                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1865                         /*
1866                          * If the invalid data looks like a cycle start packet,
1867                          * it's likely to be the result of the cycle master
1868                          * having a wrong gap count.  In this case, the self IDs
1869                          * so far are valid and should be processed so that the
1870                          * bus manager can then correct the gap count.
1871                          */
1872                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1873                                                         == 0xffff008f) {
1874                                 fw_notify("ignoring spurious self IDs\n");
1875                                 self_id_count = j;
1876                                 break;
1877                         } else {
1878                                 fw_notify("inconsistent self IDs\n");
1879                                 return;
1880                         }
1881                 }
1882                 ohci->self_id_buffer[j] =
1883                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1884         }
1885
1886         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1887                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1888                 if (self_id_count < 0) {
1889                         fw_notify("could not construct local self ID\n");
1890                         return;
1891                 }
1892         }
1893
1894         if (self_id_count == 0) {
1895                 fw_notify("inconsistent self IDs\n");
1896                 return;
1897         }
1898         rmb();
1899
1900         /*
1901          * Check the consistency of the self IDs we just read.  The
1902          * problem we face is that a new bus reset can start while we
1903          * read out the self IDs from the DMA buffer. If this happens,
1904          * the DMA buffer will be overwritten with new self IDs and we
1905          * will read out inconsistent data.  The OHCI specification
1906          * (section 11.2) recommends a technique similar to
1907          * linux/seqlock.h, where we remember the generation of the
1908          * self IDs in the buffer before reading them out and compare
1909          * it to the current generation after reading them out.  If
1910          * the two generations match we know we have a consistent set
1911          * of self IDs.
1912          */
1913
1914         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1915         if (new_generation != generation) {
1916                 fw_notify("recursive bus reset detected, "
1917                           "discarding self ids\n");
1918                 return;
1919         }
1920
1921         /* FIXME: Document how the locking works. */
1922         spin_lock_irqsave(&ohci->lock, flags);
1923
1924         ohci->generation = -1; /* prevent AT packet queueing */
1925         context_stop(&ohci->at_request_ctx);
1926         context_stop(&ohci->at_response_ctx);
1927
1928         spin_unlock_irqrestore(&ohci->lock, flags);
1929
1930         /*
1931          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1932          * packets in the AT queues and software needs to drain them.
1933          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1934          */
1935         at_context_flush(&ohci->at_request_ctx);
1936         at_context_flush(&ohci->at_response_ctx);
1937
1938         spin_lock_irqsave(&ohci->lock, flags);
1939
1940         ohci->generation = generation;
1941         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1942
1943         if (ohci->quirks & QUIRK_RESET_PACKET)
1944                 ohci->request_generation = generation;
1945
1946         /*
1947          * This next bit is unrelated to the AT context stuff but we
1948          * have to do it under the spinlock also.  If a new config rom
1949          * was set up before this reset, the old one is now no longer
1950          * in use and we can free it. Update the config rom pointers
1951          * to point to the current config rom and clear the
1952          * next_config_rom pointer so a new update can take place.
1953          */
1954
1955         if (ohci->next_config_rom != NULL) {
1956                 if (ohci->next_config_rom != ohci->config_rom) {
1957                         free_rom      = ohci->config_rom;
1958                         free_rom_bus  = ohci->config_rom_bus;
1959                 }
1960                 ohci->config_rom      = ohci->next_config_rom;
1961                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1962                 ohci->next_config_rom = NULL;
1963
1964                 /*
1965                  * Restore config_rom image and manually update
1966                  * config_rom registers.  Writing the header quadlet
1967                  * will indicate that the config rom is ready, so we
1968                  * do that last.
1969                  */
1970                 reg_write(ohci, OHCI1394_BusOptions,
1971                           be32_to_cpu(ohci->config_rom[2]));
1972                 ohci->config_rom[0] = ohci->next_header;
1973                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1974                           be32_to_cpu(ohci->next_header));
1975         }
1976
1977 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1978         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1979         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1980 #endif
1981
1982         spin_unlock_irqrestore(&ohci->lock, flags);
1983
1984         if (free_rom)
1985                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1986                                   free_rom, free_rom_bus);
1987
1988         log_selfids(ohci->node_id, generation,
1989                     self_id_count, ohci->self_id_buffer);
1990
1991         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1992                                  self_id_count, ohci->self_id_buffer,
1993                                  ohci->csr_state_setclear_abdicate);
1994         ohci->csr_state_setclear_abdicate = false;
1995 }
1996
1997 static irqreturn_t irq_handler(int irq, void *data)
1998 {
1999         struct fw_ohci *ohci = data;
2000         u32 event, iso_event;
2001         int i;
2002
2003         event = reg_read(ohci, OHCI1394_IntEventClear);
2004
2005         if (!event || !~event)
2006                 return IRQ_NONE;
2007
2008         /*
2009          * busReset and postedWriteErr must not be cleared yet
2010          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2011          */
2012         reg_write(ohci, OHCI1394_IntEventClear,
2013                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2014         log_irqs(event);
2015
2016         if (event & OHCI1394_selfIDComplete)
2017                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2018
2019         if (event & OHCI1394_RQPkt)
2020                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2021
2022         if (event & OHCI1394_RSPkt)
2023                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2024
2025         if (event & OHCI1394_reqTxComplete)
2026                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2027
2028         if (event & OHCI1394_respTxComplete)
2029                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2030
2031         if (event & OHCI1394_isochRx) {
2032                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2033                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2034
2035                 while (iso_event) {
2036                         i = ffs(iso_event) - 1;
2037                         tasklet_schedule(
2038                                 &ohci->ir_context_list[i].context.tasklet);
2039                         iso_event &= ~(1 << i);
2040                 }
2041         }
2042
2043         if (event & OHCI1394_isochTx) {
2044                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2045                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2046
2047                 while (iso_event) {
2048                         i = ffs(iso_event) - 1;
2049                         tasklet_schedule(
2050                                 &ohci->it_context_list[i].context.tasklet);
2051                         iso_event &= ~(1 << i);
2052                 }
2053         }
2054
2055         if (unlikely(event & OHCI1394_regAccessFail))
2056                 fw_error("Register access failure - "
2057                          "please notify linux1394-devel@lists.sf.net\n");
2058
2059         if (unlikely(event & OHCI1394_postedWriteErr)) {
2060                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2061                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2062                 reg_write(ohci, OHCI1394_IntEventClear,
2063                           OHCI1394_postedWriteErr);
2064                 if (printk_ratelimit())
2065                         fw_error("PCI posted write error\n");
2066         }
2067
2068         if (unlikely(event & OHCI1394_cycleTooLong)) {
2069                 if (printk_ratelimit())
2070                         fw_notify("isochronous cycle too long\n");
2071                 reg_write(ohci, OHCI1394_LinkControlSet,
2072                           OHCI1394_LinkControl_cycleMaster);
2073         }
2074
2075         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2076                 /*
2077                  * We need to clear this event bit in order to make
2078                  * cycleMatch isochronous I/O work.  In theory we should
2079                  * stop active cycleMatch iso contexts now and restart
2080                  * them at least two cycles later.  (FIXME?)
2081                  */
2082                 if (printk_ratelimit())
2083                         fw_notify("isochronous cycle inconsistent\n");
2084         }
2085
2086         if (unlikely(event & OHCI1394_unrecoverableError))
2087                 handle_dead_contexts(ohci);
2088
2089         if (event & OHCI1394_cycle64Seconds) {
2090                 spin_lock(&ohci->lock);
2091                 update_bus_time(ohci);
2092                 spin_unlock(&ohci->lock);
2093         } else
2094                 flush_writes(ohci);
2095
2096         return IRQ_HANDLED;
2097 }
2098
2099 static int software_reset(struct fw_ohci *ohci)
2100 {
2101         u32 val;
2102         int i;
2103
2104         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2105         for (i = 0; i < 500; i++) {
2106                 val = reg_read(ohci, OHCI1394_HCControlSet);
2107                 if (!~val)
2108                         return -ENODEV; /* Card was ejected. */
2109
2110                 if (!(val & OHCI1394_HCControl_softReset))
2111                         return 0;
2112
2113                 msleep(1);
2114         }
2115
2116         return -EBUSY;
2117 }
2118
2119 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2120 {
2121         size_t size = length * 4;
2122
2123         memcpy(dest, src, size);
2124         if (size < CONFIG_ROM_SIZE)
2125                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2126 }
2127
2128 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2129 {
2130         bool enable_1394a;
2131         int ret, clear, set, offset;
2132
2133         /* Check if the driver should configure link and PHY. */
2134         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2135               OHCI1394_HCControl_programPhyEnable))
2136                 return 0;
2137
2138         /* Paranoia: check whether the PHY supports 1394a, too. */
2139         enable_1394a = false;
2140         ret = read_phy_reg(ohci, 2);
2141         if (ret < 0)
2142                 return ret;
2143         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2144                 ret = read_paged_phy_reg(ohci, 1, 8);
2145                 if (ret < 0)
2146                         return ret;
2147                 if (ret >= 1)
2148                         enable_1394a = true;
2149         }
2150
2151         if (ohci->quirks & QUIRK_NO_1394A)
2152                 enable_1394a = false;
2153
2154         /* Configure PHY and link consistently. */
2155         if (enable_1394a) {
2156                 clear = 0;
2157                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2158         } else {
2159                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2160                 set = 0;
2161         }
2162         ret = update_phy_reg(ohci, 5, clear, set);
2163         if (ret < 0)
2164                 return ret;
2165
2166         if (enable_1394a)
2167                 offset = OHCI1394_HCControlSet;
2168         else
2169                 offset = OHCI1394_HCControlClear;
2170         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2171
2172         /* Clean up: configuration has been taken care of. */
2173         reg_write(ohci, OHCI1394_HCControlClear,
2174                   OHCI1394_HCControl_programPhyEnable);
2175
2176         return 0;
2177 }
2178
2179 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2180 {
2181         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2182         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2183         int reg, i;
2184
2185         reg = read_phy_reg(ohci, 2);
2186         if (reg < 0)
2187                 return reg;
2188         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2189                 return 0;
2190
2191         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2192                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2193                 if (reg < 0)
2194                         return reg;
2195                 if (reg != id[i])
2196                         return 0;
2197         }
2198         return 1;
2199 }
2200
2201 static int ohci_enable(struct fw_card *card,
2202                        const __be32 *config_rom, size_t length)
2203 {
2204         struct fw_ohci *ohci = fw_ohci(card);
2205         struct pci_dev *dev = to_pci_dev(card->device);
2206         u32 lps, seconds, version, irqs;
2207         int i, ret;
2208
2209         if (software_reset(ohci)) {
2210                 fw_error("Failed to reset ohci card.\n");
2211                 return -EBUSY;
2212         }
2213
2214         /*
2215          * Now enable LPS, which we need in order to start accessing
2216          * most of the registers.  In fact, on some cards (ALI M5251),
2217          * accessing registers in the SClk domain without LPS enabled
2218          * will lock up the machine.  Wait 50msec to make sure we have
2219          * full link enabled.  However, with some cards (well, at least
2220          * a JMicron PCIe card), we have to try again sometimes.
2221          */
2222         reg_write(ohci, OHCI1394_HCControlSet,
2223                   OHCI1394_HCControl_LPS |
2224                   OHCI1394_HCControl_postedWriteEnable);
2225         flush_writes(ohci);
2226
2227         for (lps = 0, i = 0; !lps && i < 3; i++) {
2228                 msleep(50);
2229                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2230                       OHCI1394_HCControl_LPS;
2231         }
2232
2233         if (!lps) {
2234                 fw_error("Failed to set Link Power Status\n");
2235                 return -EIO;
2236         }
2237
2238         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2239                 ret = probe_tsb41ba3d(ohci);
2240                 if (ret < 0)
2241                         return ret;
2242                 if (ret)
2243                         fw_notify("local TSB41BA3D phy\n");
2244                 else
2245                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2246         }
2247
2248         reg_write(ohci, OHCI1394_HCControlClear,
2249                   OHCI1394_HCControl_noByteSwapData);
2250
2251         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2252         reg_write(ohci, OHCI1394_LinkControlSet,
2253                   OHCI1394_LinkControl_cycleTimerEnable |
2254                   OHCI1394_LinkControl_cycleMaster);
2255
2256         reg_write(ohci, OHCI1394_ATRetries,
2257                   OHCI1394_MAX_AT_REQ_RETRIES |
2258                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2259                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2260                   (200 << 16));
2261
2262         seconds = lower_32_bits(get_seconds());
2263         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2264         ohci->bus_time = seconds & ~0x3f;
2265
2266         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2267         if (version >= OHCI_VERSION_1_1) {
2268                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2269                           0xfffffffe);
2270                 card->broadcast_channel_auto_allocated = true;
2271         }
2272
2273         /* Get implemented bits of the priority arbitration request counter. */
2274         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2275         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2276         reg_write(ohci, OHCI1394_FairnessControl, 0);
2277         card->priority_budget_implemented = ohci->pri_req_max != 0;
2278
2279         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2280         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2281         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2282
2283         ret = configure_1394a_enhancements(ohci);
2284         if (ret < 0)
2285                 return ret;
2286
2287         /* Activate link_on bit and contender bit in our self ID packets.*/
2288         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2289         if (ret < 0)
2290                 return ret;
2291
2292         /*
2293          * When the link is not yet enabled, the atomic config rom
2294          * update mechanism described below in ohci_set_config_rom()
2295          * is not active.  We have to update ConfigRomHeader and
2296          * BusOptions manually, and the write to ConfigROMmap takes
2297          * effect immediately.  We tie this to the enabling of the
2298          * link, so we have a valid config rom before enabling - the
2299          * OHCI requires that ConfigROMhdr and BusOptions have valid
2300          * values before enabling.
2301          *
2302          * However, when the ConfigROMmap is written, some controllers
2303          * always read back quadlets 0 and 2 from the config rom to
2304          * the ConfigRomHeader and BusOptions registers on bus reset.
2305          * They shouldn't do that in this initial case where the link
2306          * isn't enabled.  This means we have to use the same
2307          * workaround here, setting the bus header to 0 and then write
2308          * the right values in the bus reset tasklet.
2309          */
2310
2311         if (config_rom) {
2312                 ohci->next_config_rom =
2313                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2314                                            &ohci->next_config_rom_bus,
2315                                            GFP_KERNEL);
2316                 if (ohci->next_config_rom == NULL)
2317                         return -ENOMEM;
2318
2319                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2320         } else {
2321                 /*
2322                  * In the suspend case, config_rom is NULL, which
2323                  * means that we just reuse the old config rom.
2324                  */
2325                 ohci->next_config_rom = ohci->config_rom;
2326                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2327         }
2328
2329         ohci->next_header = ohci->next_config_rom[0];
2330         ohci->next_config_rom[0] = 0;
2331         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2332         reg_write(ohci, OHCI1394_BusOptions,
2333                   be32_to_cpu(ohci->next_config_rom[2]));
2334         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2335
2336         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2337
2338         if (!(ohci->quirks & QUIRK_NO_MSI))
2339                 pci_enable_msi(dev);
2340         if (request_irq(dev->irq, irq_handler,
2341                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2342                         ohci_driver_name, ohci)) {
2343                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2344                 pci_disable_msi(dev);
2345
2346                 if (config_rom) {
2347                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2348                                           ohci->next_config_rom,
2349                                           ohci->next_config_rom_bus);
2350                         ohci->next_config_rom = NULL;
2351                 }
2352                 return -EIO;
2353         }
2354
2355         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2356                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2357                 OHCI1394_isochTx | OHCI1394_isochRx |
2358                 OHCI1394_postedWriteErr |
2359                 OHCI1394_selfIDComplete |
2360                 OHCI1394_regAccessFail |
2361                 OHCI1394_cycle64Seconds |
2362                 OHCI1394_cycleInconsistent |
2363                 OHCI1394_unrecoverableError |
2364                 OHCI1394_cycleTooLong |
2365                 OHCI1394_masterIntEnable;
2366         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2367                 irqs |= OHCI1394_busReset;
2368         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2369
2370         reg_write(ohci, OHCI1394_HCControlSet,
2371                   OHCI1394_HCControl_linkEnable |
2372                   OHCI1394_HCControl_BIBimageValid);
2373
2374         reg_write(ohci, OHCI1394_LinkControlSet,
2375                   OHCI1394_LinkControl_rcvSelfID |
2376                   OHCI1394_LinkControl_rcvPhyPkt);
2377
2378         ar_context_run(&ohci->ar_request_ctx);
2379         ar_context_run(&ohci->ar_response_ctx);
2380
2381         flush_writes(ohci);
2382
2383         /* We are ready to go, reset bus to finish initialization. */
2384         fw_schedule_bus_reset(&ohci->card, false, true);
2385
2386         return 0;
2387 }
2388
2389 static int ohci_set_config_rom(struct fw_card *card,
2390                                const __be32 *config_rom, size_t length)
2391 {
2392         struct fw_ohci *ohci;
2393         unsigned long flags;
2394         __be32 *next_config_rom;
2395         dma_addr_t uninitialized_var(next_config_rom_bus);
2396
2397         ohci = fw_ohci(card);
2398
2399         /*
2400          * When the OHCI controller is enabled, the config rom update
2401          * mechanism is a bit tricky, but easy enough to use.  See
2402          * section 5.5.6 in the OHCI specification.
2403          *
2404          * The OHCI controller caches the new config rom address in a
2405          * shadow register (ConfigROMmapNext) and needs a bus reset
2406          * for the changes to take place.  When the bus reset is
2407          * detected, the controller loads the new values for the
2408          * ConfigRomHeader and BusOptions registers from the specified
2409          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2410          * shadow register. All automatically and atomically.
2411          *
2412          * Now, there's a twist to this story.  The automatic load of
2413          * ConfigRomHeader and BusOptions doesn't honor the
2414          * noByteSwapData bit, so with a be32 config rom, the
2415          * controller will load be32 values in to these registers
2416          * during the atomic update, even on litte endian
2417          * architectures.  The workaround we use is to put a 0 in the
2418          * header quadlet; 0 is endian agnostic and means that the
2419          * config rom isn't ready yet.  In the bus reset tasklet we
2420          * then set up the real values for the two registers.
2421          *
2422          * We use ohci->lock to avoid racing with the code that sets
2423          * ohci->next_config_rom to NULL (see bus_reset_work).
2424          */
2425
2426         next_config_rom =
2427                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2428                                    &next_config_rom_bus, GFP_KERNEL);
2429         if (next_config_rom == NULL)
2430                 return -ENOMEM;
2431
2432         spin_lock_irqsave(&ohci->lock, flags);
2433
2434         /*
2435          * If there is not an already pending config_rom update,
2436          * push our new allocation into the ohci->next_config_rom
2437          * and then mark the local variable as null so that we
2438          * won't deallocate the new buffer.
2439          *
2440          * OTOH, if there is a pending config_rom update, just
2441          * use that buffer with the new config_rom data, and
2442          * let this routine free the unused DMA allocation.
2443          */
2444
2445         if (ohci->next_config_rom == NULL) {
2446                 ohci->next_config_rom = next_config_rom;
2447                 ohci->next_config_rom_bus = next_config_rom_bus;
2448                 next_config_rom = NULL;
2449         }
2450
2451         copy_config_rom(ohci->next_config_rom, config_rom, length);
2452
2453         ohci->next_header = config_rom[0];
2454         ohci->next_config_rom[0] = 0;
2455
2456         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2457
2458         spin_unlock_irqrestore(&ohci->lock, flags);
2459
2460         /* If we didn't use the DMA allocation, delete it. */
2461         if (next_config_rom != NULL)
2462                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2463                                   next_config_rom, next_config_rom_bus);
2464
2465         /*
2466          * Now initiate a bus reset to have the changes take
2467          * effect. We clean up the old config rom memory and DMA
2468          * mappings in the bus reset tasklet, since the OHCI
2469          * controller could need to access it before the bus reset
2470          * takes effect.
2471          */
2472
2473         fw_schedule_bus_reset(&ohci->card, true, true);
2474
2475         return 0;
2476 }
2477
2478 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2479 {
2480         struct fw_ohci *ohci = fw_ohci(card);
2481
2482         at_context_transmit(&ohci->at_request_ctx, packet);
2483 }
2484
2485 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2486 {
2487         struct fw_ohci *ohci = fw_ohci(card);
2488
2489         at_context_transmit(&ohci->at_response_ctx, packet);
2490 }
2491
2492 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2493 {
2494         struct fw_ohci *ohci = fw_ohci(card);
2495         struct context *ctx = &ohci->at_request_ctx;
2496         struct driver_data *driver_data = packet->driver_data;
2497         int ret = -ENOENT;
2498
2499         tasklet_disable(&ctx->tasklet);
2500
2501         if (packet->ack != 0)
2502                 goto out;
2503
2504         if (packet->payload_mapped)
2505                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2506                                  packet->payload_length, DMA_TO_DEVICE);
2507
2508         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2509         driver_data->packet = NULL;
2510         packet->ack = RCODE_CANCELLED;
2511         packet->callback(packet, &ohci->card, packet->ack);
2512         ret = 0;
2513  out:
2514         tasklet_enable(&ctx->tasklet);
2515
2516         return ret;
2517 }
2518
2519 static int ohci_enable_phys_dma(struct fw_card *card,
2520                                 int node_id, int generation)
2521 {
2522 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2523         return 0;
2524 #else
2525         struct fw_ohci *ohci = fw_ohci(card);
2526         unsigned long flags;
2527         int n, ret = 0;
2528
2529         /*
2530          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2531          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2532          */
2533
2534         spin_lock_irqsave(&ohci->lock, flags);
2535
2536         if (ohci->generation != generation) {
2537                 ret = -ESTALE;
2538                 goto out;
2539         }
2540
2541         /*
2542          * Note, if the node ID contains a non-local bus ID, physical DMA is
2543          * enabled for _all_ nodes on remote buses.
2544          */
2545
2546         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2547         if (n < 32)
2548                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2549         else
2550                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2551
2552         flush_writes(ohci);
2553  out:
2554         spin_unlock_irqrestore(&ohci->lock, flags);
2555
2556         return ret;
2557 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2558 }
2559
2560 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2561 {
2562         struct fw_ohci *ohci = fw_ohci(card);
2563         unsigned long flags;
2564         u32 value;
2565
2566         switch (csr_offset) {
2567         case CSR_STATE_CLEAR:
2568         case CSR_STATE_SET:
2569                 if (ohci->is_root &&
2570                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2571                      OHCI1394_LinkControl_cycleMaster))
2572                         value = CSR_STATE_BIT_CMSTR;
2573                 else
2574                         value = 0;
2575                 if (ohci->csr_state_setclear_abdicate)
2576                         value |= CSR_STATE_BIT_ABDICATE;
2577
2578                 return value;
2579
2580         case CSR_NODE_IDS:
2581                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2582
2583         case CSR_CYCLE_TIME:
2584                 return get_cycle_time(ohci);
2585
2586         case CSR_BUS_TIME:
2587                 /*
2588                  * We might be called just after the cycle timer has wrapped
2589                  * around but just before the cycle64Seconds handler, so we
2590                  * better check here, too, if the bus time needs to be updated.
2591                  */
2592                 spin_lock_irqsave(&ohci->lock, flags);
2593                 value = update_bus_time(ohci);
2594                 spin_unlock_irqrestore(&ohci->lock, flags);
2595                 return value;
2596
2597         case CSR_BUSY_TIMEOUT:
2598                 value = reg_read(ohci, OHCI1394_ATRetries);
2599                 return (value >> 4) & 0x0ffff00f;
2600
2601         case CSR_PRIORITY_BUDGET:
2602                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2603                         (ohci->pri_req_max << 8);
2604
2605         default:
2606                 WARN_ON(1);
2607                 return 0;
2608         }
2609 }
2610
2611 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2612 {
2613         struct fw_ohci *ohci = fw_ohci(card);
2614         unsigned long flags;
2615
2616         switch (csr_offset) {
2617         case CSR_STATE_CLEAR:
2618                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2619                         reg_write(ohci, OHCI1394_LinkControlClear,
2620                                   OHCI1394_LinkControl_cycleMaster);
2621                         flush_writes(ohci);
2622                 }
2623                 if (value & CSR_STATE_BIT_ABDICATE)
2624                         ohci->csr_state_setclear_abdicate = false;
2625                 break;
2626
2627         case CSR_STATE_SET:
2628                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2629                         reg_write(ohci, OHCI1394_LinkControlSet,
2630                                   OHCI1394_LinkControl_cycleMaster);
2631                         flush_writes(ohci);
2632                 }
2633                 if (value & CSR_STATE_BIT_ABDICATE)
2634                         ohci->csr_state_setclear_abdicate = true;
2635                 break;
2636
2637         case CSR_NODE_IDS:
2638                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2639                 flush_writes(ohci);
2640                 break;
2641
2642         case CSR_CYCLE_TIME:
2643                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2644                 reg_write(ohci, OHCI1394_IntEventSet,
2645                           OHCI1394_cycleInconsistent);
2646                 flush_writes(ohci);
2647                 break;
2648
2649         case CSR_BUS_TIME:
2650                 spin_lock_irqsave(&ohci->lock, flags);
2651                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2652                 spin_unlock_irqrestore(&ohci->lock, flags);
2653                 break;
2654
2655         case CSR_BUSY_TIMEOUT:
2656                 value = (value & 0xf) | ((value & 0xf) << 4) |
2657                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2658                 reg_write(ohci, OHCI1394_ATRetries, value);
2659                 flush_writes(ohci);
2660                 break;
2661
2662         case CSR_PRIORITY_BUDGET:
2663                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2664                 flush_writes(ohci);
2665                 break;
2666
2667         default:
2668                 WARN_ON(1);
2669                 break;
2670         }
2671 }
2672
2673 static void copy_iso_headers(struct iso_context *ctx, void *p)
2674 {
2675         int i = ctx->header_length;
2676
2677         if (i + ctx->base.header_size > PAGE_SIZE)
2678                 return;
2679
2680         /*
2681          * The iso header is byteswapped to little endian by
2682          * the controller, but the remaining header quadlets
2683          * are big endian.  We want to present all the headers
2684          * as big endian, so we have to swap the first quadlet.
2685          */
2686         if (ctx->base.header_size > 0)
2687                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2688         if (ctx->base.header_size > 4)
2689                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2690         if (ctx->base.header_size > 8)
2691                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2692         ctx->header_length += ctx->base.header_size;
2693 }
2694
2695 static int handle_ir_packet_per_buffer(struct context *context,
2696                                        struct descriptor *d,
2697                                        struct descriptor *last)
2698 {
2699         struct iso_context *ctx =
2700                 container_of(context, struct iso_context, context);
2701         struct descriptor *pd;
2702         u32 buffer_dma;
2703         __le32 *ir_header;
2704         void *p;
2705
2706         for (pd = d; pd <= last; pd++)
2707                 if (pd->transfer_status)
2708                         break;
2709         if (pd > last)
2710                 /* Descriptor(s) not done yet, stop iteration */
2711                 return 0;
2712
2713         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2714                 d++;
2715                 buffer_dma = le32_to_cpu(d->data_address);
2716                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2717                                               buffer_dma & PAGE_MASK,
2718                                               buffer_dma & ~PAGE_MASK,
2719                                               le16_to_cpu(d->req_count),
2720                                               DMA_FROM_DEVICE);
2721         }
2722
2723         p = last + 1;
2724         copy_iso_headers(ctx, p);
2725
2726         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2727                 ir_header = (__le32 *) p;
2728                 ctx->base.callback.sc(&ctx->base,
2729                                       le32_to_cpu(ir_header[0]) & 0xffff,
2730                                       ctx->header_length, ctx->header,
2731                                       ctx->base.callback_data);
2732                 ctx->header_length = 0;
2733         }
2734
2735         return 1;
2736 }
2737
2738 /* d == last because each descriptor block is only a single descriptor. */
2739 static int handle_ir_buffer_fill(struct context *context,
2740                                  struct descriptor *d,
2741                                  struct descriptor *last)
2742 {
2743         struct iso_context *ctx =
2744                 container_of(context, struct iso_context, context);
2745         u32 buffer_dma;
2746
2747         if (!last->transfer_status)
2748                 /* Descriptor(s) not done yet, stop iteration */
2749                 return 0;
2750
2751         buffer_dma = le32_to_cpu(last->data_address);
2752         dma_sync_single_range_for_cpu(context->ohci->card.device,
2753                                       buffer_dma & PAGE_MASK,
2754                                       buffer_dma & ~PAGE_MASK,
2755                                       le16_to_cpu(last->req_count),
2756                                       DMA_FROM_DEVICE);
2757
2758         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2759                 ctx->base.callback.mc(&ctx->base,
2760                                       le32_to_cpu(last->data_address) +
2761                                       le16_to_cpu(last->req_count) -
2762                                       le16_to_cpu(last->res_count),
2763                                       ctx->base.callback_data);
2764
2765         return 1;
2766 }
2767
2768 static inline void sync_it_packet_for_cpu(struct context *context,
2769                                           struct descriptor *pd)
2770 {
2771         __le16 control;
2772         u32 buffer_dma;
2773
2774         /* only packets beginning with OUTPUT_MORE* have data buffers */
2775         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2776                 return;
2777
2778         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2779         pd += 2;
2780
2781         /*
2782          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2783          * data buffer is in the context program's coherent page and must not
2784          * be synced.
2785          */
2786         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2787             (context->current_bus          & PAGE_MASK)) {
2788                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2789                         return;
2790                 pd++;
2791         }
2792
2793         do {
2794                 buffer_dma = le32_to_cpu(pd->data_address);
2795                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2796                                               buffer_dma & PAGE_MASK,
2797                                               buffer_dma & ~PAGE_MASK,
2798                                               le16_to_cpu(pd->req_count),
2799                                               DMA_TO_DEVICE);
2800                 control = pd->control;
2801                 pd++;
2802         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2803 }
2804
2805 static int handle_it_packet(struct context *context,
2806                             struct descriptor *d,
2807                             struct descriptor *last)
2808 {
2809         struct iso_context *ctx =
2810                 container_of(context, struct iso_context, context);
2811         int i;
2812         struct descriptor *pd;
2813
2814         for (pd = d; pd <= last; pd++)
2815                 if (pd->transfer_status)
2816                         break;
2817         if (pd > last)
2818                 /* Descriptor(s) not done yet, stop iteration */
2819                 return 0;
2820
2821         sync_it_packet_for_cpu(context, d);
2822
2823         i = ctx->header_length;
2824         if (i + 4 < PAGE_SIZE) {
2825                 /* Present this value as big-endian to match the receive code */
2826                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2827                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2828                                 le16_to_cpu(pd->res_count));
2829                 ctx->header_length += 4;
2830         }
2831         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2832                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2833                                       ctx->header_length, ctx->header,
2834                                       ctx->base.callback_data);
2835                 ctx->header_length = 0;
2836         }
2837         return 1;
2838 }
2839
2840 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2841 {
2842         u32 hi = channels >> 32, lo = channels;
2843
2844         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2845         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2846         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2847         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2848         mmiowb();
2849         ohci->mc_channels = channels;
2850 }
2851
2852 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2853                                 int type, int channel, size_t header_size)
2854 {
2855         struct fw_ohci *ohci = fw_ohci(card);
2856         struct iso_context *uninitialized_var(ctx);
2857         descriptor_callback_t uninitialized_var(callback);
2858         u64 *uninitialized_var(channels);
2859         u32 *uninitialized_var(mask), uninitialized_var(regs);
2860         unsigned long flags;
2861         int index, ret = -EBUSY;
2862
2863         spin_lock_irqsave(&ohci->lock, flags);
2864
2865         switch (type) {
2866         case FW_ISO_CONTEXT_TRANSMIT:
2867                 mask     = &ohci->it_context_mask;
2868                 callback = handle_it_packet;
2869                 index    = ffs(*mask) - 1;
2870                 if (index >= 0) {
2871                         *mask &= ~(1 << index);
2872                         regs = OHCI1394_IsoXmitContextBase(index);
2873                         ctx  = &ohci->it_context_list[index];
2874                 }
2875                 break;
2876
2877         case FW_ISO_CONTEXT_RECEIVE:
2878                 channels = &ohci->ir_context_channels;
2879                 mask     = &ohci->ir_context_mask;
2880                 callback = handle_ir_packet_per_buffer;
2881                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2882                 if (index >= 0) {
2883                         *channels &= ~(1ULL << channel);
2884                         *mask     &= ~(1 << index);
2885                         regs = OHCI1394_IsoRcvContextBase(index);
2886                         ctx  = &ohci->ir_context_list[index];
2887                 }
2888                 break;
2889
2890         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2891                 mask     = &ohci->ir_context_mask;
2892                 callback = handle_ir_buffer_fill;
2893                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2894                 if (index >= 0) {
2895                         ohci->mc_allocated = true;
2896                         *mask &= ~(1 << index);
2897                         regs = OHCI1394_IsoRcvContextBase(index);
2898                         ctx  = &ohci->ir_context_list[index];
2899                 }
2900                 break;
2901
2902         default:
2903                 index = -1;
2904                 ret = -ENOSYS;
2905         }
2906
2907         spin_unlock_irqrestore(&ohci->lock, flags);
2908
2909         if (index < 0)
2910                 return ERR_PTR(ret);
2911
2912         memset(ctx, 0, sizeof(*ctx));
2913         ctx->header_length = 0;
2914         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2915         if (ctx->header == NULL) {
2916                 ret = -ENOMEM;
2917                 goto out;
2918         }
2919         ret = context_init(&ctx->context, ohci, regs, callback);
2920         if (ret < 0)
2921                 goto out_with_header;
2922
2923         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2924                 set_multichannel_mask(ohci, 0);
2925
2926         return &ctx->base;
2927
2928  out_with_header:
2929         free_page((unsigned long)ctx->header);
2930  out:
2931         spin_lock_irqsave(&ohci->lock, flags);
2932
2933         switch (type) {
2934         case FW_ISO_CONTEXT_RECEIVE:
2935                 *channels |= 1ULL << channel;
2936                 break;
2937
2938         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2939                 ohci->mc_allocated = false;
2940                 break;
2941         }
2942         *mask |= 1 << index;
2943
2944         spin_unlock_irqrestore(&ohci->lock, flags);
2945
2946         return ERR_PTR(ret);
2947 }
2948
2949 static int ohci_start_iso(struct fw_iso_context *base,
2950                           s32 cycle, u32 sync, u32 tags)
2951 {
2952         struct iso_context *ctx = container_of(base, struct iso_context, base);
2953         struct fw_ohci *ohci = ctx->context.ohci;
2954         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2955         int index;
2956
2957         /* the controller cannot start without any queued packets */
2958         if (ctx->context.last->branch_address == 0)
2959                 return -ENODATA;
2960
2961         switch (ctx->base.type) {
2962         case FW_ISO_CONTEXT_TRANSMIT:
2963                 index = ctx - ohci->it_context_list;
2964                 match = 0;
2965                 if (cycle >= 0)
2966                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2967                                 (cycle & 0x7fff) << 16;
2968
2969                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2970                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2971                 context_run(&ctx->context, match);
2972                 break;
2973
2974         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2975                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2976                 /* fall through */
2977         case FW_ISO_CONTEXT_RECEIVE:
2978                 index = ctx - ohci->ir_context_list;
2979                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2980                 if (cycle >= 0) {
2981                         match |= (cycle & 0x07fff) << 12;
2982                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2983                 }
2984
2985                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2986                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2987                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2988                 context_run(&ctx->context, control);
2989
2990                 ctx->sync = sync;
2991                 ctx->tags = tags;
2992
2993                 break;
2994         }
2995
2996         return 0;
2997 }
2998
2999 static int ohci_stop_iso(struct fw_iso_context *base)
3000 {
3001         struct fw_ohci *ohci = fw_ohci(base->card);
3002         struct iso_context *ctx = container_of(base, struct iso_context, base);
3003         int index;
3004
3005         switch (ctx->base.type) {
3006         case FW_ISO_CONTEXT_TRANSMIT:
3007                 index = ctx - ohci->it_context_list;
3008                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3009                 break;
3010
3011         case FW_ISO_CONTEXT_RECEIVE:
3012         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3013                 index = ctx - ohci->ir_context_list;
3014                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3015                 break;
3016         }
3017         flush_writes(ohci);
3018         context_stop(&ctx->context);
3019         tasklet_kill(&ctx->context.tasklet);
3020
3021         return 0;
3022 }
3023
3024 static void ohci_free_iso_context(struct fw_iso_context *base)
3025 {
3026         struct fw_ohci *ohci = fw_ohci(base->card);
3027         struct iso_context *ctx = container_of(base, struct iso_context, base);
3028         unsigned long flags;
3029         int index;
3030
3031         ohci_stop_iso(base);
3032         context_release(&ctx->context);
3033         free_page((unsigned long)ctx->header);
3034
3035         spin_lock_irqsave(&ohci->lock, flags);
3036
3037         switch (base->type) {
3038         case FW_ISO_CONTEXT_TRANSMIT:
3039                 index = ctx - ohci->it_context_list;
3040                 ohci->it_context_mask |= 1 << index;
3041                 break;
3042
3043         case FW_ISO_CONTEXT_RECEIVE:
3044                 index = ctx - ohci->ir_context_list;
3045                 ohci->ir_context_mask |= 1 << index;
3046                 ohci->ir_context_channels |= 1ULL << base->channel;
3047                 break;
3048
3049         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3050                 index = ctx - ohci->ir_context_list;
3051                 ohci->ir_context_mask |= 1 << index;
3052                 ohci->ir_context_channels |= ohci->mc_channels;
3053                 ohci->mc_channels = 0;
3054                 ohci->mc_allocated = false;
3055                 break;
3056         }
3057
3058         spin_unlock_irqrestore(&ohci->lock, flags);
3059 }
3060
3061 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3062 {
3063         struct fw_ohci *ohci = fw_ohci(base->card);
3064         unsigned long flags;
3065         int ret;
3066
3067         switch (base->type) {
3068         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3069
3070                 spin_lock_irqsave(&ohci->lock, flags);
3071
3072                 /* Don't allow multichannel to grab other contexts' channels. */
3073                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3074                         *channels = ohci->ir_context_channels;
3075                         ret = -EBUSY;
3076                 } else {
3077                         set_multichannel_mask(ohci, *channels);
3078                         ret = 0;
3079                 }
3080
3081                 spin_unlock_irqrestore(&ohci->lock, flags);
3082
3083                 break;
3084         default:
3085                 ret = -EINVAL;
3086         }
3087
3088         return ret;
3089 }
3090
3091 #ifdef CONFIG_PM
3092 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3093 {
3094         int i;
3095         struct iso_context *ctx;
3096
3097         for (i = 0 ; i < ohci->n_ir ; i++) {
3098                 ctx = &ohci->ir_context_list[i];
3099                 if (ctx->context.running)
3100                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3101         }
3102
3103         for (i = 0 ; i < ohci->n_it ; i++) {
3104                 ctx = &ohci->it_context_list[i];
3105                 if (ctx->context.running)
3106                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3107         }
3108 }
3109 #endif
3110
3111 static int queue_iso_transmit(struct iso_context *ctx,
3112                               struct fw_iso_packet *packet,
3113                               struct fw_iso_buffer *buffer,
3114                               unsigned long payload)
3115 {
3116         struct descriptor *d, *last, *pd;
3117         struct fw_iso_packet *p;
3118         __le32 *header;
3119         dma_addr_t d_bus, page_bus;
3120         u32 z, header_z, payload_z, irq;
3121         u32 payload_index, payload_end_index, next_page_index;
3122         int page, end_page, i, length, offset;
3123
3124         p = packet;
3125         payload_index = payload;
3126
3127         if (p->skip)
3128                 z = 1;
3129         else
3130                 z = 2;
3131         if (p->header_length > 0)
3132                 z++;
3133
3134         /* Determine the first page the payload isn't contained in. */
3135         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3136         if (p->payload_length > 0)
3137                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3138         else
3139                 payload_z = 0;
3140
3141         z += payload_z;
3142
3143         /* Get header size in number of descriptors. */
3144         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3145
3146         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3147         if (d == NULL)
3148                 return -ENOMEM;
3149
3150         if (!p->skip) {
3151                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3152                 d[0].req_count = cpu_to_le16(8);
3153                 /*
3154                  * Link the skip address to this descriptor itself.  This causes
3155                  * a context to skip a cycle whenever lost cycles or FIFO
3156                  * overruns occur, without dropping the data.  The application
3157                  * should then decide whether this is an error condition or not.
3158                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3159                  */
3160                 d[0].branch_address = cpu_to_le32(d_bus | z);
3161
3162                 header = (__le32 *) &d[1];
3163                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3164                                         IT_HEADER_TAG(p->tag) |
3165                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3166                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3167                                         IT_HEADER_SPEED(ctx->base.speed));
3168                 header[1] =
3169                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3170                                                           p->payload_length));
3171         }
3172
3173         if (p->header_length > 0) {
3174                 d[2].req_count    = cpu_to_le16(p->header_length);
3175                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3176                 memcpy(&d[z], p->header, p->header_length);
3177         }
3178
3179         pd = d + z - payload_z;
3180         payload_end_index = payload_index + p->payload_length;
3181         for (i = 0; i < payload_z; i++) {
3182                 page               = payload_index >> PAGE_SHIFT;
3183                 offset             = payload_index & ~PAGE_MASK;
3184                 next_page_index    = (page + 1) << PAGE_SHIFT;
3185                 length             =
3186                         min(next_page_index, payload_end_index) - payload_index;
3187                 pd[i].req_count    = cpu_to_le16(length);
3188
3189                 page_bus = page_private(buffer->pages[page]);
3190                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3191
3192                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3193                                                  page_bus, offset, length,
3194                                                  DMA_TO_DEVICE);
3195
3196                 payload_index += length;
3197         }
3198
3199         if (p->interrupt)
3200                 irq = DESCRIPTOR_IRQ_ALWAYS;
3201         else
3202                 irq = DESCRIPTOR_NO_IRQ;
3203
3204         last = z == 2 ? d : d + z - 1;
3205         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3206                                      DESCRIPTOR_STATUS |
3207                                      DESCRIPTOR_BRANCH_ALWAYS |
3208                                      irq);
3209
3210         context_append(&ctx->context, d, z, header_z);
3211
3212         return 0;
3213 }
3214
3215 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3216                                        struct fw_iso_packet *packet,
3217                                        struct fw_iso_buffer *buffer,
3218                                        unsigned long payload)
3219 {
3220         struct device *device = ctx->context.ohci->card.device;
3221         struct descriptor *d, *pd;
3222         dma_addr_t d_bus, page_bus;
3223         u32 z, header_z, rest;
3224         int i, j, length;
3225         int page, offset, packet_count, header_size, payload_per_buffer;
3226
3227         /*
3228          * The OHCI controller puts the isochronous header and trailer in the
3229          * buffer, so we need at least 8 bytes.
3230          */
3231         packet_count = packet->header_length / ctx->base.header_size;
3232         header_size  = max(ctx->base.header_size, (size_t)8);
3233
3234         /* Get header size in number of descriptors. */
3235         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3236         page     = payload >> PAGE_SHIFT;
3237         offset   = payload & ~PAGE_MASK;
3238         payload_per_buffer = packet->payload_length / packet_count;
3239
3240         for (i = 0; i < packet_count; i++) {
3241                 /* d points to the header descriptor */
3242                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3243                 d = context_get_descriptors(&ctx->context,
3244                                 z + header_z, &d_bus);
3245                 if (d == NULL)
3246                         return -ENOMEM;
3247
3248                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3249                                               DESCRIPTOR_INPUT_MORE);
3250                 if (packet->skip && i == 0)
3251                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3252                 d->req_count    = cpu_to_le16(header_size);
3253                 d->res_count    = d->req_count;
3254                 d->transfer_status = 0;
3255                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3256
3257                 rest = payload_per_buffer;
3258                 pd = d;
3259                 for (j = 1; j < z; j++) {
3260                         pd++;
3261                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3262                                                   DESCRIPTOR_INPUT_MORE);
3263
3264                         if (offset + rest < PAGE_SIZE)
3265                                 length = rest;
3266                         else
3267                                 length = PAGE_SIZE - offset;
3268                         pd->req_count = cpu_to_le16(length);
3269                         pd->res_count = pd->req_count;
3270                         pd->transfer_status = 0;
3271
3272                         page_bus = page_private(buffer->pages[page]);
3273                         pd->data_address = cpu_to_le32(page_bus + offset);
3274
3275                         dma_sync_single_range_for_device(device, page_bus,
3276                                                          offset, length,
3277                                                          DMA_FROM_DEVICE);
3278
3279                         offset = (offset + length) & ~PAGE_MASK;
3280                         rest -= length;
3281                         if (offset == 0)
3282                                 page++;
3283                 }
3284                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3285                                           DESCRIPTOR_INPUT_LAST |
3286                                           DESCRIPTOR_BRANCH_ALWAYS);
3287                 if (packet->interrupt && i == packet_count - 1)
3288                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3289
3290                 context_append(&ctx->context, d, z, header_z);
3291         }
3292
3293         return 0;
3294 }
3295
3296 static int queue_iso_buffer_fill(struct iso_context *ctx,
3297                                  struct fw_iso_packet *packet,
3298                                  struct fw_iso_buffer *buffer,
3299                                  unsigned long payload)
3300 {
3301         struct descriptor *d;
3302         dma_addr_t d_bus, page_bus;
3303         int page, offset, rest, z, i, length;
3304
3305         page   = payload >> PAGE_SHIFT;
3306         offset = payload & ~PAGE_MASK;
3307         rest   = packet->payload_length;
3308
3309         /* We need one descriptor for each page in the buffer. */
3310         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3311
3312         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3313                 return -EFAULT;
3314
3315         for (i = 0; i < z; i++) {
3316                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3317                 if (d == NULL)
3318                         return -ENOMEM;
3319
3320                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3321                                          DESCRIPTOR_BRANCH_ALWAYS);
3322                 if (packet->skip && i == 0)
3323                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3324                 if (packet->interrupt && i == z - 1)
3325                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3326
3327                 if (offset + rest < PAGE_SIZE)
3328                         length = rest;
3329                 else
3330                         length = PAGE_SIZE - offset;
3331                 d->req_count = cpu_to_le16(length);
3332                 d->res_count = d->req_count;
3333                 d->transfer_status = 0;
3334
3335                 page_bus = page_private(buffer->pages[page]);
3336                 d->data_address = cpu_to_le32(page_bus + offset);
3337
3338                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3339                                                  page_bus, offset, length,
3340                                                  DMA_FROM_DEVICE);
3341
3342                 rest -= length;
3343                 offset = 0;
3344                 page++;
3345
3346                 context_append(&ctx->context, d, 1, 0);
3347         }
3348
3349         return 0;
3350 }
3351
3352 static int ohci_queue_iso(struct fw_iso_context *base,
3353                           struct fw_iso_packet *packet,
3354                           struct fw_iso_buffer *buffer,
3355                           unsigned long payload)
3356 {
3357         struct iso_context *ctx = container_of(base, struct iso_context, base);
3358         unsigned long flags;
3359         int ret = -ENOSYS;
3360
3361         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3362         switch (base->type) {
3363         case FW_ISO_CONTEXT_TRANSMIT:
3364                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3365                 break;
3366         case FW_ISO_CONTEXT_RECEIVE:
3367                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3368                 break;
3369         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3370                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3371                 break;
3372         }
3373         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3374
3375         return ret;
3376 }
3377
3378 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3379 {
3380         struct context *ctx =
3381                         &container_of(base, struct iso_context, base)->context;
3382
3383         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3384 }
3385
3386 static const struct fw_card_driver ohci_driver = {
3387         .enable                 = ohci_enable,
3388         .read_phy_reg           = ohci_read_phy_reg,
3389         .update_phy_reg         = ohci_update_phy_reg,
3390         .set_config_rom         = ohci_set_config_rom,
3391         .send_request           = ohci_send_request,
3392         .send_response          = ohci_send_response,
3393         .cancel_packet          = ohci_cancel_packet,
3394         .enable_phys_dma        = ohci_enable_phys_dma,
3395         .read_csr               = ohci_read_csr,
3396         .write_csr              = ohci_write_csr,
3397
3398         .allocate_iso_context   = ohci_allocate_iso_context,
3399         .free_iso_context       = ohci_free_iso_context,
3400         .set_iso_channels       = ohci_set_iso_channels,
3401         .queue_iso              = ohci_queue_iso,
3402         .flush_queue_iso        = ohci_flush_queue_iso,
3403         .start_iso              = ohci_start_iso,
3404         .stop_iso               = ohci_stop_iso,
3405 };
3406
3407 #ifdef CONFIG_PPC_PMAC
3408 static void pmac_ohci_on(struct pci_dev *dev)
3409 {
3410         if (machine_is(powermac)) {
3411                 struct device_node *ofn = pci_device_to_OF_node(dev);
3412
3413                 if (ofn) {
3414                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3415                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3416                 }
3417         }
3418 }
3419
3420 static void pmac_ohci_off(struct pci_dev *dev)
3421 {
3422         if (machine_is(powermac)) {
3423                 struct device_node *ofn = pci_device_to_OF_node(dev);
3424
3425                 if (ofn) {
3426                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3427                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3428                 }
3429         }
3430 }
3431 #else
3432 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3433 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3434 #endif /* CONFIG_PPC_PMAC */
3435
3436 static int __devinit pci_probe(struct pci_dev *dev,
3437                                const struct pci_device_id *ent)
3438 {
3439         struct fw_ohci *ohci;
3440         u32 bus_options, max_receive, link_speed, version;
3441         u64 guid;
3442         int i, err;
3443         size_t size;
3444
3445         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3446                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3447                 return -ENOSYS;
3448         }
3449
3450         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3451         if (ohci == NULL) {
3452                 err = -ENOMEM;
3453                 goto fail;
3454         }
3455
3456         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3457
3458         pmac_ohci_on(dev);
3459
3460         err = pci_enable_device(dev);
3461         if (err) {
3462                 fw_error("Failed to enable OHCI hardware\n");
3463                 goto fail_free;
3464         }
3465
3466         pci_set_master(dev);
3467         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3468         pci_set_drvdata(dev, ohci);
3469
3470         spin_lock_init(&ohci->lock);
3471         mutex_init(&ohci->phy_reg_mutex);
3472
3473         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3474
3475         err = pci_request_region(dev, 0, ohci_driver_name);
3476         if (err) {
3477                 fw_error("MMIO resource unavailable\n");
3478                 goto fail_disable;
3479         }
3480
3481         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3482         if (ohci->registers == NULL) {
3483                 fw_error("Failed to remap registers\n");
3484                 err = -ENXIO;
3485                 goto fail_iomem;
3486         }
3487
3488         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3489                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3490                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3491                      ohci_quirks[i].device == dev->device) &&
3492                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3493                      ohci_quirks[i].revision >= dev->revision)) {
3494                         ohci->quirks = ohci_quirks[i].flags;
3495                         break;
3496                 }
3497         if (param_quirks)
3498                 ohci->quirks = param_quirks;
3499
3500         /*
3501          * Because dma_alloc_coherent() allocates at least one page,
3502          * we save space by using a common buffer for the AR request/
3503          * response descriptors and the self IDs buffer.
3504          */
3505         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3506         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3507         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3508                                                PAGE_SIZE,
3509                                                &ohci->misc_buffer_bus,
3510                                                GFP_KERNEL);
3511         if (!ohci->misc_buffer) {
3512                 err = -ENOMEM;
3513                 goto fail_iounmap;
3514         }
3515
3516         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3517                               OHCI1394_AsReqRcvContextControlSet);
3518         if (err < 0)
3519                 goto fail_misc_buf;
3520
3521         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3522                               OHCI1394_AsRspRcvContextControlSet);
3523         if (err < 0)
3524                 goto fail_arreq_ctx;
3525
3526         err = context_init(&ohci->at_request_ctx, ohci,
3527                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3528         if (err < 0)
3529                 goto fail_arrsp_ctx;
3530
3531         err = context_init(&ohci->at_response_ctx, ohci,
3532                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3533         if (err < 0)
3534                 goto fail_atreq_ctx;
3535
3536         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3537         ohci->ir_context_channels = ~0ULL;
3538         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3539         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3540         ohci->ir_context_mask = ohci->ir_context_support;
3541         ohci->n_ir = hweight32(ohci->ir_context_mask);
3542         size = sizeof(struct iso_context) * ohci->n_ir;
3543         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3544
3545         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3546         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3547         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3548         ohci->it_context_mask = ohci->it_context_support;
3549         ohci->n_it = hweight32(ohci->it_context_mask);
3550         size = sizeof(struct iso_context) * ohci->n_it;
3551         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3552
3553         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3554                 err = -ENOMEM;
3555                 goto fail_contexts;
3556         }
3557
3558         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3559         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3560
3561         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3562         max_receive = (bus_options >> 12) & 0xf;
3563         link_speed = bus_options & 0x7;
3564         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3565                 reg_read(ohci, OHCI1394_GUIDLo);
3566
3567         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3568         if (err)
3569                 goto fail_contexts;
3570
3571         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3572         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3573                   "%d IR + %d IT contexts, quirks 0x%x\n",
3574                   dev_name(&dev->dev), version >> 16, version & 0xff,
3575                   ohci->n_ir, ohci->n_it, ohci->quirks);
3576
3577         return 0;
3578
3579  fail_contexts:
3580         kfree(ohci->ir_context_list);
3581         kfree(ohci->it_context_list);
3582         context_release(&ohci->at_response_ctx);
3583  fail_atreq_ctx:
3584         context_release(&ohci->at_request_ctx);
3585  fail_arrsp_ctx:
3586         ar_context_release(&ohci->ar_response_ctx);
3587  fail_arreq_ctx:
3588         ar_context_release(&ohci->ar_request_ctx);
3589  fail_misc_buf:
3590         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3591                           ohci->misc_buffer, ohci->misc_buffer_bus);
3592  fail_iounmap:
3593         pci_iounmap(dev, ohci->registers);
3594  fail_iomem:
3595         pci_release_region(dev, 0);
3596  fail_disable:
3597         pci_disable_device(dev);
3598  fail_free:
3599         kfree(ohci);
3600         pmac_ohci_off(dev);
3601  fail:
3602         if (err == -ENOMEM)
3603                 fw_error("Out of memory\n");
3604
3605         return err;
3606 }
3607
3608 static void pci_remove(struct pci_dev *dev)
3609 {
3610         struct fw_ohci *ohci;
3611
3612         ohci = pci_get_drvdata(dev);
3613         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3614         flush_writes(ohci);
3615         cancel_work_sync(&ohci->bus_reset_work);
3616         fw_core_remove_card(&ohci->card);
3617
3618         /*
3619          * FIXME: Fail all pending packets here, now that the upper
3620          * layers can't queue any more.
3621          */
3622
3623         software_reset(ohci);
3624         free_irq(dev->irq, ohci);
3625
3626         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3627                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3628                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3629         if (ohci->config_rom)
3630                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3631                                   ohci->config_rom, ohci->config_rom_bus);
3632         ar_context_release(&ohci->ar_request_ctx);
3633         ar_context_release(&ohci->ar_response_ctx);
3634         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3635                           ohci->misc_buffer, ohci->misc_buffer_bus);
3636         context_release(&ohci->at_request_ctx);
3637         context_release(&ohci->at_response_ctx);
3638         kfree(ohci->it_context_list);
3639         kfree(ohci->ir_context_list);
3640         pci_disable_msi(dev);
3641         pci_iounmap(dev, ohci->registers);
3642         pci_release_region(dev, 0);
3643         pci_disable_device(dev);
3644         kfree(ohci);
3645         pmac_ohci_off(dev);
3646
3647         fw_notify("Removed fw-ohci device.\n");
3648 }
3649
3650 #ifdef CONFIG_PM
3651 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3652 {
3653         struct fw_ohci *ohci = pci_get_drvdata(dev);
3654         int err;
3655
3656         software_reset(ohci);
3657         free_irq(dev->irq, ohci);
3658         pci_disable_msi(dev);
3659         err = pci_save_state(dev);
3660         if (err) {
3661                 fw_error("pci_save_state failed\n");
3662                 return err;
3663         }
3664         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3665         if (err)
3666                 fw_error("pci_set_power_state failed with %d\n", err);
3667         pmac_ohci_off(dev);
3668
3669         return 0;
3670 }
3671
3672 static int pci_resume(struct pci_dev *dev)
3673 {
3674         struct fw_ohci *ohci = pci_get_drvdata(dev);
3675         int err;
3676
3677         pmac_ohci_on(dev);
3678         pci_set_power_state(dev, PCI_D0);
3679         pci_restore_state(dev);
3680         err = pci_enable_device(dev);
3681         if (err) {
3682                 fw_error("pci_enable_device failed\n");
3683                 return err;
3684         }
3685
3686         /* Some systems don't setup GUID register on resume from ram  */
3687         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3688                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3689                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3690                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3691         }
3692
3693         err = ohci_enable(&ohci->card, NULL, 0);
3694         if (err)
3695                 return err;
3696
3697         ohci_resume_iso_dma(ohci);
3698
3699         return 0;
3700 }
3701 #endif
3702
3703 static const struct pci_device_id pci_table[] = {
3704         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3705         { }
3706 };
3707
3708 MODULE_DEVICE_TABLE(pci, pci_table);
3709
3710 static struct pci_driver fw_ohci_pci_driver = {
3711         .name           = ohci_driver_name,
3712         .id_table       = pci_table,
3713         .probe          = pci_probe,
3714         .remove         = pci_remove,
3715 #ifdef CONFIG_PM
3716         .resume         = pci_resume,
3717         .suspend        = pci_suspend,
3718 #endif
3719 };
3720
3721 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3722 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3723 MODULE_LICENSE("GPL");
3724
3725 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3726 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3727 MODULE_ALIAS("ohci1394");
3728 #endif
3729
3730 static int __init fw_ohci_init(void)
3731 {
3732         return pci_register_driver(&fw_ohci_pci_driver);
3733 }
3734
3735 static void __exit fw_ohci_cleanup(void)
3736 {
3737         pci_unregister_driver(&fw_ohci_pci_driver);
3738 }
3739
3740 module_init(fw_ohci_init);
3741 module_exit(fw_ohci_cleanup);