drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gfp.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/pci.h>
  32 #include <linux/spinlock.h>
  33
  34 #include <asm/page.h>
  35 #include <asm/system.h>
  36
  37 #ifdef CONFIG_PPC_PMAC
  38 #include <asm/pmac_feature.h>
  39 #endif
  40
  41 #include "fw-ohci.h"
  42 #include "fw-transaction.h"
  43
  44 #define DESCRIPTOR_OUTPUT_MORE          0
  45 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  46 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  47 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  48 #define DESCRIPTOR_STATUS               (1 << 11)
  49 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  50 #define DESCRIPTOR_PING                 (1 << 7)
  51 #define DESCRIPTOR_YY                   (1 << 6)
  52 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  53 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  54 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  55 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  56 #define DESCRIPTOR_WAIT                 (3 << 0)
  57
  58 struct descriptor {
  59         __le16 req_count;
  60         __le16 control;
  61         __le32 data_address;
  62         __le32 branch_address;
  63         __le16 res_count;
  64         __le16 transfer_status;
  65 } __attribute__((aligned(16)));
  66
  67 struct db_descriptor {
  68         __le16 first_size;
  69         __le16 control;
  70         __le16 second_req_count;
  71         __le16 first_req_count;
  72         __le32 branch_address;
  73         __le16 second_res_count;
  74         __le16 first_res_count;
  75         __le32 reserved0;
  76         __le32 first_buffer;
  77         __le32 second_buffer;
  78         __le32 reserved1;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 struct ar_buffer {
  87         struct descriptor descriptor;
  88         struct ar_buffer *next;
  89         __le32 data[0];
  90 };
  91
  92 struct ar_context {
  93         struct fw_ohci *ohci;
  94         struct ar_buffer *current_buffer;
  95         struct ar_buffer *last_buffer;
  96         void *pointer;
  97         u32 regs;
  98         struct tasklet_struct tasklet;
  99 };
 100
 101 struct context;
 102
 103 typedef int (*descriptor_callback_t)(struct context *ctx,
 104                                      struct descriptor *d,
 105                                      struct descriptor *last);
 106
 107 /*
 108  * A buffer that contains a block of DMA-able coherent memory used for
 109  * storing a portion of a DMA descriptor program.
 110  */
 111 struct descriptor_buffer {
 112         struct list_head list;
 113         dma_addr_t buffer_bus;
 114         size_t buffer_size;
 115         size_t used;
 116         struct descriptor buffer[0];
 117 };
 118
 119 struct context {
 120         struct fw_ohci *ohci;
 121         u32 regs;
 122         int total_allocation;
 123
 124         /*
 125          * List of page-sized buffers for storing DMA descriptors.
 126          * Head of list contains buffers in use and tail of list contains
 127          * free buffers.
 128          */
 129         struct list_head buffer_list;
 130
 131         /*
 132          * Pointer to a buffer inside buffer_list that contains the tail
 133          * end of the current DMA program.
 134          */
 135         struct descriptor_buffer *buffer_tail;
 136
 137         /*
 138          * The descriptor containing the branch address of the first
 139          * descriptor that has not yet been filled by the device.
 140          */
 141         struct descriptor *last;
 142
 143         /*
 144          * The last descriptor in the DMA program.  It contains the branch
 145          * address that must be updated upon appending a new descriptor.
 146          */
 147         struct descriptor *prev;
 148
 149         descriptor_callback_t callback;
 150
 151         struct tasklet_struct tasklet;
 152 };
 153
 154 #define IT_HEADER_SY(v)          ((v) <<  0)
 155 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 156 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 157 #define IT_HEADER_TAG(v)         ((v) << 14)
 158 #define IT_HEADER_SPEED(v)       ((v) << 16)
 159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 160
 161 struct iso_context {
 162         struct fw_iso_context base;
 163         struct context context;
 164         int excess_bytes;
 165         void *header;
 166         size_t header_length;
 167 };
 168
 169 #define CONFIG_ROM_SIZE 1024
 170
 171 struct fw_ohci {
 172         struct fw_card card;
 173
 174         u32 version;
 175         __iomem char *registers;
 176         dma_addr_t self_id_bus;
 177         __le32 *self_id_cpu;
 178         struct tasklet_struct bus_reset_tasklet;
 179         int node_id;
 180         int generation;
 181         int request_generation; /* for timestamping incoming requests */
 182         u32 bus_seconds;
 183         bool old_uninorth;
 184         bool bus_reset_packet_quirk;
 185
 186         /*
 187          * Spinlock for accessing fw_ohci data.  Never call out of
 188          * this driver with this lock held.
 189          */
 190         spinlock_t lock;
 191         u32 self_id_buffer[512];
 192
 193         /* Config rom buffers */
 194         __be32 *config_rom;
 195         dma_addr_t config_rom_bus;
 196         __be32 *next_config_rom;
 197         dma_addr_t next_config_rom_bus;
 198         u32 next_header;
 199
 200         struct ar_context ar_request_ctx;
 201         struct ar_context ar_response_ctx;
 202         struct context at_request_ctx;
 203         struct context at_response_ctx;
 204
 205         u32 it_context_mask;
 206         struct iso_context *it_context_list;
 207         u32 ir_context_mask;
 208         struct iso_context *ir_context_list;
 209 };
 210
 211 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 212 {
 213         return container_of(card, struct fw_ohci, card);
 214 }
 215
 216 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 217 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 218 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 219 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 220 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 221 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 222
 223 #define CONTEXT_RUN     0x8000
 224 #define CONTEXT_WAKE    0x1000
 225 #define CONTEXT_DEAD    0x0800
 226 #define CONTEXT_ACTIVE  0x0400
 227
 228 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 229 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 230 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 231
 232 #define FW_OHCI_MAJOR                   240
 233 #define OHCI1394_REGISTER_SIZE          0x800
 234 #define OHCI_LOOP_COUNT                 500
 235 #define OHCI1394_PCI_HCI_Control        0x40
 236 #define SELF_ID_BUF_SIZE                0x800
 237 #define OHCI_TCODE_PHY_PACKET           0x0e
 238 #define OHCI_VERSION_1_1                0x010010
 239
 240 static char ohci_driver_name[] = KBUILD_MODNAME;
 241
 242 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 243
 244 #define OHCI_PARAM_DEBUG_AT_AR          1
 245 #define OHCI_PARAM_DEBUG_SELFIDS        2
 246 #define OHCI_PARAM_DEBUG_IRQS           4
 247 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 248
 249 static int param_debug;
 250 module_param_named(debug, param_debug, int, 0644);
 251 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 252         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 253         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 254         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 255         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 256         ", or a combination, or all = -1)");
 257
 258 static void log_irqs(u32 evt)
 259 {
 260         if (likely(!(param_debug &
 261                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 262                 return;
 263
 264         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 265             !(evt & OHCI1394_busReset))
 266                 return;
 267
 268         printk(KERN_DEBUG KBUILD_MODNAME ": IRQ "
 269                "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 270                evt,
 271                evt & OHCI1394_selfIDComplete    ? " selfID"             : "",
 272                evt & OHCI1394_RQPkt             ? " AR_req"             : "",
 273                evt & OHCI1394_RSPkt             ? " AR_resp"            : "",
 274                evt & OHCI1394_reqTxComplete     ? " AT_req"             : "",
 275                evt & OHCI1394_respTxComplete    ? " AT_resp"            : "",
 276                evt & OHCI1394_isochRx           ? " IR"                 : "",
 277                evt & OHCI1394_isochTx           ? " IT"                 : "",
 278                evt & OHCI1394_postedWriteErr    ? " postedWriteErr"     : "",
 279                evt & OHCI1394_cycleTooLong      ? " cycleTooLong"       : "",
 280                evt & OHCI1394_cycle64Seconds    ? " cycle64Seconds"     : "",
 281                evt & OHCI1394_regAccessFail     ? " regAccessFail"      : "",
 282                evt & OHCI1394_busReset          ? " busReset"           : "",
 283                evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 284                        OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 285                        OHCI1394_respTxComplete | OHCI1394_isochRx |
 286                        OHCI1394_isochTx | OHCI1394_postedWriteErr |
 287                        OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 288                        OHCI1394_regAccessFail | OHCI1394_busReset)
 289                                                 ? " ?"                  : "");
 290 }
 291
 292 static const char *speed[] = {
 293         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 294 };
 295 static const char *power[] = {
 296         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 297         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 298 };
 299 static const char port[] = { '.', '-', 'p', 'c', };
 300
 301 static char _p(u32 *s, int shift)
 302 {
 303         return port[*s >> shift & 3];
 304 }
 305
 306 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 307 {
 308         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 309                 return;
 310
 311         printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d, "
 312                "local node ID %04x\n", self_id_count, generation, node_id);
 313
 314         for (; self_id_count--; ++s)
 315                 if ((*s & 1 << 23) == 0)
 316                         printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
 317                                "%s gc=%d %s %s%s%s\n",
 318                                *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 319                                speed[*s >> 14 & 3], *s >> 16 & 63,
 320                                power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 321                                *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 322                 else
 323                         printk(KERN_DEBUG "selfID n: %08x, phy %d "
 324                                "[%c%c%c%c%c%c%c%c]\n",
 325                                *s, *s >> 24 & 63,
 326                                _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 327                                _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 328 }
 329
 330 static const char *evts[] = {
 331         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 332         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 333         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 334         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 335         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 336         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 337         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 338         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 339         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 340         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 341         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 342         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 343         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 344         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 345         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 346         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 347         [0x20] = "pending/cancelled",
 348 };
 349 static const char *tcodes[] = {
 350         [0x0] = "QW req",               [0x1] = "BW req",
 351         [0x2] = "W resp",               [0x3] = "-reserved-",
 352         [0x4] = "QR req",               [0x5] = "BR req",
 353         [0x6] = "QR resp",              [0x7] = "BR resp",
 354         [0x8] = "cycle start",          [0x9] = "Lk req",
 355         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 356         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 357         [0xe] = "link internal",        [0xf] = "-reserved-",
 358 };
 359 static const char *phys[] = {
 360         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 361         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 362 };
 363
 364 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 365 {
 366         int tcode = header[0] >> 4 & 0xf;
 367         char specific[12];
 368
 369         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 370                 return;
 371
 372         if (unlikely(evt >= ARRAY_SIZE(evts)))
 373                         evt = 0x1f;
 374
 375         if (evt == OHCI1394_evt_bus_reset) {
 376                 printk(KERN_DEBUG "A%c evt_bus_reset, generation %d\n",
 377                        dir, (header[2] >> 16) & 0xff);
 378                 return;
 379         }
 380
 381         if (header[0] == ~header[1]) {
 382                 printk(KERN_DEBUG "A%c %s, %s, %08x\n",
 383                        dir, evts[evt], phys[header[0] >> 30 & 0x3],
 384                        header[0]);
 385                 return;
 386         }
 387
 388         switch (tcode) {
 389         case 0x0: case 0x6: case 0x8:
 390                 snprintf(specific, sizeof(specific), " = %08x",
 391                          be32_to_cpu((__force __be32)header[3]));
 392                 break;
 393         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 394                 snprintf(specific, sizeof(specific), " %x,%x",
 395                          header[3] >> 16, header[3] & 0xffff);
 396                 break;
 397         default:
 398                 specific[0] = '\0';
 399         }
 400
 401         switch (tcode) {
 402         case 0xe: case 0xa:
 403                 printk(KERN_DEBUG "A%c %s, %s\n",
 404                        dir, evts[evt], tcodes[tcode]);
 405                 break;
 406         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 407                 printk(KERN_DEBUG "A%c spd %x tl %02x, "
 408                        "%04x -> %04x, %s, "
 409                        "%s, %04x%08x%s\n",
 410                        dir, speed, header[0] >> 10 & 0x3f,
 411                        header[1] >> 16, header[0] >> 16, evts[evt],
 412                        tcodes[tcode], header[1] & 0xffff, header[2], specific);
 413                 break;
 414         default:
 415                 printk(KERN_DEBUG "A%c spd %x tl %02x, "
 416                        "%04x -> %04x, %s, "
 417                        "%s%s\n",
 418                        dir, speed, header[0] >> 10 & 0x3f,
 419                        header[1] >> 16, header[0] >> 16, evts[evt],
 420                        tcodes[tcode], specific);
 421         }
 422 }
 423
 424 #else
 425
 426 #define log_irqs(evt)
 427 #define log_selfids(node_id, generation, self_id_count, sid)
 428 #define log_ar_at_event(dir, speed, header, evt)
 429
 430 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 431
 432 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 433 {
 434         writel(data, ohci->registers + offset);
 435 }
 436
 437 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 438 {
 439         return readl(ohci->registers + offset);
 440 }
 441
 442 static inline void flush_writes(const struct fw_ohci *ohci)
 443 {
 444         /* Do a dummy read to flush writes. */
 445         reg_read(ohci, OHCI1394_Version);
 446 }
 447
 448 static int
 449 ohci_update_phy_reg(struct fw_card *card, int addr,
 450                     int clear_bits, int set_bits)
 451 {
 452         struct fw_ohci *ohci = fw_ohci(card);
 453         u32 val, old;
 454
 455         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 456         flush_writes(ohci);
 457         msleep(2);
 458         val = reg_read(ohci, OHCI1394_PhyControl);
 459         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 460                 fw_error("failed to set phy reg bits.\n");
 461                 return -EBUSY;
 462         }
 463
 464         old = OHCI1394_PhyControl_ReadData(val);
 465         old = (old & ~clear_bits) | set_bits;
 466         reg_write(ohci, OHCI1394_PhyControl,
 467                   OHCI1394_PhyControl_Write(addr, old));
 468
 469         return 0;
 470 }
 471
 472 static int ar_context_add_page(struct ar_context *ctx)
 473 {
 474         struct device *dev = ctx->ohci->card.device;
 475         struct ar_buffer *ab;
 476         dma_addr_t uninitialized_var(ab_bus);
 477         size_t offset;
 478
 479         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 480         if (ab == NULL)
 481                 return -ENOMEM;
 482
 483         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 484         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 485                                                     DESCRIPTOR_STATUS |
 486                                                     DESCRIPTOR_BRANCH_ALWAYS);
 487         offset = offsetof(struct ar_buffer, data);
 488         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 489         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 490         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 491         ab->descriptor.branch_address = 0;
 492
 493         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 494         ctx->last_buffer->next = ab;
 495         ctx->last_buffer = ab;
 496
 497         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 498         flush_writes(ctx->ohci);
 499
 500         return 0;
 501 }
 502
 503 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 504 #define cond_le32_to_cpu(v) \
 505         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
 506 #else
 507 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 508 #endif
 509
 510 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 511 {
 512         struct fw_ohci *ohci = ctx->ohci;
 513         struct fw_packet p;
 514         u32 status, length, tcode;
 515         int evt;
 516
 517         p.header[0] = cond_le32_to_cpu(buffer[0]);
 518         p.header[1] = cond_le32_to_cpu(buffer[1]);
 519         p.header[2] = cond_le32_to_cpu(buffer[2]);
 520
 521         tcode = (p.header[0] >> 4) & 0x0f;
 522         switch (tcode) {
 523         case TCODE_WRITE_QUADLET_REQUEST:
 524         case TCODE_READ_QUADLET_RESPONSE:
 525                 p.header[3] = (__force __u32) buffer[3];
 526                 p.header_length = 16;
 527                 p.payload_length = 0;
 528                 break;
 529
 530         case TCODE_READ_BLOCK_REQUEST :
 531                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 532                 p.header_length = 16;
 533                 p.payload_length = 0;
 534                 break;
 535
 536         case TCODE_WRITE_BLOCK_REQUEST:
 537         case TCODE_READ_BLOCK_RESPONSE:
 538         case TCODE_LOCK_REQUEST:
 539         case TCODE_LOCK_RESPONSE:
 540                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 541                 p.header_length = 16;
 542                 p.payload_length = p.header[3] >> 16;
 543                 break;
 544
 545         case TCODE_WRITE_RESPONSE:
 546         case TCODE_READ_QUADLET_REQUEST:
 547         case OHCI_TCODE_PHY_PACKET:
 548                 p.header_length = 12;
 549                 p.payload_length = 0;
 550                 break;
 551
 552         default:
 553                 /* FIXME: Stop context, discard everything, and restart? */
 554                 p.header_length = 0;
 555                 p.payload_length = 0;
 556         }
 557
 558         p.payload = (void *) buffer + p.header_length;
 559
 560         /* FIXME: What to do about evt_* errors? */
 561         length = (p.header_length + p.payload_length + 3) / 4;
 562         status = cond_le32_to_cpu(buffer[length]);
 563         evt    = (status >> 16) & 0x1f;
 564
 565         p.ack        = evt - 16;
 566         p.speed      = (status >> 21) & 0x7;
 567         p.timestamp  = status & 0xffff;
 568         p.generation = ohci->request_generation;
 569
 570         log_ar_at_event('R', p.speed, p.header, evt);
 571
 572         /*
 573          * The OHCI bus reset handler synthesizes a phy packet with
 574          * the new generation number when a bus reset happens (see
 575          * section 8.4.2.3).  This helps us determine when a request
 576          * was received and make sure we send the response in the same
 577          * generation.  We only need this for requests; for responses
 578          * we use the unique tlabel for finding the matching
 579          * request.
 580          *
 581          * Alas some chips sometimes emit bus reset packets with a
 582          * wrong generation.  We set the correct generation for these
 583          * at a slightly incorrect time (in bus_reset_tasklet).
 584          */
 585         if (evt == OHCI1394_evt_bus_reset) {
 586                 if (!ohci->bus_reset_packet_quirk)
 587                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 588         } else if (ctx == &ohci->ar_request_ctx) {
 589                 fw_core_handle_request(&ohci->card, &p);
 590         } else {
 591                 fw_core_handle_response(&ohci->card, &p);
 592         }
 593
 594         return buffer + length + 1;
 595 }
 596
 597 static void ar_context_tasklet(unsigned long data)
 598 {
 599         struct ar_context *ctx = (struct ar_context *)data;
 600         struct fw_ohci *ohci = ctx->ohci;
 601         struct ar_buffer *ab;
 602         struct descriptor *d;
 603         void *buffer, *end;
 604
 605         ab = ctx->current_buffer;
 606         d = &ab->descriptor;
 607
 608         if (d->res_count == 0) {
 609                 size_t size, rest, offset;
 610                 dma_addr_t start_bus;
 611                 void *start;
 612
 613                 /*
 614                  * This descriptor is finished and we may have a
 615                  * packet split across this and the next buffer. We
 616                  * reuse the page for reassembling the split packet.
 617                  */
 618
 619                 offset = offsetof(struct ar_buffer, data);
 620                 start = buffer = ab;
 621                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 622
 623                 ab = ab->next;
 624                 d = &ab->descriptor;
 625                 size = buffer + PAGE_SIZE - ctx->pointer;
 626                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 627                 memmove(buffer, ctx->pointer, size);
 628                 memcpy(buffer + size, ab->data, rest);
 629                 ctx->current_buffer = ab;
 630                 ctx->pointer = (void *) ab->data + rest;
 631                 end = buffer + size + rest;
 632
 633                 while (buffer < end)
 634                         buffer = handle_ar_packet(ctx, buffer);
 635
 636                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
 637                                   start, start_bus);
 638                 ar_context_add_page(ctx);
 639         } else {
 640                 buffer = ctx->pointer;
 641                 ctx->pointer = end =
 642                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 643
 644                 while (buffer < end)
 645                         buffer = handle_ar_packet(ctx, buffer);
 646         }
 647 }
 648
 649 static int
 650 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 651 {
 652         struct ar_buffer ab;
 653
 654         ctx->regs        = regs;
 655         ctx->ohci        = ohci;
 656         ctx->last_buffer = &ab;
 657         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 658
 659         ar_context_add_page(ctx);
 660         ar_context_add_page(ctx);
 661         ctx->current_buffer = ab.next;
 662         ctx->pointer = ctx->current_buffer->data;
 663
 664         return 0;
 665 }
 666
 667 static void ar_context_run(struct ar_context *ctx)
 668 {
 669         struct ar_buffer *ab = ctx->current_buffer;
 670         dma_addr_t ab_bus;
 671         size_t offset;
 672
 673         offset = offsetof(struct ar_buffer, data);
 674         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 675
 676         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 677         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 678         flush_writes(ctx->ohci);
 679 }
 680
 681 static struct descriptor *
 682 find_branch_descriptor(struct descriptor *d, int z)
 683 {
 684         int b, key;
 685
 686         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 687         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 688
 689         /* figure out which descriptor the branch address goes in */
 690         if (z == 2 && (b == 3 || key == 2))
 691                 return d;
 692         else
 693                 return d + z - 1;
 694 }
 695
 696 static void context_tasklet(unsigned long data)
 697 {
 698         struct context *ctx = (struct context *) data;
 699         struct descriptor *d, *last;
 700         u32 address;
 701         int z;
 702         struct descriptor_buffer *desc;
 703
 704         desc = list_entry(ctx->buffer_list.next,
 705                         struct descriptor_buffer, list);
 706         last = ctx->last;
 707         while (last->branch_address != 0) {
 708                 struct descriptor_buffer *old_desc = desc;
 709                 address = le32_to_cpu(last->branch_address);
 710                 z = address & 0xf;
 711                 address &= ~0xf;
 712
 713                 /* If the branch address points to a buffer outside of the
 714                  * current buffer, advance to the next buffer. */
 715                 if (address < desc->buffer_bus ||
 716                                 address >= desc->buffer_bus + desc->used)
 717                         desc = list_entry(desc->list.next,
 718                                         struct descriptor_buffer, list);
 719                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 720                 last = find_branch_descriptor(d, z);
 721
 722                 if (!ctx->callback(ctx, d, last))
 723                         break;
 724
 725                 if (old_desc != desc) {
 726                         /* If we've advanced to the next buffer, move the
 727                          * previous buffer to the free list. */
 728                         unsigned long flags;
 729                         old_desc->used = 0;
 730                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 731                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 732                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 733                 }
 734                 ctx->last = last;
 735         }
 736 }
 737
 738 /*
 739  * Allocate a new buffer and add it to the list of free buffers for this
 740  * context.  Must be called with ohci->lock held.
 741  */
 742 static int
 743 context_add_buffer(struct context *ctx)
 744 {
 745         struct descriptor_buffer *desc;
 746         dma_addr_t uninitialized_var(bus_addr);
 747         int offset;
 748
 749         /*
 750          * 16MB of descriptors should be far more than enough for any DMA
 751          * program.  This will catch run-away userspace or DoS attacks.
 752          */
 753         if (ctx->total_allocation >= 16*1024*1024)
 754                 return -ENOMEM;
 755
 756         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 757                         &bus_addr, GFP_ATOMIC);
 758         if (!desc)
 759                 return -ENOMEM;
 760
 761         offset = (void *)&desc->buffer - (void *)desc;
 762         desc->buffer_size = PAGE_SIZE - offset;
 763         desc->buffer_bus = bus_addr + offset;
 764         desc->used = 0;
 765
 766         list_add_tail(&desc->list, &ctx->buffer_list);
 767         ctx->total_allocation += PAGE_SIZE;
 768
 769         return 0;
 770 }
 771
 772 static int
 773 context_init(struct context *ctx, struct fw_ohci *ohci,
 774              u32 regs, descriptor_callback_t callback)
 775 {
 776         ctx->ohci = ohci;
 777         ctx->regs = regs;
 778         ctx->total_allocation = 0;
 779
 780         INIT_LIST_HEAD(&ctx->buffer_list);
 781         if (context_add_buffer(ctx) < 0)
 782                 return -ENOMEM;
 783
 784         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 785                         struct descriptor_buffer, list);
 786
 787         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 788         ctx->callback = callback;
 789
 790         /*
 791          * We put a dummy descriptor in the buffer that has a NULL
 792          * branch address and looks like it's been sent.  That way we
 793          * have a descriptor to append DMA programs to.
 794          */
 795         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 796         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 797         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 798         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 799         ctx->last = ctx->buffer_tail->buffer;
 800         ctx->prev = ctx->buffer_tail->buffer;
 801
 802         return 0;
 803 }
 804
 805 static void
 806 context_release(struct context *ctx)
 807 {
 808         struct fw_card *card = &ctx->ohci->card;
 809         struct descriptor_buffer *desc, *tmp;
 810
 811         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 812                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 813                         desc->buffer_bus -
 814                         ((void *)&desc->buffer - (void *)desc));
 815 }
 816
 817 /* Must be called with ohci->lock held */
 818 static struct descriptor *
 819 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 820 {
 821         struct descriptor *d = NULL;
 822         struct descriptor_buffer *desc = ctx->buffer_tail;
 823
 824         if (z * sizeof(*d) > desc->buffer_size)
 825                 return NULL;
 826
 827         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 828                 /* No room for the descriptor in this buffer, so advance to the
 829                  * next one. */
 830
 831                 if (desc->list.next == &ctx->buffer_list) {
 832                         /* If there is no free buffer next in the list,
 833                          * allocate one. */
 834                         if (context_add_buffer(ctx) < 0)
 835                                 return NULL;
 836                 }
 837                 desc = list_entry(desc->list.next,
 838                                 struct descriptor_buffer, list);
 839                 ctx->buffer_tail = desc;
 840         }
 841
 842         d = desc->buffer + desc->used / sizeof(*d);
 843         memset(d, 0, z * sizeof(*d));
 844         *d_bus = desc->buffer_bus + desc->used;
 845
 846         return d;
 847 }
 848
 849 static void context_run(struct context *ctx, u32 extra)
 850 {
 851         struct fw_ohci *ohci = ctx->ohci;
 852
 853         reg_write(ohci, COMMAND_PTR(ctx->regs),
 854                   le32_to_cpu(ctx->last->branch_address));
 855         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 856         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 857         flush_writes(ohci);
 858 }
 859
 860 static void context_append(struct context *ctx,
 861                            struct descriptor *d, int z, int extra)
 862 {
 863         dma_addr_t d_bus;
 864         struct descriptor_buffer *desc = ctx->buffer_tail;
 865
 866         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 867
 868         desc->used += (z + extra) * sizeof(*d);
 869         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 870         ctx->prev = find_branch_descriptor(d, z);
 871
 872         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 873         flush_writes(ctx->ohci);
 874 }
 875
 876 static void context_stop(struct context *ctx)
 877 {
 878         u32 reg;
 879         int i;
 880
 881         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 882         flush_writes(ctx->ohci);
 883
 884         for (i = 0; i < 10; i++) {
 885                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 886                 if ((reg & CONTEXT_ACTIVE) == 0)
 887                         break;
 888
 889                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 890                 mdelay(1);
 891         }
 892 }
 893
 894 struct driver_data {
 895         struct fw_packet *packet;
 896 };
 897
 898 /*
 899  * This function apppends a packet to the DMA queue for transmission.
 900  * Must always be called with the ochi->lock held to ensure proper
 901  * generation handling and locking around packet queue manipulation.
 902  */
 903 static int
 904 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 905 {
 906         struct fw_ohci *ohci = ctx->ohci;
 907         dma_addr_t d_bus, uninitialized_var(payload_bus);
 908         struct driver_data *driver_data;
 909         struct descriptor *d, *last;
 910         __le32 *header;
 911         int z, tcode;
 912         u32 reg;
 913
 914         d = context_get_descriptors(ctx, 4, &d_bus);
 915         if (d == NULL) {
 916                 packet->ack = RCODE_SEND_ERROR;
 917                 return -1;
 918         }
 919
 920         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 921         d[0].res_count = cpu_to_le16(packet->timestamp);
 922
 923         /*
 924          * The DMA format for asyncronous link packets is different
 925          * from the IEEE1394 layout, so shift the fields around
 926          * accordingly.  If header_length is 8, it's a PHY packet, to
 927          * which we need to prepend an extra quadlet.
 928          */
 929
 930         header = (__le32 *) &d[1];
 931         if (packet->header_length > 8) {
 932                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 933                                         (packet->speed << 16));
 934                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 935                                         (packet->header[0] & 0xffff0000));
 936                 header[2] = cpu_to_le32(packet->header[2]);
 937
 938                 tcode = (packet->header[0] >> 4) & 0x0f;
 939                 if (TCODE_IS_BLOCK_PACKET(tcode))
 940                         header[3] = cpu_to_le32(packet->header[3]);
 941                 else
 942                         header[3] = (__force __le32) packet->header[3];
 943
 944                 d[0].req_count = cpu_to_le16(packet->header_length);
 945         } else {
 946                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 947                                         (packet->speed << 16));
 948                 header[1] = cpu_to_le32(packet->header[0]);
 949                 header[2] = cpu_to_le32(packet->header[1]);
 950                 d[0].req_count = cpu_to_le16(12);
 951         }
 952
 953         driver_data = (struct driver_data *) &d[3];
 954         driver_data->packet = packet;
 955         packet->driver_data = driver_data;
 956
 957         if (packet->payload_length > 0) {
 958                 payload_bus =
 959                         dma_map_single(ohci->card.device, packet->payload,
 960                                        packet->payload_length, DMA_TO_DEVICE);
 961                 if (dma_mapping_error(payload_bus)) {
 962                         packet->ack = RCODE_SEND_ERROR;
 963                         return -1;
 964                 }
 965
 966                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 967                 d[2].data_address = cpu_to_le32(payload_bus);
 968                 last = &d[2];
 969                 z = 3;
 970         } else {
 971                 last = &d[0];
 972                 z = 2;
 973         }
 974
 975         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 976                                      DESCRIPTOR_IRQ_ALWAYS |
 977                                      DESCRIPTOR_BRANCH_ALWAYS);
 978
 979         /*
 980          * If the controller and packet generations don't match, we need to
 981          * bail out and try again.  If IntEvent.busReset is set, the AT context
 982          * is halted, so appending to the context and trying to run it is
 983          * futile.  Most controllers do the right thing and just flush the AT
 984          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
 985          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
 986          * up stalling out.  So we just bail out in software and try again
 987          * later, and everyone is happy.
 988          * FIXME: Document how the locking works.
 989          */
 990         if (ohci->generation != packet->generation ||
 991             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
 992                 if (packet->payload_length > 0)
 993                         dma_unmap_single(ohci->card.device, payload_bus,
 994                                          packet->payload_length, DMA_TO_DEVICE);
 995                 packet->ack = RCODE_GENERATION;
 996                 return -1;
 997         }
 998
 999         context_append(ctx, d, z, 4 - z);
1000
1001         /* If the context isn't already running, start it up. */
1002         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1003         if ((reg & CONTEXT_RUN) == 0)
1004                 context_run(ctx, 0);
1005
1006         return 0;
1007 }
1008
1009 static int handle_at_packet(struct context *context,
1010                             struct descriptor *d,
1011                             struct descriptor *last)
1012 {
1013         struct driver_data *driver_data;
1014         struct fw_packet *packet;
1015         struct fw_ohci *ohci = context->ohci;
1016         dma_addr_t payload_bus;
1017         int evt;
1018
1019         if (last->transfer_status == 0)
1020                 /* This descriptor isn't done yet, stop iteration. */
1021                 return 0;
1022
1023         driver_data = (struct driver_data *) &d[3];
1024         packet = driver_data->packet;
1025         if (packet == NULL)
1026                 /* This packet was cancelled, just continue. */
1027                 return 1;
1028
1029         payload_bus = le32_to_cpu(last->data_address);
1030         if (payload_bus != 0)
1031                 dma_unmap_single(ohci->card.device, payload_bus,
1032                                  packet->payload_length, DMA_TO_DEVICE);
1033
1034         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1035         packet->timestamp = le16_to_cpu(last->res_count);
1036
1037         log_ar_at_event('T', packet->speed, packet->header, evt);
1038
1039         switch (evt) {
1040         case OHCI1394_evt_timeout:
1041                 /* Async response transmit timed out. */
1042                 packet->ack = RCODE_CANCELLED;
1043                 break;
1044
1045         case OHCI1394_evt_flushed:
1046                 /*
1047                  * The packet was flushed should give same error as
1048                  * when we try to use a stale generation count.
1049                  */
1050                 packet->ack = RCODE_GENERATION;
1051                 break;
1052
1053         case OHCI1394_evt_missing_ack:
1054                 /*
1055                  * Using a valid (current) generation count, but the
1056                  * node is not on the bus or not sending acks.
1057                  */
1058                 packet->ack = RCODE_NO_ACK;
1059                 break;
1060
1061         case ACK_COMPLETE + 0x10:
1062         case ACK_PENDING + 0x10:
1063         case ACK_BUSY_X + 0x10:
1064         case ACK_BUSY_A + 0x10:
1065         case ACK_BUSY_B + 0x10:
1066         case ACK_DATA_ERROR + 0x10:
1067         case ACK_TYPE_ERROR + 0x10:
1068                 packet->ack = evt - 0x10;
1069                 break;
1070
1071         default:
1072                 packet->ack = RCODE_SEND_ERROR;
1073                 break;
1074         }
1075
1076         packet->callback(packet, &ohci->card, packet->ack);
1077
1078         return 1;
1079 }
1080
1081 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1082 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1083 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1084 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1085 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1086
1087 static void
1088 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1089 {
1090         struct fw_packet response;
1091         int tcode, length, i;
1092
1093         tcode = HEADER_GET_TCODE(packet->header[0]);
1094         if (TCODE_IS_BLOCK_PACKET(tcode))
1095                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1096         else
1097                 length = 4;
1098
1099         i = csr - CSR_CONFIG_ROM;
1100         if (i + length > CONFIG_ROM_SIZE) {
1101                 fw_fill_response(&response, packet->header,
1102                                  RCODE_ADDRESS_ERROR, NULL, 0);
1103         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1104                 fw_fill_response(&response, packet->header,
1105                                  RCODE_TYPE_ERROR, NULL, 0);
1106         } else {
1107                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1108                                  (void *) ohci->config_rom + i, length);
1109         }
1110
1111         fw_core_handle_response(&ohci->card, &response);
1112 }
1113
1114 static void
1115 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1116 {
1117         struct fw_packet response;
1118         int tcode, length, ext_tcode, sel;
1119         __be32 *payload, lock_old;
1120         u32 lock_arg, lock_data;
1121
1122         tcode = HEADER_GET_TCODE(packet->header[0]);
1123         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1124         payload = packet->payload;
1125         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1126
1127         if (tcode == TCODE_LOCK_REQUEST &&
1128             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1129                 lock_arg = be32_to_cpu(payload[0]);
1130                 lock_data = be32_to_cpu(payload[1]);
1131         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1132                 lock_arg = 0;
1133                 lock_data = 0;
1134         } else {
1135                 fw_fill_response(&response, packet->header,
1136                                  RCODE_TYPE_ERROR, NULL, 0);
1137                 goto out;
1138         }
1139
1140         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1141         reg_write(ohci, OHCI1394_CSRData, lock_data);
1142         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1143         reg_write(ohci, OHCI1394_CSRControl, sel);
1144
1145         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1146                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1147         else
1148                 fw_notify("swap not done yet\n");
1149
1150         fw_fill_response(&response, packet->header,
1151                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1152  out:
1153         fw_core_handle_response(&ohci->card, &response);
1154 }
1155
1156 static void
1157 handle_local_request(struct context *ctx, struct fw_packet *packet)
1158 {
1159         u64 offset;
1160         u32 csr;
1161
1162         if (ctx == &ctx->ohci->at_request_ctx) {
1163                 packet->ack = ACK_PENDING;
1164                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1165         }
1166
1167         offset =
1168                 ((unsigned long long)
1169                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1170                 packet->header[2];
1171         csr = offset - CSR_REGISTER_BASE;
1172
1173         /* Handle config rom reads. */
1174         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1175                 handle_local_rom(ctx->ohci, packet, csr);
1176         else switch (csr) {
1177         case CSR_BUS_MANAGER_ID:
1178         case CSR_BANDWIDTH_AVAILABLE:
1179         case CSR_CHANNELS_AVAILABLE_HI:
1180         case CSR_CHANNELS_AVAILABLE_LO:
1181                 handle_local_lock(ctx->ohci, packet, csr);
1182                 break;
1183         default:
1184                 if (ctx == &ctx->ohci->at_request_ctx)
1185                         fw_core_handle_request(&ctx->ohci->card, packet);
1186                 else
1187                         fw_core_handle_response(&ctx->ohci->card, packet);
1188                 break;
1189         }
1190
1191         if (ctx == &ctx->ohci->at_response_ctx) {
1192                 packet->ack = ACK_COMPLETE;
1193                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1194         }
1195 }
1196
1197 static void
1198 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1199 {
1200         unsigned long flags;
1201         int retval;
1202
1203         spin_lock_irqsave(&ctx->ohci->lock, flags);
1204
1205         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1206             ctx->ohci->generation == packet->generation) {
1207                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1208                 handle_local_request(ctx, packet);
1209                 return;
1210         }
1211
1212         retval = at_context_queue_packet(ctx, packet);
1213         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1214
1215         if (retval < 0)
1216                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1217
1218 }
1219
1220 static void bus_reset_tasklet(unsigned long data)
1221 {
1222         struct fw_ohci *ohci = (struct fw_ohci *)data;
1223         int self_id_count, i, j, reg;
1224         int generation, new_generation;
1225         unsigned long flags;
1226         void *free_rom = NULL;
1227         dma_addr_t free_rom_bus = 0;
1228
1229         reg = reg_read(ohci, OHCI1394_NodeID);
1230         if (!(reg & OHCI1394_NodeID_idValid)) {
1231                 fw_notify("node ID not valid, new bus reset in progress\n");
1232                 return;
1233         }
1234         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1235                 fw_notify("malconfigured bus\n");
1236                 return;
1237         }
1238         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1239                                OHCI1394_NodeID_nodeNumber);
1240
1241         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1242         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1243                 fw_notify("inconsistent self IDs\n");
1244                 return;
1245         }
1246         /*
1247          * The count in the SelfIDCount register is the number of
1248          * bytes in the self ID receive buffer.  Since we also receive
1249          * the inverted quadlets and a header quadlet, we shift one
1250          * bit extra to get the actual number of self IDs.
1251          */
1252         self_id_count = (reg >> 3) & 0x3ff;
1253         if (self_id_count == 0) {
1254                 fw_notify("inconsistent self IDs\n");
1255                 return;
1256         }
1257         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1258         rmb();
1259
1260         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1261                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1262                         fw_notify("inconsistent self IDs\n");
1263                         return;
1264                 }
1265                 ohci->self_id_buffer[j] =
1266                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1267         }
1268         rmb();
1269
1270         /*
1271          * Check the consistency of the self IDs we just read.  The
1272          * problem we face is that a new bus reset can start while we
1273          * read out the self IDs from the DMA buffer. If this happens,
1274          * the DMA buffer will be overwritten with new self IDs and we
1275          * will read out inconsistent data.  The OHCI specification
1276          * (section 11.2) recommends a technique similar to
1277          * linux/seqlock.h, where we remember the generation of the
1278          * self IDs in the buffer before reading them out and compare
1279          * it to the current generation after reading them out.  If
1280          * the two generations match we know we have a consistent set
1281          * of self IDs.
1282          */
1283
1284         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1285         if (new_generation != generation) {
1286                 fw_notify("recursive bus reset detected, "
1287                           "discarding self ids\n");
1288                 return;
1289         }
1290
1291         /* FIXME: Document how the locking works. */
1292         spin_lock_irqsave(&ohci->lock, flags);
1293
1294         ohci->generation = generation;
1295         context_stop(&ohci->at_request_ctx);
1296         context_stop(&ohci->at_response_ctx);
1297         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1298
1299         if (ohci->bus_reset_packet_quirk)
1300                 ohci->request_generation = generation;
1301
1302         /*
1303          * This next bit is unrelated to the AT context stuff but we
1304          * have to do it under the spinlock also.  If a new config rom
1305          * was set up before this reset, the old one is now no longer
1306          * in use and we can free it. Update the config rom pointers
1307          * to point to the current config rom and clear the
1308          * next_config_rom pointer so a new udpate can take place.
1309          */
1310
1311         if (ohci->next_config_rom != NULL) {
1312                 if (ohci->next_config_rom != ohci->config_rom) {
1313                         free_rom      = ohci->config_rom;
1314                         free_rom_bus  = ohci->config_rom_bus;
1315                 }
1316                 ohci->config_rom      = ohci->next_config_rom;
1317                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1318                 ohci->next_config_rom = NULL;
1319
1320                 /*
1321                  * Restore config_rom image and manually update
1322                  * config_rom registers.  Writing the header quadlet
1323                  * will indicate that the config rom is ready, so we
1324                  * do that last.
1325                  */
1326                 reg_write(ohci, OHCI1394_BusOptions,
1327                           be32_to_cpu(ohci->config_rom[2]));
1328                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1329                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1330         }
1331
1332 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1333         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1334         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1335 #endif
1336
1337         spin_unlock_irqrestore(&ohci->lock, flags);
1338
1339         if (free_rom)
1340                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1341                                   free_rom, free_rom_bus);
1342
1343         log_selfids(ohci->node_id, generation,
1344                     self_id_count, ohci->self_id_buffer);
1345
1346         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1347                                  self_id_count, ohci->self_id_buffer);
1348 }
1349
1350 static irqreturn_t irq_handler(int irq, void *data)
1351 {
1352         struct fw_ohci *ohci = data;
1353         u32 event, iso_event, cycle_time;
1354         int i;
1355
1356         event = reg_read(ohci, OHCI1394_IntEventClear);
1357
1358         if (!event || !~event)
1359                 return IRQ_NONE;
1360
1361         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1362         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1363         log_irqs(event);
1364
1365         if (event & OHCI1394_selfIDComplete)
1366                 tasklet_schedule(&ohci->bus_reset_tasklet);
1367
1368         if (event & OHCI1394_RQPkt)
1369                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1370
1371         if (event & OHCI1394_RSPkt)
1372                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1373
1374         if (event & OHCI1394_reqTxComplete)
1375                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1376
1377         if (event & OHCI1394_respTxComplete)
1378                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1379
1380         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1381         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1382
1383         while (iso_event) {
1384                 i = ffs(iso_event) - 1;
1385                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1386                 iso_event &= ~(1 << i);
1387         }
1388
1389         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1390         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1391
1392         while (iso_event) {
1393                 i = ffs(iso_event) - 1;
1394                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1395                 iso_event &= ~(1 << i);
1396         }
1397
1398         if (unlikely(event & OHCI1394_regAccessFail))
1399                 fw_error("Register access failure - "
1400                          "please notify linux1394-devel@lists.sf.net\n");
1401
1402         if (unlikely(event & OHCI1394_postedWriteErr))
1403                 fw_error("PCI posted write error\n");
1404
1405         if (unlikely(event & OHCI1394_cycleTooLong)) {
1406                 if (printk_ratelimit())
1407                         fw_notify("isochronous cycle too long\n");
1408                 reg_write(ohci, OHCI1394_LinkControlSet,
1409                           OHCI1394_LinkControl_cycleMaster);
1410         }
1411
1412         if (event & OHCI1394_cycle64Seconds) {
1413                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1414                 if ((cycle_time & 0x80000000) == 0)
1415                         ohci->bus_seconds++;
1416         }
1417
1418         return IRQ_HANDLED;
1419 }
1420
1421 static int software_reset(struct fw_ohci *ohci)
1422 {
1423         int i;
1424
1425         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1426
1427         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1428                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1429                      OHCI1394_HCControl_softReset) == 0)
1430                         return 0;
1431                 msleep(1);
1432         }
1433
1434         return -EBUSY;
1435 }
1436
1437 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1438 {
1439         struct fw_ohci *ohci = fw_ohci(card);
1440         struct pci_dev *dev = to_pci_dev(card->device);
1441         u32 lps;
1442         int i;
1443
1444         if (software_reset(ohci)) {
1445                 fw_error("Failed to reset ohci card.\n");
1446                 return -EBUSY;
1447         }
1448
1449         /*
1450          * Now enable LPS, which we need in order to start accessing
1451          * most of the registers.  In fact, on some cards (ALI M5251),
1452          * accessing registers in the SClk domain without LPS enabled
1453          * will lock up the machine.  Wait 50msec to make sure we have
1454          * full link enabled.  However, with some cards (well, at least
1455          * a JMicron PCIe card), we have to try again sometimes.
1456          */
1457         reg_write(ohci, OHCI1394_HCControlSet,
1458                   OHCI1394_HCControl_LPS |
1459                   OHCI1394_HCControl_postedWriteEnable);
1460         flush_writes(ohci);
1461
1462         for (lps = 0, i = 0; !lps && i < 3; i++) {
1463                 msleep(50);
1464                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1465                       OHCI1394_HCControl_LPS;
1466         }
1467
1468         if (!lps) {
1469                 fw_error("Failed to set Link Power Status\n");
1470                 return -EIO;
1471         }
1472
1473         reg_write(ohci, OHCI1394_HCControlClear,
1474                   OHCI1394_HCControl_noByteSwapData);
1475
1476         reg_write(ohci, OHCI1394_LinkControlClear,
1477                   OHCI1394_LinkControl_rcvPhyPkt);
1478         reg_write(ohci, OHCI1394_LinkControlSet,
1479                   OHCI1394_LinkControl_rcvSelfID |
1480                   OHCI1394_LinkControl_cycleTimerEnable |
1481                   OHCI1394_LinkControl_cycleMaster);
1482
1483         reg_write(ohci, OHCI1394_ATRetries,
1484                   OHCI1394_MAX_AT_REQ_RETRIES |
1485                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1486                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1487
1488         ar_context_run(&ohci->ar_request_ctx);
1489         ar_context_run(&ohci->ar_response_ctx);
1490
1491         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1492         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1493         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1494         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1495         reg_write(ohci, OHCI1394_IntMaskSet,
1496                   OHCI1394_selfIDComplete |
1497                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1498                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1499                   OHCI1394_isochRx | OHCI1394_isochTx |
1500                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1501                   OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1502                   OHCI1394_masterIntEnable);
1503         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1504                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1505
1506         /* Activate link_on bit and contender bit in our self ID packets.*/
1507         if (ohci_update_phy_reg(card, 4, 0,
1508                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1509                 return -EIO;
1510
1511         /*
1512          * When the link is not yet enabled, the atomic config rom
1513          * update mechanism described below in ohci_set_config_rom()
1514          * is not active.  We have to update ConfigRomHeader and
1515          * BusOptions manually, and the write to ConfigROMmap takes
1516          * effect immediately.  We tie this to the enabling of the
1517          * link, so we have a valid config rom before enabling - the
1518          * OHCI requires that ConfigROMhdr and BusOptions have valid
1519          * values before enabling.
1520          *
1521          * However, when the ConfigROMmap is written, some controllers
1522          * always read back quadlets 0 and 2 from the config rom to
1523          * the ConfigRomHeader and BusOptions registers on bus reset.
1524          * They shouldn't do that in this initial case where the link
1525          * isn't enabled.  This means we have to use the same
1526          * workaround here, setting the bus header to 0 and then write
1527          * the right values in the bus reset tasklet.
1528          */
1529
1530         if (config_rom) {
1531                 ohci->next_config_rom =
1532                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1533                                            &ohci->next_config_rom_bus,
1534                                            GFP_KERNEL);
1535                 if (ohci->next_config_rom == NULL)
1536                         return -ENOMEM;
1537
1538                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1539                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1540         } else {
1541                 /*
1542                  * In the suspend case, config_rom is NULL, which
1543                  * means that we just reuse the old config rom.
1544                  */
1545                 ohci->next_config_rom = ohci->config_rom;
1546                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1547         }
1548
1549         ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1550         ohci->next_config_rom[0] = 0;
1551         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1552         reg_write(ohci, OHCI1394_BusOptions,
1553                   be32_to_cpu(ohci->next_config_rom[2]));
1554         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1555
1556         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1557
1558         if (request_irq(dev->irq, irq_handler,
1559                         IRQF_SHARED, ohci_driver_name, ohci)) {
1560                 fw_error("Failed to allocate shared interrupt %d.\n",
1561                          dev->irq);
1562                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1563                                   ohci->config_rom, ohci->config_rom_bus);
1564                 return -EIO;
1565         }
1566
1567         reg_write(ohci, OHCI1394_HCControlSet,
1568                   OHCI1394_HCControl_linkEnable |
1569                   OHCI1394_HCControl_BIBimageValid);
1570         flush_writes(ohci);
1571
1572         /*
1573          * We are ready to go, initiate bus reset to finish the
1574          * initialization.
1575          */
1576
1577         fw_core_initiate_bus_reset(&ohci->card, 1);
1578
1579         return 0;
1580 }
1581
1582 static int
1583 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1584 {
1585         struct fw_ohci *ohci;
1586         unsigned long flags;
1587         int retval = -EBUSY;
1588         __be32 *next_config_rom;
1589         dma_addr_t uninitialized_var(next_config_rom_bus);
1590
1591         ohci = fw_ohci(card);
1592
1593         /*
1594          * When the OHCI controller is enabled, the config rom update
1595          * mechanism is a bit tricky, but easy enough to use.  See
1596          * section 5.5.6 in the OHCI specification.
1597          *
1598          * The OHCI controller caches the new config rom address in a
1599          * shadow register (ConfigROMmapNext) and needs a bus reset
1600          * for the changes to take place.  When the bus reset is
1601          * detected, the controller loads the new values for the
1602          * ConfigRomHeader and BusOptions registers from the specified
1603          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1604          * shadow register. All automatically and atomically.
1605          *
1606          * Now, there's a twist to this story.  The automatic load of
1607          * ConfigRomHeader and BusOptions doesn't honor the
1608          * noByteSwapData bit, so with a be32 config rom, the
1609          * controller will load be32 values in to these registers
1610          * during the atomic update, even on litte endian
1611          * architectures.  The workaround we use is to put a 0 in the
1612          * header quadlet; 0 is endian agnostic and means that the
1613          * config rom isn't ready yet.  In the bus reset tasklet we
1614          * then set up the real values for the two registers.
1615          *
1616          * We use ohci->lock to avoid racing with the code that sets
1617          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1618          */
1619
1620         next_config_rom =
1621                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1622                                    &next_config_rom_bus, GFP_KERNEL);
1623         if (next_config_rom == NULL)
1624                 return -ENOMEM;
1625
1626         spin_lock_irqsave(&ohci->lock, flags);
1627
1628         if (ohci->next_config_rom == NULL) {
1629                 ohci->next_config_rom = next_config_rom;
1630                 ohci->next_config_rom_bus = next_config_rom_bus;
1631
1632                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1633                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1634                                   length * 4);
1635
1636                 ohci->next_header = config_rom[0];
1637                 ohci->next_config_rom[0] = 0;
1638
1639                 reg_write(ohci, OHCI1394_ConfigROMmap,
1640                           ohci->next_config_rom_bus);
1641                 retval = 0;
1642         }
1643
1644         spin_unlock_irqrestore(&ohci->lock, flags);
1645
1646         /*
1647          * Now initiate a bus reset to have the changes take
1648          * effect. We clean up the old config rom memory and DMA
1649          * mappings in the bus reset tasklet, since the OHCI
1650          * controller could need to access it before the bus reset
1651          * takes effect.
1652          */
1653         if (retval == 0)
1654                 fw_core_initiate_bus_reset(&ohci->card, 1);
1655         else
1656                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1657                                   next_config_rom, next_config_rom_bus);
1658
1659         return retval;
1660 }
1661
1662 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1663 {
1664         struct fw_ohci *ohci = fw_ohci(card);
1665
1666         at_context_transmit(&ohci->at_request_ctx, packet);
1667 }
1668
1669 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1670 {
1671         struct fw_ohci *ohci = fw_ohci(card);
1672
1673         at_context_transmit(&ohci->at_response_ctx, packet);
1674 }
1675
1676 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1677 {
1678         struct fw_ohci *ohci = fw_ohci(card);
1679         struct context *ctx = &ohci->at_request_ctx;
1680         struct driver_data *driver_data = packet->driver_data;
1681         int retval = -ENOENT;
1682
1683         tasklet_disable(&ctx->tasklet);
1684
1685         if (packet->ack != 0)
1686                 goto out;
1687
1688         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1689         driver_data->packet = NULL;
1690         packet->ack = RCODE_CANCELLED;
1691         packet->callback(packet, &ohci->card, packet->ack);
1692         retval = 0;
1693
1694  out:
1695         tasklet_enable(&ctx->tasklet);
1696
1697         return retval;
1698 }
1699
1700 static int
1701 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1702 {
1703 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1704         return 0;
1705 #else
1706         struct fw_ohci *ohci = fw_ohci(card);
1707         unsigned long flags;
1708         int n, retval = 0;
1709
1710         /*
1711          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1712          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1713          */
1714
1715         spin_lock_irqsave(&ohci->lock, flags);
1716
1717         if (ohci->generation != generation) {
1718                 retval = -ESTALE;
1719                 goto out;
1720         }
1721
1722         /*
1723          * Note, if the node ID contains a non-local bus ID, physical DMA is
1724          * enabled for _all_ nodes on remote buses.
1725          */
1726
1727         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1728         if (n < 32)
1729                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1730         else
1731                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1732
1733         flush_writes(ohci);
1734  out:
1735         spin_unlock_irqrestore(&ohci->lock, flags);
1736         return retval;
1737 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1738 }
1739
1740 static u64
1741 ohci_get_bus_time(struct fw_card *card)
1742 {
1743         struct fw_ohci *ohci = fw_ohci(card);
1744         u32 cycle_time;
1745         u64 bus_time;
1746
1747         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1748         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1749
1750         return bus_time;
1751 }
1752
1753 static int handle_ir_dualbuffer_packet(struct context *context,
1754                                        struct descriptor *d,
1755                                        struct descriptor *last)
1756 {
1757         struct iso_context *ctx =
1758                 container_of(context, struct iso_context, context);
1759         struct db_descriptor *db = (struct db_descriptor *) d;
1760         __le32 *ir_header;
1761         size_t header_length;
1762         void *p, *end;
1763         int i;
1764
1765         if (db->first_res_count != 0 && db->second_res_count != 0) {
1766                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1767                         /* This descriptor isn't done yet, stop iteration. */
1768                         return 0;
1769                 }
1770                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1771         }
1772
1773         header_length = le16_to_cpu(db->first_req_count) -
1774                 le16_to_cpu(db->first_res_count);
1775
1776         i = ctx->header_length;
1777         p = db + 1;
1778         end = p + header_length;
1779         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1780                 /*
1781                  * The iso header is byteswapped to little endian by
1782                  * the controller, but the remaining header quadlets
1783                  * are big endian.  We want to present all the headers
1784                  * as big endian, so we have to swap the first
1785                  * quadlet.
1786                  */
1787                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1788                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1789                 i += ctx->base.header_size;
1790                 ctx->excess_bytes +=
1791                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1792                 p += ctx->base.header_size + 4;
1793         }
1794         ctx->header_length = i;
1795
1796         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1797                 le16_to_cpu(db->second_res_count);
1798
1799         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1800                 ir_header = (__le32 *) (db + 1);
1801                 ctx->base.callback(&ctx->base,
1802                                    le32_to_cpu(ir_header[0]) & 0xffff,
1803                                    ctx->header_length, ctx->header,
1804                                    ctx->base.callback_data);
1805                 ctx->header_length = 0;
1806         }
1807
1808         return 1;
1809 }
1810
1811 static int handle_ir_packet_per_buffer(struct context *context,
1812                                        struct descriptor *d,
1813                                        struct descriptor *last)
1814 {
1815         struct iso_context *ctx =
1816                 container_of(context, struct iso_context, context);
1817         struct descriptor *pd;
1818         __le32 *ir_header;
1819         void *p;
1820         int i;
1821
1822         for (pd = d; pd <= last; pd++) {
1823                 if (pd->transfer_status)
1824                         break;
1825         }
1826         if (pd > last)
1827                 /* Descriptor(s) not done yet, stop iteration */
1828                 return 0;
1829
1830         i   = ctx->header_length;
1831         p   = last + 1;
1832
1833         if (ctx->base.header_size > 0 &&
1834                         i + ctx->base.header_size <= PAGE_SIZE) {
1835                 /*
1836                  * The iso header is byteswapped to little endian by
1837                  * the controller, but the remaining header quadlets
1838                  * are big endian.  We want to present all the headers
1839                  * as big endian, so we have to swap the first quadlet.
1840                  */
1841                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1842                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1843                 ctx->header_length += ctx->base.header_size;
1844         }
1845
1846         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1847                 ir_header = (__le32 *) p;
1848                 ctx->base.callback(&ctx->base,
1849                                    le32_to_cpu(ir_header[0]) & 0xffff,
1850                                    ctx->header_length, ctx->header,
1851                                    ctx->base.callback_data);
1852                 ctx->header_length = 0;
1853         }
1854
1855         return 1;
1856 }
1857
1858 static int handle_it_packet(struct context *context,
1859                             struct descriptor *d,
1860                             struct descriptor *last)
1861 {
1862         struct iso_context *ctx =
1863                 container_of(context, struct iso_context, context);
1864
1865         if (last->transfer_status == 0)
1866                 /* This descriptor isn't done yet, stop iteration. */
1867                 return 0;
1868
1869         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1870                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1871                                    0, NULL, ctx->base.callback_data);
1872
1873         return 1;
1874 }
1875
1876 static struct fw_iso_context *
1877 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1878 {
1879         struct fw_ohci *ohci = fw_ohci(card);
1880         struct iso_context *ctx, *list;
1881         descriptor_callback_t callback;
1882         u32 *mask, regs;
1883         unsigned long flags;
1884         int index, retval = -ENOMEM;
1885
1886         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1887                 mask = &ohci->it_context_mask;
1888                 list = ohci->it_context_list;
1889                 callback = handle_it_packet;
1890         } else {
1891                 mask = &ohci->ir_context_mask;
1892                 list = ohci->ir_context_list;
1893                 if (ohci->version >= OHCI_VERSION_1_1)
1894                         callback = handle_ir_dualbuffer_packet;
1895                 else
1896                         callback = handle_ir_packet_per_buffer;
1897         }
1898
1899         spin_lock_irqsave(&ohci->lock, flags);
1900         index = ffs(*mask) - 1;
1901         if (index >= 0)
1902                 *mask &= ~(1 << index);
1903         spin_unlock_irqrestore(&ohci->lock, flags);
1904
1905         if (index < 0)
1906                 return ERR_PTR(-EBUSY);
1907
1908         if (type == FW_ISO_CONTEXT_TRANSMIT)
1909                 regs = OHCI1394_IsoXmitContextBase(index);
1910         else
1911                 regs = OHCI1394_IsoRcvContextBase(index);
1912
1913         ctx = &list[index];
1914         memset(ctx, 0, sizeof(*ctx));
1915         ctx->header_length = 0;
1916         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1917         if (ctx->header == NULL)
1918                 goto out;
1919
1920         retval = context_init(&ctx->context, ohci, regs, callback);
1921         if (retval < 0)
1922                 goto out_with_header;
1923
1924         return &ctx->base;
1925
1926  out_with_header:
1927         free_page((unsigned long)ctx->header);
1928  out:
1929         spin_lock_irqsave(&ohci->lock, flags);
1930         *mask |= 1 << index;
1931         spin_unlock_irqrestore(&ohci->lock, flags);
1932
1933         return ERR_PTR(retval);
1934 }
1935
1936 static int ohci_start_iso(struct fw_iso_context *base,
1937                           s32 cycle, u32 sync, u32 tags)
1938 {
1939         struct iso_context *ctx = container_of(base, struct iso_context, base);
1940         struct fw_ohci *ohci = ctx->context.ohci;
1941         u32 control, match;
1942         int index;
1943
1944         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1945                 index = ctx - ohci->it_context_list;
1946                 match = 0;
1947                 if (cycle >= 0)
1948                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1949                                 (cycle & 0x7fff) << 16;
1950
1951                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1952                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1953                 context_run(&ctx->context, match);
1954         } else {
1955                 index = ctx - ohci->ir_context_list;
1956                 control = IR_CONTEXT_ISOCH_HEADER;
1957                 if (ohci->version >= OHCI_VERSION_1_1)
1958                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1959                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1960                 if (cycle >= 0) {
1961                         match |= (cycle & 0x07fff) << 12;
1962                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1963                 }
1964
1965                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1966                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1967                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1968                 context_run(&ctx->context, control);
1969         }
1970
1971         return 0;
1972 }
1973
1974 static int ohci_stop_iso(struct fw_iso_context *base)
1975 {
1976         struct fw_ohci *ohci = fw_ohci(base->card);
1977         struct iso_context *ctx = container_of(base, struct iso_context, base);
1978         int index;
1979
1980         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1981                 index = ctx - ohci->it_context_list;
1982                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1983         } else {
1984                 index = ctx - ohci->ir_context_list;
1985                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1986         }
1987         flush_writes(ohci);
1988         context_stop(&ctx->context);
1989
1990         return 0;
1991 }
1992
1993 static void ohci_free_iso_context(struct fw_iso_context *base)
1994 {
1995         struct fw_ohci *ohci = fw_ohci(base->card);
1996         struct iso_context *ctx = container_of(base, struct iso_context, base);
1997         unsigned long flags;
1998         int index;
1999
2000         ohci_stop_iso(base);
2001         context_release(&ctx->context);
2002         free_page((unsigned long)ctx->header);
2003
2004         spin_lock_irqsave(&ohci->lock, flags);
2005
2006         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2007                 index = ctx - ohci->it_context_list;
2008                 ohci->it_context_mask |= 1 << index;
2009         } else {
2010                 index = ctx - ohci->ir_context_list;
2011                 ohci->ir_context_mask |= 1 << index;
2012         }
2013
2014         spin_unlock_irqrestore(&ohci->lock, flags);
2015 }
2016
2017 static int
2018 ohci_queue_iso_transmit(struct fw_iso_context *base,
2019                         struct fw_iso_packet *packet,
2020                         struct fw_iso_buffer *buffer,
2021                         unsigned long payload)
2022 {
2023         struct iso_context *ctx = container_of(base, struct iso_context, base);
2024         struct descriptor *d, *last, *pd;
2025         struct fw_iso_packet *p;
2026         __le32 *header;
2027         dma_addr_t d_bus, page_bus;
2028         u32 z, header_z, payload_z, irq;
2029         u32 payload_index, payload_end_index, next_page_index;
2030         int page, end_page, i, length, offset;
2031
2032         /*
2033          * FIXME: Cycle lost behavior should be configurable: lose
2034          * packet, retransmit or terminate..
2035          */
2036
2037         p = packet;
2038         payload_index = payload;
2039
2040         if (p->skip)
2041                 z = 1;
2042         else
2043                 z = 2;
2044         if (p->header_length > 0)
2045                 z++;
2046
2047         /* Determine the first page the payload isn't contained in. */
2048         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2049         if (p->payload_length > 0)
2050                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2051         else
2052                 payload_z = 0;
2053
2054         z += payload_z;
2055
2056         /* Get header size in number of descriptors. */
2057         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2058
2059         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2060         if (d == NULL)
2061                 return -ENOMEM;
2062
2063         if (!p->skip) {
2064                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2065                 d[0].req_count = cpu_to_le16(8);
2066
2067                 header = (__le32 *) &d[1];
2068                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2069                                         IT_HEADER_TAG(p->tag) |
2070                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2071                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2072                                         IT_HEADER_SPEED(ctx->base.speed));
2073                 header[1] =
2074                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2075                                                           p->payload_length));
2076         }
2077
2078         if (p->header_length > 0) {
2079                 d[2].req_count    = cpu_to_le16(p->header_length);
2080                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2081                 memcpy(&d[z], p->header, p->header_length);
2082         }
2083
2084         pd = d + z - payload_z;
2085         payload_end_index = payload_index + p->payload_length;
2086         for (i = 0; i < payload_z; i++) {
2087                 page               = payload_index >> PAGE_SHIFT;
2088                 offset             = payload_index & ~PAGE_MASK;
2089                 next_page_index    = (page + 1) << PAGE_SHIFT;
2090                 length             =
2091                         min(next_page_index, payload_end_index) - payload_index;
2092                 pd[i].req_count    = cpu_to_le16(length);
2093
2094                 page_bus = page_private(buffer->pages[page]);
2095                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2096
2097                 payload_index += length;
2098         }
2099
2100         if (p->interrupt)
2101                 irq = DESCRIPTOR_IRQ_ALWAYS;
2102         else
2103                 irq = DESCRIPTOR_NO_IRQ;
2104
2105         last = z == 2 ? d : d + z - 1;
2106         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2107                                      DESCRIPTOR_STATUS |
2108                                      DESCRIPTOR_BRANCH_ALWAYS |
2109                                      irq);
2110
2111         context_append(&ctx->context, d, z, header_z);
2112
2113         return 0;
2114 }
2115
2116 static int
2117 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2118                                   struct fw_iso_packet *packet,
2119                                   struct fw_iso_buffer *buffer,
2120                                   unsigned long payload)
2121 {
2122         struct iso_context *ctx = container_of(base, struct iso_context, base);
2123         struct db_descriptor *db = NULL;
2124         struct descriptor *d;
2125         struct fw_iso_packet *p;
2126         dma_addr_t d_bus, page_bus;
2127         u32 z, header_z, length, rest;
2128         int page, offset, packet_count, header_size;
2129
2130         /*
2131          * FIXME: Cycle lost behavior should be configurable: lose
2132          * packet, retransmit or terminate..
2133          */
2134
2135         p = packet;
2136         z = 2;
2137
2138         /*
2139          * The OHCI controller puts the status word in the header
2140          * buffer too, so we need 4 extra bytes per packet.
2141          */
2142         packet_count = p->header_length / ctx->base.header_size;
2143         header_size = packet_count * (ctx->base.header_size + 4);
2144
2145         /* Get header size in number of descriptors. */
2146         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2147         page     = payload >> PAGE_SHIFT;
2148         offset   = payload & ~PAGE_MASK;
2149         rest     = p->payload_length;
2150
2151         /* FIXME: make packet-per-buffer/dual-buffer a context option */
2152         while (rest > 0) {
2153                 d = context_get_descriptors(&ctx->context,
2154                                             z + header_z, &d_bus);
2155                 if (d == NULL)
2156                         return -ENOMEM;
2157
2158                 db = (struct db_descriptor *) d;
2159                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2160                                           DESCRIPTOR_BRANCH_ALWAYS);
2161                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2162                 if (p->skip && rest == p->payload_length) {
2163                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2164                         db->first_req_count = db->first_size;
2165                 } else {
2166                         db->first_req_count = cpu_to_le16(header_size);
2167                 }
2168                 db->first_res_count = db->first_req_count;
2169                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2170
2171                 if (p->skip && rest == p->payload_length)
2172                         length = 4;
2173                 else if (offset + rest < PAGE_SIZE)
2174                         length = rest;
2175                 else
2176                         length = PAGE_SIZE - offset;
2177
2178                 db->second_req_count = cpu_to_le16(length);
2179                 db->second_res_count = db->second_req_count;
2180                 page_bus = page_private(buffer->pages[page]);
2181                 db->second_buffer = cpu_to_le32(page_bus + offset);
2182
2183                 if (p->interrupt && length == rest)
2184                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2185
2186                 context_append(&ctx->context, d, z, header_z);
2187                 offset = (offset + length) & ~PAGE_MASK;
2188                 rest -= length;
2189                 if (offset == 0)
2190                         page++;
2191         }
2192
2193         return 0;
2194 }
2195
2196 static int
2197 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2198                                          struct fw_iso_packet *packet,
2199                                          struct fw_iso_buffer *buffer,
2200                                          unsigned long payload)
2201 {
2202         struct iso_context *ctx = container_of(base, struct iso_context, base);
2203         struct descriptor *d = NULL, *pd = NULL;
2204         struct fw_iso_packet *p = packet;
2205         dma_addr_t d_bus, page_bus;
2206         u32 z, header_z, rest;
2207         int i, j, length;
2208         int page, offset, packet_count, header_size, payload_per_buffer;
2209
2210         /*
2211          * The OHCI controller puts the status word in the
2212          * buffer too, so we need 4 extra bytes per packet.
2213          */
2214         packet_count = p->header_length / ctx->base.header_size;
2215         header_size  = ctx->base.header_size + 4;
2216
2217         /* Get header size in number of descriptors. */
2218         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2219         page     = payload >> PAGE_SHIFT;
2220         offset   = payload & ~PAGE_MASK;
2221         payload_per_buffer = p->payload_length / packet_count;
2222
2223         for (i = 0; i < packet_count; i++) {
2224                 /* d points to the header descriptor */
2225                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2226                 d = context_get_descriptors(&ctx->context,
2227                                 z + header_z, &d_bus);
2228                 if (d == NULL)
2229                         return -ENOMEM;
2230
2231                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2232                                               DESCRIPTOR_INPUT_MORE);
2233                 if (p->skip && i == 0)
2234                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2235                 d->req_count    = cpu_to_le16(header_size);
2236                 d->res_count    = d->req_count;
2237                 d->transfer_status = 0;
2238                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2239
2240                 rest = payload_per_buffer;
2241                 for (j = 1; j < z; j++) {
2242                         pd = d + j;
2243                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2244                                                   DESCRIPTOR_INPUT_MORE);
2245
2246                         if (offset + rest < PAGE_SIZE)
2247                                 length = rest;
2248                         else
2249                                 length = PAGE_SIZE - offset;
2250                         pd->req_count = cpu_to_le16(length);
2251                         pd->res_count = pd->req_count;
2252                         pd->transfer_status = 0;
2253
2254                         page_bus = page_private(buffer->pages[page]);
2255                         pd->data_address = cpu_to_le32(page_bus + offset);
2256
2257                         offset = (offset + length) & ~PAGE_MASK;
2258                         rest -= length;
2259                         if (offset == 0)
2260                                 page++;
2261                 }
2262                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2263                                           DESCRIPTOR_INPUT_LAST |
2264                                           DESCRIPTOR_BRANCH_ALWAYS);
2265                 if (p->interrupt && i == packet_count - 1)
2266                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2267
2268                 context_append(&ctx->context, d, z, header_z);
2269         }
2270
2271         return 0;
2272 }
2273
2274 static int
2275 ohci_queue_iso(struct fw_iso_context *base,
2276                struct fw_iso_packet *packet,
2277                struct fw_iso_buffer *buffer,
2278                unsigned long payload)
2279 {
2280         struct iso_context *ctx = container_of(base, struct iso_context, base);
2281         unsigned long flags;
2282         int retval;
2283
2284         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2285         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2286                 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2287         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2288                 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2289                                                          buffer, payload);
2290         else
2291                 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2292                                                                 buffer,
2293                                                                 payload);
2294         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2295
2296         return retval;
2297 }
2298
2299 static const struct fw_card_driver ohci_driver = {
2300         .name                   = ohci_driver_name,
2301         .enable                 = ohci_enable,
2302         .update_phy_reg         = ohci_update_phy_reg,
2303         .set_config_rom         = ohci_set_config_rom,
2304         .send_request           = ohci_send_request,
2305         .send_response          = ohci_send_response,
2306         .cancel_packet          = ohci_cancel_packet,
2307         .enable_phys_dma        = ohci_enable_phys_dma,
2308         .get_bus_time           = ohci_get_bus_time,
2309
2310         .allocate_iso_context   = ohci_allocate_iso_context,
2311         .free_iso_context       = ohci_free_iso_context,
2312         .queue_iso              = ohci_queue_iso,
2313         .start_iso              = ohci_start_iso,
2314         .stop_iso               = ohci_stop_iso,
2315 };
2316
2317 #ifdef CONFIG_PPC_PMAC
2318 static void ohci_pmac_on(struct pci_dev *dev)
2319 {
2320         if (machine_is(powermac)) {
2321                 struct device_node *ofn = pci_device_to_OF_node(dev);
2322
2323                 if (ofn) {
2324                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2325                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2326                 }
2327         }
2328 }
2329
2330 static void ohci_pmac_off(struct pci_dev *dev)
2331 {
2332         if (machine_is(powermac)) {
2333                 struct device_node *ofn = pci_device_to_OF_node(dev);
2334
2335                 if (ofn) {
2336                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2337                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2338                 }
2339         }
2340 }
2341 #else
2342 #define ohci_pmac_on(dev)
2343 #define ohci_pmac_off(dev)
2344 #endif /* CONFIG_PPC_PMAC */
2345
2346 static int __devinit
2347 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2348 {
2349         struct fw_ohci *ohci;
2350         u32 bus_options, max_receive, link_speed;
2351         u64 guid;
2352         int err;
2353         size_t size;
2354
2355         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2356         if (ohci == NULL) {
2357                 fw_error("Could not malloc fw_ohci data.\n");
2358                 return -ENOMEM;
2359         }
2360
2361         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2362
2363         ohci_pmac_on(dev);
2364
2365         err = pci_enable_device(dev);
2366         if (err) {
2367                 fw_error("Failed to enable OHCI hardware.\n");
2368                 goto fail_free;
2369         }
2370
2371         pci_set_master(dev);
2372         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2373         pci_set_drvdata(dev, ohci);
2374
2375 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2376         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2377                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2378 #endif
2379         ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2380
2381         spin_lock_init(&ohci->lock);
2382
2383         tasklet_init(&ohci->bus_reset_tasklet,
2384                      bus_reset_tasklet, (unsigned long)ohci);
2385
2386         err = pci_request_region(dev, 0, ohci_driver_name);
2387         if (err) {
2388                 fw_error("MMIO resource unavailable\n");
2389                 goto fail_disable;
2390         }
2391
2392         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2393         if (ohci->registers == NULL) {
2394                 fw_error("Failed to remap registers\n");
2395                 err = -ENXIO;
2396                 goto fail_iomem;
2397         }
2398
2399         ar_context_init(&ohci->ar_request_ctx, ohci,
2400                         OHCI1394_AsReqRcvContextControlSet);
2401
2402         ar_context_init(&ohci->ar_response_ctx, ohci,
2403                         OHCI1394_AsRspRcvContextControlSet);
2404
2405         context_init(&ohci->at_request_ctx, ohci,
2406                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2407
2408         context_init(&ohci->at_response_ctx, ohci,
2409                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2410
2411         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2412         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2413         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2414         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2415         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2416
2417         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2418         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2419         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2420         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2421         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2422
2423         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2424                 fw_error("Out of memory for it/ir contexts.\n");
2425                 err = -ENOMEM;
2426                 goto fail_registers;
2427         }
2428
2429         /* self-id dma buffer allocation */
2430         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2431                                                SELF_ID_BUF_SIZE,
2432                                                &ohci->self_id_bus,
2433                                                GFP_KERNEL);
2434         if (ohci->self_id_cpu == NULL) {
2435                 fw_error("Out of memory for self ID buffer.\n");
2436                 err = -ENOMEM;
2437                 goto fail_registers;
2438         }
2439
2440         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2441         max_receive = (bus_options >> 12) & 0xf;
2442         link_speed = bus_options & 0x7;
2443         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2444                 reg_read(ohci, OHCI1394_GUIDLo);
2445
2446         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2447         if (err < 0)
2448                 goto fail_self_id;
2449
2450         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2451         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2452                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2453         return 0;
2454
2455  fail_self_id:
2456         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2457                           ohci->self_id_cpu, ohci->self_id_bus);
2458  fail_registers:
2459         kfree(ohci->it_context_list);
2460         kfree(ohci->ir_context_list);
2461         pci_iounmap(dev, ohci->registers);
2462  fail_iomem:
2463         pci_release_region(dev, 0);
2464  fail_disable:
2465         pci_disable_device(dev);
2466  fail_free:
2467         kfree(&ohci->card);
2468         ohci_pmac_off(dev);
2469
2470         return err;
2471 }
2472
2473 static void pci_remove(struct pci_dev *dev)
2474 {
2475         struct fw_ohci *ohci;
2476
2477         ohci = pci_get_drvdata(dev);
2478         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2479         flush_writes(ohci);
2480         fw_core_remove_card(&ohci->card);
2481
2482         /*
2483          * FIXME: Fail all pending packets here, now that the upper
2484          * layers can't queue any more.
2485          */
2486
2487         software_reset(ohci);
2488         free_irq(dev->irq, ohci);
2489         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2490                           ohci->self_id_cpu, ohci->self_id_bus);
2491         kfree(ohci->it_context_list);
2492         kfree(ohci->ir_context_list);
2493         pci_iounmap(dev, ohci->registers);
2494         pci_release_region(dev, 0);
2495         pci_disable_device(dev);
2496         kfree(&ohci->card);
2497         ohci_pmac_off(dev);
2498
2499         fw_notify("Removed fw-ohci device.\n");
2500 }
2501
2502 #ifdef CONFIG_PM
2503 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2504 {
2505         struct fw_ohci *ohci = pci_get_drvdata(dev);
2506         int err;
2507
2508         software_reset(ohci);
2509         free_irq(dev->irq, ohci);
2510         err = pci_save_state(dev);
2511         if (err) {
2512                 fw_error("pci_save_state failed\n");
2513                 return err;
2514         }
2515         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2516         if (err)
2517                 fw_error("pci_set_power_state failed with %d\n", err);
2518         ohci_pmac_off(dev);
2519
2520         return 0;
2521 }
2522
2523 static int pci_resume(struct pci_dev *dev)
2524 {
2525         struct fw_ohci *ohci = pci_get_drvdata(dev);
2526         int err;
2527
2528         ohci_pmac_on(dev);
2529         pci_set_power_state(dev, PCI_D0);
2530         pci_restore_state(dev);
2531         err = pci_enable_device(dev);
2532         if (err) {
2533                 fw_error("pci_enable_device failed\n");
2534                 return err;
2535         }
2536
2537         return ohci_enable(&ohci->card, NULL, 0);
2538 }
2539 #endif
2540
2541 static struct pci_device_id pci_table[] = {
2542         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2543         { }
2544 };
2545
2546 MODULE_DEVICE_TABLE(pci, pci_table);
2547
2548 static struct pci_driver fw_ohci_pci_driver = {
2549         .name           = ohci_driver_name,
2550         .id_table       = pci_table,
2551         .probe          = pci_probe,
2552         .remove         = pci_remove,
2553 #ifdef CONFIG_PM
2554         .resume         = pci_resume,
2555         .suspend        = pci_suspend,
2556 #endif
2557 };
2558
2559 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2560 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2561 MODULE_LICENSE("GPL");
2562
2563 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2564 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2565 MODULE_ALIAS("ohci1394");
2566 #endif
2567
2568 static int __init fw_ohci_init(void)
2569 {
2570         return pci_register_driver(&fw_ohci_pci_driver);
2571 }
2572
2573 static void __exit fw_ohci_cleanup(void)
2574 {
2575         pci_unregister_driver(&fw_ohci_pci_driver);
2576 }
2577
2578 module_init(fw_ohci_init);
2579 module_exit(fw_ohci_cleanup);