drivers/edac/r82600_edac.c

   1 /*
   2  * Radisys 82600 Embedded chipset Memory Controller kernel module
   3  * (C) 2005 EADS Astrium
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
   8  * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
   9  *
  10  * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
  11  *
  12  * Written with reference to 82600 High Integration Dual PCI System
  13  * Controller Data Book:
  14  * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
  15  * references to this document given in []
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/pci.h>
  22 #include <linux/pci_ids.h>
  23 #include <linux/slab.h>
  24 #include "edac_mc.h"
  25
  26 #define r82600_printk(level, fmt, arg...) \
  27         edac_printk(level, "r82600", fmt, ##arg)
  28
  29 #define r82600_mc_printk(mci, level, fmt, arg...) \
  30         edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
  31
  32 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
  33  * supports up to four banks of memory. The four banks can support a mix of
  34  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
  35  * each of which can be any size from 16MB to 512MB. Both registered (control
  36  * signals buffered) and unbuffered DIMM types are supported. Mixing of
  37  * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
  38  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
  39  * the CPU bus, 66MHz, 100MHz or 133MHz."
  40  */
  41
  42 #define R82600_NR_CSROWS 4
  43 #define R82600_NR_CHANS  1
  44 #define R82600_NR_DIMMS  4
  45
  46 #define R82600_BRIDGE_ID  0x8200
  47
  48 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
  49 #define R82600_DRAMC    0x57    /* Various SDRAM related control bits
  50                                  * all bits are R/W
  51                                  *
  52                                  * 7    SDRAM ISA Hole Enable
  53                                  * 6    Flash Page Mode Enable
  54                                  * 5    ECC Enable: 1=ECC 0=noECC
  55                                  * 4    DRAM DIMM Type: 1=
  56                                  * 3    BIOS Alias Disable
  57                                  * 2    SDRAM BIOS Flash Write Enable
  58                                  * 1:0  SDRAM Refresh Rate: 00=Disabled
  59                                  *          01=7.8usec (256Mbit SDRAMs)
  60                                  *          10=15.6us 11=125usec
  61                                  */
  62
  63 #define R82600_SDRAMC   0x76    /* "SDRAM Control Register"
  64                                  * More SDRAM related control bits
  65                                  * all bits are R/W
  66                                  *
  67                                  * 15:8 Reserved.
  68                                  *
  69                                  * 7:5  Special SDRAM Mode Select
  70                                  *
  71                                  * 4    Force ECC
  72                                  *
  73                                  *        1=Drive ECC bits to 0 during
  74                                  *          write cycles (i.e. ECC test mode)
  75                                  *
  76                                  *        0=Normal ECC functioning
  77                                  *
  78                                  * 3    Enhanced Paging Enable
  79                                  *
  80                                  * 2    CAS# Latency 0=3clks 1=2clks
  81                                  *
  82                                  * 1    RAS# to CAS# Delay 0=3 1=2
  83                                  *
  84                                  * 0    RAS# Precharge     0=3 1=2
  85                                  */
  86
  87 #define R82600_EAP      0x80    /* ECC Error Address Pointer Register
  88                                  *
  89                                  * 31    Disable Hardware Scrubbing (RW)
  90                                  *        0=Scrub on corrected read
  91                                  *        1=Don't scrub on corrected read
  92                                  *
  93                                  * 30:12 Error Address Pointer (RO)
  94                                  *        Upper 19 bits of error address
  95                                  *
  96                                  * 11:4  Syndrome Bits (RO)
  97                                  *
  98                                  * 3     BSERR# on multibit error (RW)
  99                                  *        1=enable 0=disable
 100                                  *
 101                                  * 2     NMI on Single Bit Eror (RW)
 102                                  *        1=NMI triggered by SBE n.b. other
 103                                  *          prerequeists
 104                                  *        0=NMI not triggered
 105                                  *
 106                                  * 1     MBE (R/WC)
 107                                  *        read 1=MBE at EAP (see above)
 108                                  *        read 0=no MBE, or SBE occurred first
 109                                  *        write 1=Clear MBE status (must also
 110                                  *          clear SBE)
 111                                  *        write 0=NOP
 112                                  *
 113                                  * 1     SBE (R/WC)
 114                                  *        read 1=SBE at EAP (see above)
 115                                  *        read 0=no SBE, or MBE occurred first
 116                                  *        write 1=Clear SBE status (must also
 117                                  *          clear MBE)
 118                                  *        write 0=NOP
 119                                  */
 120
 121 #define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
 122                                  *  Registers
 123                                  *
 124                                  * 7:0  Address lines 30:24 - upper limit of
 125                                  * each row [p57]
 126                                  */
 127
 128 struct r82600_error_info {
 129         u32 eapr;
 130 };
 131
 132 static unsigned int disable_hardware_scrub = 0;
 133
 134 static void r82600_get_error_info (struct mem_ctl_info *mci,
 135                 struct r82600_error_info *info)
 136 {
 137         pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr);
 138
 139         if (info->eapr & BIT(0))
 140                 /* Clear error to allow next error to be reported [p.62] */
 141                 pci_write_bits32(mci->pdev, R82600_EAP,
 142                                 ((u32) BIT(0) & (u32) BIT(1)),
 143                                 ((u32) BIT(0) & (u32) BIT(1)));
 144
 145         if (info->eapr & BIT(1))
 146                 /* Clear error to allow next error to be reported [p.62] */
 147                 pci_write_bits32(mci->pdev, R82600_EAP,
 148                                 ((u32) BIT(0) & (u32) BIT(1)),
 149                                 ((u32) BIT(0) & (u32) BIT(1)));
 150 }
 151
 152 static int r82600_process_error_info (struct mem_ctl_info *mci,
 153                 struct r82600_error_info *info, int handle_errors)
 154 {
 155         int error_found;
 156         u32 eapaddr, page;
 157         u32 syndrome;
 158
 159         error_found = 0;
 160
 161         /* bits 30:12 store the upper 19 bits of the 32 bit error address */
 162         eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
 163         /* Syndrome in bits 11:4 [p.62]       */
 164         syndrome = (info->eapr >> 4) & 0xFF;
 165
 166         /* the R82600 reports at less than page *
 167          * granularity (upper 19 bits only)     */
 168         page = eapaddr >> PAGE_SHIFT;
 169
 170         if (info->eapr & BIT(0)) {  /* CE? */
 171                 error_found = 1;
 172
 173                 if (handle_errors)
 174                         edac_mc_handle_ce(mci, page, 0,  /* not avail */
 175                                         syndrome,
 176                                         edac_mc_find_csrow_by_page(mci, page),
 177                                         0,  /* channel */
 178                                         mci->ctl_name);
 179         }
 180
 181         if (info->eapr & BIT(1)) {  /* UE? */
 182                 error_found = 1;
 183
 184                 if (handle_errors)
 185                         /* 82600 doesn't give enough info */
 186                         edac_mc_handle_ue(mci, page, 0,
 187                                 edac_mc_find_csrow_by_page(mci, page),
 188                                 mci->ctl_name);
 189         }
 190
 191         return error_found;
 192 }
 193
 194 static void r82600_check(struct mem_ctl_info *mci)
 195 {
 196         struct r82600_error_info info;
 197
 198         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 199         r82600_get_error_info(mci, &info);
 200         r82600_process_error_info(mci, &info, 1);
 201 }
 202
 203 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
 204 {
 205         int rc = -ENODEV;
 206         int index;
 207         struct mem_ctl_info *mci = NULL;
 208         u8 dramcr;
 209         u32 ecc_on;
 210         u32 reg_sdram;
 211         u32 eapr;
 212         u32 scrub_disabled;
 213         u32 sdram_refresh_rate;
 214         u32 row_high_limit_last = 0;
 215         struct r82600_error_info discard;
 216
 217         debugf0("%s()\n", __func__);
 218         pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
 219         pci_read_config_dword(pdev, R82600_EAP, &eapr);
 220         ecc_on = dramcr & BIT(5);
 221         reg_sdram = dramcr & BIT(4);
 222         scrub_disabled = eapr & BIT(31);
 223         sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
 224         debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
 225                 sdram_refresh_rate);
 226         debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
 227         mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
 228
 229         if (mci == NULL) {
 230                 rc = -ENOMEM;
 231                 goto fail;
 232         }
 233
 234         debugf0("%s(): mci = %p\n", __func__, mci);
 235         mci->pdev = pdev;
 236         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
 237         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 238         /* FIXME try to work out if the chip leads have been used for COM2
 239          * instead on this board? [MA6?] MAYBE:
 240          */
 241
 242         /* On the R82600, the pins for memory bits 72:65 - i.e. the   *
 243          * EC bits are shared with the pins for COM2 (!), so if COM2  *
 244          * is enabled, we assume COM2 is wired up, and thus no EDAC   *
 245          * is possible.                                               */
 246         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 247
 248         if (ecc_on) {
 249                 if (scrub_disabled)
 250                         debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
 251                                 "%#0x\n", __func__, mci, eapr);
 252         } else
 253                 mci->edac_cap = EDAC_FLAG_NONE;
 254
 255         mci->mod_name = EDAC_MOD_STR;
 256         mci->mod_ver = "$Revision: 1.1.2.6 $";
 257         mci->ctl_name = "R82600";
 258         mci->edac_check = r82600_check;
 259         mci->ctl_page_to_phys = NULL;
 260
 261         for (index = 0; index < mci->nr_csrows; index++) {
 262                 struct csrow_info *csrow = &mci->csrows[index];
 263                 u8 drbar;       /* sDram Row Boundry Address Register */
 264                 u32 row_high_limit;
 265                 u32 row_base;
 266
 267                 /* find the DRAM Chip Select Base address and mask */
 268                 pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar);
 269
 270                 debugf1("MC%d: %s() Row=%d DRBA = %#0x\n", mci->mc_idx,
 271                         __func__, index, drbar);
 272
 273                 row_high_limit = ((u32) drbar << 24);
 274 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
 275
 276                 debugf1("MC%d: %s() Row=%d, Boundry Address=%#0x, Last = "
 277                         "%#0x \n", mci->mc_idx, __func__, index,
 278                         row_high_limit, row_high_limit_last);
 279
 280                 /* Empty row [p.57] */
 281                 if (row_high_limit == row_high_limit_last)
 282                         continue;
 283
 284                 row_base = row_high_limit_last;
 285                 csrow->first_page = row_base >> PAGE_SHIFT;
 286                 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
 287                 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
 288                 /* Error address is top 19 bits - so granularity is      *
 289                  * 14 bits                                               */
 290                 csrow->grain = 1 << 14;
 291                 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
 292                 /* FIXME - check that this is unknowable with this chipset */
 293                 csrow->dtype = DEV_UNKNOWN;
 294
 295                 /* Mode is global on 82600 */
 296                 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
 297                 row_high_limit_last = row_high_limit;
 298         }
 299
 300         r82600_get_error_info(mci, &discard);  /* clear counters */
 301
 302         if (edac_mc_add_mc(mci)) {
 303                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 304                 goto fail;
 305         }
 306
 307         /* get this far and it's successful */
 308
 309         if (disable_hardware_scrub) {
 310                 debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
 311                         __func__);
 312                 pci_write_bits32(mci->pdev, R82600_EAP, BIT(31), BIT(31));
 313         }
 314
 315         debugf3("%s(): success\n", __func__);
 316         return 0;
 317
 318 fail:
 319         if (mci)
 320                 edac_mc_free(mci);
 321
 322         return rc;
 323 }
 324
 325 /* returns count (>= 0), or negative on error */
 326 static int __devinit r82600_init_one(struct pci_dev *pdev,
 327                 const struct pci_device_id *ent)
 328 {
 329         debugf0("%s()\n", __func__);
 330
 331         /* don't need to call pci_device_enable() */
 332         return r82600_probe1(pdev, ent->driver_data);
 333 }
 334
 335 static void __devexit r82600_remove_one(struct pci_dev *pdev)
 336 {
 337         struct mem_ctl_info *mci;
 338
 339         debugf0("%s()\n", __func__);
 340
 341         if ((mci = edac_mc_del_mc(pdev)) == NULL)
 342                 return;
 343
 344         edac_mc_free(mci);
 345 }
 346
 347 static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
 348         {
 349                 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
 350         },
 351         {
 352                 0,
 353         }       /* 0 terminated list. */
 354 };
 355
 356 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
 357
 358 static struct pci_driver r82600_driver = {
 359         .name = EDAC_MOD_STR,
 360         .probe = r82600_init_one,
 361         .remove = __devexit_p(r82600_remove_one),
 362         .id_table = r82600_pci_tbl,
 363 };
 364
 365 static int __init r82600_init(void)
 366 {
 367         return pci_register_driver(&r82600_driver);
 368 }
 369
 370 static void __exit r82600_exit(void)
 371 {
 372         pci_unregister_driver(&r82600_driver);
 373 }
 374
 375 module_init(r82600_init);
 376 module_exit(r82600_exit);
 377
 378 MODULE_LICENSE("GPL");
 379 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
 380         "on behalf of EADS Astrium");
 381 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
 382
 383 module_param(disable_hardware_scrub, bool, 0644);
 384 MODULE_PARM_DESC(disable_hardware_scrub,
 385                  "If set, disable the chipset's automatic scrub for CEs");