drivers/edac/r82600_edac.c

   1 /*
   2  * Radisys 82600 Embedded chipset Memory Controller kernel module
   3  * (C) 2005 EADS Astrium
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
   8  * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
   9  *
  10  * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
  11  *
  12  * Written with reference to 82600 High Integration Dual PCI System
  13  * Controller Data Book:
  14  * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
  15  * references to this document given in []
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/pci.h>
  22 #include <linux/pci_ids.h>
  23 #include <linux/slab.h>
  24 #include "edac_mc.h"
  25
  26 #define R82600_REVISION " Ver: 2.0.0 " __DATE__
  27
  28 #define r82600_printk(level, fmt, arg...) \
  29         edac_printk(level, "r82600", fmt, ##arg)
  30
  31 #define r82600_mc_printk(mci, level, fmt, arg...) \
  32         edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
  33
  34 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
  35  * supports up to four banks of memory. The four banks can support a mix of
  36  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
  37  * each of which can be any size from 16MB to 512MB. Both registered (control
  38  * signals buffered) and unbuffered DIMM types are supported. Mixing of
  39  * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
  40  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
  41  * the CPU bus, 66MHz, 100MHz or 133MHz."
  42  */
  43
  44 #define R82600_NR_CSROWS 4
  45 #define R82600_NR_CHANS  1
  46 #define R82600_NR_DIMMS  4
  47
  48 #define R82600_BRIDGE_ID  0x8200
  49
  50 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
  51 #define R82600_DRAMC    0x57    /* Various SDRAM related control bits
  52                                  * all bits are R/W
  53                                  *
  54                                  * 7    SDRAM ISA Hole Enable
  55                                  * 6    Flash Page Mode Enable
  56                                  * 5    ECC Enable: 1=ECC 0=noECC
  57                                  * 4    DRAM DIMM Type: 1=
  58                                  * 3    BIOS Alias Disable
  59                                  * 2    SDRAM BIOS Flash Write Enable
  60                                  * 1:0  SDRAM Refresh Rate: 00=Disabled
  61                                  *          01=7.8usec (256Mbit SDRAMs)
  62                                  *          10=15.6us 11=125usec
  63                                  */
  64
  65 #define R82600_SDRAMC   0x76    /* "SDRAM Control Register"
  66                                  * More SDRAM related control bits
  67                                  * all bits are R/W
  68                                  *
  69                                  * 15:8 Reserved.
  70                                  *
  71                                  * 7:5  Special SDRAM Mode Select
  72                                  *
  73                                  * 4    Force ECC
  74                                  *
  75                                  *        1=Drive ECC bits to 0 during
  76                                  *          write cycles (i.e. ECC test mode)
  77                                  *
  78                                  *        0=Normal ECC functioning
  79                                  *
  80                                  * 3    Enhanced Paging Enable
  81                                  *
  82                                  * 2    CAS# Latency 0=3clks 1=2clks
  83                                  *
  84                                  * 1    RAS# to CAS# Delay 0=3 1=2
  85                                  *
  86                                  * 0    RAS# Precharge     0=3 1=2
  87                                  */
  88
  89 #define R82600_EAP      0x80    /* ECC Error Address Pointer Register
  90                                  *
  91                                  * 31    Disable Hardware Scrubbing (RW)
  92                                  *        0=Scrub on corrected read
  93                                  *        1=Don't scrub on corrected read
  94                                  *
  95                                  * 30:12 Error Address Pointer (RO)
  96                                  *        Upper 19 bits of error address
  97                                  *
  98                                  * 11:4  Syndrome Bits (RO)
  99                                  *
 100                                  * 3     BSERR# on multibit error (RW)
 101                                  *        1=enable 0=disable
 102                                  *
 103                                  * 2     NMI on Single Bit Eror (RW)
 104                                  *        1=NMI triggered by SBE n.b. other
 105                                  *          prerequeists
 106                                  *        0=NMI not triggered
 107                                  *
 108                                  * 1     MBE (R/WC)
 109                                  *        read 1=MBE at EAP (see above)
 110                                  *        read 0=no MBE, or SBE occurred first
 111                                  *        write 1=Clear MBE status (must also
 112                                  *          clear SBE)
 113                                  *        write 0=NOP
 114                                  *
 115                                  * 1     SBE (R/WC)
 116                                  *        read 1=SBE at EAP (see above)
 117                                  *        read 0=no SBE, or MBE occurred first
 118                                  *        write 1=Clear SBE status (must also
 119                                  *          clear MBE)
 120                                  *        write 0=NOP
 121                                  */
 122
 123 #define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
 124                                  *  Registers
 125                                  *
 126                                  * 7:0  Address lines 30:24 - upper limit of
 127                                  * each row [p57]
 128                                  */
 129
 130 struct r82600_error_info {
 131         u32 eapr;
 132 };
 133
 134 static unsigned int disable_hardware_scrub = 0;
 135
 136 static void r82600_get_error_info (struct mem_ctl_info *mci,
 137                 struct r82600_error_info *info)
 138 {
 139         struct pci_dev *pdev;
 140
 141         pdev = to_pci_dev(mci->dev);
 142         pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
 143
 144         if (info->eapr & BIT(0))
 145                 /* Clear error to allow next error to be reported [p.62] */
 146                 pci_write_bits32(pdev, R82600_EAP,
 147                                 ((u32) BIT(0) & (u32) BIT(1)),
 148                                 ((u32) BIT(0) & (u32) BIT(1)));
 149
 150         if (info->eapr & BIT(1))
 151                 /* Clear error to allow next error to be reported [p.62] */
 152                 pci_write_bits32(pdev, R82600_EAP,
 153                                 ((u32) BIT(0) & (u32) BIT(1)),
 154                                 ((u32) BIT(0) & (u32) BIT(1)));
 155 }
 156
 157 static int r82600_process_error_info (struct mem_ctl_info *mci,
 158                 struct r82600_error_info *info, int handle_errors)
 159 {
 160         int error_found;
 161         u32 eapaddr, page;
 162         u32 syndrome;
 163
 164         error_found = 0;
 165
 166         /* bits 30:12 store the upper 19 bits of the 32 bit error address */
 167         eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
 168         /* Syndrome in bits 11:4 [p.62]       */
 169         syndrome = (info->eapr >> 4) & 0xFF;
 170
 171         /* the R82600 reports at less than page *
 172          * granularity (upper 19 bits only)     */
 173         page = eapaddr >> PAGE_SHIFT;
 174
 175         if (info->eapr & BIT(0)) {  /* CE? */
 176                 error_found = 1;
 177
 178                 if (handle_errors)
 179                         edac_mc_handle_ce(mci, page, 0,  /* not avail */
 180                                         syndrome,
 181                                         edac_mc_find_csrow_by_page(mci, page),
 182                                         0,  /* channel */
 183                                         mci->ctl_name);
 184         }
 185
 186         if (info->eapr & BIT(1)) {  /* UE? */
 187                 error_found = 1;
 188
 189                 if (handle_errors)
 190                         /* 82600 doesn't give enough info */
 191                         edac_mc_handle_ue(mci, page, 0,
 192                                 edac_mc_find_csrow_by_page(mci, page),
 193                                 mci->ctl_name);
 194         }
 195
 196         return error_found;
 197 }
 198
 199 static void r82600_check(struct mem_ctl_info *mci)
 200 {
 201         struct r82600_error_info info;
 202
 203         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 204         r82600_get_error_info(mci, &info);
 205         r82600_process_error_info(mci, &info, 1);
 206 }
 207
 208 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
 209 {
 210         int rc = -ENODEV;
 211         int index;
 212         struct mem_ctl_info *mci = NULL;
 213         u8 dramcr;
 214         u32 ecc_on;
 215         u32 reg_sdram;
 216         u32 eapr;
 217         u32 scrub_disabled;
 218         u32 sdram_refresh_rate;
 219         u32 row_high_limit_last = 0;
 220         struct r82600_error_info discard;
 221
 222         debugf0("%s()\n", __func__);
 223         pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
 224         pci_read_config_dword(pdev, R82600_EAP, &eapr);
 225         ecc_on = dramcr & BIT(5);
 226         reg_sdram = dramcr & BIT(4);
 227         scrub_disabled = eapr & BIT(31);
 228         sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
 229         debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
 230                 sdram_refresh_rate);
 231         debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
 232         mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
 233
 234         if (mci == NULL) {
 235                 rc = -ENOMEM;
 236                 goto fail;
 237         }
 238
 239         debugf0("%s(): mci = %p\n", __func__, mci);
 240         mci->dev = &pdev->dev;
 241         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
 242         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 243         /* FIXME try to work out if the chip leads have been used for COM2
 244          * instead on this board? [MA6?] MAYBE:
 245          */
 246
 247         /* On the R82600, the pins for memory bits 72:65 - i.e. the   *
 248          * EC bits are shared with the pins for COM2 (!), so if COM2  *
 249          * is enabled, we assume COM2 is wired up, and thus no EDAC   *
 250          * is possible.                                               */
 251         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 252
 253         if (ecc_on) {
 254                 if (scrub_disabled)
 255                         debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
 256                                 "%#0x\n", __func__, mci, eapr);
 257         } else
 258                 mci->edac_cap = EDAC_FLAG_NONE;
 259
 260         mci->mod_name = EDAC_MOD_STR;
 261         mci->mod_ver = R82600_REVISION;
 262         mci->ctl_name = "R82600";
 263         mci->edac_check = r82600_check;
 264         mci->ctl_page_to_phys = NULL;
 265
 266         for (index = 0; index < mci->nr_csrows; index++) {
 267                 struct csrow_info *csrow = &mci->csrows[index];
 268                 u8 drbar;       /* sDram Row Boundry Address Register */
 269                 u32 row_high_limit;
 270                 u32 row_base;
 271
 272                 /* find the DRAM Chip Select Base address and mask */
 273                 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
 274
 275                 debugf1("MC%d: %s() Row=%d DRBA = %#0x\n", mci->mc_idx,
 276                         __func__, index, drbar);
 277
 278                 row_high_limit = ((u32) drbar << 24);
 279 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
 280
 281                 debugf1("MC%d: %s() Row=%d, Boundry Address=%#0x, Last = "
 282                         "%#0x \n", mci->mc_idx, __func__, index,
 283                         row_high_limit, row_high_limit_last);
 284
 285                 /* Empty row [p.57] */
 286                 if (row_high_limit == row_high_limit_last)
 287                         continue;
 288
 289                 row_base = row_high_limit_last;
 290                 csrow->first_page = row_base >> PAGE_SHIFT;
 291                 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
 292                 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
 293                 /* Error address is top 19 bits - so granularity is      *
 294                  * 14 bits                                               */
 295                 csrow->grain = 1 << 14;
 296                 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
 297                 /* FIXME - check that this is unknowable with this chipset */
 298                 csrow->dtype = DEV_UNKNOWN;
 299
 300                 /* Mode is global on 82600 */
 301                 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
 302                 row_high_limit_last = row_high_limit;
 303         }
 304
 305         r82600_get_error_info(mci, &discard);  /* clear counters */
 306
 307         if (edac_mc_add_mc(mci)) {
 308                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 309                 goto fail;
 310         }
 311
 312         /* get this far and it's successful */
 313
 314         if (disable_hardware_scrub) {
 315                 debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
 316                         __func__);
 317                 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
 318         }
 319
 320         debugf3("%s(): success\n", __func__);
 321         return 0;
 322
 323 fail:
 324         if (mci)
 325                 edac_mc_free(mci);
 326
 327         return rc;
 328 }
 329
 330 /* returns count (>= 0), or negative on error */
 331 static int __devinit r82600_init_one(struct pci_dev *pdev,
 332                 const struct pci_device_id *ent)
 333 {
 334         debugf0("%s()\n", __func__);
 335
 336         /* don't need to call pci_device_enable() */
 337         return r82600_probe1(pdev, ent->driver_data);
 338 }
 339
 340 static void __devexit r82600_remove_one(struct pci_dev *pdev)
 341 {
 342         struct mem_ctl_info *mci;
 343
 344         debugf0("%s()\n", __func__);
 345
 346         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 347                 return;
 348
 349         edac_mc_free(mci);
 350 }
 351
 352 static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
 353         {
 354                 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
 355         },
 356         {
 357                 0,
 358         }       /* 0 terminated list. */
 359 };
 360
 361 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
 362
 363 static struct pci_driver r82600_driver = {
 364         .name = EDAC_MOD_STR,
 365         .probe = r82600_init_one,
 366         .remove = __devexit_p(r82600_remove_one),
 367         .id_table = r82600_pci_tbl,
 368 };
 369
 370 static int __init r82600_init(void)
 371 {
 372         return pci_register_driver(&r82600_driver);
 373 }
 374
 375 static void __exit r82600_exit(void)
 376 {
 377         pci_unregister_driver(&r82600_driver);
 378 }
 379
 380 module_init(r82600_init);
 381 module_exit(r82600_exit);
 382
 383 MODULE_LICENSE("GPL");
 384 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
 385         "on behalf of EADS Astrium");
 386 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
 387
 388 module_param(disable_hardware_scrub, bool, 0644);
 389 MODULE_PARM_DESC(disable_hardware_scrub,
 390                  "If set, disable the chipset's automatic scrub for CEs");