1 /* Intel i7 core/Nehalem Memory Controller kernel module
3 * This driver supports yhe memory controllers found on the Intel
4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
11 * Copyright (c) 2009-2010 by:
12 * Mauro Carvalho Chehab <mchehab@redhat.com>
14 * Red Hat Inc. http://www.redhat.com
16 * Forked and adapted from the i5400_edac driver
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/edac.h>
35 #include <linux/mmzone.h>
36 #include <linux/edac_mce.h>
37 #include <linux/smp.h>
38 #include <asm/processor.h>
40 #include "edac_core.h"
43 static LIST_HEAD(i7core_edac_list);
44 static DEFINE_MUTEX(i7core_edac_lock);
47 static int use_pci_fixup;
48 module_param(use_pci_fixup, int, 0444);
49 MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
51 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
52 * registers start at bus 255, and are not reported by BIOS.
53 * We currently find devices with only 2 sockets. In order to support more QPI
54 * Quick Path Interconnect, just increment this number.
56 #define MAX_SOCKET_BUSES 2
60 * Alter this version for the module when modifications are made
62 #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
63 #define EDAC_MOD_STR "i7core_edac"
68 #define i7core_printk(level, fmt, arg...) \
69 edac_printk(level, "i7core", fmt, ##arg)
71 #define i7core_mc_printk(mci, level, fmt, arg...) \
72 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
75 * i7core Memory Controller Registers
78 /* OFFSETS for Device 0 Function 0 */
80 #define MC_CFG_CONTROL 0x90
82 /* OFFSETS for Device 3 Function 0 */
84 #define MC_CONTROL 0x48
85 #define MC_STATUS 0x4c
86 #define MC_MAX_DOD 0x64
89 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
90 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
93 #define MC_TEST_ERR_RCV1 0x60
94 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
96 #define MC_TEST_ERR_RCV0 0x64
97 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
98 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
100 /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
101 #define MC_COR_ECC_CNT_0 0x80
102 #define MC_COR_ECC_CNT_1 0x84
103 #define MC_COR_ECC_CNT_2 0x88
104 #define MC_COR_ECC_CNT_3 0x8c
105 #define MC_COR_ECC_CNT_4 0x90
106 #define MC_COR_ECC_CNT_5 0x94
108 #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
109 #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
112 /* OFFSETS for Devices 4,5 and 6 Function 0 */
114 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
115 #define THREE_DIMMS_PRESENT (1 << 24)
116 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
117 #define QUAD_RANK_PRESENT (1 << 22)
118 #define REGISTERED_DIMM (1 << 15)
120 #define MC_CHANNEL_MAPPER 0x60
121 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
122 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
124 #define MC_CHANNEL_RANK_PRESENT 0x7c
125 #define RANK_PRESENT_MASK 0xffff
127 #define MC_CHANNEL_ADDR_MATCH 0xf0
128 #define MC_CHANNEL_ERROR_MASK 0xf8
129 #define MC_CHANNEL_ERROR_INJECT 0xfc
130 #define INJECT_ADDR_PARITY 0x10
131 #define INJECT_ECC 0x08
132 #define MASK_CACHELINE 0x06
133 #define MASK_FULL_CACHELINE 0x06
134 #define MASK_MSB32_CACHELINE 0x04
135 #define MASK_LSB32_CACHELINE 0x02
136 #define NO_MASK_CACHELINE 0x00
137 #define REPEAT_EN 0x01
139 /* OFFSETS for Devices 4,5 and 6 Function 1 */
141 #define MC_DOD_CH_DIMM0 0x48
142 #define MC_DOD_CH_DIMM1 0x4c
143 #define MC_DOD_CH_DIMM2 0x50
144 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
145 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
146 #define DIMM_PRESENT_MASK (1 << 9)
147 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
148 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
149 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
150 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
151 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
152 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
153 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
154 #define MC_DOD_NUMCOL_MASK 3
155 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
157 #define MC_RANK_PRESENT 0x7c
159 #define MC_SAG_CH_0 0x80
160 #define MC_SAG_CH_1 0x84
161 #define MC_SAG_CH_2 0x88
162 #define MC_SAG_CH_3 0x8c
163 #define MC_SAG_CH_4 0x90
164 #define MC_SAG_CH_5 0x94
165 #define MC_SAG_CH_6 0x98
166 #define MC_SAG_CH_7 0x9c
168 #define MC_RIR_LIMIT_CH_0 0x40
169 #define MC_RIR_LIMIT_CH_1 0x44
170 #define MC_RIR_LIMIT_CH_2 0x48
171 #define MC_RIR_LIMIT_CH_3 0x4C
172 #define MC_RIR_LIMIT_CH_4 0x50
173 #define MC_RIR_LIMIT_CH_5 0x54
174 #define MC_RIR_LIMIT_CH_6 0x58
175 #define MC_RIR_LIMIT_CH_7 0x5C
176 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
178 #define MC_RIR_WAY_CH 0x80
179 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
180 #define MC_RIR_WAY_RANK_MASK 0x7
187 #define MAX_DIMMS 3 /* Max DIMMS per channel */
188 #define MAX_MCR_FUNC 4
189 #define MAX_CHAN_FUNC 3
199 struct i7core_inject {
206 /* Error address mask */
207 int channel, dimm, rank, bank, page, col;
210 struct i7core_channel {
215 struct pci_id_descr {
222 struct pci_id_table {
223 const struct pci_id_descr *descr;
228 struct list_head list;
230 struct pci_dev **pdev;
232 struct mem_ctl_info *mci;
236 struct pci_dev *pci_noncore;
237 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
238 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
240 struct i7core_dev *i7core_dev;
242 struct i7core_info info;
243 struct i7core_inject inject;
244 struct i7core_channel channel[NUM_CHANS];
246 int ce_count_available;
247 int csrow_map[NUM_CHANS][MAX_DIMMS];
249 /* ECC corrected errors counts per udimm */
250 unsigned long udimm_ce_count[MAX_DIMMS];
251 int udimm_last_ce_count[MAX_DIMMS];
252 /* ECC corrected errors counts per rdimm */
253 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
254 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
256 unsigned int is_registered;
259 struct edac_mce edac_mce;
261 /* Fifo double buffers */
262 struct mce mce_entry[MCE_LOG_LEN];
263 struct mce mce_outentry[MCE_LOG_LEN];
265 /* Fifo in/out counters */
266 unsigned mce_in, mce_out;
268 /* Count indicator to show errors not got */
269 unsigned mce_overrun;
271 /* Struct to control EDAC polling */
272 struct edac_pci_ctl_info *i7core_pci;
275 #define PCI_DESCR(device, function, device_id) \
277 .func = (function), \
278 .dev_id = (device_id)
280 static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
281 /* Memory controller */
282 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
283 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
284 /* Exists only for RDIMM */
285 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
286 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
289 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
290 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
291 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
292 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
295 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
296 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
297 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
298 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
301 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
302 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
303 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
304 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
306 /* Generic Non-core registers */
308 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
309 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
310 * the probing code needs to test for the other address in case of
311 * failure of this one
313 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
317 static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
318 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
319 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
320 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
322 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
323 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
324 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
325 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
327 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
328 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
329 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
330 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
333 * This is the PCI device has an alternate address on some
334 * processors like Core i7 860
336 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
339 static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
340 /* Memory controller */
341 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
342 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
343 /* Exists only for RDIMM */
344 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
345 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
348 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
349 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
350 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
351 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
354 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
355 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
356 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
357 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
360 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
361 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
362 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
363 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
365 /* Generic Non-core registers */
366 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
370 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
371 static const struct pci_id_table pci_dev_table[] = {
372 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
373 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
374 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
378 * pci_device_id table for which devices we are looking for
380 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
381 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
382 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
383 {0,} /* 0 terminated list. */
386 /****************************************************************************
387 Anciliary status routines
388 ****************************************************************************/
390 /* MC_CONTROL bits */
391 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
392 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
395 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
396 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
398 /* MC_MAX_DOD read functions */
399 static inline int numdimms(u32 dimms)
401 return (dimms & 0x3) + 1;
404 static inline int numrank(u32 rank)
406 static int ranks[4] = { 1, 2, 4, -EINVAL };
408 return ranks[rank & 0x3];
411 static inline int numbank(u32 bank)
413 static int banks[4] = { 4, 8, 16, -EINVAL };
415 return banks[bank & 0x3];
418 static inline int numrow(u32 row)
420 static int rows[8] = {
421 1 << 12, 1 << 13, 1 << 14, 1 << 15,
422 1 << 16, -EINVAL, -EINVAL, -EINVAL,
425 return rows[row & 0x7];
428 static inline int numcol(u32 col)
430 static int cols[8] = {
431 1 << 10, 1 << 11, 1 << 12, -EINVAL,
433 return cols[col & 0x3];
436 static struct i7core_dev *get_i7core_dev(u8 socket)
438 struct i7core_dev *i7core_dev;
440 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
441 if (i7core_dev->socket == socket)
448 static struct i7core_dev *alloc_i7core_dev(u8 socket,
449 const struct pci_id_table *table)
451 struct i7core_dev *i7core_dev;
453 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
457 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
459 if (!i7core_dev->pdev) {
464 i7core_dev->socket = socket;
465 i7core_dev->n_devs = table->n_devs;
466 list_add_tail(&i7core_dev->list, &i7core_edac_list);
471 static void free_i7core_dev(struct i7core_dev *i7core_dev)
473 list_del(&i7core_dev->list);
474 kfree(i7core_dev->pdev);
478 /****************************************************************************
479 Memory check routines
480 ****************************************************************************/
481 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
484 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
490 for (i = 0; i < i7core_dev->n_devs; i++) {
491 if (!i7core_dev->pdev[i])
494 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
495 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
496 return i7core_dev->pdev[i];
504 * i7core_get_active_channels() - gets the number of channels and csrows
505 * @socket: Quick Path Interconnect socket
506 * @channels: Number of channels that will be returned
507 * @csrows: Number of csrows found
509 * Since EDAC core needs to know in advance the number of available channels
510 * and csrows, in order to allocate memory for csrows/channels, it is needed
511 * to run two similar steps. At the first step, implemented on this function,
512 * it checks the number of csrows/channels present at one socket.
513 * this is used in order to properly allocate the size of mci components.
515 * It should be noticed that none of the current available datasheets explain
516 * or even mention how csrows are seen by the memory controller. So, we need
517 * to add a fake description for csrows.
518 * So, this driver is attributing one DIMM memory for one csrow.
520 static int i7core_get_active_channels(const u8 socket, unsigned *channels,
523 struct pci_dev *pdev = NULL;
530 pdev = get_pdev_slot_func(socket, 3, 0);
532 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
537 /* Device 3 function 0 reads */
538 pci_read_config_dword(pdev, MC_STATUS, &status);
539 pci_read_config_dword(pdev, MC_CONTROL, &control);
541 for (i = 0; i < NUM_CHANS; i++) {
543 /* Check if the channel is active */
544 if (!(control & (1 << (8 + i))))
547 /* Check if the channel is disabled */
548 if (status & (1 << i))
551 pdev = get_pdev_slot_func(socket, i + 4, 1);
553 i7core_printk(KERN_ERR, "Couldn't find socket %d "
558 /* Devices 4-6 function 1 */
559 pci_read_config_dword(pdev,
560 MC_DOD_CH_DIMM0, &dimm_dod[0]);
561 pci_read_config_dword(pdev,
562 MC_DOD_CH_DIMM1, &dimm_dod[1]);
563 pci_read_config_dword(pdev,
564 MC_DOD_CH_DIMM2, &dimm_dod[2]);
568 for (j = 0; j < 3; j++) {
569 if (!DIMM_PRESENT(dimm_dod[j]))
575 debugf0("Number of active channels on socket %d: %d\n",
581 static int get_dimm_config(const struct mem_ctl_info *mci)
583 struct i7core_pvt *pvt = mci->pvt_info;
584 struct csrow_info *csr;
585 struct pci_dev *pdev;
588 unsigned long last_page = 0;
592 /* Get data from the MC register, function 0 */
593 pdev = pvt->pci_mcr[0];
597 /* Device 3 function 0 reads */
598 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
599 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
600 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
601 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
603 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
604 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
605 pvt->info.max_dod, pvt->info.ch_map);
607 if (ECC_ENABLED(pvt)) {
608 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
610 mode = EDAC_S8ECD8ED;
612 mode = EDAC_S4ECD4ED;
614 debugf0("ECC disabled\n");
618 /* FIXME: need to handle the error codes */
619 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
621 numdimms(pvt->info.max_dod),
622 numrank(pvt->info.max_dod >> 2),
623 numbank(pvt->info.max_dod >> 4),
624 numrow(pvt->info.max_dod >> 6),
625 numcol(pvt->info.max_dod >> 9));
627 for (i = 0; i < NUM_CHANS; i++) {
628 u32 data, dimm_dod[3], value[8];
630 if (!pvt->pci_ch[i][0])
633 if (!CH_ACTIVE(pvt, i)) {
634 debugf0("Channel %i is not active\n", i);
637 if (CH_DISABLED(pvt, i)) {
638 debugf0("Channel %i is disabled\n", i);
642 /* Devices 4-6 function 0 */
643 pci_read_config_dword(pvt->pci_ch[i][0],
644 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
646 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
649 if (data & REGISTERED_DIMM)
654 if (data & THREE_DIMMS_PRESENT)
655 pvt->channel[i].dimms = 3;
656 else if (data & SINGLE_QUAD_RANK_PRESENT)
657 pvt->channel[i].dimms = 1;
659 pvt->channel[i].dimms = 2;
662 /* Devices 4-6 function 1 */
663 pci_read_config_dword(pvt->pci_ch[i][1],
664 MC_DOD_CH_DIMM0, &dimm_dod[0]);
665 pci_read_config_dword(pvt->pci_ch[i][1],
666 MC_DOD_CH_DIMM1, &dimm_dod[1]);
667 pci_read_config_dword(pvt->pci_ch[i][1],
668 MC_DOD_CH_DIMM2, &dimm_dod[2]);
670 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
671 "%d ranks, %cDIMMs\n",
673 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
675 pvt->channel[i].ranks,
676 (data & REGISTERED_DIMM) ? 'R' : 'U');
678 for (j = 0; j < 3; j++) {
679 u32 banks, ranks, rows, cols;
682 if (!DIMM_PRESENT(dimm_dod[j]))
685 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
686 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
687 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
688 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
690 /* DDR3 has 8 I/O banks */
691 size = (rows * cols * banks * ranks) >> (20 - 3);
693 pvt->channel[i].dimms++;
695 debugf0("\tdimm %d %d Mb offset: %x, "
696 "bank: %d, rank: %d, row: %#x, col: %#x\n",
698 RANKOFFSET(dimm_dod[j]),
699 banks, ranks, rows, cols);
701 npages = MiB_TO_PAGES(size);
703 csr = &mci->csrows[csrow];
704 csr->first_page = last_page + 1;
706 csr->last_page = last_page;
707 csr->nr_pages = npages;
711 csr->csrow_idx = csrow;
712 csr->nr_channels = 1;
714 csr->channels[0].chan_idx = i;
715 csr->channels[0].ce_count = 0;
717 pvt->csrow_map[i][j] = csrow;
727 csr->dtype = DEV_X16;
730 csr->dtype = DEV_UNKNOWN;
733 csr->edac_mode = mode;
739 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
740 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
741 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
742 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
743 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
744 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
745 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
746 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
747 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
748 for (j = 0; j < 8; j++)
749 debugf1("\t\t%#x\t%#x\t%#x\n",
750 (value[j] >> 27) & 0x1,
751 (value[j] >> 24) & 0x7,
752 (value[j] && ((1 << 24) - 1)));
758 /****************************************************************************
759 Error insertion routines
760 ****************************************************************************/
762 /* The i7core has independent error injection features per channel.
763 However, to have a simpler code, we don't allow enabling error injection
764 on more than one channel.
765 Also, since a change at an inject parameter will be applied only at enable,
766 we're disabling error injection on all write calls to the sysfs nodes that
767 controls the error code injection.
769 static int disable_inject(const struct mem_ctl_info *mci)
771 struct i7core_pvt *pvt = mci->pvt_info;
773 pvt->inject.enable = 0;
775 if (!pvt->pci_ch[pvt->inject.channel][0])
778 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
779 MC_CHANNEL_ERROR_INJECT, 0);
785 * i7core inject inject.section
787 * accept and store error injection inject.section value
788 * bit 0 - refers to the lower 32-byte half cacheline
789 * bit 1 - refers to the upper 32-byte half cacheline
791 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
792 const char *data, size_t count)
794 struct i7core_pvt *pvt = mci->pvt_info;
798 if (pvt->inject.enable)
801 rc = strict_strtoul(data, 10, &value);
802 if ((rc < 0) || (value > 3))
805 pvt->inject.section = (u32) value;
809 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
812 struct i7core_pvt *pvt = mci->pvt_info;
813 return sprintf(data, "0x%08x\n", pvt->inject.section);
819 * accept and store error injection inject.section value
820 * bit 0 - repeat enable - Enable error repetition
821 * bit 1 - inject ECC error
822 * bit 2 - inject parity error
824 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
825 const char *data, size_t count)
827 struct i7core_pvt *pvt = mci->pvt_info;
831 if (pvt->inject.enable)
834 rc = strict_strtoul(data, 10, &value);
835 if ((rc < 0) || (value > 7))
838 pvt->inject.type = (u32) value;
842 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
845 struct i7core_pvt *pvt = mci->pvt_info;
846 return sprintf(data, "0x%08x\n", pvt->inject.type);
850 * i7core_inject_inject.eccmask_store
852 * The type of error (UE/CE) will depend on the inject.eccmask value:
853 * Any bits set to a 1 will flip the corresponding ECC bit
854 * Correctable errors can be injected by flipping 1 bit or the bits within
855 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
856 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
857 * uncorrectable error to be injected.
859 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
860 const char *data, size_t count)
862 struct i7core_pvt *pvt = mci->pvt_info;
866 if (pvt->inject.enable)
869 rc = strict_strtoul(data, 10, &value);
873 pvt->inject.eccmask = (u32) value;
877 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
880 struct i7core_pvt *pvt = mci->pvt_info;
881 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
887 * The type of error (UE/CE) will depend on the inject.eccmask value:
888 * Any bits set to a 1 will flip the corresponding ECC bit
889 * Correctable errors can be injected by flipping 1 bit or the bits within
890 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
891 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
892 * uncorrectable error to be injected.
895 #define DECLARE_ADDR_MATCH(param, limit) \
896 static ssize_t i7core_inject_store_##param( \
897 struct mem_ctl_info *mci, \
898 const char *data, size_t count) \
900 struct i7core_pvt *pvt; \
904 debugf1("%s()\n", __func__); \
905 pvt = mci->pvt_info; \
907 if (pvt->inject.enable) \
908 disable_inject(mci); \
910 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
913 rc = strict_strtoul(data, 10, &value); \
914 if ((rc < 0) || (value >= limit)) \
918 pvt->inject.param = value; \
923 static ssize_t i7core_inject_show_##param( \
924 struct mem_ctl_info *mci, \
927 struct i7core_pvt *pvt; \
929 pvt = mci->pvt_info; \
930 debugf1("%s() pvt=%p\n", __func__, pvt); \
931 if (pvt->inject.param < 0) \
932 return sprintf(data, "any\n"); \
934 return sprintf(data, "%d\n", pvt->inject.param);\
937 #define ATTR_ADDR_MATCH(param) \
941 .mode = (S_IRUGO | S_IWUSR) \
943 .show = i7core_inject_show_##param, \
944 .store = i7core_inject_store_##param, \
947 DECLARE_ADDR_MATCH(channel, 3);
948 DECLARE_ADDR_MATCH(dimm, 3);
949 DECLARE_ADDR_MATCH(rank, 4);
950 DECLARE_ADDR_MATCH(bank, 32);
951 DECLARE_ADDR_MATCH(page, 0x10000);
952 DECLARE_ADDR_MATCH(col, 0x4000);
954 static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
959 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
960 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
963 for (count = 0; count < 10; count++) {
966 pci_write_config_dword(dev, where, val);
967 pci_read_config_dword(dev, where, &read);
973 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
974 "write=%08x. Read=%08x\n",
975 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
982 * This routine prepares the Memory Controller for error injection.
983 * The error will be injected when some process tries to write to the
984 * memory that matches the given criteria.
985 * The criteria can be set in terms of a mask where dimm, rank, bank, page
986 * and col can be specified.
987 * A -1 value for any of the mask items will make the MCU to ignore
988 * that matching criteria for error injection.
990 * It should be noticed that the error will only happen after a write operation
991 * on a memory that matches the condition. if REPEAT_EN is not enabled at
992 * inject mask, then it will produce just one error. Otherwise, it will repeat
993 * until the injectmask would be cleaned.
995 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
996 * is reliable enough to check if the MC is using the
997 * three channels. However, this is not clear at the datasheet.
999 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
1000 const char *data, size_t count)
1002 struct i7core_pvt *pvt = mci->pvt_info;
1008 if (!pvt->pci_ch[pvt->inject.channel][0])
1011 rc = strict_strtoul(data, 10, &enable);
1016 pvt->inject.enable = 1;
1018 disable_inject(mci);
1022 /* Sets pvt->inject.dimm mask */
1023 if (pvt->inject.dimm < 0)
1026 if (pvt->channel[pvt->inject.channel].dimms > 2)
1027 mask |= (pvt->inject.dimm & 0x3LL) << 35;
1029 mask |= (pvt->inject.dimm & 0x1LL) << 36;
1032 /* Sets pvt->inject.rank mask */
1033 if (pvt->inject.rank < 0)
1036 if (pvt->channel[pvt->inject.channel].dimms > 2)
1037 mask |= (pvt->inject.rank & 0x1LL) << 34;
1039 mask |= (pvt->inject.rank & 0x3LL) << 34;
1042 /* Sets pvt->inject.bank mask */
1043 if (pvt->inject.bank < 0)
1046 mask |= (pvt->inject.bank & 0x15LL) << 30;
1048 /* Sets pvt->inject.page mask */
1049 if (pvt->inject.page < 0)
1052 mask |= (pvt->inject.page & 0xffff) << 14;
1054 /* Sets pvt->inject.column mask */
1055 if (pvt->inject.col < 0)
1058 mask |= (pvt->inject.col & 0x3fff);
1062 * bits 1-2: MASK_HALF_CACHELINE
1064 * bit 4: INJECT_ADDR_PARITY
1067 injectmask = (pvt->inject.type & 1) |
1068 (pvt->inject.section & 0x3) << 1 |
1069 (pvt->inject.type & 0x6) << (3 - 1);
1071 /* Unlock writes to registers - this register is write only */
1072 pci_write_config_dword(pvt->pci_noncore,
1073 MC_CFG_CONTROL, 0x2);
1075 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1076 MC_CHANNEL_ADDR_MATCH, mask);
1077 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1078 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1080 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1081 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1083 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1084 MC_CHANNEL_ERROR_INJECT, injectmask);
1087 * This is something undocumented, based on my tests
1088 * Without writing 8 to this register, errors aren't injected. Not sure
1091 pci_write_config_dword(pvt->pci_noncore,
1094 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1096 mask, pvt->inject.eccmask, injectmask);
1102 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1105 struct i7core_pvt *pvt = mci->pvt_info;
1108 if (!pvt->pci_ch[pvt->inject.channel][0])
1111 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1112 MC_CHANNEL_ERROR_INJECT, &injectmask);
1114 debugf0("Inject error read: 0x%018x\n", injectmask);
1116 if (injectmask & 0x0c)
1117 pvt->inject.enable = 1;
1119 return sprintf(data, "%d\n", pvt->inject.enable);
1122 #define DECLARE_COUNTER(param) \
1123 static ssize_t i7core_show_counter_##param( \
1124 struct mem_ctl_info *mci, \
1127 struct i7core_pvt *pvt = mci->pvt_info; \
1129 debugf1("%s() \n", __func__); \
1130 if (!pvt->ce_count_available || (pvt->is_registered)) \
1131 return sprintf(data, "data unavailable\n"); \
1132 return sprintf(data, "%lu\n", \
1133 pvt->udimm_ce_count[param]); \
1136 #define ATTR_COUNTER(param) \
1139 .name = __stringify(udimm##param), \
1140 .mode = (S_IRUGO | S_IWUSR) \
1142 .show = i7core_show_counter_##param \
1153 static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1154 ATTR_ADDR_MATCH(channel),
1155 ATTR_ADDR_MATCH(dimm),
1156 ATTR_ADDR_MATCH(rank),
1157 ATTR_ADDR_MATCH(bank),
1158 ATTR_ADDR_MATCH(page),
1159 ATTR_ADDR_MATCH(col),
1160 { } /* End of list */
1163 static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1164 .name = "inject_addrmatch",
1165 .mcidev_attr = i7core_addrmatch_attrs,
1168 static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1172 { .attr = { .name = NULL } }
1175 static const struct mcidev_sysfs_group i7core_udimm_counters = {
1176 .name = "all_channel_counts",
1177 .mcidev_attr = i7core_udimm_counters_attrs,
1180 static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1183 .name = "inject_section",
1184 .mode = (S_IRUGO | S_IWUSR)
1186 .show = i7core_inject_section_show,
1187 .store = i7core_inject_section_store,
1190 .name = "inject_type",
1191 .mode = (S_IRUGO | S_IWUSR)
1193 .show = i7core_inject_type_show,
1194 .store = i7core_inject_type_store,
1197 .name = "inject_eccmask",
1198 .mode = (S_IRUGO | S_IWUSR)
1200 .show = i7core_inject_eccmask_show,
1201 .store = i7core_inject_eccmask_store,
1203 .grp = &i7core_inject_addrmatch,
1206 .name = "inject_enable",
1207 .mode = (S_IRUGO | S_IWUSR)
1209 .show = i7core_inject_enable_show,
1210 .store = i7core_inject_enable_store,
1212 { } /* End of list */
1215 static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1218 .name = "inject_section",
1219 .mode = (S_IRUGO | S_IWUSR)
1221 .show = i7core_inject_section_show,
1222 .store = i7core_inject_section_store,
1225 .name = "inject_type",
1226 .mode = (S_IRUGO | S_IWUSR)
1228 .show = i7core_inject_type_show,
1229 .store = i7core_inject_type_store,
1232 .name = "inject_eccmask",
1233 .mode = (S_IRUGO | S_IWUSR)
1235 .show = i7core_inject_eccmask_show,
1236 .store = i7core_inject_eccmask_store,
1238 .grp = &i7core_inject_addrmatch,
1241 .name = "inject_enable",
1242 .mode = (S_IRUGO | S_IWUSR)
1244 .show = i7core_inject_enable_show,
1245 .store = i7core_inject_enable_store,
1247 .grp = &i7core_udimm_counters,
1249 { } /* End of list */
1252 /****************************************************************************
1253 Device initialization routines: put/get, init/exit
1254 ****************************************************************************/
1257 * i7core_put_all_devices 'put' all the devices that we have
1258 * reserved via 'get'
1260 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1264 debugf0(__FILE__ ": %s()\n", __func__);
1265 for (i = 0; i < i7core_dev->n_devs; i++) {
1266 struct pci_dev *pdev = i7core_dev->pdev[i];
1269 debugf0("Removing dev %02x:%02x.%d\n",
1271 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1276 static void i7core_put_all_devices(void)
1278 struct i7core_dev *i7core_dev, *tmp;
1280 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1281 i7core_put_devices(i7core_dev);
1282 free_i7core_dev(i7core_dev);
1286 static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1288 struct pci_dev *pdev = NULL;
1292 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1293 * aren't announced by acpi. So, we need to use a legacy scan probing
1296 while (table && table->descr) {
1297 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1298 if (unlikely(!pdev)) {
1299 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1300 pcibios_scan_specific_bus(255-i);
1307 static unsigned i7core_pci_lastbus(void)
1309 int last_bus = 0, bus;
1310 struct pci_bus *b = NULL;
1312 while ((b = pci_find_next_bus(b)) != NULL) {
1314 debugf0("Found bus %d\n", bus);
1319 debugf0("Last bus %d\n", last_bus);
1325 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
1326 * device/functions we want to reference for this driver
1328 * Need to 'get' device 16 func 1 and func 2
1330 static int i7core_get_onedevice(struct pci_dev **prev,
1331 const struct pci_id_table *table,
1332 const unsigned devno,
1333 const unsigned last_bus)
1335 struct i7core_dev *i7core_dev;
1336 const struct pci_id_descr *dev_descr = &table->descr[devno];
1338 struct pci_dev *pdev = NULL;
1342 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1343 dev_descr->dev_id, *prev);
1346 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1347 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1348 * to probe for the alternate address in case of failure
1350 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1351 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1352 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1354 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1355 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1356 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1365 if (dev_descr->optional)
1371 i7core_printk(KERN_INFO,
1372 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1373 dev_descr->dev, dev_descr->func,
1374 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1376 /* End of list, leave */
1379 bus = pdev->bus->number;
1381 socket = last_bus - bus;
1383 i7core_dev = get_i7core_dev(socket);
1385 i7core_dev = alloc_i7core_dev(socket, table);
1392 if (i7core_dev->pdev[devno]) {
1393 i7core_printk(KERN_ERR,
1394 "Duplicated device for "
1395 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1396 bus, dev_descr->dev, dev_descr->func,
1397 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1402 i7core_dev->pdev[devno] = pdev;
1405 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1406 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1407 i7core_printk(KERN_ERR,
1408 "Device PCI ID %04x:%04x "
1409 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1410 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1411 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1412 bus, dev_descr->dev, dev_descr->func);
1416 /* Be sure that the device is enabled */
1417 if (unlikely(pci_enable_device(pdev) < 0)) {
1418 i7core_printk(KERN_ERR,
1420 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1421 bus, dev_descr->dev, dev_descr->func,
1422 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1426 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1427 socket, bus, dev_descr->dev,
1429 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1436 static int i7core_get_all_devices(void)
1438 int i, j, rc, last_bus;
1439 struct pci_dev *pdev = NULL;
1440 const struct pci_id_table *table;
1442 last_bus = i7core_pci_lastbus();
1444 for (j = 0; j < ARRAY_SIZE(pci_dev_table); j++) {
1445 table = &pci_dev_table[j];
1446 for (i = 0; i < table->n_devs; i++) {
1449 rc = i7core_get_onedevice(&pdev, table, i,
1456 i7core_put_all_devices();
1466 static int mci_bind_devs(struct mem_ctl_info *mci,
1467 struct i7core_dev *i7core_dev)
1469 struct i7core_pvt *pvt = mci->pvt_info;
1470 struct pci_dev *pdev;
1473 pvt->is_registered = 0;
1474 for (i = 0; i < i7core_dev->n_devs; i++) {
1475 pdev = i7core_dev->pdev[i];
1479 func = PCI_FUNC(pdev->devfn);
1480 slot = PCI_SLOT(pdev->devfn);
1482 if (unlikely(func > MAX_MCR_FUNC))
1484 pvt->pci_mcr[func] = pdev;
1485 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1486 if (unlikely(func > MAX_CHAN_FUNC))
1488 pvt->pci_ch[slot - 4][func] = pdev;
1489 } else if (!slot && !func)
1490 pvt->pci_noncore = pdev;
1494 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1495 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1496 pdev, i7core_dev->socket);
1498 if (PCI_SLOT(pdev->devfn) == 3 &&
1499 PCI_FUNC(pdev->devfn) == 2)
1500 pvt->is_registered = 1;
1506 i7core_printk(KERN_ERR, "Device %d, function %d "
1507 "is out of the expected range\n",
1512 /****************************************************************************
1513 Error check routines
1514 ****************************************************************************/
1515 static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
1521 struct i7core_pvt *pvt = mci->pvt_info;
1522 int row = pvt->csrow_map[chan][dimm], i;
1524 for (i = 0; i < add; i++) {
1525 msg = kasprintf(GFP_KERNEL, "Corrected error "
1526 "(Socket=%d channel=%d dimm=%d)",
1527 pvt->i7core_dev->socket, chan, dimm);
1529 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1534 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1540 struct i7core_pvt *pvt = mci->pvt_info;
1541 int add0 = 0, add1 = 0, add2 = 0;
1542 /* Updates CE counters if it is not the first time here */
1543 if (pvt->ce_count_available) {
1544 /* Updates CE counters */
1546 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1547 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1548 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1552 pvt->rdimm_ce_count[chan][2] += add2;
1556 pvt->rdimm_ce_count[chan][1] += add1;
1560 pvt->rdimm_ce_count[chan][0] += add0;
1562 pvt->ce_count_available = 1;
1564 /* Store the new values */
1565 pvt->rdimm_last_ce_count[chan][2] = new2;
1566 pvt->rdimm_last_ce_count[chan][1] = new1;
1567 pvt->rdimm_last_ce_count[chan][0] = new0;
1569 /*updated the edac core */
1571 i7core_rdimm_update_csrow(mci, chan, 0, add0);
1573 i7core_rdimm_update_csrow(mci, chan, 1, add1);
1575 i7core_rdimm_update_csrow(mci, chan, 2, add2);
1579 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1581 struct i7core_pvt *pvt = mci->pvt_info;
1583 int i, new0, new1, new2;
1585 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
1586 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1588 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1590 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1592 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1594 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1596 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1598 for (i = 0 ; i < 3; i++) {
1599 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1600 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1601 /*if the channel has 3 dimms*/
1602 if (pvt->channel[i].dimms > 2) {
1603 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1604 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1605 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1607 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1608 DIMM_BOT_COR_ERR(rcv[i][0]);
1609 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1610 DIMM_BOT_COR_ERR(rcv[i][1]);
1614 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1618 /* This function is based on the device 3 function 4 registers as described on:
1619 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1620 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1621 * also available at:
1622 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1624 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1626 struct i7core_pvt *pvt = mci->pvt_info;
1628 int new0, new1, new2;
1630 if (!pvt->pci_mcr[4]) {
1631 debugf0("%s MCR registers not found\n", __func__);
1635 /* Corrected test errors */
1636 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1637 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1639 /* Store the new values */
1640 new2 = DIMM2_COR_ERR(rcv1);
1641 new1 = DIMM1_COR_ERR(rcv0);
1642 new0 = DIMM0_COR_ERR(rcv0);
1644 /* Updates CE counters if it is not the first time here */
1645 if (pvt->ce_count_available) {
1646 /* Updates CE counters */
1647 int add0, add1, add2;
1649 add2 = new2 - pvt->udimm_last_ce_count[2];
1650 add1 = new1 - pvt->udimm_last_ce_count[1];
1651 add0 = new0 - pvt->udimm_last_ce_count[0];
1655 pvt->udimm_ce_count[2] += add2;
1659 pvt->udimm_ce_count[1] += add1;
1663 pvt->udimm_ce_count[0] += add0;
1665 if (add0 | add1 | add2)
1666 i7core_printk(KERN_ERR, "New Corrected error(s): "
1667 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1670 pvt->ce_count_available = 1;
1672 /* Store the new values */
1673 pvt->udimm_last_ce_count[2] = new2;
1674 pvt->udimm_last_ce_count[1] = new1;
1675 pvt->udimm_last_ce_count[0] = new0;
1679 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1680 * Architectures Software Developer’s Manual Volume 3B.
1681 * Nehalem are defined as family 0x06, model 0x1a
1683 * The MCA registers used here are the following ones:
1684 * struct mce field MCA Register
1685 * m->status MSR_IA32_MC8_STATUS
1686 * m->addr MSR_IA32_MC8_ADDR
1687 * m->misc MSR_IA32_MC8_MISC
1688 * In the case of Nehalem, the error information is masked at .status and .misc
1691 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1692 const struct mce *m)
1694 struct i7core_pvt *pvt = mci->pvt_info;
1695 char *type, *optype, *err, *msg;
1696 unsigned long error = m->status & 0x1ff0000l;
1697 u32 optypenum = (m->status >> 4) & 0x07;
1698 u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1699 u32 dimm = (m->misc >> 16) & 0x3;
1700 u32 channel = (m->misc >> 18) & 0x3;
1701 u32 syndrome = m->misc >> 32;
1702 u32 errnum = find_first_bit(&error, 32);
1705 if (m->mcgstatus & 1)
1710 switch (optypenum) {
1712 optype = "generic undef request";
1715 optype = "read error";
1718 optype = "write error";
1721 optype = "addr/cmd error";
1724 optype = "scrubbing error";
1727 optype = "reserved";
1733 err = "read ECC error";
1736 err = "RAS ECC error";
1739 err = "write parity error";
1742 err = "redundacy loss";
1748 err = "memory range error";
1751 err = "RTID out of range";
1754 err = "address parity error";
1757 err = "byte enable parity error";
1763 /* FIXME: should convert addr into bank and rank information */
1764 msg = kasprintf(GFP_ATOMIC,
1765 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
1766 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1767 type, (long long) m->addr, m->cpu, dimm, channel,
1768 syndrome, core_err_cnt, (long long)m->status,
1769 (long long)m->misc, optype, err);
1773 csrow = pvt->csrow_map[channel][dimm];
1775 /* Call the helper to output message */
1776 if (m->mcgstatus & 1)
1777 edac_mc_handle_fbd_ue(mci, csrow, 0,
1778 0 /* FIXME: should be channel here */, msg);
1779 else if (!pvt->is_registered)
1780 edac_mc_handle_fbd_ce(mci, csrow,
1781 0 /* FIXME: should be channel here */, msg);
1787 * i7core_check_error Retrieve and process errors reported by the
1788 * hardware. Called by the Core module.
1790 static void i7core_check_error(struct mem_ctl_info *mci)
1792 struct i7core_pvt *pvt = mci->pvt_info;
1798 * MCE first step: Copy all mce errors into a temporary buffer
1799 * We use a double buffering here, to reduce the risk of
1803 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1806 goto check_ce_error;
1808 m = pvt->mce_outentry;
1809 if (pvt->mce_in + count > MCE_LOG_LEN) {
1810 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1812 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1818 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1820 pvt->mce_in += count;
1823 if (pvt->mce_overrun) {
1824 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1827 pvt->mce_overrun = 0;
1831 * MCE second step: parse errors and display
1833 for (i = 0; i < count; i++)
1834 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1837 * Now, let's increment CE error counts
1840 if (!pvt->is_registered)
1841 i7core_udimm_check_mc_ecc_err(mci);
1843 i7core_rdimm_check_mc_ecc_err(mci);
1847 * i7core_mce_check_error Replicates mcelog routine to get errors
1848 * This routine simply queues mcelog errors, and
1849 * return. The error itself should be handled later
1850 * by i7core_check_error.
1851 * WARNING: As this routine should be called at NMI time, extra care should
1852 * be taken to avoid deadlocks, and to be as fast as possible.
1854 static int i7core_mce_check_error(void *priv, struct mce *mce)
1856 struct mem_ctl_info *mci = priv;
1857 struct i7core_pvt *pvt = mci->pvt_info;
1860 * Just let mcelog handle it if the error is
1861 * outside the memory controller
1863 if (((mce->status & 0xffff) >> 7) != 1)
1866 /* Bank 8 registers are the only ones that we know how to handle */
1871 /* Only handle if it is the right mc controller */
1872 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
1877 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1883 /* Copy memory error at the ringbuffer */
1884 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1886 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1888 /* Handle fatal errors immediately */
1889 if (mce->mcgstatus & 1)
1890 i7core_check_error(mci);
1892 /* Advice mcelog that the error were handled */
1896 static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
1898 pvt->i7core_pci = edac_pci_create_generic_ctl(
1899 &pvt->i7core_dev->pdev[0]->dev,
1901 if (unlikely(!pvt->i7core_pci))
1902 pr_warn("Unable to setup PCI error report via EDAC\n");
1905 static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
1907 if (likely(pvt->i7core_pci))
1908 edac_pci_release_generic_ctl(pvt->i7core_pci);
1910 i7core_printk(KERN_ERR,
1911 "Couldn't find mem_ctl_info for socket %d\n",
1912 pvt->i7core_dev->socket);
1913 pvt->i7core_pci = NULL;
1916 static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
1918 struct mem_ctl_info *mci = i7core_dev->mci;
1919 struct i7core_pvt *pvt;
1921 if (unlikely(!mci || !mci->pvt_info)) {
1922 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
1923 __func__, &i7core_dev->pdev[0]->dev);
1925 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
1929 pvt = mci->pvt_info;
1931 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1932 __func__, mci, &i7core_dev->pdev[0]->dev);
1934 /* Disable MCE NMI handler */
1935 edac_mce_unregister(&pvt->edac_mce);
1937 /* Disable EDAC polling */
1938 i7core_pci_ctl_release(pvt);
1940 /* Remove MC sysfs nodes */
1941 edac_mc_del_mc(mci->dev);
1943 debugf1("%s: free mci struct\n", mci->ctl_name);
1944 kfree(mci->ctl_name);
1946 i7core_dev->mci = NULL;
1949 static int i7core_register_mci(struct i7core_dev *i7core_dev)
1951 struct mem_ctl_info *mci;
1952 struct i7core_pvt *pvt;
1953 int rc, channels, csrows;
1955 /* Check the number of active and not disabled channels */
1956 rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
1957 if (unlikely(rc < 0))
1960 /* allocate a new MC control structure */
1961 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
1965 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1966 __func__, mci, &i7core_dev->pdev[0]->dev);
1968 pvt = mci->pvt_info;
1969 memset(pvt, 0, sizeof(*pvt));
1972 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1973 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1976 mci->mtype_cap = MEM_FLAG_DDR3;
1977 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1978 mci->edac_cap = EDAC_FLAG_NONE;
1979 mci->mod_name = "i7core_edac.c";
1980 mci->mod_ver = I7CORE_REVISION;
1981 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
1982 i7core_dev->socket);
1983 mci->dev_name = pci_name(i7core_dev->pdev[0]);
1984 mci->ctl_page_to_phys = NULL;
1986 /* Store pci devices at mci for faster access */
1987 rc = mci_bind_devs(mci, i7core_dev);
1988 if (unlikely(rc < 0))
1991 if (pvt->is_registered)
1992 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
1994 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
1996 /* Get dimm basic config */
1997 get_dimm_config(mci);
1998 /* record ptr to the generic device */
1999 mci->dev = &i7core_dev->pdev[0]->dev;
2000 /* Set the function pointer to an actual operation function */
2001 mci->edac_check = i7core_check_error;
2003 /* add this new MC control structure to EDAC's list of MCs */
2004 if (unlikely(edac_mc_add_mc(mci))) {
2005 debugf0("MC: " __FILE__
2006 ": %s(): failed edac_mc_add_mc()\n", __func__);
2007 /* FIXME: perhaps some code should go here that disables error
2008 * reporting if we just enabled it
2015 /* Default error mask is any memory */
2016 pvt->inject.channel = 0;
2017 pvt->inject.dimm = -1;
2018 pvt->inject.rank = -1;
2019 pvt->inject.bank = -1;
2020 pvt->inject.page = -1;
2021 pvt->inject.col = -1;
2023 /* allocating generic PCI control info */
2024 i7core_pci_ctl_create(pvt);
2026 /* Registers on edac_mce in order to receive memory errors */
2027 pvt->edac_mce.priv = mci;
2028 pvt->edac_mce.check_error = i7core_mce_check_error;
2029 rc = edac_mce_register(&pvt->edac_mce);
2030 if (unlikely(rc < 0)) {
2031 debugf0("MC: " __FILE__
2032 ": %s(): failed edac_mce_register()\n", __func__);
2036 /* Associates i7core_dev and mci for future usage */
2037 pvt->i7core_dev = i7core_dev;
2038 i7core_dev->mci = mci;
2043 i7core_pci_ctl_release(pvt);
2044 edac_mc_del_mc(mci->dev);
2046 kfree(mci->ctl_name);
2048 i7core_dev->mci = NULL;
2053 * i7core_probe Probe for ONE instance of device to see if it is
2056 * 0 for FOUND a device
2057 * < 0 for error code
2060 static int __devinit i7core_probe(struct pci_dev *pdev,
2061 const struct pci_device_id *id)
2064 struct i7core_dev *i7core_dev;
2066 /* get the pci devices we want to reserve for our use */
2067 mutex_lock(&i7core_edac_lock);
2070 * All memory controllers are allocated at the first pass.
2072 if (unlikely(probed >= 1)) {
2073 mutex_unlock(&i7core_edac_lock);
2078 rc = i7core_get_all_devices();
2079 if (unlikely(rc < 0))
2082 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2083 rc = i7core_register_mci(i7core_dev);
2084 if (unlikely(rc < 0))
2088 i7core_printk(KERN_INFO, "Driver loaded.\n");
2090 mutex_unlock(&i7core_edac_lock);
2094 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2095 if (i7core_dev->mci)
2096 i7core_unregister_mci(i7core_dev);
2098 i7core_put_all_devices();
2100 mutex_unlock(&i7core_edac_lock);
2105 * i7core_remove destructor for one instance of device
2108 static void __devexit i7core_remove(struct pci_dev *pdev)
2110 struct i7core_dev *i7core_dev;
2112 debugf0(__FILE__ ": %s()\n", __func__);
2115 * we have a trouble here: pdev value for removal will be wrong, since
2116 * it will point to the X58 register used to detect that the machine
2117 * is a Nehalem or upper design. However, due to the way several PCI
2118 * devices are grouped together to provide MC functionality, we need
2119 * to use a different method for releasing the devices
2122 mutex_lock(&i7core_edac_lock);
2124 if (unlikely(!probed)) {
2125 mutex_unlock(&i7core_edac_lock);
2129 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2130 if (i7core_dev->mci)
2131 i7core_unregister_mci(i7core_dev);
2134 /* Release PCI resources */
2135 i7core_put_all_devices();
2139 mutex_unlock(&i7core_edac_lock);
2142 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2145 * i7core_driver pci_driver structure for this module
2148 static struct pci_driver i7core_driver = {
2149 .name = "i7core_edac",
2150 .probe = i7core_probe,
2151 .remove = __devexit_p(i7core_remove),
2152 .id_table = i7core_pci_tbl,
2156 * i7core_init Module entry function
2157 * Try to initialize this module for its devices
2159 static int __init i7core_init(void)
2163 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2165 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2169 i7core_xeon_pci_fixup(pci_dev_table);
2171 pci_rc = pci_register_driver(&i7core_driver);
2176 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2183 * i7core_exit() Module exit function
2184 * Unregister the driver
2186 static void __exit i7core_exit(void)
2188 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2189 pci_unregister_driver(&i7core_driver);
2192 module_init(i7core_init);
2193 module_exit(i7core_exit);
2195 MODULE_LICENSE("GPL");
2196 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2197 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2198 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2201 module_param(edac_op_state, int, 0444);
2202 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");