drivers/edac/i3000_edac.c

   1 /*
   2  * Intel 3000/3010 Memory Controller kernel module
   3  * Copyright (C) 2007 Akamai Technologies, Inc.
   4  * Shamelessly copied from:
   5  *      Intel D82875P Memory Controller kernel module
   6  *      (C) 2003 Linux Networx (http://lnxi.com)
   7  *
   8  * This file may be distributed under the terms of the
   9  * GNU General Public License.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/slab.h>
  17 #include "edac_core.h"
  18
  19 #define I3000_REVISION          "1.1"
  20
  21 #define EDAC_MOD_STR            "i3000_edac"
  22
  23 #define I3000_RANKS             8
  24 #define I3000_RANKS_PER_CHANNEL 4
  25 #define I3000_CHANNELS          2
  26
  27 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
  28
  29 #define I3000_MCHBAR            0x44    /* MCH Memory Mapped Register BAR */
  30 #define I3000_MCHBAR_MASK       0xffffc000
  31 #define I3000_MMR_WINDOW_SIZE   16384
  32
  33 #define I3000_EDEAP     0x70    /* Extended DRAM Error Address Pointer (8b)
  34                                  *
  35                                  * 7:1   reserved
  36                                  * 0     bit 32 of address
  37                                  */
  38 #define I3000_DEAP      0x58    /* DRAM Error Address Pointer (32b)
  39                                  *
  40                                  * 31:7  address
  41                                  * 6:1   reserved
  42                                  * 0     Error channel 0/1
  43                                  */
  44 #define I3000_DEAP_GRAIN                (1 << 7)
  45
  46 static inline unsigned long deap_pfn(u8 edeap, u32 deap)
  47 {
  48         deap >>= PAGE_SHIFT;
  49         deap |= (edeap & 1) << (32 - PAGE_SHIFT);
  50         return deap;
  51 }
  52
  53 static inline unsigned long deap_offset(u32 deap)
  54 {
  55         return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
  56 }
  57
  58 static inline int deap_channel(u32 deap)
  59 {
  60         return deap & 1;
  61 }
  62
  63 #define I3000_DERRSYN   0x5c    /* DRAM Error Syndrome (8b)
  64                                  *
  65                                  *  7:0  DRAM ECC Syndrome
  66                                  */
  67
  68 #define I3000_ERRSTS    0xc8    /* Error Status Register (16b)
  69                                  *
  70                                  * 15:12 reserved
  71                                  * 11    MCH Thermal Sensor Event
  72                                  *         for SMI/SCI/SERR
  73                                  * 10    reserved
  74                                  *  9    LOCK to non-DRAM Memory Flag (LCKF)
  75                                  *  8    Received Refresh Timeout Flag (RRTOF)
  76                                  *  7:2  reserved
  77                                  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
  78                                  *  0    Single-bit DRAM ECC Error Flag (DSERR)
  79                                  */
  80 #define I3000_ERRSTS_BITS       0x0b03  /* bits which indicate errors */
  81 #define I3000_ERRSTS_UE         0x0002
  82 #define I3000_ERRSTS_CE         0x0001
  83
  84 #define I3000_ERRCMD    0xca    /* Error Command (16b)
  85                                  *
  86                                  * 15:12 reserved
  87                                  * 11    SERR on MCH Thermal Sensor Event
  88                                  *         (TSESERR)
  89                                  * 10    reserved
  90                                  *  9    SERR on LOCK to non-DRAM Memory
  91                                  *         (LCKERR)
  92                                  *  8    SERR on DRAM Refresh Timeout
  93                                  *         (DRTOERR)
  94                                  *  7:2  reserved
  95                                  *  1    SERR Multi-Bit DRAM ECC Error
  96                                  *         (DMERR)
  97                                  *  0    SERR on Single-Bit ECC Error
  98                                  *         (DSERR)
  99                                  */
 100
 101 /* Intel  MMIO register space - device 0 function 0 - MMR space */
 102
 103 #define I3000_DRB_SHIFT 25      /* 32MiB grain */
 104
 105 #define I3000_C0DRB     0x100   /* Channel 0 DRAM Rank Boundary (8b x 4)
 106                                  *
 107                                  * 7:0   Channel 0 DRAM Rank Boundary Address
 108                                  */
 109 #define I3000_C1DRB     0x180   /* Channel 1 DRAM Rank Boundary (8b x 4)
 110                                  *
 111                                  * 7:0   Channel 1 DRAM Rank Boundary Address
 112                                  */
 113
 114 #define I3000_C0DRA     0x108   /* Channel 0 DRAM Rank Attribute (8b x 2)
 115                                  *
 116                                  * 7     reserved
 117                                  * 6:4   DRAM odd Rank Attribute
 118                                  * 3     reserved
 119                                  * 2:0   DRAM even Rank Attribute
 120                                  *
 121                                  * Each attribute defines the page
 122                                  * size of the corresponding rank:
 123                                  *     000: unpopulated
 124                                  *     001: reserved
 125                                  *     010: 4 KB
 126                                  *     011: 8 KB
 127                                  *     100: 16 KB
 128                                  *     Others: reserved
 129                                  */
 130 #define I3000_C1DRA     0x188   /* Channel 1 DRAM Rank Attribute (8b x 2) */
 131
 132 static inline unsigned char odd_rank_attrib(unsigned char dra)
 133 {
 134         return (dra & 0x70) >> 4;
 135 }
 136
 137 static inline unsigned char even_rank_attrib(unsigned char dra)
 138 {
 139         return dra & 0x07;
 140 }
 141
 142 #define I3000_C0DRC0    0x120   /* DRAM Controller Mode 0 (32b)
 143                                  *
 144                                  * 31:30 reserved
 145                                  * 29    Initialization Complete (IC)
 146                                  * 28:11 reserved
 147                                  * 10:8  Refresh Mode Select (RMS)
 148                                  * 7     reserved
 149                                  * 6:4   Mode Select (SMS)
 150                                  * 3:2   reserved
 151                                  * 1:0   DRAM Type (DT)
 152                                  */
 153
 154 #define I3000_C0DRC1    0x124   /* DRAM Controller Mode 1 (32b)
 155                                  *
 156                                  * 31    Enhanced Addressing Enable (ENHADE)
 157                                  * 30:0  reserved
 158                                  */
 159
 160 enum i3000p_chips {
 161         I3000 = 0,
 162 };
 163
 164 struct i3000_dev_info {
 165         const char *ctl_name;
 166 };
 167
 168 struct i3000_error_info {
 169         u16 errsts;
 170         u8 derrsyn;
 171         u8 edeap;
 172         u32 deap;
 173         u16 errsts2;
 174 };
 175
 176 static const struct i3000_dev_info i3000_devs[] = {
 177         [I3000] = {
 178                 .ctl_name = "i3000"},
 179 };
 180
 181 static struct pci_dev *mci_pdev;
 182 static int i3000_registered = 1;
 183 static struct edac_pci_ctl_info *i3000_pci;
 184
 185 static void i3000_get_error_info(struct mem_ctl_info *mci,
 186                                  struct i3000_error_info *info)
 187 {
 188         struct pci_dev *pdev;
 189
 190         pdev = to_pci_dev(mci->dev);
 191
 192         /*
 193          * This is a mess because there is no atomic way to read all the
 194          * registers at once and the registers can transition from CE being
 195          * overwritten by UE.
 196          */
 197         pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
 198         if (!(info->errsts & I3000_ERRSTS_BITS))
 199                 return;
 200         pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
 201         pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
 202         pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
 203         pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
 204
 205         /*
 206          * If the error is the same for both reads then the first set
 207          * of reads is valid.  If there is a change then there is a CE
 208          * with no info and the second set of reads is valid and
 209          * should be UE info.
 210          */
 211         if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
 212                 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
 213                 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
 214                 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
 215         }
 216
 217         /*
 218          * Clear any error bits.
 219          * (Yes, we really clear bits by writing 1 to them.)
 220          */
 221         pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
 222                          I3000_ERRSTS_BITS);
 223 }
 224
 225 static int i3000_process_error_info(struct mem_ctl_info *mci,
 226                                 struct i3000_error_info *info,
 227                                 int handle_errors)
 228 {
 229         int row, multi_chan, channel;
 230         unsigned long pfn, offset;
 231
 232         multi_chan = mci->csrows[0].nr_channels - 1;
 233
 234         if (!(info->errsts & I3000_ERRSTS_BITS))
 235                 return 0;
 236
 237         if (!handle_errors)
 238                 return 1;
 239
 240         if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
 241                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 242                 info->errsts = info->errsts2;
 243         }
 244
 245         pfn = deap_pfn(info->edeap, info->deap);
 246         offset = deap_offset(info->deap);
 247         channel = deap_channel(info->deap);
 248
 249         row = edac_mc_find_csrow_by_page(mci, pfn);
 250
 251         if (info->errsts & I3000_ERRSTS_UE)
 252                 edac_mc_handle_ue(mci, pfn, offset, row, "i3000 UE");
 253         else
 254                 edac_mc_handle_ce(mci, pfn, offset, info->derrsyn, row,
 255                                 multi_chan ? channel : 0, "i3000 CE");
 256
 257         return 1;
 258 }
 259
 260 static void i3000_check(struct mem_ctl_info *mci)
 261 {
 262         struct i3000_error_info info;
 263
 264         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 265         i3000_get_error_info(mci, &info);
 266         i3000_process_error_info(mci, &info, 1);
 267 }
 268
 269 static int i3000_is_interleaved(const unsigned char *c0dra,
 270                                 const unsigned char *c1dra,
 271                                 const unsigned char *c0drb,
 272                                 const unsigned char *c1drb)
 273 {
 274         int i;
 275
 276         /*
 277          * If the channels aren't populated identically then
 278          * we're not interleaved.
 279          */
 280         for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
 281                 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
 282                         even_rank_attrib(c0dra[i]) !=
 283                                                 even_rank_attrib(c1dra[i]))
 284                         return 0;
 285
 286         /*
 287          * If the rank boundaries for the two channels are different
 288          * then we're not interleaved.
 289          */
 290         for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
 291                 if (c0drb[i] != c1drb[i])
 292                         return 0;
 293
 294         return 1;
 295 }
 296
 297 static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
 298 {
 299         int rc;
 300         int i;
 301         struct mem_ctl_info *mci = NULL;
 302         unsigned long last_cumul_size;
 303         int interleaved, nr_channels;
 304         unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
 305         unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
 306         unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
 307         unsigned long mchbar;
 308         void __iomem *window;
 309
 310         debugf0("MC: %s()\n", __func__);
 311
 312         pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
 313         mchbar &= I3000_MCHBAR_MASK;
 314         window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
 315         if (!window) {
 316                 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
 317                         mchbar);
 318                 return -ENODEV;
 319         }
 320
 321         c0dra[0] = readb(window + I3000_C0DRA + 0);     /* ranks 0,1 */
 322         c0dra[1] = readb(window + I3000_C0DRA + 1);     /* ranks 2,3 */
 323         c1dra[0] = readb(window + I3000_C1DRA + 0);     /* ranks 0,1 */
 324         c1dra[1] = readb(window + I3000_C1DRA + 1);     /* ranks 2,3 */
 325
 326         for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
 327                 c0drb[i] = readb(window + I3000_C0DRB + i);
 328                 c1drb[i] = readb(window + I3000_C1DRB + i);
 329         }
 330
 331         iounmap(window);
 332
 333         /*
 334          * Figure out how many channels we have.
 335          *
 336          * If we have what the datasheet calls "asymmetric channels"
 337          * (essentially the same as what was called "virtual single
 338          * channel mode" in the i82875) then it's a single channel as
 339          * far as EDAC is concerned.
 340          */
 341         interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
 342         nr_channels = interleaved ? 2 : 1;
 343         mci = edac_mc_alloc(0, I3000_RANKS / nr_channels, nr_channels, 0);
 344         if (!mci)
 345                 return -ENOMEM;
 346
 347         debugf3("MC: %s(): init mci\n", __func__);
 348
 349         mci->dev = &pdev->dev;
 350         mci->mtype_cap = MEM_FLAG_DDR2;
 351
 352         mci->edac_ctl_cap = EDAC_FLAG_SECDED;
 353         mci->edac_cap = EDAC_FLAG_SECDED;
 354
 355         mci->mod_name = EDAC_MOD_STR;
 356         mci->mod_ver = I3000_REVISION;
 357         mci->ctl_name = i3000_devs[dev_idx].ctl_name;
 358         mci->dev_name = pci_name(pdev);
 359         mci->edac_check = i3000_check;
 360         mci->ctl_page_to_phys = NULL;
 361
 362         /*
 363          * The dram rank boundary (DRB) reg values are boundary addresses
 364          * for each DRAM rank with a granularity of 32MB.  DRB regs are
 365          * cumulative; the last one will contain the total memory
 366          * contained in all ranks.
 367          *
 368          * If we're in interleaved mode then we're only walking through
 369          * the ranks of controller 0, so we double all the values we see.
 370          */
 371         for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
 372                 u8 value;
 373                 u32 cumul_size;
 374                 struct csrow_info *csrow = &mci->csrows[i];
 375
 376                 value = drb[i];
 377                 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
 378                 if (interleaved)
 379                         cumul_size <<= 1;
 380                 debugf3("MC: %s(): (%d) cumul_size 0x%x\n",
 381                         __func__, i, cumul_size);
 382                 if (cumul_size == last_cumul_size) {
 383                         csrow->mtype = MEM_EMPTY;
 384                         continue;
 385                 }
 386
 387                 csrow->first_page = last_cumul_size;
 388                 csrow->last_page = cumul_size - 1;
 389                 csrow->nr_pages = cumul_size - last_cumul_size;
 390                 last_cumul_size = cumul_size;
 391                 csrow->grain = I3000_DEAP_GRAIN;
 392                 csrow->mtype = MEM_DDR2;
 393                 csrow->dtype = DEV_UNKNOWN;
 394                 csrow->edac_mode = EDAC_UNKNOWN;
 395         }
 396
 397         /*
 398          * Clear any error bits.
 399          * (Yes, we really clear bits by writing 1 to them.)
 400          */
 401         pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
 402                          I3000_ERRSTS_BITS);
 403
 404         rc = -ENODEV;
 405         if (edac_mc_add_mc(mci)) {
 406                 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
 407                 goto fail;
 408         }
 409
 410         /* allocating generic PCI control info */
 411         i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 412         if (!i3000_pci) {
 413                 printk(KERN_WARNING
 414                         "%s(): Unable to create PCI control\n",
 415                         __func__);
 416                 printk(KERN_WARNING
 417                         "%s(): PCI error report via EDAC not setup\n",
 418                         __func__);
 419         }
 420
 421         /* get this far and it's successful */
 422         debugf3("MC: %s(): success\n", __func__);
 423         return 0;
 424
 425 fail:
 426         if (mci)
 427                 edac_mc_free(mci);
 428
 429         return rc;
 430 }
 431
 432 /* returns count (>= 0), or negative on error */
 433 static int __devinit i3000_init_one(struct pci_dev *pdev,
 434                                 const struct pci_device_id *ent)
 435 {
 436         int rc;
 437
 438         debugf0("MC: %s()\n", __func__);
 439
 440         if (pci_enable_device(pdev) < 0)
 441                 return -EIO;
 442
 443         rc = i3000_probe1(pdev, ent->driver_data);
 444         if (!mci_pdev)
 445                 mci_pdev = pci_dev_get(pdev);
 446
 447         return rc;
 448 }
 449
 450 static void __devexit i3000_remove_one(struct pci_dev *pdev)
 451 {
 452         struct mem_ctl_info *mci;
 453
 454         debugf0("%s()\n", __func__);
 455
 456         if (i3000_pci)
 457                 edac_pci_release_generic_ctl(i3000_pci);
 458
 459         mci = edac_mc_del_mc(&pdev->dev);
 460         if (!mci)
 461                 return;
 462
 463         edac_mc_free(mci);
 464 }
 465
 466 static const struct pci_device_id i3000_pci_tbl[] __devinitdata = {
 467         {
 468          PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 469          I3000},
 470         {
 471          0,
 472          }                      /* 0 terminated list. */
 473 };
 474
 475 MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
 476
 477 static struct pci_driver i3000_driver = {
 478         .name = EDAC_MOD_STR,
 479         .probe = i3000_init_one,
 480         .remove = __devexit_p(i3000_remove_one),
 481         .id_table = i3000_pci_tbl,
 482 };
 483
 484 static int __init i3000_init(void)
 485 {
 486         int pci_rc;
 487
 488         debugf3("MC: %s()\n", __func__);
 489         pci_rc = pci_register_driver(&i3000_driver);
 490         if (pci_rc < 0)
 491                 goto fail0;
 492
 493         if (!mci_pdev) {
 494                 i3000_registered = 0;
 495                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 496                                         PCI_DEVICE_ID_INTEL_3000_HB, NULL);
 497                 if (!mci_pdev) {
 498                         debugf0("i3000 pci_get_device fail\n");
 499                         pci_rc = -ENODEV;
 500                         goto fail1;
 501                 }
 502
 503                 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
 504                 if (pci_rc < 0) {
 505                         debugf0("i3000 init fail\n");
 506                         pci_rc = -ENODEV;
 507                         goto fail1;
 508                 }
 509         }
 510
 511         return 0;
 512
 513 fail1:
 514         pci_unregister_driver(&i3000_driver);
 515
 516 fail0:
 517         if (mci_pdev)
 518                 pci_dev_put(mci_pdev);
 519
 520         return pci_rc;
 521 }
 522
 523 static void __exit i3000_exit(void)
 524 {
 525         debugf3("MC: %s()\n", __func__);
 526
 527         pci_unregister_driver(&i3000_driver);
 528         if (!i3000_registered) {
 529                 i3000_remove_one(mci_pdev);
 530                 pci_dev_put(mci_pdev);
 531         }
 532 }
 533
 534 module_init(i3000_init);
 535 module_exit(i3000_exit);
 536
 537 MODULE_LICENSE("GPL");
 538 MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
 539 MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");