drivers/edac/e7xxx_edac.c

   1 /*
   2  * Intel e7xxx Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e7xxx_chips" below for supported chipsets
   8  *
   9  * Written by Thayne Harbaugh
  10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  11  *      http://www.anime.net/~goemon/linux-ecc/
  12  *
  13  * Contributors:
  14  *      Eric Biederman (Linux Networx)
  15  *      Tom Zimmerman (Linux Networx)
  16  *      Jim Garlick (Lawrence Livermore National Labs)
  17  *      Dave Peterson (Lawrence Livermore National Labs)
  18  *      That One Guy (Some other place)
  19  *      Wang Zhenyu (intel.com)
  20  *
  21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
  22  *
  23  */
  24
  25
  26 #include <linux/config.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/pci_ids.h>
  31 #include <linux/slab.h>
  32 #include "edac_mc.h"
  33
  34
  35 #define e7xxx_printk(level, fmt, arg...) \
  36     edac_printk(level, "e7xxx", fmt, ##arg)
  37
  38
  39 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
  40     edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
  41
  42
  43 #ifndef PCI_DEVICE_ID_INTEL_7205_0
  44 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
  45 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
  46
  47 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
  48 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
  49 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
  50
  51 #ifndef PCI_DEVICE_ID_INTEL_7500_0
  52 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
  53 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
  54
  55 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
  56 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
  57 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
  58
  59 #ifndef PCI_DEVICE_ID_INTEL_7501_0
  60 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
  61 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
  62
  63 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
  64 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
  65 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
  66
  67 #ifndef PCI_DEVICE_ID_INTEL_7505_0
  68 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
  69 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
  70
  71 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
  72 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
  73 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
  74
  75
  76 #define E7XXX_NR_CSROWS         8       /* number of csrows */
  77 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
  78
  79
  80 /* E7XXX register addresses - device 0 function 0 */
  81 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
  82 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
  83                                         /*
  84                                          * 31   Device width row 7 0=x8 1=x4
  85                                          * 27   Device width row 6
  86                                          * 23   Device width row 5
  87                                          * 19   Device width row 4
  88                                          * 15   Device width row 3
  89                                          * 11   Device width row 2
  90                                          *  7   Device width row 1
  91                                          *  3   Device width row 0
  92                                          */
  93 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
  94                                         /*
  95                                          * 22    Number channels 0=1,1=2
  96                                          * 19:18 DRB Granularity 32/64MB
  97                                          */
  98 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  99 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
 100 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
 101
 102 /* E7XXX register addresses - device 0 function 1 */
 103 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
 104 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
 105 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
 106                                         /*     error address register (32b) */
 107                                         /*
 108                                          * 31:28 Reserved
 109                                          * 27:6  CE address (4k block 33:12)
 110                                          *  5:0  Reserved
 111                                          */
 112 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
 113                                         /*     error address register (32b) */
 114                                         /*
 115                                          * 31:28 Reserved
 116                                          * 27:6  CE address (4k block 33:12)
 117                                          *  5:0  Reserved
 118                                          */
 119 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
 120                                         /*     error syndrome register (16b) */
 121
 122 enum e7xxx_chips {
 123         E7500 = 0,
 124         E7501,
 125         E7505,
 126         E7205,
 127 };
 128
 129
 130 struct e7xxx_pvt {
 131         struct pci_dev *bridge_ck;
 132         u32 tolm;
 133         u32 remapbase;
 134         u32 remaplimit;
 135         const struct e7xxx_dev_info *dev_info;
 136 };
 137
 138
 139 struct e7xxx_dev_info {
 140         u16 err_dev;
 141         const char *ctl_name;
 142 };
 143
 144
 145 struct e7xxx_error_info {
 146         u8 dram_ferr;
 147         u8 dram_nerr;
 148         u32 dram_celog_add;
 149         u16 dram_celog_syndrome;
 150         u32 dram_uelog_add;
 151 };
 152
 153 static const struct e7xxx_dev_info e7xxx_devs[] = {
 154         [E7500] = {
 155                    .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
 156                    .ctl_name = "E7500"},
 157         [E7501] = {
 158                    .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
 159                    .ctl_name = "E7501"},
 160         [E7505] = {
 161                    .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
 162                    .ctl_name = "E7505"},
 163         [E7205] = {
 164                    .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
 165                    .ctl_name = "E7205"},
 166 };
 167
 168
 169 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
 170 static inline int e7xxx_find_channel(u16 syndrome)
 171 {
 172         debugf3("%s()\n", __func__);
 173
 174         if ((syndrome & 0xff00) == 0)
 175                 return 0;
 176         if ((syndrome & 0x00ff) == 0)
 177                 return 1;
 178         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
 179                 return 0;
 180         return 1;
 181 }
 182
 183
 184 static unsigned long
 185 ctl_page_to_phys(struct mem_ctl_info *mci, unsigned long page)
 186 {
 187         u32 remap;
 188         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
 189
 190         debugf3("%s()\n", __func__);
 191
 192         if ((page < pvt->tolm) ||
 193             ((page >= 0x100000) && (page < pvt->remapbase)))
 194                 return page;
 195         remap = (page - pvt->tolm) + pvt->remapbase;
 196         if (remap < pvt->remaplimit)
 197                 return remap;
 198         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 199         return pvt->tolm - 1;
 200 }
 201
 202
 203 static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
 204 {
 205         u32 error_1b, page;
 206         u16 syndrome;
 207         int row;
 208         int channel;
 209
 210         debugf3("%s()\n", __func__);
 211
 212         /* read the error address */
 213         error_1b = info->dram_celog_add;
 214         /* FIXME - should use PAGE_SHIFT */
 215         page = error_1b >> 6;   /* convert the address to 4k page */
 216         /* read the syndrome */
 217         syndrome = info->dram_celog_syndrome;
 218         /* FIXME - check for -1 */
 219         row = edac_mc_find_csrow_by_page(mci, page);
 220         /* convert syndrome to channel */
 221         channel = e7xxx_find_channel(syndrome);
 222         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel,
 223                                "e7xxx CE");
 224 }
 225
 226
 227 static void process_ce_no_info(struct mem_ctl_info *mci)
 228 {
 229         debugf3("%s()\n", __func__);
 230         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
 231 }
 232
 233
 234 static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
 235 {
 236         u32 error_2b, block_page;
 237         int row;
 238
 239         debugf3("%s()\n", __func__);
 240
 241         /* read the error address */
 242         error_2b = info->dram_uelog_add;
 243         /* FIXME - should use PAGE_SHIFT */
 244         block_page = error_2b >> 6;     /* convert to 4k address */
 245         row = edac_mc_find_csrow_by_page(mci, block_page);
 246         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
 247 }
 248
 249
 250 static void process_ue_no_info(struct mem_ctl_info *mci)
 251 {
 252         debugf3("%s()\n", __func__);
 253         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
 254 }
 255
 256
 257 static void e7xxx_get_error_info (struct mem_ctl_info *mci,
 258                 struct e7xxx_error_info *info)
 259 {
 260         struct e7xxx_pvt *pvt;
 261
 262         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 263         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
 264             &info->dram_ferr);
 265         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
 266             &info->dram_nerr);
 267
 268         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
 269                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
 270                     &info->dram_celog_add);
 271                 pci_read_config_word(pvt->bridge_ck,
 272                     E7XXX_DRAM_CELOG_SYNDROME, &info->dram_celog_syndrome);
 273         }
 274
 275         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
 276                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
 277                     &info->dram_uelog_add);
 278
 279         if (info->dram_ferr & 3)
 280                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03,
 281                     0x03);
 282
 283         if (info->dram_nerr & 3)
 284                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03,
 285                     0x03);
 286 }
 287
 288
 289 static int e7xxx_process_error_info (struct mem_ctl_info *mci,
 290                 struct e7xxx_error_info *info, int handle_errors)
 291 {
 292         int error_found;
 293
 294         error_found = 0;
 295
 296         /* decode and report errors */
 297         if (info->dram_ferr & 1) {      /* check first error correctable */
 298                 error_found = 1;
 299
 300                 if (handle_errors)
 301                         process_ce(mci, info);
 302         }
 303
 304         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
 305                 error_found = 1;
 306
 307                 if (handle_errors)
 308                         process_ue(mci, info);
 309         }
 310
 311         if (info->dram_nerr & 1) {      /* check next error correctable */
 312                 error_found = 1;
 313
 314                 if (handle_errors) {
 315                         if (info->dram_ferr & 1)
 316                                 process_ce_no_info(mci);
 317                         else
 318                                 process_ce(mci, info);
 319                 }
 320         }
 321
 322         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
 323                 error_found = 1;
 324
 325                 if (handle_errors) {
 326                         if (info->dram_ferr & 2)
 327                                 process_ue_no_info(mci);
 328                         else
 329                                 process_ue(mci, info);
 330                 }
 331         }
 332
 333         return error_found;
 334 }
 335
 336
 337 static void e7xxx_check(struct mem_ctl_info *mci)
 338 {
 339         struct e7xxx_error_info info;
 340
 341         debugf3("%s()\n", __func__);
 342         e7xxx_get_error_info(mci, &info);
 343         e7xxx_process_error_info(mci, &info, 1);
 344 }
 345
 346
 347 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
 348 {
 349         int rc = -ENODEV;
 350         int index;
 351         u16 pci_data;
 352         struct mem_ctl_info *mci = NULL;
 353         struct e7xxx_pvt *pvt = NULL;
 354         u32 drc;
 355         int drc_chan = 1;       /* Number of channels 0=1chan,1=2chan */
 356         int drc_drbg = 1;       /* DRB granularity 0=32mb,1=64mb */
 357         int drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
 358         u32 dra;
 359         unsigned long last_cumul_size;
 360
 361
 362         debugf0("%s(): mci\n", __func__);
 363
 364         /* need to find out the number of channels */
 365         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
 366         /* only e7501 can be single channel */
 367         if (dev_idx == E7501) {
 368                 drc_chan = ((drc >> 22) & 0x1);
 369                 drc_drbg = (drc >> 18) & 0x3;
 370         }
 371         drc_ddim = (drc >> 20) & 0x3;
 372
 373         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
 374
 375         if (mci == NULL) {
 376                 rc = -ENOMEM;
 377                 goto fail;
 378         }
 379
 380         debugf3("%s(): init mci\n", __func__);
 381
 382         mci->mtype_cap = MEM_FLAG_RDDR;
 383         mci->edac_ctl_cap =
 384             EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED;
 385         /* FIXME - what if different memory types are in different csrows? */
 386         mci->mod_name = BS_MOD_STR;
 387         mci->mod_ver = "$Revision: 1.5.2.9 $";
 388         mci->pdev = pdev;
 389
 390         debugf3("%s(): init pvt\n", __func__);
 391         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 392         pvt->dev_info = &e7xxx_devs[dev_idx];
 393         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 394                                          pvt->dev_info->err_dev,
 395                                          pvt->bridge_ck);
 396         if (!pvt->bridge_ck) {
 397                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
 398                              "vendor %x device 0x%x (broken BIOS?)\n",
 399                              PCI_VENDOR_ID_INTEL,
 400                              e7xxx_devs[dev_idx].err_dev);
 401                 goto fail;
 402         }
 403
 404         debugf3("%s(): more mci init\n", __func__);
 405         mci->ctl_name = pvt->dev_info->ctl_name;
 406
 407         mci->edac_check = e7xxx_check;
 408         mci->ctl_page_to_phys = ctl_page_to_phys;
 409
 410         /* find out the device types */
 411         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
 412
 413         /*
 414          * The dram row boundary (DRB) reg values are boundary address
 415          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 416          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 417          * contain the total memory contained in all eight rows.
 418          */
 419         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
 420                 u8 value;
 421                 u32 cumul_size;
 422                 /* mem_dev 0=x8, 1=x4 */
 423                 int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
 424                 struct csrow_info *csrow = &mci->csrows[index];
 425
 426                 pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value);
 427                 /* convert a 64 or 32 MiB DRB to a page size. */
 428                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 429                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 430                         cumul_size);
 431                 if (cumul_size == last_cumul_size)
 432                         continue;       /* not populated */
 433
 434                 csrow->first_page = last_cumul_size;
 435                 csrow->last_page = cumul_size - 1;
 436                 csrow->nr_pages = cumul_size - last_cumul_size;
 437                 last_cumul_size = cumul_size;
 438                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 439                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 440                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 441
 442                 /*
 443                  * if single channel or x8 devices then SECDED
 444                  * if dual channel and x4 then S4ECD4ED
 445                  */
 446                 if (drc_ddim) {
 447                         if (drc_chan && mem_dev) {
 448                                 csrow->edac_mode = EDAC_S4ECD4ED;
 449                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 450                         } else {
 451                                 csrow->edac_mode = EDAC_SECDED;
 452                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 453                         }
 454                 } else
 455                         csrow->edac_mode = EDAC_NONE;
 456         }
 457
 458         mci->edac_cap |= EDAC_FLAG_NONE;
 459
 460         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
 461         /* load the top of low memory, remap base, and remap limit vars */
 462         pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data);
 463         pvt->tolm = ((u32) pci_data) << 4;
 464         pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data);
 465         pvt->remapbase = ((u32) pci_data) << 14;
 466         pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data);
 467         pvt->remaplimit = ((u32) pci_data) << 14;
 468         e7xxx_printk(KERN_INFO,
 469                      "tolm = %x, remapbase = %x, remaplimit = %x\n",
 470                      pvt->tolm, pvt->remapbase, pvt->remaplimit);
 471
 472         /* clear any pending errors, or initial state bits */
 473         pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
 474         pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
 475
 476         if (edac_mc_add_mc(mci) != 0) {
 477                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 478                 goto fail;
 479         }
 480
 481         /* get this far and it's successful */
 482         debugf3("%s(): success\n", __func__);
 483         return 0;
 484
 485 fail:
 486         if (mci != NULL) {
 487                 if(pvt != NULL && pvt->bridge_ck)
 488                         pci_dev_put(pvt->bridge_ck);
 489                 edac_mc_free(mci);
 490         }
 491
 492         return rc;
 493 }
 494
 495 /* returns count (>= 0), or negative on error */
 496 static int __devinit
 497 e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 498 {
 499         debugf0("%s()\n", __func__);
 500
 501         /* wake up and enable device */
 502         return pci_enable_device(pdev) ?
 503             -EIO : e7xxx_probe1(pdev, ent->driver_data);
 504 }
 505
 506
 507 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
 508 {
 509         struct mem_ctl_info *mci;
 510         struct e7xxx_pvt *pvt;
 511
 512         debugf0("%s()\n", __func__);
 513
 514         if (((mci = edac_mc_find_mci_by_pdev(pdev)) != 0) &&
 515             edac_mc_del_mc(mci)) {
 516                 pvt = (struct e7xxx_pvt *) mci->pvt_info;
 517                 pci_dev_put(pvt->bridge_ck);
 518                 edac_mc_free(mci);
 519         }
 520 }
 521
 522
 523 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
 524         {PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 525          E7205},
 526         {PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 527          E7500},
 528         {PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 529          E7501},
 530         {PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 531          E7505},
 532         {0,}                    /* 0 terminated list. */
 533 };
 534
 535 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
 536
 537
 538 static struct pci_driver e7xxx_driver = {
 539         .name = BS_MOD_STR,
 540         .probe = e7xxx_init_one,
 541         .remove = __devexit_p(e7xxx_remove_one),
 542         .id_table = e7xxx_pci_tbl,
 543 };
 544
 545
 546 static int __init e7xxx_init(void)
 547 {
 548         return pci_register_driver(&e7xxx_driver);
 549 }
 550
 551
 552 static void __exit e7xxx_exit(void)
 553 {
 554         pci_unregister_driver(&e7xxx_driver);
 555 }
 556
 557 module_init(e7xxx_init);
 558 module_exit(e7xxx_exit);
 559
 560
 561 MODULE_LICENSE("GPL");
 562 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
 563               "Based on.work by Dan Hollis et al");
 564 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");