drivers/edac/e7xxx_edac.c

   1 /*
   2  * Intel e7xxx Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e7xxx_chips" below for supported chipsets
   8  *
   9  * Written by Thayne Harbaugh
  10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  11  *      http://www.anime.net/~goemon/linux-ecc/
  12  *
  13  * Contributors:
  14  *      Eric Biederman (Linux Networx)
  15  *      Tom Zimmerman (Linux Networx)
  16  *      Jim Garlick (Lawrence Livermore National Labs)
  17  *      Dave Peterson (Lawrence Livermore National Labs)
  18  *      That One Guy (Some other place)
  19  *      Wang Zhenyu (intel.com)
  20  *
  21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/pci_ids.h>
  29 #include <linux/slab.h>
  30 #include "edac_mc.h"
  31
  32 #define E7XXX_REVISION " Ver: 2.0.1 " __DATE__
  33 #define EDAC_MOD_STR    "e7xxx_edac"
  34
  35 #define e7xxx_printk(level, fmt, arg...) \
  36         edac_printk(level, "e7xxx", fmt, ##arg)
  37
  38 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
  39         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
  40
  41 #ifndef PCI_DEVICE_ID_INTEL_7205_0
  42 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
  43 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
  44
  45 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
  46 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
  47 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
  48
  49 #ifndef PCI_DEVICE_ID_INTEL_7500_0
  50 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
  51 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
  52
  53 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
  54 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
  55 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
  56
  57 #ifndef PCI_DEVICE_ID_INTEL_7501_0
  58 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
  59 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
  60
  61 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
  62 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
  63 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
  64
  65 #ifndef PCI_DEVICE_ID_INTEL_7505_0
  66 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
  67 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
  68
  69 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
  70 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
  71 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
  72
  73 #define E7XXX_NR_CSROWS         8       /* number of csrows */
  74 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
  75
  76 /* E7XXX register addresses - device 0 function 0 */
  77 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
  78 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
  79                                         /*
  80                                          * 31   Device width row 7 0=x8 1=x4
  81                                          * 27   Device width row 6
  82                                          * 23   Device width row 5
  83                                          * 19   Device width row 4
  84                                          * 15   Device width row 3
  85                                          * 11   Device width row 2
  86                                          *  7   Device width row 1
  87                                          *  3   Device width row 0
  88                                          */
  89 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
  90                                         /*
  91                                          * 22    Number channels 0=1,1=2
  92                                          * 19:18 DRB Granularity 32/64MB
  93                                          */
  94 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  95 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  96 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  97
  98 /* E7XXX register addresses - device 0 function 1 */
  99 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
 100 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
 101 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
 102                                         /*     error address register (32b) */
 103                                         /*
 104                                          * 31:28 Reserved
 105                                          * 27:6  CE address (4k block 33:12)
 106                                          *  5:0  Reserved
 107                                          */
 108 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
 109                                         /*     error address register (32b) */
 110                                         /*
 111                                          * 31:28 Reserved
 112                                          * 27:6  CE address (4k block 33:12)
 113                                          *  5:0  Reserved
 114                                          */
 115 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
 116                                         /*     error syndrome register (16b) */
 117
 118 enum e7xxx_chips {
 119         E7500 = 0,
 120         E7501,
 121         E7505,
 122         E7205,
 123 };
 124
 125 struct e7xxx_pvt {
 126         struct pci_dev *bridge_ck;
 127         u32 tolm;
 128         u32 remapbase;
 129         u32 remaplimit;
 130         const struct e7xxx_dev_info *dev_info;
 131 };
 132
 133 struct e7xxx_dev_info {
 134         u16 err_dev;
 135         const char *ctl_name;
 136 };
 137
 138 struct e7xxx_error_info {
 139         u8 dram_ferr;
 140         u8 dram_nerr;
 141         u32 dram_celog_add;
 142         u16 dram_celog_syndrome;
 143         u32 dram_uelog_add;
 144 };
 145
 146 static const struct e7xxx_dev_info e7xxx_devs[] = {
 147         [E7500] = {
 148                 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
 149                 .ctl_name = "E7500"
 150         },
 151         [E7501] = {
 152                 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
 153                 .ctl_name = "E7501"
 154         },
 155         [E7505] = {
 156                 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
 157                 .ctl_name = "E7505"
 158         },
 159         [E7205] = {
 160                 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
 161                 .ctl_name = "E7205"
 162         },
 163 };
 164
 165 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
 166 static inline int e7xxx_find_channel(u16 syndrome)
 167 {
 168         debugf3("%s()\n", __func__);
 169
 170         if ((syndrome & 0xff00) == 0)
 171                 return 0;
 172
 173         if ((syndrome & 0x00ff) == 0)
 174                 return 1;
 175
 176         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
 177                 return 0;
 178
 179         return 1;
 180 }
 181
 182 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 183                 unsigned long page)
 184 {
 185         u32 remap;
 186         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
 187
 188         debugf3("%s()\n", __func__);
 189
 190         if ((page < pvt->tolm) ||
 191                         ((page >= 0x100000) && (page < pvt->remapbase)))
 192                 return page;
 193
 194         remap = (page - pvt->tolm) + pvt->remapbase;
 195
 196         if (remap < pvt->remaplimit)
 197                 return remap;
 198
 199         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 200         return pvt->tolm - 1;
 201 }
 202
 203 static void process_ce(struct mem_ctl_info *mci,
 204                 struct e7xxx_error_info *info)
 205 {
 206         u32 error_1b, page;
 207         u16 syndrome;
 208         int row;
 209         int channel;
 210
 211         debugf3("%s()\n", __func__);
 212         /* read the error address */
 213         error_1b = info->dram_celog_add;
 214         /* FIXME - should use PAGE_SHIFT */
 215         page = error_1b >> 6;  /* convert the address to 4k page */
 216         /* read the syndrome */
 217         syndrome = info->dram_celog_syndrome;
 218         /* FIXME - check for -1 */
 219         row = edac_mc_find_csrow_by_page(mci, page);
 220         /* convert syndrome to channel */
 221         channel = e7xxx_find_channel(syndrome);
 222         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
 223 }
 224
 225 static void process_ce_no_info(struct mem_ctl_info *mci)
 226 {
 227         debugf3("%s()\n", __func__);
 228         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
 229 }
 230
 231 static void process_ue(struct mem_ctl_info *mci,
 232                 struct e7xxx_error_info *info)
 233 {
 234         u32 error_2b, block_page;
 235         int row;
 236
 237         debugf3("%s()\n", __func__);
 238         /* read the error address */
 239         error_2b = info->dram_uelog_add;
 240         /* FIXME - should use PAGE_SHIFT */
 241         block_page = error_2b >> 6;  /* convert to 4k address */
 242         row = edac_mc_find_csrow_by_page(mci, block_page);
 243         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
 244 }
 245
 246 static void process_ue_no_info(struct mem_ctl_info *mci)
 247 {
 248         debugf3("%s()\n", __func__);
 249         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
 250 }
 251
 252 static void e7xxx_get_error_info (struct mem_ctl_info *mci,
 253                 struct e7xxx_error_info *info)
 254 {
 255         struct e7xxx_pvt *pvt;
 256
 257         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 258         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
 259                         &info->dram_ferr);
 260         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
 261                         &info->dram_nerr);
 262
 263         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
 264                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
 265                                 &info->dram_celog_add);
 266                 pci_read_config_word(pvt->bridge_ck,
 267                                 E7XXX_DRAM_CELOG_SYNDROME,
 268                                 &info->dram_celog_syndrome);
 269         }
 270
 271         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
 272                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
 273                                 &info->dram_uelog_add);
 274
 275         if (info->dram_ferr & 3)
 276                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
 277
 278         if (info->dram_nerr & 3)
 279                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
 280 }
 281
 282 static int e7xxx_process_error_info (struct mem_ctl_info *mci,
 283                 struct e7xxx_error_info *info, int handle_errors)
 284 {
 285         int error_found;
 286
 287         error_found = 0;
 288
 289         /* decode and report errors */
 290         if (info->dram_ferr & 1) {      /* check first error correctable */
 291                 error_found = 1;
 292
 293                 if (handle_errors)
 294                         process_ce(mci, info);
 295         }
 296
 297         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
 298                 error_found = 1;
 299
 300                 if (handle_errors)
 301                         process_ue(mci, info);
 302         }
 303
 304         if (info->dram_nerr & 1) {      /* check next error correctable */
 305                 error_found = 1;
 306
 307                 if (handle_errors) {
 308                         if (info->dram_ferr & 1)
 309                                 process_ce_no_info(mci);
 310                         else
 311                                 process_ce(mci, info);
 312                 }
 313         }
 314
 315         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
 316                 error_found = 1;
 317
 318                 if (handle_errors) {
 319                         if (info->dram_ferr & 2)
 320                                 process_ue_no_info(mci);
 321                         else
 322                                 process_ue(mci, info);
 323                 }
 324         }
 325
 326         return error_found;
 327 }
 328
 329 static void e7xxx_check(struct mem_ctl_info *mci)
 330 {
 331         struct e7xxx_error_info info;
 332
 333         debugf3("%s()\n", __func__);
 334         e7xxx_get_error_info(mci, &info);
 335         e7xxx_process_error_info(mci, &info, 1);
 336 }
 337
 338 /* Return 1 if dual channel mode is active.  Else return 0. */
 339 static inline int dual_channel_active(u32 drc, int dev_idx)
 340 {
 341         return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
 342 }
 343
 344
 345 /* Return DRB granularity (0=32mb, 1=64mb). */
 346 static inline int drb_granularity(u32 drc, int dev_idx)
 347 {
 348         /* only e7501 can be single channel */
 349         return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
 350 }
 351
 352
 353 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 354                 int dev_idx, u32 drc)
 355 {
 356         unsigned long last_cumul_size;
 357         int index;
 358         u8 value;
 359         u32 dra, cumul_size;
 360         int drc_chan, drc_drbg, drc_ddim, mem_dev;
 361         struct csrow_info *csrow;
 362
 363         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
 364         drc_chan = dual_channel_active(drc, dev_idx);
 365         drc_drbg = drb_granularity(drc, dev_idx);
 366         drc_ddim = (drc >> 20) & 0x3;
 367         last_cumul_size = 0;
 368
 369         /* The dram row boundary (DRB) reg values are boundary address
 370          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 371          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 372          * contain the total memory contained in all eight rows.
 373          */
 374         for (index = 0; index < mci->nr_csrows; index++) {
 375                 /* mem_dev 0=x8, 1=x4 */
 376                 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
 377                 csrow = &mci->csrows[index];
 378
 379                 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
 380                 /* convert a 64 or 32 MiB DRB to a page size. */
 381                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 382                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 383                         cumul_size);
 384                 if (cumul_size == last_cumul_size)
 385                         continue;       /* not populated */
 386
 387                 csrow->first_page = last_cumul_size;
 388                 csrow->last_page = cumul_size - 1;
 389                 csrow->nr_pages = cumul_size - last_cumul_size;
 390                 last_cumul_size = cumul_size;
 391                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 392                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 393                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 394
 395                 /*
 396                  * if single channel or x8 devices then SECDED
 397                  * if dual channel and x4 then S4ECD4ED
 398                  */
 399                 if (drc_ddim) {
 400                         if (drc_chan && mem_dev) {
 401                                 csrow->edac_mode = EDAC_S4ECD4ED;
 402                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 403                         } else {
 404                                 csrow->edac_mode = EDAC_SECDED;
 405                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 406                         }
 407                 } else
 408                         csrow->edac_mode = EDAC_NONE;
 409         }
 410 }
 411
 412 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
 413 {
 414         u16 pci_data;
 415         struct mem_ctl_info *mci = NULL;
 416         struct e7xxx_pvt *pvt = NULL;
 417         u32 drc;
 418         int drc_chan;
 419         struct e7xxx_error_info discard;
 420
 421         debugf0("%s(): mci\n", __func__);
 422         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
 423
 424         drc_chan = dual_channel_active(drc, dev_idx);
 425         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
 426
 427         if (mci == NULL)
 428                 return -ENOMEM;
 429
 430         debugf3("%s(): init mci\n", __func__);
 431         mci->mtype_cap = MEM_FLAG_RDDR;
 432         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 433                         EDAC_FLAG_S4ECD4ED;
 434         /* FIXME - what if different memory types are in different csrows? */
 435         mci->mod_name = EDAC_MOD_STR;
 436         mci->mod_ver = E7XXX_REVISION;
 437         mci->dev = &pdev->dev;
 438         debugf3("%s(): init pvt\n", __func__);
 439         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 440         pvt->dev_info = &e7xxx_devs[dev_idx];
 441         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 442                                         pvt->dev_info->err_dev,
 443                                         pvt->bridge_ck);
 444
 445         if (!pvt->bridge_ck) {
 446                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
 447                         "vendor %x device 0x%x (broken BIOS?)\n",
 448                         PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
 449                 goto fail0;
 450         }
 451
 452         debugf3("%s(): more mci init\n", __func__);
 453         mci->ctl_name = pvt->dev_info->ctl_name;
 454         mci->edac_check = e7xxx_check;
 455         mci->ctl_page_to_phys = ctl_page_to_phys;
 456         e7xxx_init_csrows(mci, pdev, dev_idx, drc);
 457         mci->edac_cap |= EDAC_FLAG_NONE;
 458         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
 459         /* load the top of low memory, remap base, and remap limit vars */
 460         pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
 461         pvt->tolm = ((u32) pci_data) << 4;
 462         pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
 463         pvt->remapbase = ((u32) pci_data) << 14;
 464         pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
 465         pvt->remaplimit = ((u32) pci_data) << 14;
 466         e7xxx_printk(KERN_INFO,
 467                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
 468                 pvt->remapbase, pvt->remaplimit);
 469
 470         /* clear any pending errors, or initial state bits */
 471         e7xxx_get_error_info(mci, &discard);
 472
 473         /* Here we assume that we will never see multiple instances of this
 474          * type of memory controller.  The ID is therefore hardcoded to 0.
 475          */
 476         if (edac_mc_add_mc(mci,0)) {
 477                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 478                 goto fail1;
 479         }
 480
 481         /* get this far and it's successful */
 482         debugf3("%s(): success\n", __func__);
 483         return 0;
 484
 485 fail1:
 486         pci_dev_put(pvt->bridge_ck);
 487
 488 fail0:
 489         edac_mc_free(mci);
 490
 491         return -ENODEV;
 492 }
 493
 494 /* returns count (>= 0), or negative on error */
 495 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
 496                 const struct pci_device_id *ent)
 497 {
 498         debugf0("%s()\n", __func__);
 499
 500         /* wake up and enable device */
 501         return pci_enable_device(pdev) ?
 502                 -EIO : e7xxx_probe1(pdev, ent->driver_data);
 503 }
 504
 505 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
 506 {
 507         struct mem_ctl_info *mci;
 508         struct e7xxx_pvt *pvt;
 509
 510         debugf0("%s()\n", __func__);
 511
 512         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 513                 return;
 514
 515         pvt = (struct e7xxx_pvt *) mci->pvt_info;
 516         pci_dev_put(pvt->bridge_ck);
 517         edac_mc_free(mci);
 518 }
 519
 520 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
 521         {
 522                 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 523                 E7205
 524         },
 525         {
 526                 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 527                 E7500
 528         },
 529         {
 530                 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 531                 E7501
 532         },
 533         {
 534                 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 535                 E7505
 536         },
 537         {
 538                 0,
 539         }       /* 0 terminated list. */
 540 };
 541
 542 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
 543
 544 static struct pci_driver e7xxx_driver = {
 545         .name = EDAC_MOD_STR,
 546         .probe = e7xxx_init_one,
 547         .remove = __devexit_p(e7xxx_remove_one),
 548         .id_table = e7xxx_pci_tbl,
 549 };
 550
 551 static int __init e7xxx_init(void)
 552 {
 553         return pci_register_driver(&e7xxx_driver);
 554 }
 555
 556 static void __exit e7xxx_exit(void)
 557 {
 558         pci_unregister_driver(&e7xxx_driver);
 559 }
 560
 561 module_init(e7xxx_init);
 562 module_exit(e7xxx_exit);
 563
 564 MODULE_LICENSE("GPL");
 565 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
 566         "Based on.work by Dan Hollis et al");
 567 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");