drivers/dma/ste_dma40.c

   1 /*
   2  * driver/dma/ste_dma40.c
   3  *
   4  * Copyright (C) ST-Ericsson 2007-2010
   5  * License terms: GNU General Public License (GPL) version 2
   6  * Author: Per Friden <per.friden@stericsson.com>
   7  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   8  *
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17
  18 #include <plat/ste_dma40.h>
  19
  20 #include "ste_dma40_ll.h"
  21
  22 #define D40_NAME "dma40"
  23
  24 #define D40_PHY_CHAN -1
  25
  26 /* For masking out/in 2 bit channel positions */
  27 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
  28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  29
  30 /* Maximum iterations taken before giving up suspending a channel */
  31 #define D40_SUSPEND_MAX_IT 500
  32
  33 /* Hardware requirement on LCLA alignment */
  34 #define LCLA_ALIGNMENT 0x40000
  35 /* Attempts before giving up to trying to get pages that are aligned */
  36 #define MAX_LCLA_ALLOC_ATTEMPTS 256
  37
  38 /* Bit markings for allocation map */
  39 #define D40_ALLOC_FREE          (1 << 31)
  40 #define D40_ALLOC_PHY           (1 << 30)
  41 #define D40_ALLOC_LOG_FREE      0
  42
  43 /* Hardware designer of the block */
  44 #define D40_HW_DESIGNER 0x8
  45
  46 /**
  47  * enum 40_command - The different commands and/or statuses.
  48  *
  49  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
  50  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
  51  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
  52  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
  53  */
  54 enum d40_command {
  55         D40_DMA_STOP            = 0,
  56         D40_DMA_RUN             = 1,
  57         D40_DMA_SUSPEND_REQ     = 2,
  58         D40_DMA_SUSPENDED       = 3
  59 };
  60
  61 /**
  62  * struct d40_lli_pool - Structure for keeping LLIs in memory
  63  *
  64  * @base: Pointer to memory area when the pre_alloc_lli's are not large
  65  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
  66  * pre_alloc_lli is used.
  67  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
  68  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
  69  * one buffer to one buffer.
  70  */
  71 struct d40_lli_pool {
  72         void    *base;
  73         int      size;
  74         /* Space for dst and src, plus an extra for padding */
  75         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
  76 };
  77
  78 /**
  79  * struct d40_desc - A descriptor is one DMA job.
  80  *
  81  * @lli_phy: LLI settings for physical channel. Both src and dst=
  82  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
  83  * lli_len equals one.
  84  * @lli_log: Same as above but for logical channels.
  85  * @lli_pool: The pool with two entries pre-allocated.
  86  * @lli_len: Number of llis of current descriptor.
  87  * @lli_count: Number of transfered llis.
  88  * @lli_tx_len: Max number of LLIs per transfer, there can be
  89  * many transfer for one descriptor.
  90  * @txd: DMA engine struct. Used for among other things for communication
  91  * during a transfer.
  92  * @node: List entry.
  93  * @dir: The transfer direction of this job.
  94  * @is_in_client_list: true if the client owns this descriptor.
  95  *
  96  * This descriptor is used for both logical and physical transfers.
  97  */
  98
  99 struct d40_desc {
 100         /* LLI physical */
 101         struct d40_phy_lli_bidir         lli_phy;
 102         /* LLI logical */
 103         struct d40_log_lli_bidir         lli_log;
 104
 105         struct d40_lli_pool              lli_pool;
 106         int                              lli_len;
 107         int                              lli_count;
 108         u32                              lli_tx_len;
 109
 110         struct dma_async_tx_descriptor   txd;
 111         struct list_head                 node;
 112
 113         enum dma_data_direction          dir;
 114         bool                             is_in_client_list;
 115 };
 116
 117 /**
 118  * struct d40_lcla_pool - LCLA pool settings and data.
 119  *
 120  * @base: The virtual address of LCLA. 18 bit aligned.
 121  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
 122  * This pointer is only there for clean-up on error.
 123  * @pages: The number of pages needed for all physical channels.
 124  * Only used later for clean-up on error
 125  * @lock: Lock to protect the content in this struct.
 126  * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
 127  * @num_blocks: The number of entries of alloc_map. Equals to the
 128  * number of physical channels.
 129  */
 130 struct d40_lcla_pool {
 131         void            *base;
 132         void            *base_unaligned;
 133         int              pages;
 134         spinlock_t       lock;
 135         u32             *alloc_map;
 136         int              num_blocks;
 137 };
 138
 139 /**
 140  * struct d40_phy_res - struct for handling eventlines mapped to physical
 141  * channels.
 142  *
 143  * @lock: A lock protection this entity.
 144  * @num: The physical channel number of this entity.
 145  * @allocated_src: Bit mapped to show which src event line's are mapped to
 146  * this physical channel. Can also be free or physically allocated.
 147  * @allocated_dst: Same as for src but is dst.
 148  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
 149  * event line number. Both allocated_src and allocated_dst can not be
 150  * allocated to a physical channel, since the interrupt handler has then
 151  * no way of figure out which one the interrupt belongs to.
 152  */
 153 struct d40_phy_res {
 154         spinlock_t lock;
 155         int        num;
 156         u32        allocated_src;
 157         u32        allocated_dst;
 158 };
 159
 160 struct d40_base;
 161
 162 /**
 163  * struct d40_chan - Struct that describes a channel.
 164  *
 165  * @lock: A spinlock to protect this struct.
 166  * @log_num: The logical number, if any of this channel.
 167  * @completed: Starts with 1, after first interrupt it is set to dma engine's
 168  * current cookie.
 169  * @pending_tx: The number of pending transfers. Used between interrupt handler
 170  * and tasklet.
 171  * @busy: Set to true when transfer is ongoing on this channel.
 172  * @phy_chan: Pointer to physical channel which this instance runs on. If this
 173  * point is NULL, then the channel is not allocated.
 174  * @chan: DMA engine handle.
 175  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
 176  * transfer and call client callback.
 177  * @client: Cliented owned descriptor list.
 178  * @active: Active descriptor.
 179  * @queue: Queued jobs.
 180  * @dma_cfg: The client configuration of this dma channel.
 181  * @base: Pointer to the device instance struct.
 182  * @src_def_cfg: Default cfg register setting for src.
 183  * @dst_def_cfg: Default cfg register setting for dst.
 184  * @log_def: Default logical channel settings.
 185  * @lcla: Space for one dst src pair for logical channel transfers.
 186  * @lcpa: Pointer to dst and src lcpa settings.
 187  *
 188  * This struct can either "be" a logical or a physical channel.
 189  */
 190 struct d40_chan {
 191         spinlock_t                       lock;
 192         int                              log_num;
 193         /* ID of the most recent completed transfer */
 194         int                              completed;
 195         int                              pending_tx;
 196         bool                             busy;
 197         struct d40_phy_res              *phy_chan;
 198         struct dma_chan                  chan;
 199         struct tasklet_struct            tasklet;
 200         struct list_head                 client;
 201         struct list_head                 active;
 202         struct list_head                 queue;
 203         struct stedma40_chan_cfg         dma_cfg;
 204         struct d40_base                 *base;
 205         /* Default register configurations */
 206         u32                              src_def_cfg;
 207         u32                              dst_def_cfg;
 208         struct d40_def_lcsp              log_def;
 209         struct d40_lcla_elem             lcla;
 210         struct d40_log_lli_full         *lcpa;
 211         /* Runtime reconfiguration */
 212         dma_addr_t                      runtime_addr;
 213         enum dma_data_direction         runtime_direction;
 214 };
 215
 216 /**
 217  * struct d40_base - The big global struct, one for each probe'd instance.
 218  *
 219  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
 220  * @execmd_lock: Lock for execute command usage since several channels share
 221  * the same physical register.
 222  * @dev: The device structure.
 223  * @virtbase: The virtual base address of the DMA's register.
 224  * @rev: silicon revision detected.
 225  * @clk: Pointer to the DMA clock structure.
 226  * @phy_start: Physical memory start of the DMA registers.
 227  * @phy_size: Size of the DMA register map.
 228  * @irq: The IRQ number.
 229  * @num_phy_chans: The number of physical channels. Read from HW. This
 230  * is the number of available channels for this driver, not counting "Secure
 231  * mode" allocated physical channels.
 232  * @num_log_chans: The number of logical channels. Calculated from
 233  * num_phy_chans.
 234  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
 235  * @dma_slave: dma_device channels that can do only do slave transfers.
 236  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
 237  * @phy_chans: Room for all possible physical channels in system.
 238  * @log_chans: Room for all possible logical channels in system.
 239  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
 240  * to log_chans entries.
 241  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
 242  * to phy_chans entries.
 243  * @plat_data: Pointer to provided platform_data which is the driver
 244  * configuration.
 245  * @phy_res: Vector containing all physical channels.
 246  * @lcla_pool: lcla pool settings and data.
 247  * @lcpa_base: The virtual mapped address of LCPA.
 248  * @phy_lcpa: The physical address of the LCPA.
 249  * @lcpa_size: The size of the LCPA area.
 250  * @desc_slab: cache for descriptors.
 251  */
 252 struct d40_base {
 253         spinlock_t                       interrupt_lock;
 254         spinlock_t                       execmd_lock;
 255         struct device                    *dev;
 256         void __iomem                     *virtbase;
 257         u8                                rev:4;
 258         struct clk                       *clk;
 259         phys_addr_t                       phy_start;
 260         resource_size_t                   phy_size;
 261         int                               irq;
 262         int                               num_phy_chans;
 263         int                               num_log_chans;
 264         struct dma_device                 dma_both;
 265         struct dma_device                 dma_slave;
 266         struct dma_device                 dma_memcpy;
 267         struct d40_chan                  *phy_chans;
 268         struct d40_chan                  *log_chans;
 269         struct d40_chan                 **lookup_log_chans;
 270         struct d40_chan                 **lookup_phy_chans;
 271         struct stedma40_platform_data    *plat_data;
 272         /* Physical half channels */
 273         struct d40_phy_res               *phy_res;
 274         struct d40_lcla_pool              lcla_pool;
 275         void                             *lcpa_base;
 276         dma_addr_t                        phy_lcpa;
 277         resource_size_t                   lcpa_size;
 278         struct kmem_cache                *desc_slab;
 279 };
 280
 281 /**
 282  * struct d40_interrupt_lookup - lookup table for interrupt handler
 283  *
 284  * @src: Interrupt mask register.
 285  * @clr: Interrupt clear register.
 286  * @is_error: true if this is an error interrupt.
 287  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
 288  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
 289  */
 290 struct d40_interrupt_lookup {
 291         u32 src;
 292         u32 clr;
 293         bool is_error;
 294         int offset;
 295 };
 296
 297 /**
 298  * struct d40_reg_val - simple lookup struct
 299  *
 300  * @reg: The register.
 301  * @val: The value that belongs to the register in reg.
 302  */
 303 struct d40_reg_val {
 304         unsigned int reg;
 305         unsigned int val;
 306 };
 307
 308 static int d40_pool_lli_alloc(struct d40_desc *d40d,
 309                               int lli_len, bool is_log)
 310 {
 311         u32 align;
 312         void *base;
 313
 314         if (is_log)
 315                 align = sizeof(struct d40_log_lli);
 316         else
 317                 align = sizeof(struct d40_phy_lli);
 318
 319         if (lli_len == 1) {
 320                 base = d40d->lli_pool.pre_alloc_lli;
 321                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
 322                 d40d->lli_pool.base = NULL;
 323         } else {
 324                 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
 325
 326                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
 327                 d40d->lli_pool.base = base;
 328
 329                 if (d40d->lli_pool.base == NULL)
 330                         return -ENOMEM;
 331         }
 332
 333         if (is_log) {
 334                 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
 335                                               align);
 336                 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
 337                                               align);
 338         } else {
 339                 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
 340                                               align);
 341                 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
 342                                               align);
 343
 344                 d40d->lli_phy.src_addr = virt_to_phys(d40d->lli_phy.src);
 345                 d40d->lli_phy.dst_addr = virt_to_phys(d40d->lli_phy.dst);
 346         }
 347
 348         return 0;
 349 }
 350
 351 static void d40_pool_lli_free(struct d40_desc *d40d)
 352 {
 353         kfree(d40d->lli_pool.base);
 354         d40d->lli_pool.base = NULL;
 355         d40d->lli_pool.size = 0;
 356         d40d->lli_log.src = NULL;
 357         d40d->lli_log.dst = NULL;
 358         d40d->lli_phy.src = NULL;
 359         d40d->lli_phy.dst = NULL;
 360         d40d->lli_phy.src_addr = 0;
 361         d40d->lli_phy.dst_addr = 0;
 362 }
 363
 364 static dma_cookie_t d40_assign_cookie(struct d40_chan *d40c,
 365                                       struct d40_desc *desc)
 366 {
 367         dma_cookie_t cookie = d40c->chan.cookie;
 368
 369         if (++cookie < 0)
 370                 cookie = 1;
 371
 372         d40c->chan.cookie = cookie;
 373         desc->txd.cookie = cookie;
 374
 375         return cookie;
 376 }
 377
 378 static void d40_desc_remove(struct d40_desc *d40d)
 379 {
 380         list_del(&d40d->node);
 381 }
 382
 383 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
 384 {
 385         struct d40_desc *d;
 386         struct d40_desc *_d;
 387
 388         if (!list_empty(&d40c->client)) {
 389                 list_for_each_entry_safe(d, _d, &d40c->client, node)
 390                         if (async_tx_test_ack(&d->txd)) {
 391                                 d40_pool_lli_free(d);
 392                                 d40_desc_remove(d);
 393                                 break;
 394                         }
 395         } else {
 396                 d = kmem_cache_alloc(d40c->base->desc_slab, GFP_NOWAIT);
 397                 if (d != NULL) {
 398                         memset(d, 0, sizeof(struct d40_desc));
 399                         INIT_LIST_HEAD(&d->node);
 400                 }
 401         }
 402         return d;
 403 }
 404
 405 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
 406 {
 407         kmem_cache_free(d40c->base->desc_slab, d40d);
 408 }
 409
 410 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
 411 {
 412         list_add_tail(&desc->node, &d40c->active);
 413 }
 414
 415 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
 416 {
 417         struct d40_desc *d;
 418
 419         if (list_empty(&d40c->active))
 420                 return NULL;
 421
 422         d = list_first_entry(&d40c->active,
 423                              struct d40_desc,
 424                              node);
 425         return d;
 426 }
 427
 428 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
 429 {
 430         list_add_tail(&desc->node, &d40c->queue);
 431 }
 432
 433 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
 434 {
 435         struct d40_desc *d;
 436
 437         if (list_empty(&d40c->queue))
 438                 return NULL;
 439
 440         d = list_first_entry(&d40c->queue,
 441                              struct d40_desc,
 442                              node);
 443         return d;
 444 }
 445
 446 /* Support functions for logical channels */
 447
 448 static int d40_lcla_id_get(struct d40_chan *d40c)
 449 {
 450         int src_id = 0;
 451         int dst_id = 0;
 452         struct d40_log_lli *lcla_lidx_base =
 453                 d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024;
 454         int i;
 455         int lli_per_log = d40c->base->plat_data->llis_per_log;
 456         unsigned long flags;
 457
 458         if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0)
 459                 return 0;
 460
 461         if (d40c->base->lcla_pool.num_blocks > 32)
 462                 return -EINVAL;
 463
 464         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 465
 466         for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) {
 467                 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
 468                       (0x1 << i))) {
 469                         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
 470                                 (0x1 << i);
 471                         break;
 472                 }
 473         }
 474         src_id = i;
 475         if (src_id >= d40c->base->lcla_pool.num_blocks)
 476                 goto err;
 477
 478         for (; i < d40c->base->lcla_pool.num_blocks; i++) {
 479                 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
 480                       (0x1 << i))) {
 481                         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
 482                                 (0x1 << i);
 483                         break;
 484                 }
 485         }
 486
 487         dst_id = i;
 488         if (dst_id == src_id)
 489                 goto err;
 490
 491         d40c->lcla.src_id = src_id;
 492         d40c->lcla.dst_id = dst_id;
 493         d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1;
 494         d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1;
 495
 496         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 497         return 0;
 498 err:
 499         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 500         return -EINVAL;
 501 }
 502
 503
 504 static int d40_channel_execute_command(struct d40_chan *d40c,
 505                                        enum d40_command command)
 506 {
 507         int status, i;
 508         void __iomem *active_reg;
 509         int ret = 0;
 510         unsigned long flags;
 511         u32 wmask;
 512
 513         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
 514
 515         if (d40c->phy_chan->num % 2 == 0)
 516                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
 517         else
 518                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
 519
 520         if (command == D40_DMA_SUSPEND_REQ) {
 521                 status = (readl(active_reg) &
 522                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
 523                         D40_CHAN_POS(d40c->phy_chan->num);
 524
 525                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
 526                         goto done;
 527         }
 528
 529         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
 530         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
 531                active_reg);
 532
 533         if (command == D40_DMA_SUSPEND_REQ) {
 534
 535                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
 536                         status = (readl(active_reg) &
 537                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
 538                                 D40_CHAN_POS(d40c->phy_chan->num);
 539
 540                         cpu_relax();
 541                         /*
 542                          * Reduce the number of bus accesses while
 543                          * waiting for the DMA to suspend.
 544                          */
 545                         udelay(3);
 546
 547                         if (status == D40_DMA_STOP ||
 548                             status == D40_DMA_SUSPENDED)
 549                                 break;
 550                 }
 551
 552                 if (i == D40_SUSPEND_MAX_IT) {
 553                         dev_err(&d40c->chan.dev->device,
 554                                 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
 555                                 __func__, d40c->phy_chan->num, d40c->log_num,
 556                                 status);
 557                         dump_stack();
 558                         ret = -EBUSY;
 559                 }
 560
 561         }
 562 done:
 563         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
 564         return ret;
 565 }
 566
 567 static void d40_term_all(struct d40_chan *d40c)
 568 {
 569         struct d40_desc *d40d;
 570         unsigned long flags;
 571
 572         /* Release active descriptors */
 573         while ((d40d = d40_first_active_get(d40c))) {
 574                 d40_desc_remove(d40d);
 575
 576                 /* Return desc to free-list */
 577                 d40_desc_free(d40c, d40d);
 578         }
 579
 580         /* Release queued descriptors waiting for transfer */
 581         while ((d40d = d40_first_queued(d40c))) {
 582                 d40_desc_remove(d40d);
 583
 584                 /* Return desc to free-list */
 585                 d40_desc_free(d40c, d40d);
 586         }
 587
 588         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 589
 590         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
 591                 (~(0x1 << d40c->lcla.dst_id));
 592         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
 593                 (~(0x1 << d40c->lcla.src_id));
 594
 595         d40c->lcla.src_id = -1;
 596         d40c->lcla.dst_id = -1;
 597
 598         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 599
 600         d40c->pending_tx = 0;
 601         d40c->busy = false;
 602 }
 603
 604 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
 605 {
 606         u32 val;
 607         unsigned long flags;
 608
 609         /* Notice, that disable requires the physical channel to be stopped */
 610         if (do_enable)
 611                 val = D40_ACTIVATE_EVENTLINE;
 612         else
 613                 val = D40_DEACTIVATE_EVENTLINE;
 614
 615         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
 616
 617         /* Enable event line connected to device (or memcpy) */
 618         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
 619             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
 620                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 621
 622                 writel((val << D40_EVENTLINE_POS(event)) |
 623                        ~D40_EVENTLINE_MASK(event),
 624                        d40c->base->virtbase + D40_DREG_PCBASE +
 625                        d40c->phy_chan->num * D40_DREG_PCDELTA +
 626                        D40_CHAN_REG_SSLNK);
 627         }
 628         if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
 629                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 630
 631                 writel((val << D40_EVENTLINE_POS(event)) |
 632                        ~D40_EVENTLINE_MASK(event),
 633                        d40c->base->virtbase + D40_DREG_PCBASE +
 634                        d40c->phy_chan->num * D40_DREG_PCDELTA +
 635                        D40_CHAN_REG_SDLNK);
 636         }
 637
 638         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
 639 }
 640
 641 static u32 d40_chan_has_events(struct d40_chan *d40c)
 642 {
 643         u32 val;
 644
 645         val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
 646                     d40c->phy_chan->num * D40_DREG_PCDELTA +
 647                     D40_CHAN_REG_SSLNK);
 648
 649         val |= readl(d40c->base->virtbase + D40_DREG_PCBASE +
 650                      d40c->phy_chan->num * D40_DREG_PCDELTA +
 651                      D40_CHAN_REG_SDLNK);
 652         return val;
 653 }
 654
 655 static void d40_config_write(struct d40_chan *d40c)
 656 {
 657         u32 addr_base;
 658         u32 var;
 659
 660         /* Odd addresses are even addresses + 4 */
 661         addr_base = (d40c->phy_chan->num % 2) * 4;
 662         /* Setup channel mode to logical or physical */
 663         var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) <<
 664                 D40_CHAN_POS(d40c->phy_chan->num);
 665         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
 666
 667         /* Setup operational mode option register */
 668         var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) &
 669                0x3) << D40_CHAN_POS(d40c->phy_chan->num);
 670
 671         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
 672
 673         if (d40c->log_num != D40_PHY_CHAN) {
 674                 /* Set default config for CFG reg */
 675                 writel(d40c->src_def_cfg,
 676                        d40c->base->virtbase + D40_DREG_PCBASE +
 677                        d40c->phy_chan->num * D40_DREG_PCDELTA +
 678                        D40_CHAN_REG_SSCFG);
 679                 writel(d40c->dst_def_cfg,
 680                        d40c->base->virtbase + D40_DREG_PCBASE +
 681                        d40c->phy_chan->num * D40_DREG_PCDELTA +
 682                        D40_CHAN_REG_SDCFG);
 683
 684                 /* Set LIDX for lcla */
 685                 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
 686                        D40_SREG_ELEM_LOG_LIDX_MASK,
 687                        d40c->base->virtbase + D40_DREG_PCBASE +
 688                        d40c->phy_chan->num * D40_DREG_PCDELTA +
 689                        D40_CHAN_REG_SDELT);
 690
 691                 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
 692                        D40_SREG_ELEM_LOG_LIDX_MASK,
 693                        d40c->base->virtbase + D40_DREG_PCBASE +
 694                        d40c->phy_chan->num * D40_DREG_PCDELTA +
 695                        D40_CHAN_REG_SSELT);
 696
 697         }
 698 }
 699
 700 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
 701 {
 702         if (d40d->lli_phy.dst && d40d->lli_phy.src) {
 703                 d40_phy_lli_write(d40c->base->virtbase,
 704                                   d40c->phy_chan->num,
 705                                   d40d->lli_phy.dst,
 706                                   d40d->lli_phy.src);
 707         } else if (d40d->lli_log.dst && d40d->lli_log.src) {
 708                 struct d40_log_lli *src = d40d->lli_log.src;
 709                 struct d40_log_lli *dst = d40d->lli_log.dst;
 710                 int s;
 711
 712                 src += d40d->lli_count;
 713                 dst += d40d->lli_count;
 714                 s = d40_log_lli_write(d40c->lcpa,
 715                                       d40c->lcla.src, d40c->lcla.dst,
 716                                       dst, src,
 717                                       d40c->base->plat_data->llis_per_log);
 718
 719                 /* If s equals to zero, the job is not linked */
 720                 if (s > 0) {
 721                         (void) dma_map_single(d40c->base->dev, d40c->lcla.src,
 722                                               s * sizeof(struct d40_log_lli),
 723                                               DMA_TO_DEVICE);
 724                         (void) dma_map_single(d40c->base->dev, d40c->lcla.dst,
 725                                               s * sizeof(struct d40_log_lli),
 726                                               DMA_TO_DEVICE);
 727                 }
 728         }
 729         d40d->lli_count += d40d->lli_tx_len;
 730 }
 731
 732 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 733 {
 734         struct d40_chan *d40c = container_of(tx->chan,
 735                                              struct d40_chan,
 736                                              chan);
 737         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
 738         unsigned long flags;
 739
 740         spin_lock_irqsave(&d40c->lock, flags);
 741
 742         tx->cookie = d40_assign_cookie(d40c, d40d);
 743
 744         d40_desc_queue(d40c, d40d);
 745
 746         spin_unlock_irqrestore(&d40c->lock, flags);
 747
 748         return tx->cookie;
 749 }
 750
 751 static int d40_start(struct d40_chan *d40c)
 752 {
 753         if (d40c->base->rev == 0) {
 754                 int err;
 755
 756                 if (d40c->log_num != D40_PHY_CHAN) {
 757                         err = d40_channel_execute_command(d40c,
 758                                                           D40_DMA_SUSPEND_REQ);
 759                         if (err)
 760                                 return err;
 761                 }
 762         }
 763
 764         if (d40c->log_num != D40_PHY_CHAN)
 765                 d40_config_set_event(d40c, true);
 766
 767         return d40_channel_execute_command(d40c, D40_DMA_RUN);
 768 }
 769
 770 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
 771 {
 772         struct d40_desc *d40d;
 773         int err;
 774
 775         /* Start queued jobs, if any */
 776         d40d = d40_first_queued(d40c);
 777
 778         if (d40d != NULL) {
 779                 d40c->busy = true;
 780
 781                 /* Remove from queue */
 782                 d40_desc_remove(d40d);
 783
 784                 /* Add to active queue */
 785                 d40_desc_submit(d40c, d40d);
 786
 787                 /* Initiate DMA job */
 788                 d40_desc_load(d40c, d40d);
 789
 790                 /* Start dma job */
 791                 err = d40_start(d40c);
 792
 793                 if (err)
 794                         return NULL;
 795         }
 796
 797         return d40d;
 798 }
 799
 800 /* called from interrupt context */
 801 static void dma_tc_handle(struct d40_chan *d40c)
 802 {
 803         struct d40_desc *d40d;
 804
 805         if (!d40c->phy_chan)
 806                 return;
 807
 808         /* Get first active entry from list */
 809         d40d = d40_first_active_get(d40c);
 810
 811         if (d40d == NULL)
 812                 return;
 813
 814         if (d40d->lli_count < d40d->lli_len) {
 815
 816                 d40_desc_load(d40c, d40d);
 817                 /* Start dma job */
 818                 (void) d40_start(d40c);
 819                 return;
 820         }
 821
 822         if (d40_queue_start(d40c) == NULL)
 823                 d40c->busy = false;
 824
 825         d40c->pending_tx++;
 826         tasklet_schedule(&d40c->tasklet);
 827
 828 }
 829
 830 static void dma_tasklet(unsigned long data)
 831 {
 832         struct d40_chan *d40c = (struct d40_chan *) data;
 833         struct d40_desc *d40d_fin;
 834         unsigned long flags;
 835         dma_async_tx_callback callback;
 836         void *callback_param;
 837
 838         spin_lock_irqsave(&d40c->lock, flags);
 839
 840         /* Get first active entry from list */
 841         d40d_fin = d40_first_active_get(d40c);
 842
 843         if (d40d_fin == NULL)
 844                 goto err;
 845
 846         d40c->completed = d40d_fin->txd.cookie;
 847
 848         /*
 849          * If terminating a channel pending_tx is set to zero.
 850          * This prevents any finished active jobs to return to the client.
 851          */
 852         if (d40c->pending_tx == 0) {
 853                 spin_unlock_irqrestore(&d40c->lock, flags);
 854                 return;
 855         }
 856
 857         /* Callback to client */
 858         callback = d40d_fin->txd.callback;
 859         callback_param = d40d_fin->txd.callback_param;
 860
 861         if (async_tx_test_ack(&d40d_fin->txd)) {
 862                 d40_pool_lli_free(d40d_fin);
 863                 d40_desc_remove(d40d_fin);
 864                 /* Return desc to free-list */
 865                 d40_desc_free(d40c, d40d_fin);
 866         } else {
 867                 if (!d40d_fin->is_in_client_list) {
 868                         d40_desc_remove(d40d_fin);
 869                         list_add_tail(&d40d_fin->node, &d40c->client);
 870                         d40d_fin->is_in_client_list = true;
 871                 }
 872         }
 873
 874         d40c->pending_tx--;
 875
 876         if (d40c->pending_tx)
 877                 tasklet_schedule(&d40c->tasklet);
 878
 879         spin_unlock_irqrestore(&d40c->lock, flags);
 880
 881         if (callback && (d40d_fin->txd.flags & DMA_PREP_INTERRUPT))
 882                 callback(callback_param);
 883
 884         return;
 885
 886  err:
 887         /* Rescue manouver if receiving double interrupts */
 888         if (d40c->pending_tx > 0)
 889                 d40c->pending_tx--;
 890         spin_unlock_irqrestore(&d40c->lock, flags);
 891 }
 892
 893 static irqreturn_t d40_handle_interrupt(int irq, void *data)
 894 {
 895         static const struct d40_interrupt_lookup il[] = {
 896                 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
 897                 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
 898                 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
 899                 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
 900                 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
 901                 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
 902                 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
 903                 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
 904                 {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
 905                 {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
 906         };
 907
 908         int i;
 909         u32 regs[ARRAY_SIZE(il)];
 910         u32 idx;
 911         u32 row;
 912         long chan = -1;
 913         struct d40_chan *d40c;
 914         unsigned long flags;
 915         struct d40_base *base = data;
 916
 917         spin_lock_irqsave(&base->interrupt_lock, flags);
 918
 919         /* Read interrupt status of both logical and physical channels */
 920         for (i = 0; i < ARRAY_SIZE(il); i++)
 921                 regs[i] = readl(base->virtbase + il[i].src);
 922
 923         for (;;) {
 924
 925                 chan = find_next_bit((unsigned long *)regs,
 926                                      BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
 927
 928                 /* No more set bits found? */
 929                 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
 930                         break;
 931
 932                 row = chan / BITS_PER_LONG;
 933                 idx = chan & (BITS_PER_LONG - 1);
 934
 935                 /* ACK interrupt */
 936                 writel(1 << idx, base->virtbase + il[row].clr);
 937
 938                 if (il[row].offset == D40_PHY_CHAN)
 939                         d40c = base->lookup_phy_chans[idx];
 940                 else
 941                         d40c = base->lookup_log_chans[il[row].offset + idx];
 942                 spin_lock(&d40c->lock);
 943
 944                 if (!il[row].is_error)
 945                         dma_tc_handle(d40c);
 946                 else
 947                         dev_err(base->dev,
 948                                 "[%s] IRQ chan: %ld offset %d idx %d\n",
 949                                 __func__, chan, il[row].offset, idx);
 950
 951                 spin_unlock(&d40c->lock);
 952         }
 953
 954         spin_unlock_irqrestore(&base->interrupt_lock, flags);
 955
 956         return IRQ_HANDLED;
 957 }
 958
 959
 960 static int d40_validate_conf(struct d40_chan *d40c,
 961                              struct stedma40_chan_cfg *conf)
 962 {
 963         int res = 0;
 964         u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
 965         u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
 966         bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
 967                 == STEDMA40_CHANNEL_IN_LOG_MODE;
 968
 969         if (!conf->dir) {
 970                 dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
 971                         __func__);
 972                 res = -EINVAL;
 973         }
 974
 975         if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
 976             d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
 977             d40c->runtime_addr == 0) {
 978
 979                 dev_err(&d40c->chan.dev->device,
 980                         "[%s] Invalid TX channel address (%d)\n",
 981                         __func__, conf->dst_dev_type);
 982                 res = -EINVAL;
 983         }
 984
 985         if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
 986             d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
 987             d40c->runtime_addr == 0) {
 988                 dev_err(&d40c->chan.dev->device,
 989                         "[%s] Invalid RX channel address (%d)\n",
 990                         __func__, conf->src_dev_type);
 991                 res = -EINVAL;
 992         }
 993
 994         if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
 995             dst_event_group == STEDMA40_DEV_DST_MEMORY) {
 996                 dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
 997                         __func__);
 998                 res = -EINVAL;
 999         }
1000
1001         if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1002             src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1003                 dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
1004                         __func__);
1005                 res = -EINVAL;
1006         }
1007
1008         if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1009             dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1010                 dev_err(&d40c->chan.dev->device,
1011                         "[%s] No event line\n", __func__);
1012                 res = -EINVAL;
1013         }
1014
1015         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1016             (src_event_group != dst_event_group)) {
1017                 dev_err(&d40c->chan.dev->device,
1018                         "[%s] Invalid event group\n", __func__);
1019                 res = -EINVAL;
1020         }
1021
1022         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1023                 /*
1024                  * DMAC HW supports it. Will be added to this driver,
1025                  * in case any dma client requires it.
1026                  */
1027                 dev_err(&d40c->chan.dev->device,
1028                         "[%s] periph to periph not supported\n",
1029                         __func__);
1030                 res = -EINVAL;
1031         }
1032
1033         return res;
1034 }
1035
1036 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1037                                int log_event_line, bool is_log)
1038 {
1039         unsigned long flags;
1040         spin_lock_irqsave(&phy->lock, flags);
1041         if (!is_log) {
1042                 /* Physical interrupts are masked per physical full channel */
1043                 if (phy->allocated_src == D40_ALLOC_FREE &&
1044                     phy->allocated_dst == D40_ALLOC_FREE) {
1045                         phy->allocated_dst = D40_ALLOC_PHY;
1046                         phy->allocated_src = D40_ALLOC_PHY;
1047                         goto found;
1048                 } else
1049                         goto not_found;
1050         }
1051
1052         /* Logical channel */
1053         if (is_src) {
1054                 if (phy->allocated_src == D40_ALLOC_PHY)
1055                         goto not_found;
1056
1057                 if (phy->allocated_src == D40_ALLOC_FREE)
1058                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1059
1060                 if (!(phy->allocated_src & (1 << log_event_line))) {
1061                         phy->allocated_src |= 1 << log_event_line;
1062                         goto found;
1063                 } else
1064                         goto not_found;
1065         } else {
1066                 if (phy->allocated_dst == D40_ALLOC_PHY)
1067                         goto not_found;
1068
1069                 if (phy->allocated_dst == D40_ALLOC_FREE)
1070                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1071
1072                 if (!(phy->allocated_dst & (1 << log_event_line))) {
1073                         phy->allocated_dst |= 1 << log_event_line;
1074                         goto found;
1075                 } else
1076                         goto not_found;
1077         }
1078
1079 not_found:
1080         spin_unlock_irqrestore(&phy->lock, flags);
1081         return false;
1082 found:
1083         spin_unlock_irqrestore(&phy->lock, flags);
1084         return true;
1085 }
1086
1087 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1088                                int log_event_line)
1089 {
1090         unsigned long flags;
1091         bool is_free = false;
1092
1093         spin_lock_irqsave(&phy->lock, flags);
1094         if (!log_event_line) {
1095                 /* Physical interrupts are masked per physical full channel */
1096                 phy->allocated_dst = D40_ALLOC_FREE;
1097                 phy->allocated_src = D40_ALLOC_FREE;
1098                 is_free = true;
1099                 goto out;
1100         }
1101
1102         /* Logical channel */
1103         if (is_src) {
1104                 phy->allocated_src &= ~(1 << log_event_line);
1105                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1106                         phy->allocated_src = D40_ALLOC_FREE;
1107         } else {
1108                 phy->allocated_dst &= ~(1 << log_event_line);
1109                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1110                         phy->allocated_dst = D40_ALLOC_FREE;
1111         }
1112
1113         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1114                    D40_ALLOC_FREE);
1115
1116 out:
1117         spin_unlock_irqrestore(&phy->lock, flags);
1118
1119         return is_free;
1120 }
1121
1122 static int d40_allocate_channel(struct d40_chan *d40c)
1123 {
1124         int dev_type;
1125         int event_group;
1126         int event_line;
1127         struct d40_phy_res *phys;
1128         int i;
1129         int j;
1130         int log_num;
1131         bool is_src;
1132         bool is_log = (d40c->dma_cfg.channel_type &
1133                        STEDMA40_CHANNEL_IN_OPER_MODE)
1134                 == STEDMA40_CHANNEL_IN_LOG_MODE;
1135
1136
1137         phys = d40c->base->phy_res;
1138
1139         if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1140                 dev_type = d40c->dma_cfg.src_dev_type;
1141                 log_num = 2 * dev_type;
1142                 is_src = true;
1143         } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1144                    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1145                 /* dst event lines are used for logical memcpy */
1146                 dev_type = d40c->dma_cfg.dst_dev_type;
1147                 log_num = 2 * dev_type + 1;
1148                 is_src = false;
1149         } else
1150                 return -EINVAL;
1151
1152         event_group = D40_TYPE_TO_GROUP(dev_type);
1153         event_line = D40_TYPE_TO_EVENT(dev_type);
1154
1155         if (!is_log) {
1156                 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1157                         /* Find physical half channel */
1158                         for (i = 0; i < d40c->base->num_phy_chans; i++) {
1159
1160                                 if (d40_alloc_mask_set(&phys[i], is_src,
1161                                                        0, is_log))
1162                                         goto found_phy;
1163                         }
1164                 } else
1165                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1166                                 int phy_num = j  + event_group * 2;
1167                                 for (i = phy_num; i < phy_num + 2; i++) {
1168                                         if (d40_alloc_mask_set(&phys[i],
1169                                                                is_src,
1170                                                                0,
1171                                                                is_log))
1172                                                 goto found_phy;
1173                                 }
1174                         }
1175                 return -EINVAL;
1176 found_phy:
1177                 d40c->phy_chan = &phys[i];
1178                 d40c->log_num = D40_PHY_CHAN;
1179                 goto out;
1180         }
1181         if (dev_type == -1)
1182                 return -EINVAL;
1183
1184         /* Find logical channel */
1185         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1186                 int phy_num = j + event_group * 2;
1187                 /*
1188                  * Spread logical channels across all available physical rather
1189                  * than pack every logical channel at the first available phy
1190                  * channels.
1191                  */
1192                 if (is_src) {
1193                         for (i = phy_num; i < phy_num + 2; i++) {
1194                                 if (d40_alloc_mask_set(&phys[i], is_src,
1195                                                        event_line, is_log))
1196                                         goto found_log;
1197                         }
1198                 } else {
1199                         for (i = phy_num + 1; i >= phy_num; i--) {
1200                                 if (d40_alloc_mask_set(&phys[i], is_src,
1201                                                        event_line, is_log))
1202                                         goto found_log;
1203                         }
1204                 }
1205         }
1206         return -EINVAL;
1207
1208 found_log:
1209         d40c->phy_chan = &phys[i];
1210         d40c->log_num = log_num;
1211 out:
1212
1213         if (is_log)
1214                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1215         else
1216                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1217
1218         return 0;
1219
1220 }
1221
1222 static int d40_config_memcpy(struct d40_chan *d40c)
1223 {
1224         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1225
1226         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1227                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1228                 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1229                 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1230                         memcpy[d40c->chan.chan_id];
1231
1232         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1233                    dma_has_cap(DMA_SLAVE, cap)) {
1234                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1235         } else {
1236                 dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
1237                         __func__);
1238                 return -EINVAL;
1239         }
1240
1241         return 0;
1242 }
1243
1244
1245 static int d40_free_dma(struct d40_chan *d40c)
1246 {
1247
1248         int res = 0;
1249         u32 event;
1250         struct d40_phy_res *phy = d40c->phy_chan;
1251         bool is_src;
1252         struct d40_desc *d;
1253         struct d40_desc *_d;
1254
1255
1256         /* Terminate all queued and active transfers */
1257         d40_term_all(d40c);
1258
1259         /* Release client owned descriptors */
1260         if (!list_empty(&d40c->client))
1261                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1262                         d40_pool_lli_free(d);
1263                         d40_desc_remove(d);
1264                         /* Return desc to free-list */
1265                         d40_desc_free(d40c, d);
1266                 }
1267
1268         if (phy == NULL) {
1269                 dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
1270                         __func__);
1271                 return -EINVAL;
1272         }
1273
1274         if (phy->allocated_src == D40_ALLOC_FREE &&
1275             phy->allocated_dst == D40_ALLOC_FREE) {
1276                 dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
1277                         __func__);
1278                 return -EINVAL;
1279         }
1280
1281         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1282             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1283                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1284                 is_src = false;
1285         } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1286                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1287                 is_src = true;
1288         } else {
1289                 dev_err(&d40c->chan.dev->device,
1290                         "[%s] Unknown direction\n", __func__);
1291                 return -EINVAL;
1292         }
1293
1294         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1295         if (res) {
1296                 dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
1297                         __func__);
1298                 return res;
1299         }
1300
1301         if (d40c->log_num != D40_PHY_CHAN) {
1302                 /* Release logical channel, deactivate the event line */
1303
1304                 d40_config_set_event(d40c, false);
1305                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1306
1307                 /*
1308                  * Check if there are more logical allocation
1309                  * on this phy channel.
1310                  */
1311                 if (!d40_alloc_mask_free(phy, is_src, event)) {
1312                         /* Resume the other logical channels if any */
1313                         if (d40_chan_has_events(d40c)) {
1314                                 res = d40_channel_execute_command(d40c,
1315                                                                   D40_DMA_RUN);
1316                                 if (res) {
1317                                         dev_err(&d40c->chan.dev->device,
1318                                                 "[%s] Executing RUN command\n",
1319                                                 __func__);
1320                                         return res;
1321                                 }
1322                         }
1323                         return 0;
1324                 }
1325         } else {
1326                 (void) d40_alloc_mask_free(phy, is_src, 0);
1327         }
1328
1329         /* Release physical channel */
1330         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1331         if (res) {
1332                 dev_err(&d40c->chan.dev->device,
1333                         "[%s] Failed to stop channel\n", __func__);
1334                 return res;
1335         }
1336         d40c->phy_chan = NULL;
1337         /* Invalidate channel type */
1338         d40c->dma_cfg.channel_type = 0;
1339         d40c->base->lookup_phy_chans[phy->num] = NULL;
1340
1341         return 0;
1342 }
1343
1344 static int d40_pause(struct dma_chan *chan)
1345 {
1346         struct d40_chan *d40c =
1347                 container_of(chan, struct d40_chan, chan);
1348         int res;
1349         unsigned long flags;
1350
1351         spin_lock_irqsave(&d40c->lock, flags);
1352
1353         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1354         if (res == 0) {
1355                 if (d40c->log_num != D40_PHY_CHAN) {
1356                         d40_config_set_event(d40c, false);
1357                         /* Resume the other logical channels if any */
1358                         if (d40_chan_has_events(d40c))
1359                                 res = d40_channel_execute_command(d40c,
1360                                                                   D40_DMA_RUN);
1361                 }
1362         }
1363
1364         spin_unlock_irqrestore(&d40c->lock, flags);
1365         return res;
1366 }
1367
1368 static bool d40_is_paused(struct d40_chan *d40c)
1369 {
1370         bool is_paused = false;
1371         unsigned long flags;
1372         void __iomem *active_reg;
1373         u32 status;
1374         u32 event;
1375
1376         spin_lock_irqsave(&d40c->lock, flags);
1377
1378         if (d40c->log_num == D40_PHY_CHAN) {
1379                 if (d40c->phy_chan->num % 2 == 0)
1380                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1381                 else
1382                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1383
1384                 status = (readl(active_reg) &
1385                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1386                         D40_CHAN_POS(d40c->phy_chan->num);
1387                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1388                         is_paused = true;
1389
1390                 goto _exit;
1391         }
1392
1393         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1394             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
1395                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1396         else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1397                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1398         else {
1399                 dev_err(&d40c->chan.dev->device,
1400                         "[%s] Unknown direction\n", __func__);
1401                 goto _exit;
1402         }
1403         status = d40_chan_has_events(d40c);
1404         status = (status & D40_EVENTLINE_MASK(event)) >>
1405                 D40_EVENTLINE_POS(event);
1406
1407         if (status != D40_DMA_RUN)
1408                 is_paused = true;
1409 _exit:
1410         spin_unlock_irqrestore(&d40c->lock, flags);
1411         return is_paused;
1412
1413 }
1414
1415
1416 static bool d40_tx_is_linked(struct d40_chan *d40c)
1417 {
1418         bool is_link;
1419
1420         if (d40c->log_num != D40_PHY_CHAN)
1421                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
1422         else
1423                 is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
1424                                 d40c->phy_chan->num * D40_DREG_PCDELTA +
1425                                 D40_CHAN_REG_SDLNK) &
1426                         D40_SREG_LNK_PHYS_LNK_MASK;
1427         return is_link;
1428 }
1429
1430 static u32 d40_residue(struct d40_chan *d40c)
1431 {
1432         u32 num_elt;
1433
1434         if (d40c->log_num != D40_PHY_CHAN)
1435                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1436                         >> D40_MEM_LCSP2_ECNT_POS;
1437         else
1438                 num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
1439                                  d40c->phy_chan->num * D40_DREG_PCDELTA +
1440                                  D40_CHAN_REG_SDELT) &
1441                            D40_SREG_ELEM_PHY_ECNT_MASK) >>
1442                         D40_SREG_ELEM_PHY_ECNT_POS;
1443         return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1444 }
1445
1446 static int d40_resume(struct dma_chan *chan)
1447 {
1448         struct d40_chan *d40c =
1449                 container_of(chan, struct d40_chan, chan);
1450         int res = 0;
1451         unsigned long flags;
1452
1453         spin_lock_irqsave(&d40c->lock, flags);
1454
1455         if (d40c->base->rev == 0)
1456                 if (d40c->log_num != D40_PHY_CHAN) {
1457                         res = d40_channel_execute_command(d40c,
1458                                                           D40_DMA_SUSPEND_REQ);
1459                         goto no_suspend;
1460                 }
1461
1462         /* If bytes left to transfer or linked tx resume job */
1463         if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1464                 if (d40c->log_num != D40_PHY_CHAN)
1465                         d40_config_set_event(d40c, true);
1466                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1467         }
1468
1469 no_suspend:
1470         spin_unlock_irqrestore(&d40c->lock, flags);
1471         return res;
1472 }
1473
1474 static u32 stedma40_residue(struct dma_chan *chan)
1475 {
1476         struct d40_chan *d40c =
1477                 container_of(chan, struct d40_chan, chan);
1478         u32 bytes_left;
1479         unsigned long flags;
1480
1481         spin_lock_irqsave(&d40c->lock, flags);
1482         bytes_left = d40_residue(d40c);
1483         spin_unlock_irqrestore(&d40c->lock, flags);
1484
1485         return bytes_left;
1486 }
1487
1488 /* Public DMA functions in addition to the DMA engine framework */
1489
1490 int stedma40_set_psize(struct dma_chan *chan,
1491                        int src_psize,
1492                        int dst_psize)
1493 {
1494         struct d40_chan *d40c =
1495                 container_of(chan, struct d40_chan, chan);
1496         unsigned long flags;
1497
1498         spin_lock_irqsave(&d40c->lock, flags);
1499
1500         if (d40c->log_num != D40_PHY_CHAN) {
1501                 d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1502                 d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1503                 d40c->log_def.lcsp1 |= src_psize <<
1504                         D40_MEM_LCSP1_SCFG_PSIZE_POS;
1505                 d40c->log_def.lcsp3 |= dst_psize <<
1506                         D40_MEM_LCSP1_SCFG_PSIZE_POS;
1507                 goto out;
1508         }
1509
1510         if (src_psize == STEDMA40_PSIZE_PHY_1)
1511                 d40c->src_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1512         else {
1513                 d40c->src_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1514                 d40c->src_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1515                                        D40_SREG_CFG_PSIZE_POS);
1516                 d40c->src_def_cfg |= src_psize << D40_SREG_CFG_PSIZE_POS;
1517         }
1518
1519         if (dst_psize == STEDMA40_PSIZE_PHY_1)
1520                 d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1521         else {
1522                 d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1523                 d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1524                                        D40_SREG_CFG_PSIZE_POS);
1525                 d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS;
1526         }
1527 out:
1528         spin_unlock_irqrestore(&d40c->lock, flags);
1529         return 0;
1530 }
1531 EXPORT_SYMBOL(stedma40_set_psize);
1532
1533 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1534                                                    struct scatterlist *sgl_dst,
1535                                                    struct scatterlist *sgl_src,
1536                                                    unsigned int sgl_len,
1537                                                    unsigned long dma_flags)
1538 {
1539         int res;
1540         struct d40_desc *d40d;
1541         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1542                                              chan);
1543         unsigned long flags;
1544
1545         if (d40c->phy_chan == NULL) {
1546                 dev_err(&d40c->chan.dev->device,
1547                         "[%s] Unallocated channel.\n", __func__);
1548                 return ERR_PTR(-EINVAL);
1549         }
1550
1551         spin_lock_irqsave(&d40c->lock, flags);
1552         d40d = d40_desc_get(d40c);
1553
1554         if (d40d == NULL)
1555                 goto err;
1556
1557         d40d->lli_len = sgl_len;
1558         d40d->lli_tx_len = d40d->lli_len;
1559         d40d->txd.flags = dma_flags;
1560
1561         if (d40c->log_num != D40_PHY_CHAN) {
1562                 if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
1563                         d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1564
1565                 if (sgl_len > 1)
1566                         /*
1567                          * Check if there is space available in lcla. If not,
1568                          * split list into 1-length and run only in lcpa
1569                          * space.
1570                          */
1571                         if (d40_lcla_id_get(d40c) != 0)
1572                                 d40d->lli_tx_len = 1;
1573
1574                 if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
1575                         dev_err(&d40c->chan.dev->device,
1576                                 "[%s] Out of memory\n", __func__);
1577                         goto err;
1578                 }
1579
1580                 (void) d40_log_sg_to_lli(d40c->lcla.src_id,
1581                                          sgl_src,
1582                                          sgl_len,
1583                                          d40d->lli_log.src,
1584                                          d40c->log_def.lcsp1,
1585                                          d40c->dma_cfg.src_info.data_width,
1586                                          d40d->lli_tx_len,
1587                                          d40c->base->plat_data->llis_per_log);
1588
1589                 (void) d40_log_sg_to_lli(d40c->lcla.dst_id,
1590                                          sgl_dst,
1591                                          sgl_len,
1592                                          d40d->lli_log.dst,
1593                                          d40c->log_def.lcsp3,
1594                                          d40c->dma_cfg.dst_info.data_width,
1595                                          d40d->lli_tx_len,
1596                                          d40c->base->plat_data->llis_per_log);
1597
1598
1599         } else {
1600                 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1601                         dev_err(&d40c->chan.dev->device,
1602                                 "[%s] Out of memory\n", __func__);
1603                         goto err;
1604                 }
1605
1606                 res = d40_phy_sg_to_lli(sgl_src,
1607                                         sgl_len,
1608                                         0,
1609                                         d40d->lli_phy.src,
1610                                         d40d->lli_phy.src_addr,
1611                                         d40c->src_def_cfg,
1612                                         d40c->dma_cfg.src_info.data_width,
1613                                         d40c->dma_cfg.src_info.psize);
1614
1615                 if (res < 0)
1616                         goto err;
1617
1618                 res = d40_phy_sg_to_lli(sgl_dst,
1619                                         sgl_len,
1620                                         0,
1621                                         d40d->lli_phy.dst,
1622                                         d40d->lli_phy.dst_addr,
1623                                         d40c->dst_def_cfg,
1624                                         d40c->dma_cfg.dst_info.data_width,
1625                                         d40c->dma_cfg.dst_info.psize);
1626
1627                 if (res < 0)
1628                         goto err;
1629
1630                 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1631                                       d40d->lli_pool.size, DMA_TO_DEVICE);
1632         }
1633
1634         dma_async_tx_descriptor_init(&d40d->txd, chan);
1635
1636         d40d->txd.tx_submit = d40_tx_submit;
1637
1638         spin_unlock_irqrestore(&d40c->lock, flags);
1639
1640         return &d40d->txd;
1641 err:
1642         spin_unlock_irqrestore(&d40c->lock, flags);
1643         return NULL;
1644 }
1645 EXPORT_SYMBOL(stedma40_memcpy_sg);
1646
1647 bool stedma40_filter(struct dma_chan *chan, void *data)
1648 {
1649         struct stedma40_chan_cfg *info = data;
1650         struct d40_chan *d40c =
1651                 container_of(chan, struct d40_chan, chan);
1652         int err;
1653
1654         if (data) {
1655                 err = d40_validate_conf(d40c, info);
1656                 if (!err)
1657                         d40c->dma_cfg = *info;
1658         } else
1659                 err = d40_config_memcpy(d40c);
1660
1661         return err == 0;
1662 }
1663 EXPORT_SYMBOL(stedma40_filter);
1664
1665 /* DMA ENGINE functions */
1666 static int d40_alloc_chan_resources(struct dma_chan *chan)
1667 {
1668         int err;
1669         unsigned long flags;
1670         struct d40_chan *d40c =
1671                 container_of(chan, struct d40_chan, chan);
1672         bool is_free_phy;
1673         spin_lock_irqsave(&d40c->lock, flags);
1674
1675         d40c->completed = chan->cookie = 1;
1676
1677         /*
1678          * If no dma configuration is set (channel_type == 0)
1679          * use default configuration (memcpy)
1680          */
1681         if (d40c->dma_cfg.channel_type == 0) {
1682                 err = d40_config_memcpy(d40c);
1683                 if (err) {
1684                         dev_err(&d40c->chan.dev->device,
1685                                 "[%s] Failed to configure memcpy channel\n",
1686                                 __func__);
1687                         goto fail;
1688                 }
1689         }
1690         is_free_phy = (d40c->phy_chan == NULL);
1691
1692         err = d40_allocate_channel(d40c);
1693         if (err) {
1694                 dev_err(&d40c->chan.dev->device,
1695                         "[%s] Failed to allocate channel\n", __func__);
1696                 goto fail;
1697         }
1698
1699         /* Fill in basic CFG register values */
1700         d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1701                     &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
1702
1703         if (d40c->log_num != D40_PHY_CHAN) {
1704                 d40_log_cfg(&d40c->dma_cfg,
1705                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1706
1707                 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1708                         d40c->lcpa = d40c->base->lcpa_base +
1709                           d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1710                 else
1711                         d40c->lcpa = d40c->base->lcpa_base +
1712                           d40c->dma_cfg.dst_dev_type *
1713                           D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1714         }
1715
1716         /*
1717          * Only write channel configuration to the DMA if the physical
1718          * resource is free. In case of multiple logical channels
1719          * on the same physical resource, only the first write is necessary.
1720          */
1721         if (is_free_phy)
1722                 d40_config_write(d40c);
1723 fail:
1724         spin_unlock_irqrestore(&d40c->lock, flags);
1725         return err;
1726 }
1727
1728 static void d40_free_chan_resources(struct dma_chan *chan)
1729 {
1730         struct d40_chan *d40c =
1731                 container_of(chan, struct d40_chan, chan);
1732         int err;
1733         unsigned long flags;
1734
1735         if (d40c->phy_chan == NULL) {
1736                 dev_err(&d40c->chan.dev->device,
1737                         "[%s] Cannot free unallocated channel\n", __func__);
1738                 return;
1739         }
1740
1741
1742         spin_lock_irqsave(&d40c->lock, flags);
1743
1744         err = d40_free_dma(d40c);
1745
1746         if (err)
1747                 dev_err(&d40c->chan.dev->device,
1748                         "[%s] Failed to free channel\n", __func__);
1749         spin_unlock_irqrestore(&d40c->lock, flags);
1750 }
1751
1752 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1753                                                        dma_addr_t dst,
1754                                                        dma_addr_t src,
1755                                                        size_t size,
1756                                                        unsigned long dma_flags)
1757 {
1758         struct d40_desc *d40d;
1759         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1760                                              chan);
1761         unsigned long flags;
1762         int err = 0;
1763
1764         if (d40c->phy_chan == NULL) {
1765                 dev_err(&d40c->chan.dev->device,
1766                         "[%s] Channel is not allocated.\n", __func__);
1767                 return ERR_PTR(-EINVAL);
1768         }
1769
1770         spin_lock_irqsave(&d40c->lock, flags);
1771         d40d = d40_desc_get(d40c);
1772
1773         if (d40d == NULL) {
1774                 dev_err(&d40c->chan.dev->device,
1775                         "[%s] Descriptor is NULL\n", __func__);
1776                 goto err;
1777         }
1778
1779         d40d->txd.flags = dma_flags;
1780
1781         dma_async_tx_descriptor_init(&d40d->txd, chan);
1782
1783         d40d->txd.tx_submit = d40_tx_submit;
1784
1785         if (d40c->log_num != D40_PHY_CHAN) {
1786
1787                 if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
1788                         dev_err(&d40c->chan.dev->device,
1789                                 "[%s] Out of memory\n", __func__);
1790                         goto err;
1791                 }
1792                 d40d->lli_len = 1;
1793                 d40d->lli_tx_len = 1;
1794
1795                 d40_log_fill_lli(d40d->lli_log.src,
1796                                  src,
1797                                  size,
1798                                  0,
1799                                  d40c->log_def.lcsp1,
1800                                  d40c->dma_cfg.src_info.data_width,
1801                                  false, true);
1802
1803                 d40_log_fill_lli(d40d->lli_log.dst,
1804                                  dst,
1805                                  size,
1806                                  0,
1807                                  d40c->log_def.lcsp3,
1808                                  d40c->dma_cfg.dst_info.data_width,
1809                                  true, true);
1810
1811         } else {
1812
1813                 if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
1814                         dev_err(&d40c->chan.dev->device,
1815                                 "[%s] Out of memory\n", __func__);
1816                         goto err;
1817                 }
1818
1819                 err = d40_phy_fill_lli(d40d->lli_phy.src,
1820                                        src,
1821                                        size,
1822                                        d40c->dma_cfg.src_info.psize,
1823                                        0,
1824                                        d40c->src_def_cfg,
1825                                        true,
1826                                        d40c->dma_cfg.src_info.data_width,
1827                                        false);
1828                 if (err)
1829                         goto err_fill_lli;
1830
1831                 err = d40_phy_fill_lli(d40d->lli_phy.dst,
1832                                        dst,
1833                                        size,
1834                                        d40c->dma_cfg.dst_info.psize,
1835                                        0,
1836                                        d40c->dst_def_cfg,
1837                                        true,
1838                                        d40c->dma_cfg.dst_info.data_width,
1839                                        false);
1840
1841                 if (err)
1842                         goto err_fill_lli;
1843
1844                 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1845                                       d40d->lli_pool.size, DMA_TO_DEVICE);
1846         }
1847
1848         spin_unlock_irqrestore(&d40c->lock, flags);
1849         return &d40d->txd;
1850
1851 err_fill_lli:
1852         dev_err(&d40c->chan.dev->device,
1853                 "[%s] Failed filling in PHY LLI\n", __func__);
1854         d40_pool_lli_free(d40d);
1855 err:
1856         spin_unlock_irqrestore(&d40c->lock, flags);
1857         return NULL;
1858 }
1859
1860 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1861                                  struct d40_chan *d40c,
1862                                  struct scatterlist *sgl,
1863                                  unsigned int sg_len,
1864                                  enum dma_data_direction direction,
1865                                  unsigned long dma_flags)
1866 {
1867         dma_addr_t dev_addr = 0;
1868         int total_size;
1869
1870         if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
1871                 dev_err(&d40c->chan.dev->device,
1872                         "[%s] Out of memory\n", __func__);
1873                 return -ENOMEM;
1874         }
1875
1876         d40d->lli_len = sg_len;
1877         if (d40d->lli_len <= d40c->base->plat_data->llis_per_log)
1878                 d40d->lli_tx_len = d40d->lli_len;
1879         else
1880                 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1881
1882         if (sg_len > 1)
1883                 /*
1884                  * Check if there is space available in lcla.
1885                  * If not, split list into 1-length and run only
1886                  * in lcpa space.
1887                  */
1888                 if (d40_lcla_id_get(d40c) != 0)
1889                         d40d->lli_tx_len = 1;
1890
1891         if (direction == DMA_FROM_DEVICE)
1892                 if (d40c->runtime_addr)
1893                         dev_addr = d40c->runtime_addr;
1894                 else
1895                         dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1896         else if (direction == DMA_TO_DEVICE)
1897                 if (d40c->runtime_addr)
1898                         dev_addr = d40c->runtime_addr;
1899                 else
1900                         dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1901
1902         else
1903                 return -EINVAL;
1904
1905         total_size = d40_log_sg_to_dev(&d40c->lcla,
1906                                        sgl, sg_len,
1907                                        &d40d->lli_log,
1908                                        &d40c->log_def,
1909                                        d40c->dma_cfg.src_info.data_width,
1910                                        d40c->dma_cfg.dst_info.data_width,
1911                                        direction,
1912                                        dev_addr, d40d->lli_tx_len,
1913                                        d40c->base->plat_data->llis_per_log);
1914
1915         if (total_size < 0)
1916                 return -EINVAL;
1917
1918         return 0;
1919 }
1920
1921 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
1922                                  struct d40_chan *d40c,
1923                                  struct scatterlist *sgl,
1924                                  unsigned int sgl_len,
1925                                  enum dma_data_direction direction,
1926                                  unsigned long dma_flags)
1927 {
1928         dma_addr_t src_dev_addr;
1929         dma_addr_t dst_dev_addr;
1930         int res;
1931
1932         if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1933                 dev_err(&d40c->chan.dev->device,
1934                         "[%s] Out of memory\n", __func__);
1935                 return -ENOMEM;
1936         }
1937
1938         d40d->lli_len = sgl_len;
1939         d40d->lli_tx_len = sgl_len;
1940
1941         if (direction == DMA_FROM_DEVICE) {
1942                 dst_dev_addr = 0;
1943                 if (d40c->runtime_addr)
1944                         src_dev_addr = d40c->runtime_addr;
1945                 else
1946                         src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1947         } else if (direction == DMA_TO_DEVICE) {
1948                 if (d40c->runtime_addr)
1949                         dst_dev_addr = d40c->runtime_addr;
1950                 else
1951                         dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1952                 src_dev_addr = 0;
1953         } else
1954                 return -EINVAL;
1955
1956         res = d40_phy_sg_to_lli(sgl,
1957                                 sgl_len,
1958                                 src_dev_addr,
1959                                 d40d->lli_phy.src,
1960                                 d40d->lli_phy.src_addr,
1961                                 d40c->src_def_cfg,
1962                                 d40c->dma_cfg.src_info.data_width,
1963                                 d40c->dma_cfg.src_info.psize);
1964         if (res < 0)
1965                 return res;
1966
1967         res = d40_phy_sg_to_lli(sgl,
1968                                 sgl_len,
1969                                 dst_dev_addr,
1970                                 d40d->lli_phy.dst,
1971                                 d40d->lli_phy.dst_addr,
1972                                 d40c->dst_def_cfg,
1973                                 d40c->dma_cfg.dst_info.data_width,
1974                                 d40c->dma_cfg.dst_info.psize);
1975         if (res < 0)
1976                 return res;
1977
1978         (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1979                               d40d->lli_pool.size, DMA_TO_DEVICE);
1980         return 0;
1981 }
1982
1983 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
1984                                                          struct scatterlist *sgl,
1985                                                          unsigned int sg_len,
1986                                                          enum dma_data_direction direction,
1987                                                          unsigned long dma_flags)
1988 {
1989         struct d40_desc *d40d;
1990         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1991                                              chan);
1992         unsigned long flags;
1993         int err;
1994
1995         if (d40c->phy_chan == NULL) {
1996                 dev_err(&d40c->chan.dev->device,
1997                         "[%s] Cannot prepare unallocated channel\n", __func__);
1998                 return ERR_PTR(-EINVAL);
1999         }
2000
2001         if (d40c->dma_cfg.pre_transfer)
2002                 d40c->dma_cfg.pre_transfer(chan,
2003                                            d40c->dma_cfg.pre_transfer_data,
2004                                            sg_dma_len(sgl));
2005
2006         spin_lock_irqsave(&d40c->lock, flags);
2007         d40d = d40_desc_get(d40c);
2008         spin_unlock_irqrestore(&d40c->lock, flags);
2009
2010         if (d40d == NULL)
2011                 return NULL;
2012
2013         if (d40c->log_num != D40_PHY_CHAN)
2014                 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2015                                             direction, dma_flags);
2016         else
2017                 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2018                                             direction, dma_flags);
2019         if (err) {
2020                 dev_err(&d40c->chan.dev->device,
2021                         "[%s] Failed to prepare %s slave sg job: %d\n",
2022                         __func__,
2023                         d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err);
2024                 return NULL;
2025         }
2026
2027         d40d->txd.flags = dma_flags;
2028
2029         dma_async_tx_descriptor_init(&d40d->txd, chan);
2030
2031         d40d->txd.tx_submit = d40_tx_submit;
2032
2033         return &d40d->txd;
2034 }
2035
2036 static enum dma_status d40_tx_status(struct dma_chan *chan,
2037                                      dma_cookie_t cookie,
2038                                      struct dma_tx_state *txstate)
2039 {
2040         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2041         dma_cookie_t last_used;
2042         dma_cookie_t last_complete;
2043         int ret;
2044
2045         if (d40c->phy_chan == NULL) {
2046                 dev_err(&d40c->chan.dev->device,
2047                         "[%s] Cannot read status of unallocated channel\n",
2048                         __func__);
2049                 return -EINVAL;
2050         }
2051
2052         last_complete = d40c->completed;
2053         last_used = chan->cookie;
2054
2055         if (d40_is_paused(d40c))
2056                 ret = DMA_PAUSED;
2057         else
2058                 ret = dma_async_is_complete(cookie, last_complete, last_used);
2059
2060         dma_set_tx_state(txstate, last_complete, last_used,
2061                          stedma40_residue(chan));
2062
2063         return ret;
2064 }
2065
2066 static void d40_issue_pending(struct dma_chan *chan)
2067 {
2068         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2069         unsigned long flags;
2070
2071         if (d40c->phy_chan == NULL) {
2072                 dev_err(&d40c->chan.dev->device,
2073                         "[%s] Channel is not allocated!\n", __func__);
2074                 return;
2075         }
2076
2077         spin_lock_irqsave(&d40c->lock, flags);
2078
2079         /* Busy means that pending jobs are already being processed */
2080         if (!d40c->busy)
2081                 (void) d40_queue_start(d40c);
2082
2083         spin_unlock_irqrestore(&d40c->lock, flags);
2084 }
2085
2086 /* Runtime reconfiguration extension */
2087 static void d40_set_runtime_config(struct dma_chan *chan,
2088                                struct dma_slave_config *config)
2089 {
2090         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2091         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2092         enum dma_slave_buswidth config_addr_width;
2093         dma_addr_t config_addr;
2094         u32 config_maxburst;
2095         enum stedma40_periph_data_width addr_width;
2096         int psize;
2097
2098         if (config->direction == DMA_FROM_DEVICE) {
2099                 dma_addr_t dev_addr_rx =
2100                         d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2101
2102                 config_addr = config->src_addr;
2103                 if (dev_addr_rx)
2104                         dev_dbg(d40c->base->dev,
2105                                 "channel has a pre-wired RX address %08x "
2106                                 "overriding with %08x\n",
2107                                 dev_addr_rx, config_addr);
2108                 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2109                         dev_dbg(d40c->base->dev,
2110                                 "channel was not configured for peripheral "
2111                                 "to memory transfer (%d) overriding\n",
2112                                 cfg->dir);
2113                 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2114
2115                 config_addr_width = config->src_addr_width;
2116                 config_maxburst = config->src_maxburst;
2117
2118         } else if (config->direction == DMA_TO_DEVICE) {
2119                 dma_addr_t dev_addr_tx =
2120                         d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2121
2122                 config_addr = config->dst_addr;
2123                 if (dev_addr_tx)
2124                         dev_dbg(d40c->base->dev,
2125                                 "channel has a pre-wired TX address %08x "
2126                                 "overriding with %08x\n",
2127                                 dev_addr_tx, config_addr);
2128                 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2129                         dev_dbg(d40c->base->dev,
2130                                 "channel was not configured for memory "
2131                                 "to peripheral transfer (%d) overriding\n",
2132                                 cfg->dir);
2133                 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2134
2135                 config_addr_width = config->dst_addr_width;
2136                 config_maxburst = config->dst_maxburst;
2137
2138         } else {
2139                 dev_err(d40c->base->dev,
2140                         "unrecognized channel direction %d\n",
2141                         config->direction);
2142                 return;
2143         }
2144
2145         switch (config_addr_width) {
2146         case DMA_SLAVE_BUSWIDTH_1_BYTE:
2147                 addr_width = STEDMA40_BYTE_WIDTH;
2148                 break;
2149         case DMA_SLAVE_BUSWIDTH_2_BYTES:
2150                 addr_width = STEDMA40_HALFWORD_WIDTH;
2151                 break;
2152         case DMA_SLAVE_BUSWIDTH_4_BYTES:
2153                 addr_width = STEDMA40_WORD_WIDTH;
2154                 break;
2155         case DMA_SLAVE_BUSWIDTH_8_BYTES:
2156                 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2157                 break;
2158         default:
2159                 dev_err(d40c->base->dev,
2160                         "illegal peripheral address width "
2161                         "requested (%d)\n",
2162                         config->src_addr_width);
2163                 return;
2164         }
2165
2166         if (config_maxburst >= 16)
2167                 psize = STEDMA40_PSIZE_LOG_16;
2168         else if (config_maxburst >= 8)
2169                 psize = STEDMA40_PSIZE_LOG_8;
2170         else if (config_maxburst >= 4)
2171                 psize = STEDMA40_PSIZE_LOG_4;
2172         else
2173                 psize = STEDMA40_PSIZE_LOG_1;
2174
2175         /* Set up all the endpoint configs */
2176         cfg->src_info.data_width = addr_width;
2177         cfg->src_info.psize = psize;
2178         cfg->src_info.endianess = STEDMA40_LITTLE_ENDIAN;
2179         cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2180         cfg->dst_info.data_width = addr_width;
2181         cfg->dst_info.psize = psize;
2182         cfg->dst_info.endianess = STEDMA40_LITTLE_ENDIAN;
2183         cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2184
2185         /* These settings will take precedence later */
2186         d40c->runtime_addr = config_addr;
2187         d40c->runtime_direction = config->direction;
2188         dev_dbg(d40c->base->dev,
2189                 "configured channel %s for %s, data width %d, "
2190                 "maxburst %d bytes, LE, no flow control\n",
2191                 dma_chan_name(chan),
2192                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2193                 config_addr_width,
2194                 config_maxburst);
2195 }
2196
2197 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2198                        unsigned long arg)
2199 {
2200         unsigned long flags;
2201         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2202
2203         if (d40c->phy_chan == NULL) {
2204                 dev_err(&d40c->chan.dev->device,
2205                         "[%s] Channel is not allocated!\n", __func__);
2206                 return -EINVAL;
2207         }
2208
2209         switch (cmd) {
2210         case DMA_TERMINATE_ALL:
2211                 spin_lock_irqsave(&d40c->lock, flags);
2212                 d40_term_all(d40c);
2213                 spin_unlock_irqrestore(&d40c->lock, flags);
2214                 return 0;
2215         case DMA_PAUSE:
2216                 return d40_pause(chan);
2217         case DMA_RESUME:
2218                 return d40_resume(chan);
2219         case DMA_SLAVE_CONFIG:
2220                 d40_set_runtime_config(chan,
2221                         (struct dma_slave_config *) arg);
2222                 return 0;
2223         default:
2224                 break;
2225         }
2226
2227         /* Other commands are unimplemented */
2228         return -ENXIO;
2229 }
2230
2231 /* Initialization functions */
2232
2233 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2234                                  struct d40_chan *chans, int offset,
2235                                  int num_chans)
2236 {
2237         int i = 0;
2238         struct d40_chan *d40c;
2239
2240         INIT_LIST_HEAD(&dma->channels);
2241
2242         for (i = offset; i < offset + num_chans; i++) {
2243                 d40c = &chans[i];
2244                 d40c->base = base;
2245                 d40c->chan.device = dma;
2246
2247                 /* Invalidate lcla element */
2248                 d40c->lcla.src_id = -1;
2249                 d40c->lcla.dst_id = -1;
2250
2251                 spin_lock_init(&d40c->lock);
2252
2253                 d40c->log_num = D40_PHY_CHAN;
2254
2255                 INIT_LIST_HEAD(&d40c->active);
2256                 INIT_LIST_HEAD(&d40c->queue);
2257                 INIT_LIST_HEAD(&d40c->client);
2258
2259                 tasklet_init(&d40c->tasklet, dma_tasklet,
2260                              (unsigned long) d40c);
2261
2262                 list_add_tail(&d40c->chan.device_node,
2263                               &dma->channels);
2264         }
2265 }
2266
2267 static int __init d40_dmaengine_init(struct d40_base *base,
2268                                      int num_reserved_chans)
2269 {
2270         int err ;
2271
2272         d40_chan_init(base, &base->dma_slave, base->log_chans,
2273                       0, base->num_log_chans);
2274
2275         dma_cap_zero(base->dma_slave.cap_mask);
2276         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2277
2278         base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2279         base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2280         base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2281         base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2282         base->dma_slave.device_tx_status = d40_tx_status;
2283         base->dma_slave.device_issue_pending = d40_issue_pending;
2284         base->dma_slave.device_control = d40_control;
2285         base->dma_slave.dev = base->dev;
2286
2287         err = dma_async_device_register(&base->dma_slave);
2288
2289         if (err) {
2290                 dev_err(base->dev,
2291                         "[%s] Failed to register slave channels\n",
2292                         __func__);
2293                 goto failure1;
2294         }
2295
2296         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2297                       base->num_log_chans, base->plat_data->memcpy_len);
2298
2299         dma_cap_zero(base->dma_memcpy.cap_mask);
2300         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2301
2302         base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2303         base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2304         base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2305         base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2306         base->dma_memcpy.device_tx_status = d40_tx_status;
2307         base->dma_memcpy.device_issue_pending = d40_issue_pending;
2308         base->dma_memcpy.device_control = d40_control;
2309         base->dma_memcpy.dev = base->dev;
2310         /*
2311          * This controller can only access address at even
2312          * 32bit boundaries, i.e. 2^2
2313          */
2314         base->dma_memcpy.copy_align = 2;
2315
2316         err = dma_async_device_register(&base->dma_memcpy);
2317
2318         if (err) {
2319                 dev_err(base->dev,
2320                         "[%s] Failed to regsiter memcpy only channels\n",
2321                         __func__);
2322                 goto failure2;
2323         }
2324
2325         d40_chan_init(base, &base->dma_both, base->phy_chans,
2326                       0, num_reserved_chans);
2327
2328         dma_cap_zero(base->dma_both.cap_mask);
2329         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2330         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2331
2332         base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2333         base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2334         base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2335         base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2336         base->dma_both.device_tx_status = d40_tx_status;
2337         base->dma_both.device_issue_pending = d40_issue_pending;
2338         base->dma_both.device_control = d40_control;
2339         base->dma_both.dev = base->dev;
2340         base->dma_both.copy_align = 2;
2341         err = dma_async_device_register(&base->dma_both);
2342
2343         if (err) {
2344                 dev_err(base->dev,
2345                         "[%s] Failed to register logical and physical capable channels\n",
2346                         __func__);
2347                 goto failure3;
2348         }
2349         return 0;
2350 failure3:
2351         dma_async_device_unregister(&base->dma_memcpy);
2352 failure2:
2353         dma_async_device_unregister(&base->dma_slave);
2354 failure1:
2355         return err;
2356 }
2357
2358 /* Initialization functions. */
2359
2360 static int __init d40_phy_res_init(struct d40_base *base)
2361 {
2362         int i;
2363         int num_phy_chans_avail = 0;
2364         u32 val[2];
2365         int odd_even_bit = -2;
2366
2367         val[0] = readl(base->virtbase + D40_DREG_PRSME);
2368         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2369
2370         for (i = 0; i < base->num_phy_chans; i++) {
2371                 base->phy_res[i].num = i;
2372                 odd_even_bit += 2 * ((i % 2) == 0);
2373                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2374                         /* Mark security only channels as occupied */
2375                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2376                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2377                 } else {
2378                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2379                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2380                         num_phy_chans_avail++;
2381                 }
2382                 spin_lock_init(&base->phy_res[i].lock);
2383         }
2384
2385         /* Mark disabled channels as occupied */
2386         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2387                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2388                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2389                         num_phy_chans_avail--;
2390         }
2391
2392         dev_info(base->dev, "%d of %d physical DMA channels available\n",
2393                  num_phy_chans_avail, base->num_phy_chans);
2394
2395         /* Verify settings extended vs standard */
2396         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2397
2398         for (i = 0; i < base->num_phy_chans; i++) {
2399
2400                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2401                     (val[0] & 0x3) != 1)
2402                         dev_info(base->dev,
2403                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
2404                                  __func__, i, val[0] & 0x3);
2405
2406                 val[0] = val[0] >> 2;
2407         }
2408
2409         return num_phy_chans_avail;
2410 }
2411
2412 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2413 {
2414         static const struct d40_reg_val dma_id_regs[] = {
2415                 /* Peripheral Id */
2416                 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2417                 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2418                 /*
2419                  * D40_DREG_PERIPHID2 Depends on HW revision:
2420                  *  MOP500/HREF ED has 0x0008,
2421                  *  ? has 0x0018,
2422                  *  HREF V1 has 0x0028
2423                  */
2424                 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2425
2426                 /* PCell Id */
2427                 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2428                 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2429                 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2430                 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2431         };
2432         struct stedma40_platform_data *plat_data;
2433         struct clk *clk = NULL;
2434         void __iomem *virtbase = NULL;
2435         struct resource *res = NULL;
2436         struct d40_base *base = NULL;
2437         int num_log_chans = 0;
2438         int num_phy_chans;
2439         int i;
2440         u32 val;
2441         u32 rev;
2442
2443         clk = clk_get(&pdev->dev, NULL);
2444
2445         if (IS_ERR(clk)) {
2446                 dev_err(&pdev->dev, "[%s] No matching clock found\n",
2447                         __func__);
2448                 goto failure;
2449         }
2450
2451         clk_enable(clk);
2452
2453         /* Get IO for DMAC base address */
2454         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2455         if (!res)
2456                 goto failure;
2457
2458         if (request_mem_region(res->start, resource_size(res),
2459                                D40_NAME " I/O base") == NULL)
2460                 goto failure;
2461
2462         virtbase = ioremap(res->start, resource_size(res));
2463         if (!virtbase)
2464                 goto failure;
2465
2466         /* HW version check */
2467         for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2468                 if (dma_id_regs[i].val !=
2469                     readl(virtbase + dma_id_regs[i].reg)) {
2470                         dev_err(&pdev->dev,
2471                                 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2472                                 __func__,
2473                                 dma_id_regs[i].val,
2474                                 dma_id_regs[i].reg,
2475                                 readl(virtbase + dma_id_regs[i].reg));
2476                         goto failure;
2477                 }
2478         }
2479
2480         /* Get silicon revision and designer */
2481         val = readl(virtbase + D40_DREG_PERIPHID2);
2482
2483         if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2484             D40_HW_DESIGNER) {
2485                 dev_err(&pdev->dev,
2486                         "[%s] Unknown designer! Got %x wanted %x\n",
2487                         __func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK,
2488                         D40_HW_DESIGNER);
2489                 goto failure;
2490         }
2491
2492         rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2493                 D40_DREG_PERIPHID2_REV_POS;
2494
2495         /* The number of physical channels on this HW */
2496         num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2497
2498         dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2499                  rev, res->start);
2500
2501         plat_data = pdev->dev.platform_data;
2502
2503         /* Count the number of logical channels in use */
2504         for (i = 0; i < plat_data->dev_len; i++)
2505                 if (plat_data->dev_rx[i] != 0)
2506                         num_log_chans++;
2507
2508         for (i = 0; i < plat_data->dev_len; i++)
2509                 if (plat_data->dev_tx[i] != 0)
2510                         num_log_chans++;
2511
2512         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2513                        (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2514                        sizeof(struct d40_chan), GFP_KERNEL);
2515
2516         if (base == NULL) {
2517                 dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
2518                 goto failure;
2519         }
2520
2521         base->rev = rev;
2522         base->clk = clk;
2523         base->num_phy_chans = num_phy_chans;
2524         base->num_log_chans = num_log_chans;
2525         base->phy_start = res->start;
2526         base->phy_size = resource_size(res);
2527         base->virtbase = virtbase;
2528         base->plat_data = plat_data;
2529         base->dev = &pdev->dev;
2530         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2531         base->log_chans = &base->phy_chans[num_phy_chans];
2532
2533         base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2534                                 GFP_KERNEL);
2535         if (!base->phy_res)
2536                 goto failure;
2537
2538         base->lookup_phy_chans = kzalloc(num_phy_chans *
2539                                          sizeof(struct d40_chan *),
2540                                          GFP_KERNEL);
2541         if (!base->lookup_phy_chans)
2542                 goto failure;
2543
2544         if (num_log_chans + plat_data->memcpy_len) {
2545                 /*
2546                  * The max number of logical channels are event lines for all
2547                  * src devices and dst devices
2548                  */
2549                 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2550                                                  sizeof(struct d40_chan *),
2551                                                  GFP_KERNEL);
2552                 if (!base->lookup_log_chans)
2553                         goto failure;
2554         }
2555         base->lcla_pool.alloc_map = kzalloc(num_phy_chans * sizeof(u32),
2556                                             GFP_KERNEL);
2557         if (!base->lcla_pool.alloc_map)
2558                 goto failure;
2559
2560         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2561                                             0, SLAB_HWCACHE_ALIGN,
2562                                             NULL);
2563         if (base->desc_slab == NULL)
2564                 goto failure;
2565
2566         return base;
2567
2568 failure:
2569         if (clk) {
2570                 clk_disable(clk);
2571                 clk_put(clk);
2572         }
2573         if (virtbase)
2574                 iounmap(virtbase);
2575         if (res)
2576                 release_mem_region(res->start,
2577                                    resource_size(res));
2578         if (virtbase)
2579                 iounmap(virtbase);
2580
2581         if (base) {
2582                 kfree(base->lcla_pool.alloc_map);
2583                 kfree(base->lookup_log_chans);
2584                 kfree(base->lookup_phy_chans);
2585                 kfree(base->phy_res);
2586                 kfree(base);
2587         }
2588
2589         return NULL;
2590 }
2591
2592 static void __init d40_hw_init(struct d40_base *base)
2593 {
2594
2595         static const struct d40_reg_val dma_init_reg[] = {
2596                 /* Clock every part of the DMA block from start */
2597                 { .reg = D40_DREG_GCC,    .val = 0x0000ff01},
2598
2599                 /* Interrupts on all logical channels */
2600                 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2601                 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2602                 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2603                 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2604                 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2605                 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2606                 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2607                 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2608                 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2609                 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2610                 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2611                 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2612         };
2613         int i;
2614         u32 prmseo[2] = {0, 0};
2615         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2616         u32 pcmis = 0;
2617         u32 pcicr = 0;
2618
2619         for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2620                 writel(dma_init_reg[i].val,
2621                        base->virtbase + dma_init_reg[i].reg);
2622
2623         /* Configure all our dma channels to default settings */
2624         for (i = 0; i < base->num_phy_chans; i++) {
2625
2626                 activeo[i % 2] = activeo[i % 2] << 2;
2627
2628                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2629                     == D40_ALLOC_PHY) {
2630                         activeo[i % 2] |= 3;
2631                         continue;
2632                 }
2633
2634                 /* Enable interrupt # */
2635                 pcmis = (pcmis << 1) | 1;
2636
2637                 /* Clear interrupt # */
2638                 pcicr = (pcicr << 1) | 1;
2639
2640                 /* Set channel to physical mode */
2641                 prmseo[i % 2] = prmseo[i % 2] << 2;
2642                 prmseo[i % 2] |= 1;
2643
2644         }
2645
2646         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2647         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2648         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2649         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2650
2651         /* Write which interrupt to enable */
2652         writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2653
2654         /* Write which interrupt to clear */
2655         writel(pcicr, base->virtbase + D40_DREG_PCICR);
2656
2657 }
2658
2659 static int __init d40_lcla_allocate(struct d40_base *base)
2660 {
2661         unsigned long *page_list;
2662         int i, j;
2663         int ret = 0;
2664
2665         /*
2666          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2667          * To full fill this hardware requirement without wasting 256 kb
2668          * we allocate pages until we get an aligned one.
2669          */
2670         page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2671                             GFP_KERNEL);
2672
2673         if (!page_list) {
2674                 ret = -ENOMEM;
2675                 goto failure;
2676         }
2677
2678         /* Calculating how many pages that are required */
2679         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2680
2681         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2682                 page_list[i] = __get_free_pages(GFP_KERNEL,
2683                                                 base->lcla_pool.pages);
2684                 if (!page_list[i]) {
2685
2686                         dev_err(base->dev,
2687                                 "[%s] Failed to allocate %d pages.\n",
2688                                 __func__, base->lcla_pool.pages);
2689
2690                         for (j = 0; j < i; j++)
2691                                 free_pages(page_list[j], base->lcla_pool.pages);
2692                         goto failure;
2693                 }
2694
2695                 if ((virt_to_phys((void *)page_list[i]) &
2696                      (LCLA_ALIGNMENT - 1)) == 0)
2697                         break;
2698         }
2699
2700         for (j = 0; j < i; j++)
2701                 free_pages(page_list[j], base->lcla_pool.pages);
2702
2703         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2704                 base->lcla_pool.base = (void *)page_list[i];
2705         } else {
2706                 /* After many attempts, no succees with finding the correct
2707                  * alignment try with allocating a big buffer */
2708                 dev_warn(base->dev,
2709                          "[%s] Failed to get %d pages @ 18 bit align.\n",
2710                          __func__, base->lcla_pool.pages);
2711                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2712                                                          base->num_phy_chans +
2713                                                          LCLA_ALIGNMENT,
2714                                                          GFP_KERNEL);
2715                 if (!base->lcla_pool.base_unaligned) {
2716                         ret = -ENOMEM;
2717                         goto failure;
2718                 }
2719
2720                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2721                                                  LCLA_ALIGNMENT);
2722         }
2723
2724         writel(virt_to_phys(base->lcla_pool.base),
2725                base->virtbase + D40_DREG_LCLA);
2726 failure:
2727         kfree(page_list);
2728         return ret;
2729 }
2730
2731 static int __init d40_probe(struct platform_device *pdev)
2732 {
2733         int err;
2734         int ret = -ENOENT;
2735         struct d40_base *base;
2736         struct resource *res = NULL;
2737         int num_reserved_chans;
2738         u32 val;
2739
2740         base = d40_hw_detect_init(pdev);
2741
2742         if (!base)
2743                 goto failure;
2744
2745         num_reserved_chans = d40_phy_res_init(base);
2746
2747         platform_set_drvdata(pdev, base);
2748
2749         spin_lock_init(&base->interrupt_lock);
2750         spin_lock_init(&base->execmd_lock);
2751
2752         /* Get IO for logical channel parameter address */
2753         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2754         if (!res) {
2755                 ret = -ENOENT;
2756                 dev_err(&pdev->dev,
2757                         "[%s] No \"lcpa\" memory resource\n",
2758                         __func__);
2759                 goto failure;
2760         }
2761         base->lcpa_size = resource_size(res);
2762         base->phy_lcpa = res->start;
2763
2764         if (request_mem_region(res->start, resource_size(res),
2765                                D40_NAME " I/O lcpa") == NULL) {
2766                 ret = -EBUSY;
2767                 dev_err(&pdev->dev,
2768                         "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2769                         __func__, res->start, res->end);
2770                 goto failure;
2771         }
2772
2773         /* We make use of ESRAM memory for this. */
2774         val = readl(base->virtbase + D40_DREG_LCPA);
2775         if (res->start != val && val != 0) {
2776                 dev_warn(&pdev->dev,
2777                          "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2778                          __func__, val, res->start);
2779         } else
2780                 writel(res->start, base->virtbase + D40_DREG_LCPA);
2781
2782         base->lcpa_base = ioremap(res->start, resource_size(res));
2783         if (!base->lcpa_base) {
2784                 ret = -ENOMEM;
2785                 dev_err(&pdev->dev,
2786                         "[%s] Failed to ioremap LCPA region\n",
2787                         __func__);
2788                 goto failure;
2789         }
2790
2791         ret = d40_lcla_allocate(base);
2792         if (ret) {
2793                 dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
2794                         __func__);
2795                 goto failure;
2796         }
2797
2798         spin_lock_init(&base->lcla_pool.lock);
2799
2800         base->lcla_pool.num_blocks = base->num_phy_chans;
2801
2802         base->irq = platform_get_irq(pdev, 0);
2803
2804         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2805
2806         if (ret) {
2807                 dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
2808                 goto failure;
2809         }
2810
2811         err = d40_dmaengine_init(base, num_reserved_chans);
2812         if (err)
2813                 goto failure;
2814
2815         d40_hw_init(base);
2816
2817         dev_info(base->dev, "initialized\n");
2818         return 0;
2819
2820 failure:
2821         if (base) {
2822                 if (base->desc_slab)
2823                         kmem_cache_destroy(base->desc_slab);
2824                 if (base->virtbase)
2825                         iounmap(base->virtbase);
2826                 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2827                         free_pages((unsigned long)base->lcla_pool.base,
2828                                    base->lcla_pool.pages);
2829                 if (base->lcla_pool.base_unaligned)
2830                         kfree(base->lcla_pool.base_unaligned);
2831                 if (base->phy_lcpa)
2832                         release_mem_region(base->phy_lcpa,
2833                                            base->lcpa_size);
2834                 if (base->phy_start)
2835                         release_mem_region(base->phy_start,
2836                                            base->phy_size);
2837                 if (base->clk) {
2838                         clk_disable(base->clk);
2839                         clk_put(base->clk);
2840                 }
2841
2842                 kfree(base->lcla_pool.alloc_map);
2843                 kfree(base->lookup_log_chans);
2844                 kfree(base->lookup_phy_chans);
2845                 kfree(base->phy_res);
2846                 kfree(base);
2847         }
2848
2849         dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
2850         return ret;
2851 }
2852
2853 static struct platform_driver d40_driver = {
2854         .driver = {
2855                 .owner = THIS_MODULE,
2856                 .name  = D40_NAME,
2857         },
2858 };
2859
2860 int __init stedma40_init(void)
2861 {
2862         return platform_driver_probe(&d40_driver, d40_probe);
2863 }
2864 arch_initcall(stedma40_init);