drivers/dma/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * - DMA of SuperH does not have Hardware DMA chain mode.
  16  * - MAX DMA size is 16MB.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28
  29 #include <asm/dmaengine.h>
  30
  31 #include "shdma.h"
  32
  33 /* DMA descriptor control */
  34 enum sh_dmae_desc_status {
  35         DESC_IDLE,
  36         DESC_PREPARED,
  37         DESC_SUBMITTED,
  38         DESC_COMPLETED, /* completed, have to call callback */
  39         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
  40 };
  41
  42 #define NR_DESCS_PER_CHANNEL 32
  43 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  44 #define LOG2_DEFAULT_XFER_SIZE  2
  45
  46 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
  47 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
  48
  49 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
  50
  51 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  52 {
  53         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  54 }
  55
  56 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  57 {
  58         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  59 }
  60
  61 static u16 dmaor_read(struct sh_dmae_device *shdev)
  62 {
  63         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
  64 }
  65
  66 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  67 {
  68         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
  69 }
  70
  71 /*
  72  * Reset DMA controller
  73  *
  74  * SH7780 has two DMAOR register
  75  */
  76 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
  77 {
  78         unsigned short dmaor = dmaor_read(shdev);
  79
  80         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
  81 }
  82
  83 static int sh_dmae_rst(struct sh_dmae_device *shdev)
  84 {
  85         unsigned short dmaor;
  86
  87         sh_dmae_ctl_stop(shdev);
  88         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
  89
  90         dmaor_write(shdev, dmaor);
  91         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
  92                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
  93                 return -EINVAL;
  94         }
  95         return 0;
  96 }
  97
  98 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
  99 {
 100         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 101
 102         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 103                 return true; /* working */
 104
 105         return false; /* waiting */
 106 }
 107
 108 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 109 {
 110         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 111                                                 struct sh_dmae_device, common);
 112         struct sh_dmae_pdata *pdata = shdev->pdata;
 113         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 114                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 115
 116         if (cnt >= pdata->ts_shift_num)
 117                 cnt = 0;
 118
 119         return pdata->ts_shift[cnt];
 120 }
 121
 122 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 123 {
 124         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 125                                                 struct sh_dmae_device, common);
 126         struct sh_dmae_pdata *pdata = shdev->pdata;
 127         int i;
 128
 129         for (i = 0; i < pdata->ts_shift_num; i++)
 130                 if (pdata->ts_shift[i] == l2size)
 131                         break;
 132
 133         if (i == pdata->ts_shift_num)
 134                 i = 0;
 135
 136         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 137                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 138 }
 139
 140 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 141 {
 142         sh_dmae_writel(sh_chan, hw->sar, SAR);
 143         sh_dmae_writel(sh_chan, hw->dar, DAR);
 144         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 145 }
 146
 147 static void dmae_start(struct sh_dmae_chan *sh_chan)
 148 {
 149         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 150
 151         chcr |= CHCR_DE | CHCR_IE;
 152         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
 153 }
 154
 155 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 156 {
 157         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 158
 159         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 160         sh_dmae_writel(sh_chan, chcr, CHCR);
 161 }
 162
 163 static void dmae_init(struct sh_dmae_chan *sh_chan)
 164 {
 165         /*
 166          * Default configuration for dual address memory-memory transfer.
 167          * 0x400 represents auto-request.
 168          */
 169         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 170                                                    LOG2_DEFAULT_XFER_SIZE);
 171         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 172         sh_dmae_writel(sh_chan, chcr, CHCR);
 173 }
 174
 175 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 176 {
 177         /* When DMA was working, can not set data to CHCR */
 178         if (dmae_is_busy(sh_chan))
 179                 return -EBUSY;
 180
 181         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 182         sh_dmae_writel(sh_chan, val, CHCR);
 183
 184         return 0;
 185 }
 186
 187 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 188 {
 189         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 190                                                 struct sh_dmae_device, common);
 191         struct sh_dmae_pdata *pdata = shdev->pdata;
 192         struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
 193         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
 194         int shift = chan_pdata->dmars_bit;
 195
 196         if (dmae_is_busy(sh_chan))
 197                 return -EBUSY;
 198
 199         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 200                      addr);
 201
 202         return 0;
 203 }
 204
 205 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 206 {
 207         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
 208         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
 209         dma_async_tx_callback callback = tx->callback;
 210         dma_cookie_t cookie;
 211
 212         spin_lock_bh(&sh_chan->desc_lock);
 213
 214         cookie = sh_chan->common.cookie;
 215         cookie++;
 216         if (cookie < 0)
 217                 cookie = 1;
 218
 219         sh_chan->common.cookie = cookie;
 220         tx->cookie = cookie;
 221
 222         /* Mark all chunks of this descriptor as submitted, move to the queue */
 223         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
 224                 /*
 225                  * All chunks are on the global ld_free, so, we have to find
 226                  * the end of the chain ourselves
 227                  */
 228                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
 229                                       chunk->async_tx.cookie > 0 ||
 230                                       chunk->async_tx.cookie == -EBUSY ||
 231                                       &chunk->node == &sh_chan->ld_free))
 232                         break;
 233                 chunk->mark = DESC_SUBMITTED;
 234                 /* Callback goes to the last chunk */
 235                 chunk->async_tx.callback = NULL;
 236                 chunk->cookie = cookie;
 237                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
 238                 last = chunk;
 239         }
 240
 241         last->async_tx.callback = callback;
 242         last->async_tx.callback_param = tx->callback_param;
 243
 244         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
 245                 tx->cookie, &last->async_tx, sh_chan->id,
 246                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
 247
 248         spin_unlock_bh(&sh_chan->desc_lock);
 249
 250         return cookie;
 251 }
 252
 253 /* Called with desc_lock held */
 254 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
 255 {
 256         struct sh_desc *desc;
 257
 258         list_for_each_entry(desc, &sh_chan->ld_free, node)
 259                 if (desc->mark != DESC_PREPARED) {
 260                         BUG_ON(desc->mark != DESC_IDLE);
 261                         list_del(&desc->node);
 262                         return desc;
 263                 }
 264
 265         return NULL;
 266 }
 267
 268 static struct sh_dmae_slave_config *sh_dmae_find_slave(
 269         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
 270 {
 271         struct dma_device *dma_dev = sh_chan->common.device;
 272         struct sh_dmae_device *shdev = container_of(dma_dev,
 273                                         struct sh_dmae_device, common);
 274         struct sh_dmae_pdata *pdata = shdev->pdata;
 275         int i;
 276
 277         if (param->slave_id >= SHDMA_SLAVE_NUMBER)
 278                 return NULL;
 279
 280         for (i = 0; i < pdata->slave_num; i++)
 281                 if (pdata->slave[i].slave_id == param->slave_id)
 282                         return pdata->slave + i;
 283
 284         return NULL;
 285 }
 286
 287 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
 288 {
 289         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 290         struct sh_desc *desc;
 291         struct sh_dmae_slave *param = chan->private;
 292
 293         pm_runtime_get_sync(sh_chan->dev);
 294
 295         /*
 296          * This relies on the guarantee from dmaengine that alloc_chan_resources
 297          * never runs concurrently with itself or free_chan_resources.
 298          */
 299         if (param) {
 300                 struct sh_dmae_slave_config *cfg;
 301
 302                 cfg = sh_dmae_find_slave(sh_chan, param);
 303                 if (!cfg)
 304                         return -EINVAL;
 305
 306                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used))
 307                         return -EBUSY;
 308
 309                 param->config = cfg;
 310
 311                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 312                 dmae_set_chcr(sh_chan, cfg->chcr);
 313         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
 314                 dmae_init(sh_chan);
 315         }
 316
 317         spin_lock_bh(&sh_chan->desc_lock);
 318         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
 319                 spin_unlock_bh(&sh_chan->desc_lock);
 320                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
 321                 if (!desc) {
 322                         spin_lock_bh(&sh_chan->desc_lock);
 323                         break;
 324                 }
 325                 dma_async_tx_descriptor_init(&desc->async_tx,
 326                                         &sh_chan->common);
 327                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
 328                 desc->mark = DESC_IDLE;
 329
 330                 spin_lock_bh(&sh_chan->desc_lock);
 331                 list_add(&desc->node, &sh_chan->ld_free);
 332                 sh_chan->descs_allocated++;
 333         }
 334         spin_unlock_bh(&sh_chan->desc_lock);
 335
 336         if (!sh_chan->descs_allocated)
 337                 pm_runtime_put(sh_chan->dev);
 338
 339         return sh_chan->descs_allocated;
 340 }
 341
 342 /*
 343  * sh_dma_free_chan_resources - Free all resources of the channel.
 344  */
 345 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
 346 {
 347         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 348         struct sh_desc *desc, *_desc;
 349         LIST_HEAD(list);
 350         int descs = sh_chan->descs_allocated;
 351
 352         dmae_halt(sh_chan);
 353
 354         /* Prepared and not submitted descriptors can still be on the queue */
 355         if (!list_empty(&sh_chan->ld_queue))
 356                 sh_dmae_chan_ld_cleanup(sh_chan, true);
 357
 358         if (chan->private) {
 359                 /* The caller is holding dma_list_mutex */
 360                 struct sh_dmae_slave *param = chan->private;
 361                 clear_bit(param->slave_id, sh_dmae_slave_used);
 362         }
 363
 364         spin_lock_bh(&sh_chan->desc_lock);
 365
 366         list_splice_init(&sh_chan->ld_free, &list);
 367         sh_chan->descs_allocated = 0;
 368
 369         spin_unlock_bh(&sh_chan->desc_lock);
 370
 371         if (descs > 0)
 372                 pm_runtime_put(sh_chan->dev);
 373
 374         list_for_each_entry_safe(desc, _desc, &list, node)
 375                 kfree(desc);
 376 }
 377
 378 /**
 379  * sh_dmae_add_desc - get, set up and return one transfer descriptor
 380  * @sh_chan:    DMA channel
 381  * @flags:      DMA transfer flags
 382  * @dest:       destination DMA address, incremented when direction equals
 383  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
 384  * @src:        source DMA address, incremented when direction equals
 385  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
 386  * @len:        DMA transfer length
 387  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
 388  * @direction:  needed for slave DMA to decide which address to keep constant,
 389  *              equals DMA_BIDIRECTIONAL for MEMCPY
 390  * Returns 0 or an error
 391  * Locks: called with desc_lock held
 392  */
 393 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
 394         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
 395         struct sh_desc **first, enum dma_data_direction direction)
 396 {
 397         struct sh_desc *new;
 398         size_t copy_size;
 399
 400         if (!*len)
 401                 return NULL;
 402
 403         /* Allocate the link descriptor from the free list */
 404         new = sh_dmae_get_desc(sh_chan);
 405         if (!new) {
 406                 dev_err(sh_chan->dev, "No free link descriptor available\n");
 407                 return NULL;
 408         }
 409
 410         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
 411
 412         new->hw.sar = *src;
 413         new->hw.dar = *dest;
 414         new->hw.tcr = copy_size;
 415
 416         if (!*first) {
 417                 /* First desc */
 418                 new->async_tx.cookie = -EBUSY;
 419                 *first = new;
 420         } else {
 421                 /* Other desc - invisible to the user */
 422                 new->async_tx.cookie = -EINVAL;
 423         }
 424
 425         dev_dbg(sh_chan->dev,
 426                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
 427                 copy_size, *len, *src, *dest, &new->async_tx,
 428                 new->async_tx.cookie, sh_chan->xmit_shift);
 429
 430         new->mark = DESC_PREPARED;
 431         new->async_tx.flags = flags;
 432         new->direction = direction;
 433
 434         *len -= copy_size;
 435         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
 436                 *src += copy_size;
 437         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
 438                 *dest += copy_size;
 439
 440         return new;
 441 }
 442
 443 /*
 444  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
 445  *
 446  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
 447  * converted to scatter-gather to guarantee consistent locking and a correct
 448  * list manipulation. For slave DMA direction carries the usual meaning, and,
 449  * logically, the SG list is RAM and the addr variable contains slave address,
 450  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
 451  * and the SG list contains only one element and points at the source buffer.
 452  */
 453 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
 454         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
 455         enum dma_data_direction direction, unsigned long flags)
 456 {
 457         struct scatterlist *sg;
 458         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
 459         LIST_HEAD(tx_list);
 460         int chunks = 0;
 461         int i;
 462
 463         if (!sg_len)
 464                 return NULL;
 465
 466         for_each_sg(sgl, sg, sg_len, i)
 467                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
 468                         (SH_DMA_TCR_MAX + 1);
 469
 470         /* Have to lock the whole loop to protect against concurrent release */
 471         spin_lock_bh(&sh_chan->desc_lock);
 472
 473         /*
 474          * Chaining:
 475          * first descriptor is what user is dealing with in all API calls, its
 476          *      cookie is at first set to -EBUSY, at tx-submit to a positive
 477          *      number
 478          * if more than one chunk is needed further chunks have cookie = -EINVAL
 479          * the last chunk, if not equal to the first, has cookie = -ENOSPC
 480          * all chunks are linked onto the tx_list head with their .node heads
 481          *      only during this function, then they are immediately spliced
 482          *      back onto the free list in form of a chain
 483          */
 484         for_each_sg(sgl, sg, sg_len, i) {
 485                 dma_addr_t sg_addr = sg_dma_address(sg);
 486                 size_t len = sg_dma_len(sg);
 487
 488                 if (!len)
 489                         goto err_get_desc;
 490
 491                 do {
 492                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
 493                                 i, sg, len, (unsigned long long)sg_addr);
 494
 495                         if (direction == DMA_FROM_DEVICE)
 496                                 new = sh_dmae_add_desc(sh_chan, flags,
 497                                                 &sg_addr, addr, &len, &first,
 498                                                 direction);
 499                         else
 500                                 new = sh_dmae_add_desc(sh_chan, flags,
 501                                                 addr, &sg_addr, &len, &first,
 502                                                 direction);
 503                         if (!new)
 504                                 goto err_get_desc;
 505
 506                         new->chunks = chunks--;
 507                         list_add_tail(&new->node, &tx_list);
 508                 } while (len);
 509         }
 510
 511         if (new != first)
 512                 new->async_tx.cookie = -ENOSPC;
 513
 514         /* Put them back on the free list, so, they don't get lost */
 515         list_splice_tail(&tx_list, &sh_chan->ld_free);
 516
 517         spin_unlock_bh(&sh_chan->desc_lock);
 518
 519         return &first->async_tx;
 520
 521 err_get_desc:
 522         list_for_each_entry(new, &tx_list, node)
 523                 new->mark = DESC_IDLE;
 524         list_splice(&tx_list, &sh_chan->ld_free);
 525
 526         spin_unlock_bh(&sh_chan->desc_lock);
 527
 528         return NULL;
 529 }
 530
 531 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
 532         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 533         size_t len, unsigned long flags)
 534 {
 535         struct sh_dmae_chan *sh_chan;
 536         struct scatterlist sg;
 537
 538         if (!chan || !len)
 539                 return NULL;
 540
 541         chan->private = NULL;
 542
 543         sh_chan = to_sh_chan(chan);
 544
 545         sg_init_table(&sg, 1);
 546         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
 547                     offset_in_page(dma_src));
 548         sg_dma_address(&sg) = dma_src;
 549         sg_dma_len(&sg) = len;
 550
 551         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
 552                                flags);
 553 }
 554
 555 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
 556         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 557         enum dma_data_direction direction, unsigned long flags)
 558 {
 559         struct sh_dmae_slave *param;
 560         struct sh_dmae_chan *sh_chan;
 561
 562         if (!chan)
 563                 return NULL;
 564
 565         sh_chan = to_sh_chan(chan);
 566         param = chan->private;
 567
 568         /* Someone calling slave DMA on a public channel? */
 569         if (!param || !sg_len) {
 570                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
 571                          __func__, param, sg_len, param ? param->slave_id : -1);
 572                 return NULL;
 573         }
 574
 575         /*
 576          * if (param != NULL), this is a successfully requested slave channel,
 577          * therefore param->config != NULL too.
 578          */
 579         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &param->config->addr,
 580                                direction, flags);
 581 }
 582
 583 static void sh_dmae_terminate_all(struct dma_chan *chan)
 584 {
 585         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 586
 587         if (!chan)
 588                 return;
 589
 590         dmae_halt(sh_chan);
 591
 592         spin_lock_bh(&sh_chan->desc_lock);
 593         if (!list_empty(&sh_chan->ld_queue)) {
 594                 /* Record partial transfer */
 595                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
 596                                                   struct sh_desc, node);
 597                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
 598                         sh_chan->xmit_shift;
 599
 600         }
 601         spin_unlock_bh(&sh_chan->desc_lock);
 602
 603         sh_dmae_chan_ld_cleanup(sh_chan, true);
 604 }
 605
 606 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 607 {
 608         struct sh_desc *desc, *_desc;
 609         /* Is the "exposed" head of a chain acked? */
 610         bool head_acked = false;
 611         dma_cookie_t cookie = 0;
 612         dma_async_tx_callback callback = NULL;
 613         void *param = NULL;
 614
 615         spin_lock_bh(&sh_chan->desc_lock);
 616         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
 617                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 618
 619                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
 620                 BUG_ON(desc->mark != DESC_SUBMITTED &&
 621                        desc->mark != DESC_COMPLETED &&
 622                        desc->mark != DESC_WAITING);
 623
 624                 /*
 625                  * queue is ordered, and we use this loop to (1) clean up all
 626                  * completed descriptors, and to (2) update descriptor flags of
 627                  * any chunks in a (partially) completed chain
 628                  */
 629                 if (!all && desc->mark == DESC_SUBMITTED &&
 630                     desc->cookie != cookie)
 631                         break;
 632
 633                 if (tx->cookie > 0)
 634                         cookie = tx->cookie;
 635
 636                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
 637                         if (sh_chan->completed_cookie != desc->cookie - 1)
 638                                 dev_dbg(sh_chan->dev,
 639                                         "Completing cookie %d, expected %d\n",
 640                                         desc->cookie,
 641                                         sh_chan->completed_cookie + 1);
 642                         sh_chan->completed_cookie = desc->cookie;
 643                 }
 644
 645                 /* Call callback on the last chunk */
 646                 if (desc->mark == DESC_COMPLETED && tx->callback) {
 647                         desc->mark = DESC_WAITING;
 648                         callback = tx->callback;
 649                         param = tx->callback_param;
 650                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
 651                                 tx->cookie, tx, sh_chan->id);
 652                         BUG_ON(desc->chunks != 1);
 653                         break;
 654                 }
 655
 656                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
 657                         if (desc->mark == DESC_COMPLETED) {
 658                                 BUG_ON(tx->cookie < 0);
 659                                 desc->mark = DESC_WAITING;
 660                         }
 661                         head_acked = async_tx_test_ack(tx);
 662                 } else {
 663                         switch (desc->mark) {
 664                         case DESC_COMPLETED:
 665                                 desc->mark = DESC_WAITING;
 666                                 /* Fall through */
 667                         case DESC_WAITING:
 668                                 if (head_acked)
 669                                         async_tx_ack(&desc->async_tx);
 670                         }
 671                 }
 672
 673                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
 674                         tx, tx->cookie);
 675
 676                 if (((desc->mark == DESC_COMPLETED ||
 677                       desc->mark == DESC_WAITING) &&
 678                      async_tx_test_ack(&desc->async_tx)) || all) {
 679                         /* Remove from ld_queue list */
 680                         desc->mark = DESC_IDLE;
 681                         list_move(&desc->node, &sh_chan->ld_free);
 682                 }
 683         }
 684         spin_unlock_bh(&sh_chan->desc_lock);
 685
 686         if (callback)
 687                 callback(param);
 688
 689         return callback;
 690 }
 691
 692 /*
 693  * sh_chan_ld_cleanup - Clean up link descriptors
 694  *
 695  * This function cleans up the ld_queue of DMA channel.
 696  */
 697 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 698 {
 699         while (__ld_cleanup(sh_chan, all))
 700                 ;
 701 }
 702
 703 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
 704 {
 705         struct sh_desc *desc;
 706
 707         spin_lock_bh(&sh_chan->desc_lock);
 708         /* DMA work check */
 709         if (dmae_is_busy(sh_chan)) {
 710                 spin_unlock_bh(&sh_chan->desc_lock);
 711                 return;
 712         }
 713
 714         /* Find the first not transferred desciptor */
 715         list_for_each_entry(desc, &sh_chan->ld_queue, node)
 716                 if (desc->mark == DESC_SUBMITTED) {
 717                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
 718                                 desc->async_tx.cookie, sh_chan->id,
 719                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
 720                         /* Get the ld start address from ld_queue */
 721                         dmae_set_reg(sh_chan, &desc->hw);
 722                         dmae_start(sh_chan);
 723                         break;
 724                 }
 725
 726         spin_unlock_bh(&sh_chan->desc_lock);
 727 }
 728
 729 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
 730 {
 731         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 732         sh_chan_xfer_ld_queue(sh_chan);
 733 }
 734
 735 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
 736                                         dma_cookie_t cookie,
 737                                         dma_cookie_t *done,
 738                                         dma_cookie_t *used)
 739 {
 740         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 741         dma_cookie_t last_used;
 742         dma_cookie_t last_complete;
 743         enum dma_status status;
 744
 745         sh_dmae_chan_ld_cleanup(sh_chan, false);
 746
 747         last_used = chan->cookie;
 748         last_complete = sh_chan->completed_cookie;
 749         BUG_ON(last_complete < 0);
 750
 751         if (done)
 752                 *done = last_complete;
 753
 754         if (used)
 755                 *used = last_used;
 756
 757         spin_lock_bh(&sh_chan->desc_lock);
 758
 759         status = dma_async_is_complete(cookie, last_complete, last_used);
 760
 761         /*
 762          * If we don't find cookie on the queue, it has been aborted and we have
 763          * to report error
 764          */
 765         if (status != DMA_SUCCESS) {
 766                 struct sh_desc *desc;
 767                 status = DMA_ERROR;
 768                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
 769                         if (desc->cookie == cookie) {
 770                                 status = DMA_IN_PROGRESS;
 771                                 break;
 772                         }
 773         }
 774
 775         spin_unlock_bh(&sh_chan->desc_lock);
 776
 777         return status;
 778 }
 779
 780 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
 781 {
 782         irqreturn_t ret = IRQ_NONE;
 783         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 784         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 785
 786         if (chcr & CHCR_TE) {
 787                 /* DMA stop */
 788                 dmae_halt(sh_chan);
 789
 790                 ret = IRQ_HANDLED;
 791                 tasklet_schedule(&sh_chan->tasklet);
 792         }
 793
 794         return ret;
 795 }
 796
 797 #if defined(CONFIG_CPU_SH4)
 798 static irqreturn_t sh_dmae_err(int irq, void *data)
 799 {
 800         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
 801         int i;
 802
 803         /* halt the dma controller */
 804         sh_dmae_ctl_stop(shdev);
 805
 806         /* We cannot detect, which channel caused the error, have to reset all */
 807         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
 808                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 809                 if (sh_chan) {
 810                         struct sh_desc *desc;
 811                         /* Stop the channel */
 812                         dmae_halt(sh_chan);
 813                         /* Complete all  */
 814                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 815                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 816                                 desc->mark = DESC_IDLE;
 817                                 if (tx->callback)
 818                                         tx->callback(tx->callback_param);
 819                         }
 820                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
 821                 }
 822         }
 823         sh_dmae_rst(shdev);
 824
 825         return IRQ_HANDLED;
 826 }
 827 #endif
 828
 829 static void dmae_do_tasklet(unsigned long data)
 830 {
 831         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 832         struct sh_desc *desc;
 833         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 834         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 835
 836         spin_lock(&sh_chan->desc_lock);
 837         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 838                 if (desc->mark == DESC_SUBMITTED &&
 839                     ((desc->direction == DMA_FROM_DEVICE &&
 840                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
 841                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
 842                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
 843                                 desc->async_tx.cookie, &desc->async_tx,
 844                                 desc->hw.dar);
 845                         desc->mark = DESC_COMPLETED;
 846                         break;
 847                 }
 848         }
 849         spin_unlock(&sh_chan->desc_lock);
 850
 851         /* Next desc */
 852         sh_chan_xfer_ld_queue(sh_chan);
 853         sh_dmae_chan_ld_cleanup(sh_chan, false);
 854 }
 855
 856 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 857                                         int irq, unsigned long flags)
 858 {
 859         int err;
 860         struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 861         struct platform_device *pdev = to_platform_device(shdev->common.dev);
 862         struct sh_dmae_chan *new_sh_chan;
 863
 864         /* alloc channel */
 865         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
 866         if (!new_sh_chan) {
 867                 dev_err(shdev->common.dev,
 868                         "No free memory for allocating dma channels!\n");
 869                 return -ENOMEM;
 870         }
 871
 872         /* copy struct dma_device */
 873         new_sh_chan->common.device = &shdev->common;
 874
 875         new_sh_chan->dev = shdev->common.dev;
 876         new_sh_chan->id = id;
 877         new_sh_chan->irq = irq;
 878         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
 879
 880         /* Init DMA tasklet */
 881         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
 882                         (unsigned long)new_sh_chan);
 883
 884         /* Init the channel */
 885         dmae_init(new_sh_chan);
 886
 887         spin_lock_init(&new_sh_chan->desc_lock);
 888
 889         /* Init descripter manage list */
 890         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
 891         INIT_LIST_HEAD(&new_sh_chan->ld_free);
 892
 893         /* Add the channel to DMA device channel list */
 894         list_add_tail(&new_sh_chan->common.device_node,
 895                         &shdev->common.channels);
 896         shdev->common.chancnt++;
 897
 898         if (pdev->id >= 0)
 899                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
 900                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
 901         else
 902                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
 903                          "sh-dma%d", new_sh_chan->id);
 904
 905         /* set up channel irq */
 906         err = request_irq(irq, &sh_dmae_interrupt, flags,
 907                           new_sh_chan->dev_id, new_sh_chan);
 908         if (err) {
 909                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
 910                         "with return %d\n", id, err);
 911                 goto err_no_irq;
 912         }
 913
 914         shdev->chan[id] = new_sh_chan;
 915         return 0;
 916
 917 err_no_irq:
 918         /* remove from dmaengine device node */
 919         list_del(&new_sh_chan->common.device_node);
 920         kfree(new_sh_chan);
 921         return err;
 922 }
 923
 924 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
 925 {
 926         int i;
 927
 928         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
 929                 if (shdev->chan[i]) {
 930                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 931
 932                         free_irq(sh_chan->irq, sh_chan);
 933
 934                         list_del(&sh_chan->common.device_node);
 935                         kfree(sh_chan);
 936                         shdev->chan[i] = NULL;
 937                 }
 938         }
 939         shdev->common.chancnt = 0;
 940 }
 941
 942 static int __init sh_dmae_probe(struct platform_device *pdev)
 943 {
 944         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
 945         unsigned long irqflags = IRQF_DISABLED,
 946                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
 947         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
 948         int err, i, irq_cnt = 0, irqres = 0;
 949         struct sh_dmae_device *shdev;
 950         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 951
 952         /* get platform data */
 953         if (!pdata || !pdata->channel_num)
 954                 return -ENODEV;
 955
 956         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 957         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
 958         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 959         /*
 960          * IRQ resources:
 961          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
 962          *    the error IRQ, in which case it is the only IRQ in this resource:
 963          *    start == end. If it is the only IRQ resource, all channels also
 964          *    use the same IRQ.
 965          * 2. DMA channel IRQ resources can be specified one per resource or in
 966          *    ranges (start != end)
 967          * 3. iff all events (channels and, optionally, error) on this
 968          *    controller use the same IRQ, only one IRQ resource can be
 969          *    specified, otherwise there must be one IRQ per channel, even if
 970          *    some of them are equal
 971          * 4. if all IRQs on this controller are equal or if some specific IRQs
 972          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
 973          *    requested with the IRQF_SHARED flag
 974          */
 975         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 976         if (!chan || !errirq_res)
 977                 return -ENODEV;
 978
 979         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
 980                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
 981                 return -EBUSY;
 982         }
 983
 984         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
 985                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
 986                 err = -EBUSY;
 987                 goto ermrdmars;
 988         }
 989
 990         err = -ENOMEM;
 991         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
 992         if (!shdev) {
 993                 dev_err(&pdev->dev, "Not enough memory\n");
 994                 goto ealloc;
 995         }
 996
 997         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
 998         if (!shdev->chan_reg)
 999                 goto emapchan;
1000         if (dmars) {
1001                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1002                 if (!shdev->dmars)
1003                         goto emapdmars;
1004         }
1005
1006         /* platform data */
1007         shdev->pdata = pdata;
1008
1009         pm_runtime_enable(&pdev->dev);
1010         pm_runtime_get_sync(&pdev->dev);
1011
1012         /* reset dma controller */
1013         err = sh_dmae_rst(shdev);
1014         if (err)
1015                 goto rst_err;
1016
1017         INIT_LIST_HEAD(&shdev->common.channels);
1018
1019         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1020         if (dmars)
1021                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1022
1023         shdev->common.device_alloc_chan_resources
1024                 = sh_dmae_alloc_chan_resources;
1025         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1026         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1027         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
1028         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1029
1030         /* Compulsory for DMA_SLAVE fields */
1031         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1032         shdev->common.device_terminate_all = sh_dmae_terminate_all;
1033
1034         shdev->common.dev = &pdev->dev;
1035         /* Default transfer size of 32 bytes requires 32-byte alignment */
1036         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1037
1038 #if defined(CONFIG_CPU_SH4)
1039         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1040
1041         if (!chanirq_res)
1042                 chanirq_res = errirq_res;
1043         else
1044                 irqres++;
1045
1046         if (chanirq_res == errirq_res ||
1047             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1048                 irqflags = IRQF_SHARED;
1049
1050         errirq = errirq_res->start;
1051
1052         err = request_irq(errirq, sh_dmae_err, irqflags,
1053                           "DMAC Address Error", shdev);
1054         if (err) {
1055                 dev_err(&pdev->dev,
1056                         "DMA failed requesting irq #%d, error %d\n",
1057                         errirq, err);
1058                 goto eirq_err;
1059         }
1060
1061 #else
1062         chanirq_res = errirq_res;
1063 #endif /* CONFIG_CPU_SH4 */
1064
1065         if (chanirq_res->start == chanirq_res->end &&
1066             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1067                 /* Special case - all multiplexed */
1068                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1069                         chan_irq[irq_cnt] = chanirq_res->start;
1070                         chan_flag[irq_cnt] = IRQF_SHARED;
1071                 }
1072         } else {
1073                 do {
1074                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1075                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1076                                     IORESOURCE_IRQ_SHAREABLE)
1077                                         chan_flag[irq_cnt] = IRQF_SHARED;
1078                                 else
1079                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1080                                 dev_dbg(&pdev->dev,
1081                                         "Found IRQ %d for channel %d\n",
1082                                         i, irq_cnt);
1083                                 chan_irq[irq_cnt++] = i;
1084                         }
1085                         chanirq_res = platform_get_resource(pdev,
1086                                                 IORESOURCE_IRQ, ++irqres);
1087                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1088         }
1089
1090         if (irq_cnt < pdata->channel_num)
1091                 goto eirqres;
1092
1093         /* Create DMA Channel */
1094         for (i = 0; i < pdata->channel_num; i++) {
1095                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1096                 if (err)
1097                         goto chan_probe_err;
1098         }
1099
1100         pm_runtime_put(&pdev->dev);
1101
1102         platform_set_drvdata(pdev, shdev);
1103         dma_async_device_register(&shdev->common);
1104
1105         return err;
1106
1107 chan_probe_err:
1108         sh_dmae_chan_remove(shdev);
1109 eirqres:
1110 #if defined(CONFIG_CPU_SH4)
1111         free_irq(errirq, shdev);
1112 eirq_err:
1113 #endif
1114 rst_err:
1115         pm_runtime_put(&pdev->dev);
1116         if (dmars)
1117                 iounmap(shdev->dmars);
1118 emapdmars:
1119         iounmap(shdev->chan_reg);
1120 emapchan:
1121         kfree(shdev);
1122 ealloc:
1123         if (dmars)
1124                 release_mem_region(dmars->start, resource_size(dmars));
1125 ermrdmars:
1126         release_mem_region(chan->start, resource_size(chan));
1127
1128         return err;
1129 }
1130
1131 static int __exit sh_dmae_remove(struct platform_device *pdev)
1132 {
1133         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1134         struct resource *res;
1135         int errirq = platform_get_irq(pdev, 0);
1136
1137         dma_async_device_unregister(&shdev->common);
1138
1139         if (errirq > 0)
1140                 free_irq(errirq, shdev);
1141
1142         /* channel data remove */
1143         sh_dmae_chan_remove(shdev);
1144
1145         pm_runtime_disable(&pdev->dev);
1146
1147         if (shdev->dmars)
1148                 iounmap(shdev->dmars);
1149         iounmap(shdev->chan_reg);
1150
1151         kfree(shdev);
1152
1153         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154         if (res)
1155                 release_mem_region(res->start, resource_size(res));
1156         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1157         if (res)
1158                 release_mem_region(res->start, resource_size(res));
1159
1160         return 0;
1161 }
1162
1163 static void sh_dmae_shutdown(struct platform_device *pdev)
1164 {
1165         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1166         sh_dmae_ctl_stop(shdev);
1167 }
1168
1169 static struct platform_driver sh_dmae_driver = {
1170         .remove         = __exit_p(sh_dmae_remove),
1171         .shutdown       = sh_dmae_shutdown,
1172         .driver = {
1173                 .name   = "sh-dma-engine",
1174         },
1175 };
1176
1177 static int __init sh_dmae_init(void)
1178 {
1179         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1180 }
1181 module_init(sh_dmae_init);
1182
1183 static void __exit sh_dmae_exit(void)
1184 {
1185         platform_driver_unregister(&sh_dmae_driver);
1186 }
1187 module_exit(sh_dmae_exit);
1188
1189 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1190 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1191 MODULE_LICENSE("GPL");