drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/clk.h>
  26 #include <linux/wait.h>
  27 #include <linux/sched.h>
  28 #include <linux/semaphore.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/device.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/firmware.h>
  33 #include <linux/slab.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dmaengine.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38
  39 #include <asm/irq.h>
  40 #include <mach/sdma.h>
  41 #include <mach/dma.h>
  42 #include <mach/hardware.h>
  43
  44 /* SDMA registers */
  45 #define SDMA_H_C0PTR            0x000
  46 #define SDMA_H_INTR             0x004
  47 #define SDMA_H_STATSTOP         0x008
  48 #define SDMA_H_START            0x00c
  49 #define SDMA_H_EVTOVR           0x010
  50 #define SDMA_H_DSPOVR           0x014
  51 #define SDMA_H_HOSTOVR          0x018
  52 #define SDMA_H_EVTPEND          0x01c
  53 #define SDMA_H_DSPENBL          0x020
  54 #define SDMA_H_RESET            0x024
  55 #define SDMA_H_EVTERR           0x028
  56 #define SDMA_H_INTRMSK          0x02c
  57 #define SDMA_H_PSW              0x030
  58 #define SDMA_H_EVTERRDBG        0x034
  59 #define SDMA_H_CONFIG           0x038
  60 #define SDMA_ONCE_ENB           0x040
  61 #define SDMA_ONCE_DATA          0x044
  62 #define SDMA_ONCE_INSTR         0x048
  63 #define SDMA_ONCE_STAT          0x04c
  64 #define SDMA_ONCE_CMD           0x050
  65 #define SDMA_EVT_MIRROR         0x054
  66 #define SDMA_ILLINSTADDR        0x058
  67 #define SDMA_CHN0ADDR           0x05c
  68 #define SDMA_ONCE_RTB           0x060
  69 #define SDMA_XTRIG_CONF1        0x070
  70 #define SDMA_XTRIG_CONF2        0x074
  71 #define SDMA_CHNENBL0_IMX35     0x200
  72 #define SDMA_CHNENBL0_IMX31     0x080
  73 #define SDMA_CHNPRI_0           0x100
  74
  75 /*
  76  * Buffer descriptor status values.
  77  */
  78 #define BD_DONE  0x01
  79 #define BD_WRAP  0x02
  80 #define BD_CONT  0x04
  81 #define BD_INTR  0x08
  82 #define BD_RROR  0x10
  83 #define BD_LAST  0x20
  84 #define BD_EXTD  0x80
  85
  86 /*
  87  * Data Node descriptor status values.
  88  */
  89 #define DND_END_OF_FRAME  0x80
  90 #define DND_END_OF_XFER   0x40
  91 #define DND_DONE          0x20
  92 #define DND_UNUSED        0x01
  93
  94 /*
  95  * IPCV2 descriptor status values.
  96  */
  97 #define BD_IPCV2_END_OF_FRAME  0x40
  98
  99 #define IPCV2_MAX_NODES        50
 100 /*
 101  * Error bit set in the CCB status field by the SDMA,
 102  * in setbd routine, in case of a transfer error
 103  */
 104 #define DATA_ERROR  0x10000000
 105
 106 /*
 107  * Buffer descriptor commands.
 108  */
 109 #define C0_ADDR             0x01
 110 #define C0_LOAD             0x02
 111 #define C0_DUMP             0x03
 112 #define C0_SETCTX           0x07
 113 #define C0_GETCTX           0x03
 114 #define C0_SETDM            0x01
 115 #define C0_SETPM            0x04
 116 #define C0_GETDM            0x02
 117 #define C0_GETPM            0x08
 118 /*
 119  * Change endianness indicator in the BD command field
 120  */
 121 #define CHANGE_ENDIANNESS   0x80
 122
 123 /*
 124  * Mode/Count of data node descriptors - IPCv2
 125  */
 126 struct sdma_mode_count {
 127         u32 count   : 16; /* size of the buffer pointed by this BD */
 128         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 129         u32 command :  8; /* command mostlky used for channel 0 */
 130 };
 131
 132 /*
 133  * Buffer descriptor
 134  */
 135 struct sdma_buffer_descriptor {
 136         struct sdma_mode_count  mode;
 137         u32 buffer_addr;        /* address of the buffer described */
 138         u32 ext_buffer_addr;    /* extended buffer address */
 139 } __attribute__ ((packed));
 140
 141 /**
 142  * struct sdma_channel_control - Channel control Block
 143  *
 144  * @current_bd_ptr      current buffer descriptor processed
 145  * @base_bd_ptr         first element of buffer descriptor array
 146  * @unused              padding. The SDMA engine expects an array of 128 byte
 147  *                      control blocks
 148  */
 149 struct sdma_channel_control {
 150         u32 current_bd_ptr;
 151         u32 base_bd_ptr;
 152         u32 unused[2];
 153 } __attribute__ ((packed));
 154
 155 /**
 156  * struct sdma_state_registers - SDMA context for a channel
 157  *
 158  * @pc:         program counter
 159  * @t:          test bit: status of arithmetic & test instruction
 160  * @rpc:        return program counter
 161  * @sf:         source fault while loading data
 162  * @spc:        loop start program counter
 163  * @df:         destination fault while storing data
 164  * @epc:        loop end program counter
 165  * @lm:         loop mode
 166  */
 167 struct sdma_state_registers {
 168         u32 pc     :14;
 169         u32 unused1: 1;
 170         u32 t      : 1;
 171         u32 rpc    :14;
 172         u32 unused0: 1;
 173         u32 sf     : 1;
 174         u32 spc    :14;
 175         u32 unused2: 1;
 176         u32 df     : 1;
 177         u32 epc    :14;
 178         u32 lm     : 2;
 179 } __attribute__ ((packed));
 180
 181 /**
 182  * struct sdma_context_data - sdma context specific to a channel
 183  *
 184  * @channel_state:      channel state bits
 185  * @gReg:               general registers
 186  * @mda:                burst dma destination address register
 187  * @msa:                burst dma source address register
 188  * @ms:                 burst dma status register
 189  * @md:                 burst dma data register
 190  * @pda:                peripheral dma destination address register
 191  * @psa:                peripheral dma source address register
 192  * @ps:                 peripheral dma status register
 193  * @pd:                 peripheral dma data register
 194  * @ca:                 CRC polynomial register
 195  * @cs:                 CRC accumulator register
 196  * @dda:                dedicated core destination address register
 197  * @dsa:                dedicated core source address register
 198  * @ds:                 dedicated core status register
 199  * @dd:                 dedicated core data register
 200  */
 201 struct sdma_context_data {
 202         struct sdma_state_registers  channel_state;
 203         u32  gReg[8];
 204         u32  mda;
 205         u32  msa;
 206         u32  ms;
 207         u32  md;
 208         u32  pda;
 209         u32  psa;
 210         u32  ps;
 211         u32  pd;
 212         u32  ca;
 213         u32  cs;
 214         u32  dda;
 215         u32  dsa;
 216         u32  ds;
 217         u32  dd;
 218         u32  scratch0;
 219         u32  scratch1;
 220         u32  scratch2;
 221         u32  scratch3;
 222         u32  scratch4;
 223         u32  scratch5;
 224         u32  scratch6;
 225         u32  scratch7;
 226 } __attribute__ ((packed));
 227
 228 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 229
 230 struct sdma_engine;
 231
 232 /**
 233  * struct sdma_channel - housekeeping for a SDMA channel
 234  *
 235  * @sdma                pointer to the SDMA engine for this channel
 236  * @channel             the channel number, matches dmaengine chan_id + 1
 237  * @direction           transfer type. Needed for setting SDMA script
 238  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 239  * @event_id0           aka dma request line
 240  * @event_id1           for channels that use 2 events
 241  * @word_size           peripheral access size
 242  * @buf_tail            ID of the buffer that was processed
 243  * @done                channel completion
 244  * @num_bd              max NUM_BD. number of descriptors currently handling
 245  */
 246 struct sdma_channel {
 247         struct sdma_engine              *sdma;
 248         unsigned int                    channel;
 249         enum dma_data_direction         direction;
 250         enum sdma_peripheral_type       peripheral_type;
 251         unsigned int                    event_id0;
 252         unsigned int                    event_id1;
 253         enum dma_slave_buswidth         word_size;
 254         unsigned int                    buf_tail;
 255         struct completion               done;
 256         unsigned int                    num_bd;
 257         struct sdma_buffer_descriptor   *bd;
 258         dma_addr_t                      bd_phys;
 259         unsigned int                    pc_from_device, pc_to_device;
 260         unsigned long                   flags;
 261         dma_addr_t                      per_address;
 262         u32                             event_mask0, event_mask1;
 263         u32                             watermark_level;
 264         u32                             shp_addr, per_addr;
 265         struct dma_chan                 chan;
 266         spinlock_t                      lock;
 267         struct dma_async_tx_descriptor  desc;
 268         dma_cookie_t                    last_completed;
 269         enum dma_status                 status;
 270 };
 271
 272 #define IMX_DMA_SG_LOOP         (1 << 0)
 273
 274 #define MAX_DMA_CHANNELS 32
 275 #define MXC_SDMA_DEFAULT_PRIORITY 1
 276 #define MXC_SDMA_MIN_PRIORITY 1
 277 #define MXC_SDMA_MAX_PRIORITY 7
 278
 279 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 280
 281 /**
 282  * struct sdma_firmware_header - Layout of the firmware image
 283  *
 284  * @magic               "SDMA"
 285  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 286  *                      changes.
 287  * @version_minor       firmware minor version (for binary compatible changes)
 288  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 289  * @num_script_addrs    Number of script addresses in this image
 290  * @ram_code_start      offset of SDMA ram image in this firmware image
 291  * @ram_code_size       size of SDMA ram image
 292  * @script_addrs        Stores the start address of the SDMA scripts
 293  *                      (in SDMA memory space)
 294  */
 295 struct sdma_firmware_header {
 296         u32     magic;
 297         u32     version_major;
 298         u32     version_minor;
 299         u32     script_addrs_start;
 300         u32     num_script_addrs;
 301         u32     ram_code_start;
 302         u32     ram_code_size;
 303 };
 304
 305 enum sdma_devtype {
 306         IMX31_SDMA,     /* runs on i.mx31 */
 307         IMX35_SDMA,     /* runs on i.mx35 and later */
 308 };
 309
 310 struct sdma_engine {
 311         struct device                   *dev;
 312         struct device_dma_parameters    dma_parms;
 313         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 314         struct sdma_channel_control     *channel_control;
 315         void __iomem                    *regs;
 316         enum sdma_devtype               devtype;
 317         unsigned int                    num_events;
 318         struct sdma_context_data        *context;
 319         dma_addr_t                      context_phys;
 320         struct dma_device               dma_device;
 321         struct clk                      *clk;
 322         struct mutex                    channel_0_lock;
 323         struct sdma_script_start_addrs  *script_addrs;
 324 };
 325
 326 static struct platform_device_id sdma_devtypes[] = {
 327         {
 328                 .name = "imx31-sdma",
 329                 .driver_data = IMX31_SDMA,
 330         }, {
 331                 .name = "imx35-sdma",
 332                 .driver_data = IMX35_SDMA,
 333         }, {
 334                 /* sentinel */
 335         }
 336 };
 337 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 338
 339 static const struct of_device_id sdma_dt_ids[] = {
 340         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
 341         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
 342         { /* sentinel */ }
 343 };
 344 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 345
 346 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
 347 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
 348 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 349 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 350
 351 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 352 {
 353         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
 354                                                       SDMA_CHNENBL0_IMX35);
 355         return chnenbl0 + event * 4;
 356 }
 357
 358 static int sdma_config_ownership(struct sdma_channel *sdmac,
 359                 bool event_override, bool mcu_override, bool dsp_override)
 360 {
 361         struct sdma_engine *sdma = sdmac->sdma;
 362         int channel = sdmac->channel;
 363         u32 evt, mcu, dsp;
 364
 365         if (event_override && mcu_override && dsp_override)
 366                 return -EINVAL;
 367
 368         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
 369         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
 370         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
 371
 372         if (dsp_override)
 373                 dsp &= ~(1 << channel);
 374         else
 375                 dsp |= (1 << channel);
 376
 377         if (event_override)
 378                 evt &= ~(1 << channel);
 379         else
 380                 evt |= (1 << channel);
 381
 382         if (mcu_override)
 383                 mcu &= ~(1 << channel);
 384         else
 385                 mcu |= (1 << channel);
 386
 387         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
 388         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
 389         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
 390
 391         return 0;
 392 }
 393
 394 /*
 395  * sdma_run_channel - run a channel and wait till it's done
 396  */
 397 static int sdma_run_channel(struct sdma_channel *sdmac)
 398 {
 399         struct sdma_engine *sdma = sdmac->sdma;
 400         int channel = sdmac->channel;
 401         int ret;
 402
 403         init_completion(&sdmac->done);
 404
 405         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 406
 407         ret = wait_for_completion_timeout(&sdmac->done, HZ);
 408
 409         return ret ? 0 : -ETIMEDOUT;
 410 }
 411
 412 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 413                 u32 address)
 414 {
 415         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 416         void *buf_virt;
 417         dma_addr_t buf_phys;
 418         int ret;
 419
 420         mutex_lock(&sdma->channel_0_lock);
 421
 422         buf_virt = dma_alloc_coherent(NULL,
 423                         size,
 424                         &buf_phys, GFP_KERNEL);
 425         if (!buf_virt) {
 426                 ret = -ENOMEM;
 427                 goto err_out;
 428         }
 429
 430         bd0->mode.command = C0_SETPM;
 431         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 432         bd0->mode.count = size / 2;
 433         bd0->buffer_addr = buf_phys;
 434         bd0->ext_buffer_addr = address;
 435
 436         memcpy(buf_virt, buf, size);
 437
 438         ret = sdma_run_channel(&sdma->channel[0]);
 439
 440         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 441
 442 err_out:
 443         mutex_unlock(&sdma->channel_0_lock);
 444
 445         return ret;
 446 }
 447
 448 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 449 {
 450         struct sdma_engine *sdma = sdmac->sdma;
 451         int channel = sdmac->channel;
 452         u32 val;
 453         u32 chnenbl = chnenbl_ofs(sdma, event);
 454
 455         val = __raw_readl(sdma->regs + chnenbl);
 456         val |= (1 << channel);
 457         __raw_writel(val, sdma->regs + chnenbl);
 458 }
 459
 460 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 461 {
 462         struct sdma_engine *sdma = sdmac->sdma;
 463         int channel = sdmac->channel;
 464         u32 chnenbl = chnenbl_ofs(sdma, event);
 465         u32 val;
 466
 467         val = __raw_readl(sdma->regs + chnenbl);
 468         val &= ~(1 << channel);
 469         __raw_writel(val, sdma->regs + chnenbl);
 470 }
 471
 472 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 473 {
 474         struct sdma_buffer_descriptor *bd;
 475
 476         /*
 477          * loop mode. Iterate over descriptors, re-setup them and
 478          * call callback function.
 479          */
 480         while (1) {
 481                 bd = &sdmac->bd[sdmac->buf_tail];
 482
 483                 if (bd->mode.status & BD_DONE)
 484                         break;
 485
 486                 if (bd->mode.status & BD_RROR)
 487                         sdmac->status = DMA_ERROR;
 488                 else
 489                         sdmac->status = DMA_IN_PROGRESS;
 490
 491                 bd->mode.status |= BD_DONE;
 492                 sdmac->buf_tail++;
 493                 sdmac->buf_tail %= sdmac->num_bd;
 494
 495                 if (sdmac->desc.callback)
 496                         sdmac->desc.callback(sdmac->desc.callback_param);
 497         }
 498 }
 499
 500 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 501 {
 502         struct sdma_buffer_descriptor *bd;
 503         int i, error = 0;
 504
 505         /*
 506          * non loop mode. Iterate over all descriptors, collect
 507          * errors and call callback function
 508          */
 509         for (i = 0; i < sdmac->num_bd; i++) {
 510                 bd = &sdmac->bd[i];
 511
 512                  if (bd->mode.status & (BD_DONE | BD_RROR))
 513                         error = -EIO;
 514         }
 515
 516         if (error)
 517                 sdmac->status = DMA_ERROR;
 518         else
 519                 sdmac->status = DMA_SUCCESS;
 520
 521         if (sdmac->desc.callback)
 522                 sdmac->desc.callback(sdmac->desc.callback_param);
 523         sdmac->last_completed = sdmac->desc.cookie;
 524 }
 525
 526 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 527 {
 528         complete(&sdmac->done);
 529
 530         /* not interested in channel 0 interrupts */
 531         if (sdmac->channel == 0)
 532                 return;
 533
 534         if (sdmac->flags & IMX_DMA_SG_LOOP)
 535                 sdma_handle_channel_loop(sdmac);
 536         else
 537                 mxc_sdma_handle_channel_normal(sdmac);
 538 }
 539
 540 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 541 {
 542         struct sdma_engine *sdma = dev_id;
 543         u32 stat;
 544
 545         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
 546         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
 547
 548         while (stat) {
 549                 int channel = fls(stat) - 1;
 550                 struct sdma_channel *sdmac = &sdma->channel[channel];
 551
 552                 mxc_sdma_handle_channel(sdmac);
 553
 554                 stat &= ~(1 << channel);
 555         }
 556
 557         return IRQ_HANDLED;
 558 }
 559
 560 /*
 561  * sets the pc of SDMA script according to the peripheral type
 562  */
 563 static void sdma_get_pc(struct sdma_channel *sdmac,
 564                 enum sdma_peripheral_type peripheral_type)
 565 {
 566         struct sdma_engine *sdma = sdmac->sdma;
 567         int per_2_emi = 0, emi_2_per = 0;
 568         /*
 569          * These are needed once we start to support transfers between
 570          * two peripherals or memory-to-memory transfers
 571          */
 572         int per_2_per = 0, emi_2_emi = 0;
 573
 574         sdmac->pc_from_device = 0;
 575         sdmac->pc_to_device = 0;
 576
 577         switch (peripheral_type) {
 578         case IMX_DMATYPE_MEMORY:
 579                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 580                 break;
 581         case IMX_DMATYPE_DSP:
 582                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 583                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 584                 break;
 585         case IMX_DMATYPE_FIRI:
 586                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 587                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 588                 break;
 589         case IMX_DMATYPE_UART:
 590                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 591                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 592                 break;
 593         case IMX_DMATYPE_UART_SP:
 594                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 595                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 596                 break;
 597         case IMX_DMATYPE_ATA:
 598                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 599                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 600                 break;
 601         case IMX_DMATYPE_CSPI:
 602         case IMX_DMATYPE_EXT:
 603         case IMX_DMATYPE_SSI:
 604                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 605                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 606                 break;
 607         case IMX_DMATYPE_SSI_SP:
 608         case IMX_DMATYPE_MMC:
 609         case IMX_DMATYPE_SDHC:
 610         case IMX_DMATYPE_CSPI_SP:
 611         case IMX_DMATYPE_ESAI:
 612         case IMX_DMATYPE_MSHC_SP:
 613                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 614                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 615                 break;
 616         case IMX_DMATYPE_ASRC:
 617                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 618                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 619                 per_2_per = sdma->script_addrs->per_2_per_addr;
 620                 break;
 621         case IMX_DMATYPE_MSHC:
 622                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 623                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 624                 break;
 625         case IMX_DMATYPE_CCM:
 626                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 627                 break;
 628         case IMX_DMATYPE_SPDIF:
 629                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 630                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 631                 break;
 632         case IMX_DMATYPE_IPU_MEMORY:
 633                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 634                 break;
 635         default:
 636                 break;
 637         }
 638
 639         sdmac->pc_from_device = per_2_emi;
 640         sdmac->pc_to_device = emi_2_per;
 641 }
 642
 643 static int sdma_load_context(struct sdma_channel *sdmac)
 644 {
 645         struct sdma_engine *sdma = sdmac->sdma;
 646         int channel = sdmac->channel;
 647         int load_address;
 648         struct sdma_context_data *context = sdma->context;
 649         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 650         int ret;
 651
 652         if (sdmac->direction == DMA_FROM_DEVICE) {
 653                 load_address = sdmac->pc_from_device;
 654         } else {
 655                 load_address = sdmac->pc_to_device;
 656         }
 657
 658         if (load_address < 0)
 659                 return load_address;
 660
 661         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 662         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
 663         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 664         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 665         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
 666         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 667
 668         mutex_lock(&sdma->channel_0_lock);
 669
 670         memset(context, 0, sizeof(*context));
 671         context->channel_state.pc = load_address;
 672
 673         /* Send by context the event mask,base address for peripheral
 674          * and watermark level
 675          */
 676         context->gReg[0] = sdmac->event_mask1;
 677         context->gReg[1] = sdmac->event_mask0;
 678         context->gReg[2] = sdmac->per_addr;
 679         context->gReg[6] = sdmac->shp_addr;
 680         context->gReg[7] = sdmac->watermark_level;
 681
 682         bd0->mode.command = C0_SETDM;
 683         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 684         bd0->mode.count = sizeof(*context) / 4;
 685         bd0->buffer_addr = sdma->context_phys;
 686         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 687
 688         ret = sdma_run_channel(&sdma->channel[0]);
 689
 690         mutex_unlock(&sdma->channel_0_lock);
 691
 692         return ret;
 693 }
 694
 695 static void sdma_disable_channel(struct sdma_channel *sdmac)
 696 {
 697         struct sdma_engine *sdma = sdmac->sdma;
 698         int channel = sdmac->channel;
 699
 700         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
 701         sdmac->status = DMA_ERROR;
 702 }
 703
 704 static int sdma_config_channel(struct sdma_channel *sdmac)
 705 {
 706         int ret;
 707
 708         sdma_disable_channel(sdmac);
 709
 710         sdmac->event_mask0 = 0;
 711         sdmac->event_mask1 = 0;
 712         sdmac->shp_addr = 0;
 713         sdmac->per_addr = 0;
 714
 715         if (sdmac->event_id0) {
 716                 if (sdmac->event_id0 > 32)
 717                         return -EINVAL;
 718                 sdma_event_enable(sdmac, sdmac->event_id0);
 719         }
 720
 721         switch (sdmac->peripheral_type) {
 722         case IMX_DMATYPE_DSP:
 723                 sdma_config_ownership(sdmac, false, true, true);
 724                 break;
 725         case IMX_DMATYPE_MEMORY:
 726                 sdma_config_ownership(sdmac, false, true, false);
 727                 break;
 728         default:
 729                 sdma_config_ownership(sdmac, true, true, false);
 730                 break;
 731         }
 732
 733         sdma_get_pc(sdmac, sdmac->peripheral_type);
 734
 735         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 736                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 737                 /* Handle multiple event channels differently */
 738                 if (sdmac->event_id1) {
 739                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
 740                         if (sdmac->event_id1 > 31)
 741                                 sdmac->watermark_level |= 1 << 31;
 742                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
 743                         if (sdmac->event_id0 > 31)
 744                                 sdmac->watermark_level |= 1 << 30;
 745                 } else {
 746                         sdmac->event_mask0 = 1 << sdmac->event_id0;
 747                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
 748                 }
 749                 /* Watermark Level */
 750                 sdmac->watermark_level |= sdmac->watermark_level;
 751                 /* Address */
 752                 sdmac->shp_addr = sdmac->per_address;
 753         } else {
 754                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 755         }
 756
 757         ret = sdma_load_context(sdmac);
 758
 759         return ret;
 760 }
 761
 762 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 763                 unsigned int priority)
 764 {
 765         struct sdma_engine *sdma = sdmac->sdma;
 766         int channel = sdmac->channel;
 767
 768         if (priority < MXC_SDMA_MIN_PRIORITY
 769             || priority > MXC_SDMA_MAX_PRIORITY) {
 770                 return -EINVAL;
 771         }
 772
 773         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 774
 775         return 0;
 776 }
 777
 778 static int sdma_request_channel(struct sdma_channel *sdmac)
 779 {
 780         struct sdma_engine *sdma = sdmac->sdma;
 781         int channel = sdmac->channel;
 782         int ret = -EBUSY;
 783
 784         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 785         if (!sdmac->bd) {
 786                 ret = -ENOMEM;
 787                 goto out;
 788         }
 789
 790         memset(sdmac->bd, 0, PAGE_SIZE);
 791
 792         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 793         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 794
 795         clk_enable(sdma->clk);
 796
 797         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 798
 799         init_completion(&sdmac->done);
 800
 801         sdmac->buf_tail = 0;
 802
 803         return 0;
 804 out:
 805
 806         return ret;
 807 }
 808
 809 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 810 {
 811         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 812 }
 813
 814 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
 815 {
 816         dma_cookie_t cookie = sdmac->chan.cookie;
 817
 818         if (++cookie < 0)
 819                 cookie = 1;
 820
 821         sdmac->chan.cookie = cookie;
 822         sdmac->desc.cookie = cookie;
 823
 824         return cookie;
 825 }
 826
 827 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 828 {
 829         return container_of(chan, struct sdma_channel, chan);
 830 }
 831
 832 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 833 {
 834         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 835         struct sdma_engine *sdma = sdmac->sdma;
 836         dma_cookie_t cookie;
 837
 838         spin_lock_irq(&sdmac->lock);
 839
 840         cookie = sdma_assign_cookie(sdmac);
 841
 842         sdma_enable_channel(sdma, sdmac->channel);
 843
 844         spin_unlock_irq(&sdmac->lock);
 845
 846         return cookie;
 847 }
 848
 849 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 850 {
 851         struct sdma_channel *sdmac = to_sdma_chan(chan);
 852         struct imx_dma_data *data = chan->private;
 853         int prio, ret;
 854
 855         if (!data)
 856                 return -EINVAL;
 857
 858         switch (data->priority) {
 859         case DMA_PRIO_HIGH:
 860                 prio = 3;
 861                 break;
 862         case DMA_PRIO_MEDIUM:
 863                 prio = 2;
 864                 break;
 865         case DMA_PRIO_LOW:
 866         default:
 867                 prio = 1;
 868                 break;
 869         }
 870
 871         sdmac->peripheral_type = data->peripheral_type;
 872         sdmac->event_id0 = data->dma_request;
 873         ret = sdma_set_channel_priority(sdmac, prio);
 874         if (ret)
 875                 return ret;
 876
 877         ret = sdma_request_channel(sdmac);
 878         if (ret)
 879                 return ret;
 880
 881         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 882         sdmac->desc.tx_submit = sdma_tx_submit;
 883         /* txd.flags will be overwritten in prep funcs */
 884         sdmac->desc.flags = DMA_CTRL_ACK;
 885
 886         return 0;
 887 }
 888
 889 static void sdma_free_chan_resources(struct dma_chan *chan)
 890 {
 891         struct sdma_channel *sdmac = to_sdma_chan(chan);
 892         struct sdma_engine *sdma = sdmac->sdma;
 893
 894         sdma_disable_channel(sdmac);
 895
 896         if (sdmac->event_id0)
 897                 sdma_event_disable(sdmac, sdmac->event_id0);
 898         if (sdmac->event_id1)
 899                 sdma_event_disable(sdmac, sdmac->event_id1);
 900
 901         sdmac->event_id0 = 0;
 902         sdmac->event_id1 = 0;
 903
 904         sdma_set_channel_priority(sdmac, 0);
 905
 906         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 907
 908         clk_disable(sdma->clk);
 909 }
 910
 911 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 912                 struct dma_chan *chan, struct scatterlist *sgl,
 913                 unsigned int sg_len, enum dma_data_direction direction,
 914                 unsigned long flags)
 915 {
 916         struct sdma_channel *sdmac = to_sdma_chan(chan);
 917         struct sdma_engine *sdma = sdmac->sdma;
 918         int ret, i, count;
 919         int channel = sdmac->channel;
 920         struct scatterlist *sg;
 921
 922         if (sdmac->status == DMA_IN_PROGRESS)
 923                 return NULL;
 924         sdmac->status = DMA_IN_PROGRESS;
 925
 926         sdmac->flags = 0;
 927
 928         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
 929                         sg_len, channel);
 930
 931         sdmac->direction = direction;
 932         ret = sdma_load_context(sdmac);
 933         if (ret)
 934                 goto err_out;
 935
 936         if (sg_len > NUM_BD) {
 937                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
 938                                 channel, sg_len, NUM_BD);
 939                 ret = -EINVAL;
 940                 goto err_out;
 941         }
 942
 943         for_each_sg(sgl, sg, sg_len, i) {
 944                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
 945                 int param;
 946
 947                 bd->buffer_addr = sg->dma_address;
 948
 949                 count = sg->length;
 950
 951                 if (count > 0xffff) {
 952                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
 953                                         channel, count, 0xffff);
 954                         ret = -EINVAL;
 955                         goto err_out;
 956                 }
 957
 958                 bd->mode.count = count;
 959
 960                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
 961                         ret =  -EINVAL;
 962                         goto err_out;
 963                 }
 964
 965                 switch (sdmac->word_size) {
 966                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 967                         bd->mode.command = 0;
 968                         if (count & 3 || sg->dma_address & 3)
 969                                 return NULL;
 970                         break;
 971                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 972                         bd->mode.command = 2;
 973                         if (count & 1 || sg->dma_address & 1)
 974                                 return NULL;
 975                         break;
 976                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 977                         bd->mode.command = 1;
 978                         break;
 979                 default:
 980                         return NULL;
 981                 }
 982
 983                 param = BD_DONE | BD_EXTD | BD_CONT;
 984
 985                 if (i + 1 == sg_len) {
 986                         param |= BD_INTR;
 987                         param |= BD_LAST;
 988                         param &= ~BD_CONT;
 989                 }
 990
 991                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
 992                                 i, count, sg->dma_address,
 993                                 param & BD_WRAP ? "wrap" : "",
 994                                 param & BD_INTR ? " intr" : "");
 995
 996                 bd->mode.status = param;
 997         }
 998
 999         sdmac->num_bd = sg_len;
1000         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1001
1002         return &sdmac->desc;
1003 err_out:
1004         sdmac->status = DMA_ERROR;
1005         return NULL;
1006 }
1007
1008 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1009                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1010                 size_t period_len, enum dma_data_direction direction)
1011 {
1012         struct sdma_channel *sdmac = to_sdma_chan(chan);
1013         struct sdma_engine *sdma = sdmac->sdma;
1014         int num_periods = buf_len / period_len;
1015         int channel = sdmac->channel;
1016         int ret, i = 0, buf = 0;
1017
1018         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1019
1020         if (sdmac->status == DMA_IN_PROGRESS)
1021                 return NULL;
1022
1023         sdmac->status = DMA_IN_PROGRESS;
1024
1025         sdmac->flags |= IMX_DMA_SG_LOOP;
1026         sdmac->direction = direction;
1027         ret = sdma_load_context(sdmac);
1028         if (ret)
1029                 goto err_out;
1030
1031         if (num_periods > NUM_BD) {
1032                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1033                                 channel, num_periods, NUM_BD);
1034                 goto err_out;
1035         }
1036
1037         if (period_len > 0xffff) {
1038                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1039                                 channel, period_len, 0xffff);
1040                 goto err_out;
1041         }
1042
1043         while (buf < buf_len) {
1044                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1045                 int param;
1046
1047                 bd->buffer_addr = dma_addr;
1048
1049                 bd->mode.count = period_len;
1050
1051                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1052                         goto err_out;
1053                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1054                         bd->mode.command = 0;
1055                 else
1056                         bd->mode.command = sdmac->word_size;
1057
1058                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1059                 if (i + 1 == num_periods)
1060                         param |= BD_WRAP;
1061
1062                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1063                                 i, period_len, dma_addr,
1064                                 param & BD_WRAP ? "wrap" : "",
1065                                 param & BD_INTR ? " intr" : "");
1066
1067                 bd->mode.status = param;
1068
1069                 dma_addr += period_len;
1070                 buf += period_len;
1071
1072                 i++;
1073         }
1074
1075         sdmac->num_bd = num_periods;
1076         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1077
1078         return &sdmac->desc;
1079 err_out:
1080         sdmac->status = DMA_ERROR;
1081         return NULL;
1082 }
1083
1084 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1085                 unsigned long arg)
1086 {
1087         struct sdma_channel *sdmac = to_sdma_chan(chan);
1088         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1089
1090         switch (cmd) {
1091         case DMA_TERMINATE_ALL:
1092                 sdma_disable_channel(sdmac);
1093                 return 0;
1094         case DMA_SLAVE_CONFIG:
1095                 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1096                         sdmac->per_address = dmaengine_cfg->src_addr;
1097                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1098                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1099                 } else {
1100                         sdmac->per_address = dmaengine_cfg->dst_addr;
1101                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1102                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1103                 }
1104                 return sdma_config_channel(sdmac);
1105         default:
1106                 return -ENOSYS;
1107         }
1108
1109         return -EINVAL;
1110 }
1111
1112 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1113                                             dma_cookie_t cookie,
1114                                             struct dma_tx_state *txstate)
1115 {
1116         struct sdma_channel *sdmac = to_sdma_chan(chan);
1117         dma_cookie_t last_used;
1118
1119         last_used = chan->cookie;
1120
1121         dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1122
1123         return sdmac->status;
1124 }
1125
1126 static void sdma_issue_pending(struct dma_chan *chan)
1127 {
1128         /*
1129          * Nothing to do. We only have a single descriptor
1130          */
1131 }
1132
1133 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1134
1135 static void sdma_add_scripts(struct sdma_engine *sdma,
1136                 const struct sdma_script_start_addrs *addr)
1137 {
1138         s32 *addr_arr = (u32 *)addr;
1139         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1140         int i;
1141
1142         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1143                 if (addr_arr[i] > 0)
1144                         saddr_arr[i] = addr_arr[i];
1145 }
1146
1147 static void sdma_load_firmware(const struct firmware *fw, void *context)
1148 {
1149         struct sdma_engine *sdma = context;
1150         const struct sdma_firmware_header *header;
1151         const struct sdma_script_start_addrs *addr;
1152         unsigned short *ram_code;
1153
1154         if (!fw) {
1155                 dev_err(sdma->dev, "firmware not found\n");
1156                 return;
1157         }
1158
1159         if (fw->size < sizeof(*header))
1160                 goto err_firmware;
1161
1162         header = (struct sdma_firmware_header *)fw->data;
1163
1164         if (header->magic != SDMA_FIRMWARE_MAGIC)
1165                 goto err_firmware;
1166         if (header->ram_code_start + header->ram_code_size > fw->size)
1167                 goto err_firmware;
1168
1169         addr = (void *)header + header->script_addrs_start;
1170         ram_code = (void *)header + header->ram_code_start;
1171
1172         clk_enable(sdma->clk);
1173         /* download the RAM image for SDMA */
1174         sdma_load_script(sdma, ram_code,
1175                         header->ram_code_size,
1176                         addr->ram_code_start_addr);
1177         clk_disable(sdma->clk);
1178
1179         sdma_add_scripts(sdma, addr);
1180
1181         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1182                         header->version_major,
1183                         header->version_minor);
1184
1185 err_firmware:
1186         release_firmware(fw);
1187 }
1188
1189 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1190                 const char *fw_name)
1191 {
1192         int ret;
1193
1194         ret = request_firmware_nowait(THIS_MODULE,
1195                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1196                         GFP_KERNEL, sdma, sdma_load_firmware);
1197
1198         return ret;
1199 }
1200
1201 static int __init sdma_init(struct sdma_engine *sdma)
1202 {
1203         int i, ret;
1204         dma_addr_t ccb_phys;
1205
1206         switch (sdma->devtype) {
1207         case IMX31_SDMA:
1208                 sdma->num_events = 32;
1209                 break;
1210         case IMX35_SDMA:
1211                 sdma->num_events = 48;
1212                 break;
1213         default:
1214                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1215                         sdma->devtype);
1216                 return -ENODEV;
1217         }
1218
1219         clk_enable(sdma->clk);
1220
1221         /* Be sure SDMA has not started yet */
1222         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1223
1224         sdma->channel_control = dma_alloc_coherent(NULL,
1225                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1226                         sizeof(struct sdma_context_data),
1227                         &ccb_phys, GFP_KERNEL);
1228
1229         if (!sdma->channel_control) {
1230                 ret = -ENOMEM;
1231                 goto err_dma_alloc;
1232         }
1233
1234         sdma->context = (void *)sdma->channel_control +
1235                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1236         sdma->context_phys = ccb_phys +
1237                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1238
1239         /* Zero-out the CCB structures array just allocated */
1240         memset(sdma->channel_control, 0,
1241                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1242
1243         /* disable all channels */
1244         for (i = 0; i < sdma->num_events; i++)
1245                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1246
1247         /* All channels have priority 0 */
1248         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1249                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1250
1251         ret = sdma_request_channel(&sdma->channel[0]);
1252         if (ret)
1253                 goto err_dma_alloc;
1254
1255         sdma_config_ownership(&sdma->channel[0], false, true, false);
1256
1257         /* Set Command Channel (Channel Zero) */
1258         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1259
1260         /* Set bits of CONFIG register but with static context switching */
1261         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1262         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1263
1264         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1265
1266         /* Set bits of CONFIG register with given context switching mode */
1267         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1268
1269         /* Initializes channel's priorities */
1270         sdma_set_channel_priority(&sdma->channel[0], 7);
1271
1272         clk_disable(sdma->clk);
1273
1274         return 0;
1275
1276 err_dma_alloc:
1277         clk_disable(sdma->clk);
1278         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1279         return ret;
1280 }
1281
1282 static int __init sdma_probe(struct platform_device *pdev)
1283 {
1284         const struct of_device_id *of_id =
1285                         of_match_device(sdma_dt_ids, &pdev->dev);
1286         struct device_node *np = pdev->dev.of_node;
1287         const char *fw_name;
1288         int ret;
1289         int irq;
1290         struct resource *iores;
1291         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1292         int i;
1293         struct sdma_engine *sdma;
1294         s32 *saddr_arr;
1295
1296         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1297         if (!sdma)
1298                 return -ENOMEM;
1299
1300         mutex_init(&sdma->channel_0_lock);
1301
1302         sdma->dev = &pdev->dev;
1303
1304         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1305         irq = platform_get_irq(pdev, 0);
1306         if (!iores || irq < 0) {
1307                 ret = -EINVAL;
1308                 goto err_irq;
1309         }
1310
1311         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1312                 ret = -EBUSY;
1313                 goto err_request_region;
1314         }
1315
1316         sdma->clk = clk_get(&pdev->dev, NULL);
1317         if (IS_ERR(sdma->clk)) {
1318                 ret = PTR_ERR(sdma->clk);
1319                 goto err_clk;
1320         }
1321
1322         sdma->regs = ioremap(iores->start, resource_size(iores));
1323         if (!sdma->regs) {
1324                 ret = -ENOMEM;
1325                 goto err_ioremap;
1326         }
1327
1328         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1329         if (ret)
1330                 goto err_request_irq;
1331
1332         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1333         if (!sdma->script_addrs) {
1334                 ret = -ENOMEM;
1335                 goto err_alloc;
1336         }
1337
1338         /* initially no scripts available */
1339         saddr_arr = (s32 *)sdma->script_addrs;
1340         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1341                 saddr_arr[i] = -EINVAL;
1342
1343         if (of_id)
1344                 pdev->id_entry = of_id->data;
1345         sdma->devtype = pdev->id_entry->driver_data;
1346
1347         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1348         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1349
1350         INIT_LIST_HEAD(&sdma->dma_device.channels);
1351         /* Initialize channel parameters */
1352         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1353                 struct sdma_channel *sdmac = &sdma->channel[i];
1354
1355                 sdmac->sdma = sdma;
1356                 spin_lock_init(&sdmac->lock);
1357
1358                 sdmac->chan.device = &sdma->dma_device;
1359                 sdmac->channel = i;
1360
1361                 /*
1362                  * Add the channel to the DMAC list. Do not add channel 0 though
1363                  * because we need it internally in the SDMA driver. This also means
1364                  * that channel 0 in dmaengine counting matches sdma channel 1.
1365                  */
1366                 if (i)
1367                         list_add_tail(&sdmac->chan.device_node,
1368                                         &sdma->dma_device.channels);
1369         }
1370
1371         ret = sdma_init(sdma);
1372         if (ret)
1373                 goto err_init;
1374
1375         if (pdata && pdata->script_addrs)
1376                 sdma_add_scripts(sdma, pdata->script_addrs);
1377
1378         if (pdata) {
1379                 sdma_get_firmware(sdma, pdata->fw_name);
1380         } else {
1381                 /*
1382                  * Because that device tree does not encode ROM script address,
1383                  * the RAM script in firmware is mandatory for device tree
1384                  * probe, otherwise it fails.
1385                  */
1386                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1387                                               &fw_name);
1388                 if (ret) {
1389                         dev_err(&pdev->dev, "failed to get firmware name\n");
1390                         goto err_init;
1391                 }
1392
1393                 ret = sdma_get_firmware(sdma, fw_name);
1394                 if (ret) {
1395                         dev_err(&pdev->dev, "failed to get firmware\n");
1396                         goto err_init;
1397                 }
1398         }
1399
1400         sdma->dma_device.dev = &pdev->dev;
1401
1402         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1403         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1404         sdma->dma_device.device_tx_status = sdma_tx_status;
1405         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1406         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1407         sdma->dma_device.device_control = sdma_control;
1408         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1409         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1410         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1411
1412         ret = dma_async_device_register(&sdma->dma_device);
1413         if (ret) {
1414                 dev_err(&pdev->dev, "unable to register\n");
1415                 goto err_init;
1416         }
1417
1418         dev_info(sdma->dev, "initialized\n");
1419
1420         return 0;
1421
1422 err_init:
1423         kfree(sdma->script_addrs);
1424 err_alloc:
1425         free_irq(irq, sdma);
1426 err_request_irq:
1427         iounmap(sdma->regs);
1428 err_ioremap:
1429         clk_put(sdma->clk);
1430 err_clk:
1431         release_mem_region(iores->start, resource_size(iores));
1432 err_request_region:
1433 err_irq:
1434         kfree(sdma);
1435         return ret;
1436 }
1437
1438 static int __exit sdma_remove(struct platform_device *pdev)
1439 {
1440         return -EBUSY;
1441 }
1442
1443 static struct platform_driver sdma_driver = {
1444         .driver         = {
1445                 .name   = "imx-sdma",
1446                 .of_match_table = sdma_dt_ids,
1447         },
1448         .id_table       = sdma_devtypes,
1449         .remove         = __exit_p(sdma_remove),
1450 };
1451
1452 static int __init sdma_module_init(void)
1453 {
1454         return platform_driver_probe(&sdma_driver, sdma_probe);
1455 }
1456 module_init(sdma_module_init);
1457
1458 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1459 MODULE_DESCRIPTION("i.MX SDMA driver");
1460 MODULE_LICENSE("GPL");