drivers/dma/coh901318.c

   1 /*
   2  * driver/dma/coh901318.c
   3  *
   4  * Copyright (C) 2007-2009 ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  * DMA driver for COH 901 318
   7  * Author: Per Friden <per.friden@stericsson.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h> /* printk() */
  13 #include <linux/fs.h> /* everything... */
  14 #include <linux/slab.h> /* kmalloc() */
  15 #include <linux/dmaengine.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/device.h>
  18 #include <linux/irqreturn.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/debugfs.h>
  23 #include <mach/coh901318.h>
  24
  25 #include "coh901318_lli.h"
  26
  27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
  28
  29 #ifdef VERBOSE_DEBUG
  30 #define COH_DBG(x) ({ if (1) x; 0; })
  31 #else
  32 #define COH_DBG(x) ({ if (0) x; 0; })
  33 #endif
  34
  35 struct coh901318_desc {
  36         struct dma_async_tx_descriptor desc;
  37         struct list_head node;
  38         struct scatterlist *sg;
  39         unsigned int sg_len;
  40         struct coh901318_lli *lli;
  41         enum dma_data_direction dir;
  42         unsigned long flags;
  43 };
  44
  45 struct coh901318_base {
  46         struct device *dev;
  47         void __iomem *virtbase;
  48         struct coh901318_pool pool;
  49         struct powersave pm;
  50         struct dma_device dma_slave;
  51         struct dma_device dma_memcpy;
  52         struct coh901318_chan *chans;
  53         struct coh901318_platform *platform;
  54 };
  55
  56 struct coh901318_chan {
  57         spinlock_t lock;
  58         int allocated;
  59         int completed;
  60         int id;
  61         int stopped;
  62
  63         struct work_struct free_work;
  64         struct dma_chan chan;
  65
  66         struct tasklet_struct tasklet;
  67
  68         struct list_head active;
  69         struct list_head queue;
  70         struct list_head free;
  71
  72         unsigned long nbr_active_done;
  73         unsigned long busy;
  74
  75         u32 runtime_addr;
  76         u32 runtime_ctrl;
  77
  78         struct coh901318_base *base;
  79 };
  80
  81 static void coh901318_list_print(struct coh901318_chan *cohc,
  82                                  struct coh901318_lli *lli)
  83 {
  84         struct coh901318_lli *l = lli;
  85         int i = 0;
  86
  87         while (l) {
  88                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
  89                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
  90                          i, l, l->control, l->src_addr, l->dst_addr,
  91                          l->link_addr, l->virt_link_addr);
  92                 i++;
  93                 l = l->virt_link_addr;
  94         }
  95 }
  96
  97 #ifdef CONFIG_DEBUG_FS
  98
  99 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
 100
 101 static struct coh901318_base *debugfs_dma_base;
 102 static struct dentry *dma_dentry;
 103
 104 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
 105 {
 106
 107         file->private_data = inode->i_private;
 108         return 0;
 109 }
 110
 111 static int coh901318_debugfs_read(struct file *file, char __user *buf,
 112                                   size_t count, loff_t *f_pos)
 113 {
 114         u64 started_channels = debugfs_dma_base->pm.started_channels;
 115         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
 116         int i;
 117         int ret = 0;
 118         char *dev_buf;
 119         char *tmp;
 120         int dev_size;
 121
 122         dev_buf = kmalloc(4*1024, GFP_KERNEL);
 123         if (dev_buf == NULL)
 124                 goto err_kmalloc;
 125         tmp = dev_buf;
 126
 127         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
 128
 129         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
 130                 if (started_channels & (1 << i))
 131                         tmp += sprintf(tmp, "channel %d\n", i);
 132
 133         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
 134         dev_size = tmp  - dev_buf;
 135
 136         /* No more to read if offset != 0 */
 137         if (*f_pos > dev_size)
 138                 goto out;
 139
 140         if (count > dev_size - *f_pos)
 141                 count = dev_size - *f_pos;
 142
 143         if (copy_to_user(buf, dev_buf + *f_pos, count))
 144                 ret = -EINVAL;
 145         ret = count;
 146         *f_pos += count;
 147
 148  out:
 149         kfree(dev_buf);
 150         return ret;
 151
 152  err_kmalloc:
 153         return 0;
 154 }
 155
 156 static const struct file_operations coh901318_debugfs_status_operations = {
 157         .owner          = THIS_MODULE,
 158         .open           = coh901318_debugfs_open,
 159         .read           = coh901318_debugfs_read,
 160 };
 161
 162
 163 static int __init init_coh901318_debugfs(void)
 164 {
 165
 166         dma_dentry = debugfs_create_dir("dma", NULL);
 167
 168         (void) debugfs_create_file("status",
 169                                    S_IFREG | S_IRUGO,
 170                                    dma_dentry, NULL,
 171                                    &coh901318_debugfs_status_operations);
 172         return 0;
 173 }
 174
 175 static void __exit exit_coh901318_debugfs(void)
 176 {
 177         debugfs_remove_recursive(dma_dentry);
 178 }
 179
 180 module_init(init_coh901318_debugfs);
 181 module_exit(exit_coh901318_debugfs);
 182 #else
 183
 184 #define COH901318_DEBUGFS_ASSIGN(x, y)
 185
 186 #endif /* CONFIG_DEBUG_FS */
 187
 188 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
 189 {
 190         return container_of(chan, struct coh901318_chan, chan);
 191 }
 192
 193 static inline dma_addr_t
 194 cohc_dev_addr(struct coh901318_chan *cohc)
 195 {
 196         /* Runtime supplied address will take precedence */
 197         if (cohc->runtime_addr)
 198                 return cohc->runtime_addr;
 199         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
 200 }
 201
 202 static inline const struct coh901318_params *
 203 cohc_chan_param(struct coh901318_chan *cohc)
 204 {
 205         return &cohc->base->platform->chan_conf[cohc->id].param;
 206 }
 207
 208 static inline const struct coh_dma_channel *
 209 cohc_chan_conf(struct coh901318_chan *cohc)
 210 {
 211         return &cohc->base->platform->chan_conf[cohc->id];
 212 }
 213
 214 static void enable_powersave(struct coh901318_chan *cohc)
 215 {
 216         unsigned long flags;
 217         struct powersave *pm = &cohc->base->pm;
 218
 219         spin_lock_irqsave(&pm->lock, flags);
 220
 221         pm->started_channels &= ~(1ULL << cohc->id);
 222
 223         if (!pm->started_channels) {
 224                 /* DMA no longer intends to access memory */
 225                 cohc->base->platform->access_memory_state(cohc->base->dev,
 226                                                           false);
 227         }
 228
 229         spin_unlock_irqrestore(&pm->lock, flags);
 230 }
 231 static void disable_powersave(struct coh901318_chan *cohc)
 232 {
 233         unsigned long flags;
 234         struct powersave *pm = &cohc->base->pm;
 235
 236         spin_lock_irqsave(&pm->lock, flags);
 237
 238         if (!pm->started_channels) {
 239                 /* DMA intends to access memory */
 240                 cohc->base->platform->access_memory_state(cohc->base->dev,
 241                                                           true);
 242         }
 243
 244         pm->started_channels |= (1ULL << cohc->id);
 245
 246         spin_unlock_irqrestore(&pm->lock, flags);
 247 }
 248
 249 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
 250 {
 251         int channel = cohc->id;
 252         void __iomem *virtbase = cohc->base->virtbase;
 253
 254         writel(control,
 255                virtbase + COH901318_CX_CTRL +
 256                COH901318_CX_CTRL_SPACING * channel);
 257         return 0;
 258 }
 259
 260 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
 261 {
 262         int channel = cohc->id;
 263         void __iomem *virtbase = cohc->base->virtbase;
 264
 265         writel(conf,
 266                virtbase + COH901318_CX_CFG +
 267                COH901318_CX_CFG_SPACING*channel);
 268         return 0;
 269 }
 270
 271
 272 static int coh901318_start(struct coh901318_chan *cohc)
 273 {
 274         u32 val;
 275         int channel = cohc->id;
 276         void __iomem *virtbase = cohc->base->virtbase;
 277
 278         disable_powersave(cohc);
 279
 280         val = readl(virtbase + COH901318_CX_CFG +
 281                     COH901318_CX_CFG_SPACING * channel);
 282
 283         /* Enable channel */
 284         val |= COH901318_CX_CFG_CH_ENABLE;
 285         writel(val, virtbase + COH901318_CX_CFG +
 286                COH901318_CX_CFG_SPACING * channel);
 287
 288         return 0;
 289 }
 290
 291 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 292                                       struct coh901318_lli *lli)
 293 {
 294         int channel = cohc->id;
 295         void __iomem *virtbase = cohc->base->virtbase;
 296
 297         BUG_ON(readl(virtbase + COH901318_CX_STAT +
 298                      COH901318_CX_STAT_SPACING*channel) &
 299                COH901318_CX_STAT_ACTIVE);
 300
 301         writel(lli->src_addr,
 302                virtbase + COH901318_CX_SRC_ADDR +
 303                COH901318_CX_SRC_ADDR_SPACING * channel);
 304
 305         writel(lli->dst_addr, virtbase +
 306                COH901318_CX_DST_ADDR +
 307                COH901318_CX_DST_ADDR_SPACING * channel);
 308
 309         writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
 310                COH901318_CX_LNK_ADDR_SPACING * channel);
 311
 312         writel(lli->control, virtbase + COH901318_CX_CTRL +
 313                COH901318_CX_CTRL_SPACING * channel);
 314
 315         return 0;
 316 }
 317 static dma_cookie_t
 318 coh901318_assign_cookie(struct coh901318_chan *cohc,
 319                         struct coh901318_desc *cohd)
 320 {
 321         dma_cookie_t cookie = cohc->chan.cookie;
 322
 323         if (++cookie < 0)
 324                 cookie = 1;
 325
 326         cohc->chan.cookie = cookie;
 327         cohd->desc.cookie = cookie;
 328
 329         return cookie;
 330 }
 331
 332 static struct coh901318_desc *
 333 coh901318_desc_get(struct coh901318_chan *cohc)
 334 {
 335         struct coh901318_desc *desc;
 336
 337         if (list_empty(&cohc->free)) {
 338                 /* alloc new desc because we're out of used ones
 339                  * TODO: alloc a pile of descs instead of just one,
 340                  * avoid many small allocations.
 341                  */
 342                 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
 343                 if (desc == NULL)
 344                         goto out;
 345                 INIT_LIST_HEAD(&desc->node);
 346                 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
 347         } else {
 348                 /* Reuse an old desc. */
 349                 desc = list_first_entry(&cohc->free,
 350                                         struct coh901318_desc,
 351                                         node);
 352                 list_del(&desc->node);
 353                 /* Initialize it a bit so it's not insane */
 354                 desc->sg = NULL;
 355                 desc->sg_len = 0;
 356                 desc->desc.callback = NULL;
 357                 desc->desc.callback_param = NULL;
 358         }
 359
 360  out:
 361         return desc;
 362 }
 363
 364 static void
 365 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
 366 {
 367         list_add_tail(&cohd->node, &cohc->free);
 368 }
 369
 370 /* call with irq lock held */
 371 static void
 372 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 373 {
 374         list_add_tail(&desc->node, &cohc->active);
 375 }
 376
 377 static struct coh901318_desc *
 378 coh901318_first_active_get(struct coh901318_chan *cohc)
 379 {
 380         struct coh901318_desc *d;
 381
 382         if (list_empty(&cohc->active))
 383                 return NULL;
 384
 385         d = list_first_entry(&cohc->active,
 386                              struct coh901318_desc,
 387                              node);
 388         return d;
 389 }
 390
 391 static void
 392 coh901318_desc_remove(struct coh901318_desc *cohd)
 393 {
 394         list_del(&cohd->node);
 395 }
 396
 397 static void
 398 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
 399 {
 400         list_add_tail(&desc->node, &cohc->queue);
 401 }
 402
 403 static struct coh901318_desc *
 404 coh901318_first_queued(struct coh901318_chan *cohc)
 405 {
 406         struct coh901318_desc *d;
 407
 408         if (list_empty(&cohc->queue))
 409                 return NULL;
 410
 411         d = list_first_entry(&cohc->queue,
 412                              struct coh901318_desc,
 413                              node);
 414         return d;
 415 }
 416
 417 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
 418 {
 419         struct coh901318_lli *lli = in_lli;
 420         u32 bytes = 0;
 421
 422         while (lli) {
 423                 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
 424                 lli = lli->virt_link_addr;
 425         }
 426         return bytes;
 427 }
 428
 429 /*
 430  * Get the number of bytes left to transfer on this channel,
 431  * it is unwise to call this before stopping the channel for
 432  * absolute measures, but for a rough guess you can still call
 433  * it.
 434  */
 435 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
 436 {
 437         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 438         struct coh901318_desc *cohd;
 439         struct list_head *pos;
 440         unsigned long flags;
 441         u32 left = 0;
 442         int i = 0;
 443
 444         spin_lock_irqsave(&cohc->lock, flags);
 445
 446         /*
 447          * If there are many queued jobs, we iterate and add the
 448          * size of them all. We take a special look on the first
 449          * job though, since it is probably active.
 450          */
 451         list_for_each(pos, &cohc->active) {
 452                 /*
 453                  * The first job in the list will be working on the
 454                  * hardware. The job can be stopped but still active,
 455                  * so that the transfer counter is somewhere inside
 456                  * the buffer.
 457                  */
 458                 cohd = list_entry(pos, struct coh901318_desc, node);
 459
 460                 if (i == 0) {
 461                         struct coh901318_lli *lli;
 462                         dma_addr_t ladd;
 463
 464                         /* Read current transfer count value */
 465                         left = readl(cohc->base->virtbase +
 466                                      COH901318_CX_CTRL +
 467                                      COH901318_CX_CTRL_SPACING * cohc->id) &
 468                                 COH901318_CX_CTRL_TC_VALUE_MASK;
 469
 470                         /* See if the transfer is linked... */
 471                         ladd = readl(cohc->base->virtbase +
 472                                      COH901318_CX_LNK_ADDR +
 473                                      COH901318_CX_LNK_ADDR_SPACING *
 474                                      cohc->id) &
 475                                 ~COH901318_CX_LNK_LINK_IMMEDIATE;
 476                         /* Single transaction */
 477                         if (!ladd)
 478                                 continue;
 479
 480                         /*
 481                          * Linked transaction, follow the lli, find the
 482                          * currently processing lli, and proceed to the next
 483                          */
 484                         lli = cohd->lli;
 485                         while (lli && lli->link_addr != ladd)
 486                                 lli = lli->virt_link_addr;
 487
 488                         if (lli)
 489                                 lli = lli->virt_link_addr;
 490
 491                         /*
 492                          * Follow remaining lli links around to count the total
 493                          * number of bytes left
 494                          */
 495                         left += coh901318_get_bytes_in_lli(lli);
 496                 } else {
 497                         left += coh901318_get_bytes_in_lli(cohd->lli);
 498                 }
 499                 i++;
 500         }
 501
 502         /* Also count bytes in the queued jobs */
 503         list_for_each(pos, &cohc->queue) {
 504                 cohd = list_entry(pos, struct coh901318_desc, node);
 505                 left += coh901318_get_bytes_in_lli(cohd->lli);
 506         }
 507
 508         spin_unlock_irqrestore(&cohc->lock, flags);
 509
 510         return left;
 511 }
 512
 513 /*
 514  * Pauses a transfer without losing data. Enables power save.
 515  * Use this function in conjunction with coh901318_resume.
 516  */
 517 static void coh901318_pause(struct dma_chan *chan)
 518 {
 519         u32 val;
 520         unsigned long flags;
 521         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 522         int channel = cohc->id;
 523         void __iomem *virtbase = cohc->base->virtbase;
 524
 525         spin_lock_irqsave(&cohc->lock, flags);
 526
 527         /* Disable channel in HW */
 528         val = readl(virtbase + COH901318_CX_CFG +
 529                     COH901318_CX_CFG_SPACING * channel);
 530
 531         /* Stopping infinit transfer */
 532         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
 533             (val & COH901318_CX_CFG_CH_ENABLE))
 534                 cohc->stopped = 1;
 535
 536
 537         val &= ~COH901318_CX_CFG_CH_ENABLE;
 538         /* Enable twice, HW bug work around */
 539         writel(val, virtbase + COH901318_CX_CFG +
 540                COH901318_CX_CFG_SPACING * channel);
 541         writel(val, virtbase + COH901318_CX_CFG +
 542                COH901318_CX_CFG_SPACING * channel);
 543
 544         /* Spin-wait for it to actually go inactive */
 545         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
 546                      channel) & COH901318_CX_STAT_ACTIVE)
 547                 cpu_relax();
 548
 549         /* Check if we stopped an active job */
 550         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
 551                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
 552                 cohc->stopped = 1;
 553
 554         enable_powersave(cohc);
 555
 556         spin_unlock_irqrestore(&cohc->lock, flags);
 557 }
 558
 559 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
 560    Power save is handled.
 561 */
 562 static void coh901318_resume(struct dma_chan *chan)
 563 {
 564         u32 val;
 565         unsigned long flags;
 566         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 567         int channel = cohc->id;
 568
 569         spin_lock_irqsave(&cohc->lock, flags);
 570
 571         disable_powersave(cohc);
 572
 573         if (cohc->stopped) {
 574                 /* Enable channel in HW */
 575                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
 576                             COH901318_CX_CFG_SPACING * channel);
 577
 578                 val |= COH901318_CX_CFG_CH_ENABLE;
 579
 580                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
 581                        COH901318_CX_CFG_SPACING*channel);
 582
 583                 cohc->stopped = 0;
 584         }
 585
 586         spin_unlock_irqrestore(&cohc->lock, flags);
 587 }
 588
 589 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 590 {
 591         unsigned int ch_nr = (unsigned int) chan_id;
 592
 593         if (ch_nr == to_coh901318_chan(chan)->id)
 594                 return true;
 595
 596         return false;
 597 }
 598 EXPORT_SYMBOL(coh901318_filter_id);
 599
 600 /*
 601  * DMA channel allocation
 602  */
 603 static int coh901318_config(struct coh901318_chan *cohc,
 604                             struct coh901318_params *param)
 605 {
 606         unsigned long flags;
 607         const struct coh901318_params *p;
 608         int channel = cohc->id;
 609         void __iomem *virtbase = cohc->base->virtbase;
 610
 611         spin_lock_irqsave(&cohc->lock, flags);
 612
 613         if (param)
 614                 p = param;
 615         else
 616                 p = &cohc->base->platform->chan_conf[channel].param;
 617
 618         /* Clear any pending BE or TC interrupt */
 619         if (channel < 32) {
 620                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
 621                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
 622         } else {
 623                 writel(1 << (channel - 32), virtbase +
 624                        COH901318_BE_INT_CLEAR2);
 625                 writel(1 << (channel - 32), virtbase +
 626                        COH901318_TC_INT_CLEAR2);
 627         }
 628
 629         coh901318_set_conf(cohc, p->config);
 630         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
 631
 632         spin_unlock_irqrestore(&cohc->lock, flags);
 633
 634         return 0;
 635 }
 636
 637 /* must lock when calling this function
 638  * start queued jobs, if any
 639  * TODO: start all queued jobs in one go
 640  *
 641  * Returns descriptor if queued job is started otherwise NULL.
 642  * If the queue is empty NULL is returned.
 643  */
 644 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
 645 {
 646         struct coh901318_desc *cohd;
 647
 648         /*
 649          * start queued jobs, if any
 650          * TODO: transmit all queued jobs in one go
 651          */
 652         cohd = coh901318_first_queued(cohc);
 653
 654         if (cohd != NULL) {
 655                 /* Remove from queue */
 656                 coh901318_desc_remove(cohd);
 657                 /* initiate DMA job */
 658                 cohc->busy = 1;
 659
 660                 coh901318_desc_submit(cohc, cohd);
 661
 662                 coh901318_prep_linked_list(cohc, cohd->lli);
 663
 664                 /* start dma job on this channel */
 665                 coh901318_start(cohc);
 666
 667         }
 668
 669         return cohd;
 670 }
 671
 672 /*
 673  * This tasklet is called from the interrupt handler to
 674  * handle each descriptor (DMA job) that is sent to a channel.
 675  */
 676 static void dma_tasklet(unsigned long data)
 677 {
 678         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
 679         struct coh901318_desc *cohd_fin;
 680         unsigned long flags;
 681         dma_async_tx_callback callback;
 682         void *callback_param;
 683
 684         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
 685                  " nbr_active_done %ld\n", __func__,
 686                  cohc->id, cohc->nbr_active_done);
 687
 688         spin_lock_irqsave(&cohc->lock, flags);
 689
 690         /* get first active descriptor entry from list */
 691         cohd_fin = coh901318_first_active_get(cohc);
 692
 693         if (cohd_fin == NULL)
 694                 goto err;
 695
 696         /* locate callback to client */
 697         callback = cohd_fin->desc.callback;
 698         callback_param = cohd_fin->desc.callback_param;
 699
 700         /* sign this job as completed on the channel */
 701         cohc->completed = cohd_fin->desc.cookie;
 702
 703         /* release the lli allocation and remove the descriptor */
 704         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
 705
 706         /* return desc to free-list */
 707         coh901318_desc_remove(cohd_fin);
 708         coh901318_desc_free(cohc, cohd_fin);
 709
 710         spin_unlock_irqrestore(&cohc->lock, flags);
 711
 712         /* Call the callback when we're done */
 713         if (callback)
 714                 callback(callback_param);
 715
 716         spin_lock_irqsave(&cohc->lock, flags);
 717
 718         /*
 719          * If another interrupt fired while the tasklet was scheduling,
 720          * we don't get called twice, so we have this number of active
 721          * counter that keep track of the number of IRQs expected to
 722          * be handled for this channel. If there happen to be more than
 723          * one IRQ to be ack:ed, we simply schedule this tasklet again.
 724          */
 725         cohc->nbr_active_done--;
 726         if (cohc->nbr_active_done) {
 727                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
 728                         "came in while we were scheduling this tasklet\n");
 729                 if (cohc_chan_conf(cohc)->priority_high)
 730                         tasklet_hi_schedule(&cohc->tasklet);
 731                 else
 732                         tasklet_schedule(&cohc->tasklet);
 733         }
 734
 735         spin_unlock_irqrestore(&cohc->lock, flags);
 736
 737         return;
 738
 739  err:
 740         spin_unlock_irqrestore(&cohc->lock, flags);
 741         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
 742 }
 743
 744
 745 /* called from interrupt context */
 746 static void dma_tc_handle(struct coh901318_chan *cohc)
 747 {
 748         /*
 749          * If the channel is not allocated, then we shouldn't have
 750          * any TC interrupts on it.
 751          */
 752         if (!cohc->allocated) {
 753                 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
 754                         "unallocated channel\n");
 755                 return;
 756         }
 757
 758         spin_lock(&cohc->lock);
 759
 760         /*
 761          * When we reach this point, at least one queue item
 762          * should have been moved over from cohc->queue to
 763          * cohc->active and run to completion, that is why we're
 764          * getting a terminal count interrupt is it not?
 765          * If you get this BUG() the most probable cause is that
 766          * the individual nodes in the lli chain have IRQ enabled,
 767          * so check your platform config for lli chain ctrl.
 768          */
 769         BUG_ON(list_empty(&cohc->active));
 770
 771         cohc->nbr_active_done++;
 772
 773         /*
 774          * This attempt to take a job from cohc->queue, put it
 775          * into cohc->active and start it.
 776          */
 777         if (coh901318_queue_start(cohc) == NULL)
 778                 cohc->busy = 0;
 779
 780         spin_unlock(&cohc->lock);
 781
 782         /*
 783          * This tasklet will remove items from cohc->active
 784          * and thus terminates them.
 785          */
 786         if (cohc_chan_conf(cohc)->priority_high)
 787                 tasklet_hi_schedule(&cohc->tasklet);
 788         else
 789                 tasklet_schedule(&cohc->tasklet);
 790 }
 791
 792
 793 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 794 {
 795         u32 status1;
 796         u32 status2;
 797         int i;
 798         int ch;
 799         struct coh901318_base *base  = dev_id;
 800         struct coh901318_chan *cohc;
 801         void __iomem *virtbase = base->virtbase;
 802
 803         status1 = readl(virtbase + COH901318_INT_STATUS1);
 804         status2 = readl(virtbase + COH901318_INT_STATUS2);
 805
 806         if (unlikely(status1 == 0 && status2 == 0)) {
 807                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
 808                 return IRQ_HANDLED;
 809         }
 810
 811         /* TODO: consider handle IRQ in tasklet here to
 812          *       minimize interrupt latency */
 813
 814         /* Check the first 32 DMA channels for IRQ */
 815         while (status1) {
 816                 /* Find first bit set, return as a number. */
 817                 i = ffs(status1) - 1;
 818                 ch = i;
 819
 820                 cohc = &base->chans[ch];
 821                 spin_lock(&cohc->lock);
 822
 823                 /* Mask off this bit */
 824                 status1 &= ~(1 << i);
 825                 /* Check the individual channel bits */
 826                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
 827                         dev_crit(COHC_2_DEV(cohc),
 828                                  "DMA bus error on channel %d!\n", ch);
 829                         BUG_ON(1);
 830                         /* Clear BE interrupt */
 831                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
 832                 } else {
 833                         /* Caused by TC, really? */
 834                         if (unlikely(!test_bit(i, virtbase +
 835                                                COH901318_TC_INT_STATUS1))) {
 836                                 dev_warn(COHC_2_DEV(cohc),
 837                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 838                                 /* Clear TC interrupt */
 839                                 BUG_ON(1);
 840                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 841                         } else {
 842                                 /* Enable powersave if transfer has finished */
 843                                 if (!(readl(virtbase + COH901318_CX_STAT +
 844                                             COH901318_CX_STAT_SPACING*ch) &
 845                                       COH901318_CX_STAT_ENABLED)) {
 846                                         enable_powersave(cohc);
 847                                 }
 848
 849                                 /* Must clear TC interrupt before calling
 850                                  * dma_tc_handle
 851                                  * in case tc_handle initate a new dma job
 852                                  */
 853                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
 854
 855                                 dma_tc_handle(cohc);
 856                         }
 857                 }
 858                 spin_unlock(&cohc->lock);
 859         }
 860
 861         /* Check the remaining 32 DMA channels for IRQ */
 862         while (status2) {
 863                 /* Find first bit set, return as a number. */
 864                 i = ffs(status2) - 1;
 865                 ch = i + 32;
 866                 cohc = &base->chans[ch];
 867                 spin_lock(&cohc->lock);
 868
 869                 /* Mask off this bit */
 870                 status2 &= ~(1 << i);
 871                 /* Check the individual channel bits */
 872                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
 873                         dev_crit(COHC_2_DEV(cohc),
 874                                  "DMA bus error on channel %d!\n", ch);
 875                         /* Clear BE interrupt */
 876                         BUG_ON(1);
 877                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
 878                 } else {
 879                         /* Caused by TC, really? */
 880                         if (unlikely(!test_bit(i, virtbase +
 881                                                COH901318_TC_INT_STATUS2))) {
 882                                 dev_warn(COHC_2_DEV(cohc),
 883                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
 884                                 /* Clear TC interrupt */
 885                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 886                                 BUG_ON(1);
 887                         } else {
 888                                 /* Enable powersave if transfer has finished */
 889                                 if (!(readl(virtbase + COH901318_CX_STAT +
 890                                             COH901318_CX_STAT_SPACING*ch) &
 891                                       COH901318_CX_STAT_ENABLED)) {
 892                                         enable_powersave(cohc);
 893                                 }
 894                                 /* Must clear TC interrupt before calling
 895                                  * dma_tc_handle
 896                                  * in case tc_handle initate a new dma job
 897                                  */
 898                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
 899
 900                                 dma_tc_handle(cohc);
 901                         }
 902                 }
 903                 spin_unlock(&cohc->lock);
 904         }
 905
 906         return IRQ_HANDLED;
 907 }
 908
 909 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 910 {
 911         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 912         unsigned long flags;
 913
 914         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
 915                  __func__, cohc->id);
 916
 917         if (chan->client_count > 1)
 918                 return -EBUSY;
 919
 920         spin_lock_irqsave(&cohc->lock, flags);
 921
 922         coh901318_config(cohc, NULL);
 923
 924         cohc->allocated = 1;
 925         cohc->completed = chan->cookie = 1;
 926
 927         spin_unlock_irqrestore(&cohc->lock, flags);
 928
 929         return 1;
 930 }
 931
 932 static void
 933 coh901318_free_chan_resources(struct dma_chan *chan)
 934 {
 935         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
 936         int channel = cohc->id;
 937         unsigned long flags;
 938
 939         spin_lock_irqsave(&cohc->lock, flags);
 940
 941         /* Disable HW */
 942         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
 943                COH901318_CX_CFG_SPACING*channel);
 944         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
 945                COH901318_CX_CTRL_SPACING*channel);
 946
 947         cohc->allocated = 0;
 948
 949         spin_unlock_irqrestore(&cohc->lock, flags);
 950
 951         chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
 952 }
 953
 954
 955 static dma_cookie_t
 956 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 957 {
 958         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
 959                                                    desc);
 960         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 961         unsigned long flags;
 962
 963         spin_lock_irqsave(&cohc->lock, flags);
 964
 965         tx->cookie = coh901318_assign_cookie(cohc, cohd);
 966
 967         coh901318_desc_queue(cohc, cohd);
 968
 969         spin_unlock_irqrestore(&cohc->lock, flags);
 970
 971         return tx->cookie;
 972 }
 973
 974 static struct dma_async_tx_descriptor *
 975 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 976                       size_t size, unsigned long flags)
 977 {
 978         struct coh901318_lli *lli;
 979         struct coh901318_desc *cohd;
 980         unsigned long flg;
 981         struct coh901318_chan *cohc = to_coh901318_chan(chan);
 982         int lli_len;
 983         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
 984         int ret;
 985
 986         spin_lock_irqsave(&cohc->lock, flg);
 987
 988         dev_vdbg(COHC_2_DEV(cohc),
 989                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
 990                  __func__, cohc->id, src, dest, size);
 991
 992         if (flags & DMA_PREP_INTERRUPT)
 993                 /* Trigger interrupt after last lli */
 994                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
 995
 996         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
 997         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
 998                 lli_len++;
 999
1000         lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
1001
1002         if (lli == NULL)
1003                 goto err;
1004
1005         ret = coh901318_lli_fill_memcpy(
1006                 &cohc->base->pool, lli, src, size, dest,
1007                 cohc_chan_param(cohc)->ctrl_lli_chained,
1008                 ctrl_last);
1009         if (ret)
1010                 goto err;
1011
1012         COH_DBG(coh901318_list_print(cohc, lli));
1013
1014         /* Pick a descriptor to handle this transfer */
1015         cohd = coh901318_desc_get(cohc);
1016         cohd->lli = lli;
1017         cohd->flags = flags;
1018         cohd->desc.tx_submit = coh901318_tx_submit;
1019
1020         spin_unlock_irqrestore(&cohc->lock, flg);
1021
1022         return &cohd->desc;
1023  err:
1024         spin_unlock_irqrestore(&cohc->lock, flg);
1025         return NULL;
1026 }
1027
1028 static struct dma_async_tx_descriptor *
1029 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1030                         unsigned int sg_len, enum dma_data_direction direction,
1031                         unsigned long flags)
1032 {
1033         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1034         struct coh901318_lli *lli;
1035         struct coh901318_desc *cohd;
1036         const struct coh901318_params *params;
1037         struct scatterlist *sg;
1038         int len = 0;
1039         int size;
1040         int i;
1041         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1042         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1043         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1044         u32 config;
1045         unsigned long flg;
1046         int ret;
1047
1048         if (!sgl)
1049                 goto out;
1050         if (sgl->length == 0)
1051                 goto out;
1052
1053         spin_lock_irqsave(&cohc->lock, flg);
1054
1055         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1056                  __func__, sg_len, direction);
1057
1058         if (flags & DMA_PREP_INTERRUPT)
1059                 /* Trigger interrupt after last lli */
1060                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1061
1062         params = cohc_chan_param(cohc);
1063         config = params->config;
1064         /*
1065          * Add runtime-specific control on top, make
1066          * sure the bits you set per peripheral channel are
1067          * cleared in the default config from the platform.
1068          */
1069         ctrl_chained |= cohc->runtime_ctrl;
1070         ctrl_last |= cohc->runtime_ctrl;
1071         ctrl |= cohc->runtime_ctrl;
1072
1073         if (direction == DMA_TO_DEVICE) {
1074                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1075                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1076
1077                 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1078                 ctrl_chained |= tx_flags;
1079                 ctrl_last |= tx_flags;
1080                 ctrl |= tx_flags;
1081         } else if (direction == DMA_FROM_DEVICE) {
1082                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1083                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1084
1085                 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1086                 ctrl_chained |= rx_flags;
1087                 ctrl_last |= rx_flags;
1088                 ctrl |= rx_flags;
1089         } else
1090                 goto err_direction;
1091
1092         coh901318_set_conf(cohc, config);
1093
1094         /* The dma only supports transmitting packages up to
1095          * MAX_DMA_PACKET_SIZE. Calculate to total number of
1096          * dma elemts required to send the entire sg list
1097          */
1098         for_each_sg(sgl, sg, sg_len, i) {
1099                 unsigned int factor;
1100                 size = sg_dma_len(sg);
1101
1102                 if (size <= MAX_DMA_PACKET_SIZE) {
1103                         len++;
1104                         continue;
1105                 }
1106
1107                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1108                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1109                         factor++;
1110
1111                 len += factor;
1112         }
1113
1114         pr_debug("Allocate %d lli:s for this transfer\n", len);
1115         lli = coh901318_lli_alloc(&cohc->base->pool, len);
1116
1117         if (lli == NULL)
1118                 goto err_dma_alloc;
1119
1120         /* initiate allocated lli list */
1121         ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1122                                     cohc_dev_addr(cohc),
1123                                     ctrl_chained,
1124                                     ctrl,
1125                                     ctrl_last,
1126                                     direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1127         if (ret)
1128                 goto err_lli_fill;
1129
1130         /*
1131          * Set the default ctrl for the channel to the one from the lli,
1132          * things may have changed due to odd buffer alignment etc.
1133          */
1134         coh901318_set_ctrl(cohc, lli->control);
1135
1136         COH_DBG(coh901318_list_print(cohc, lli));
1137
1138         /* Pick a descriptor to handle this transfer */
1139         cohd = coh901318_desc_get(cohc);
1140         cohd->dir = direction;
1141         cohd->flags = flags;
1142         cohd->desc.tx_submit = coh901318_tx_submit;
1143         cohd->lli = lli;
1144
1145         spin_unlock_irqrestore(&cohc->lock, flg);
1146
1147         return &cohd->desc;
1148  err_lli_fill:
1149  err_dma_alloc:
1150  err_direction:
1151         spin_unlock_irqrestore(&cohc->lock, flg);
1152  out:
1153         return NULL;
1154 }
1155
1156 static enum dma_status
1157 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1158                  struct dma_tx_state *txstate)
1159 {
1160         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1161         dma_cookie_t last_used;
1162         dma_cookie_t last_complete;
1163         int ret;
1164
1165         last_complete = cohc->completed;
1166         last_used = chan->cookie;
1167
1168         ret = dma_async_is_complete(cookie, last_complete, last_used);
1169
1170         dma_set_tx_state(txstate, last_complete, last_used,
1171                          coh901318_get_bytes_left(chan));
1172         if (ret == DMA_IN_PROGRESS && cohc->stopped)
1173                 ret = DMA_PAUSED;
1174
1175         return ret;
1176 }
1177
1178 static void
1179 coh901318_issue_pending(struct dma_chan *chan)
1180 {
1181         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1182         unsigned long flags;
1183
1184         spin_lock_irqsave(&cohc->lock, flags);
1185
1186         /*
1187          * Busy means that pending jobs are already being processed,
1188          * and then there is no point in starting the queue: the
1189          * terminal count interrupt on the channel will take the next
1190          * job on the queue and execute it anyway.
1191          */
1192         if (!cohc->busy)
1193                 coh901318_queue_start(cohc);
1194
1195         spin_unlock_irqrestore(&cohc->lock, flags);
1196 }
1197
1198 /*
1199  * Here we wrap in the runtime dma control interface
1200  */
1201 struct burst_table {
1202         int burst_8bit;
1203         int burst_16bit;
1204         int burst_32bit;
1205         u32 reg;
1206 };
1207
1208 static const struct burst_table burst_sizes[] = {
1209         {
1210                 .burst_8bit = 64,
1211                 .burst_16bit = 32,
1212                 .burst_32bit = 16,
1213                 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1214         },
1215         {
1216                 .burst_8bit = 48,
1217                 .burst_16bit = 24,
1218                 .burst_32bit = 12,
1219                 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1220         },
1221         {
1222                 .burst_8bit = 32,
1223                 .burst_16bit = 16,
1224                 .burst_32bit = 8,
1225                 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1226         },
1227         {
1228                 .burst_8bit = 16,
1229                 .burst_16bit = 8,
1230                 .burst_32bit = 4,
1231                 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1232         },
1233         {
1234                 .burst_8bit = 8,
1235                 .burst_16bit = 4,
1236                 .burst_32bit = 2,
1237                 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1238         },
1239         {
1240                 .burst_8bit = 4,
1241                 .burst_16bit = 2,
1242                 .burst_32bit = 1,
1243                 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1244         },
1245         {
1246                 .burst_8bit = 2,
1247                 .burst_16bit = 1,
1248                 .burst_32bit = 0,
1249                 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1250         },
1251         {
1252                 .burst_8bit = 1,
1253                 .burst_16bit = 0,
1254                 .burst_32bit = 0,
1255                 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1256         },
1257 };
1258
1259 static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1260                         struct dma_slave_config *config)
1261 {
1262         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1263         dma_addr_t addr;
1264         enum dma_slave_buswidth addr_width;
1265         u32 maxburst;
1266         u32 runtime_ctrl = 0;
1267         int i = 0;
1268
1269         /* We only support mem to per or per to mem transfers */
1270         if (config->direction == DMA_FROM_DEVICE) {
1271                 addr = config->src_addr;
1272                 addr_width = config->src_addr_width;
1273                 maxburst = config->src_maxburst;
1274         } else if (config->direction == DMA_TO_DEVICE) {
1275                 addr = config->dst_addr;
1276                 addr_width = config->dst_addr_width;
1277                 maxburst = config->dst_maxburst;
1278         } else {
1279                 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1280                 return;
1281         }
1282
1283         dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1284                 addr_width);
1285         switch (addr_width)  {
1286         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1287                 runtime_ctrl |=
1288                         COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1289                         COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1290
1291                 while (i < ARRAY_SIZE(burst_sizes)) {
1292                         if (burst_sizes[i].burst_8bit <= maxburst)
1293                                 break;
1294                         i++;
1295                 }
1296
1297                 break;
1298         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1299                 runtime_ctrl |=
1300                         COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1301                         COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1302
1303                 while (i < ARRAY_SIZE(burst_sizes)) {
1304                         if (burst_sizes[i].burst_16bit <= maxburst)
1305                                 break;
1306                         i++;
1307                 }
1308
1309                 break;
1310         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1311                 /* Direction doesn't matter here, it's 32/32 bits */
1312                 runtime_ctrl |=
1313                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1314                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1315
1316                 while (i < ARRAY_SIZE(burst_sizes)) {
1317                         if (burst_sizes[i].burst_32bit <= maxburst)
1318                                 break;
1319                         i++;
1320                 }
1321
1322                 break;
1323         default:
1324                 dev_err(COHC_2_DEV(cohc),
1325                         "bad runtimeconfig: alien address width\n");
1326                 return;
1327         }
1328
1329         runtime_ctrl |= burst_sizes[i].reg;
1330         dev_dbg(COHC_2_DEV(cohc),
1331                 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1332                 burst_sizes[i].burst_8bit, addr_width, maxburst);
1333
1334         cohc->runtime_addr = addr;
1335         cohc->runtime_ctrl = runtime_ctrl;
1336 }
1337
1338 static int
1339 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1340                   unsigned long arg)
1341 {
1342         unsigned long flags;
1343         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1344         struct coh901318_desc *cohd;
1345         void __iomem *virtbase = cohc->base->virtbase;
1346
1347         if (cmd == DMA_SLAVE_CONFIG) {
1348                 struct dma_slave_config *config =
1349                         (struct dma_slave_config *) arg;
1350
1351                 coh901318_dma_set_runtimeconfig(chan, config);
1352                 return 0;
1353           }
1354
1355         if (cmd == DMA_PAUSE) {
1356                 coh901318_pause(chan);
1357                 return 0;
1358         }
1359
1360         if (cmd == DMA_RESUME) {
1361                 coh901318_resume(chan);
1362                 return 0;
1363         }
1364
1365         if (cmd != DMA_TERMINATE_ALL)
1366                 return -ENXIO;
1367
1368         /* The remainder of this function terminates the transfer */
1369         coh901318_pause(chan);
1370         spin_lock_irqsave(&cohc->lock, flags);
1371
1372         /* Clear any pending BE or TC interrupt */
1373         if (cohc->id < 32) {
1374                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1375                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1376         } else {
1377                 writel(1 << (cohc->id - 32), virtbase +
1378                        COH901318_BE_INT_CLEAR2);
1379                 writel(1 << (cohc->id - 32), virtbase +
1380                        COH901318_TC_INT_CLEAR2);
1381         }
1382
1383         enable_powersave(cohc);
1384
1385         while ((cohd = coh901318_first_active_get(cohc))) {
1386                 /* release the lli allocation*/
1387                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1388
1389                 /* return desc to free-list */
1390                 coh901318_desc_remove(cohd);
1391                 coh901318_desc_free(cohc, cohd);
1392         }
1393
1394         while ((cohd = coh901318_first_queued(cohc))) {
1395                 /* release the lli allocation*/
1396                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1397
1398                 /* return desc to free-list */
1399                 coh901318_desc_remove(cohd);
1400                 coh901318_desc_free(cohc, cohd);
1401         }
1402
1403
1404         cohc->nbr_active_done = 0;
1405         cohc->busy = 0;
1406
1407         spin_unlock_irqrestore(&cohc->lock, flags);
1408
1409         return 0;
1410 }
1411
1412 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1413                          struct coh901318_base *base)
1414 {
1415         int chans_i;
1416         int i = 0;
1417         struct coh901318_chan *cohc;
1418
1419         INIT_LIST_HEAD(&dma->channels);
1420
1421         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1422                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1423                         cohc = &base->chans[i];
1424
1425                         cohc->base = base;
1426                         cohc->chan.device = dma;
1427                         cohc->id = i;
1428
1429                         /* TODO: do we really need this lock if only one
1430                          * client is connected to each channel?
1431                          */
1432
1433                         spin_lock_init(&cohc->lock);
1434
1435                         cohc->nbr_active_done = 0;
1436                         cohc->busy = 0;
1437                         INIT_LIST_HEAD(&cohc->free);
1438                         INIT_LIST_HEAD(&cohc->active);
1439                         INIT_LIST_HEAD(&cohc->queue);
1440
1441                         tasklet_init(&cohc->tasklet, dma_tasklet,
1442                                      (unsigned long) cohc);
1443
1444                         list_add_tail(&cohc->chan.device_node,
1445                                       &dma->channels);
1446                 }
1447         }
1448 }
1449
1450 static int __init coh901318_probe(struct platform_device *pdev)
1451 {
1452         int err = 0;
1453         struct coh901318_platform *pdata;
1454         struct coh901318_base *base;
1455         int irq;
1456         struct resource *io;
1457
1458         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1459         if (!io)
1460                 goto err_get_resource;
1461
1462         /* Map DMA controller registers to virtual memory */
1463         if (request_mem_region(io->start,
1464                                resource_size(io),
1465                                pdev->dev.driver->name) == NULL) {
1466                 err = -EBUSY;
1467                 goto err_request_mem;
1468         }
1469
1470         pdata = pdev->dev.platform_data;
1471         if (!pdata)
1472                 goto err_no_platformdata;
1473
1474         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1475                        pdata->max_channels *
1476                        sizeof(struct coh901318_chan),
1477                        GFP_KERNEL);
1478         if (!base)
1479                 goto err_alloc_coh_dma_channels;
1480
1481         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1482
1483         base->virtbase = ioremap(io->start, resource_size(io));
1484         if (!base->virtbase) {
1485                 err = -ENOMEM;
1486                 goto err_no_ioremap;
1487         }
1488
1489         base->dev = &pdev->dev;
1490         base->platform = pdata;
1491         spin_lock_init(&base->pm.lock);
1492         base->pm.started_channels = 0;
1493
1494         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1495
1496         platform_set_drvdata(pdev, base);
1497
1498         irq = platform_get_irq(pdev, 0);
1499         if (irq < 0)
1500                 goto err_no_irq;
1501
1502         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1503                           "coh901318", base);
1504         if (err) {
1505                 dev_crit(&pdev->dev,
1506                          "Cannot allocate IRQ for DMA controller!\n");
1507                 goto err_request_irq;
1508         }
1509
1510         err = coh901318_pool_create(&base->pool, &pdev->dev,
1511                                     sizeof(struct coh901318_lli),
1512                                     32);
1513         if (err)
1514                 goto err_pool_create;
1515
1516         /* init channels for device transfers */
1517         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1518                             base);
1519
1520         dma_cap_zero(base->dma_slave.cap_mask);
1521         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1522
1523         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1524         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1525         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1526         base->dma_slave.device_tx_status = coh901318_tx_status;
1527         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1528         base->dma_slave.device_control = coh901318_control;
1529         base->dma_slave.dev = &pdev->dev;
1530
1531         err = dma_async_device_register(&base->dma_slave);
1532
1533         if (err)
1534                 goto err_register_slave;
1535
1536         /* init channels for memcpy */
1537         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1538                             base);
1539
1540         dma_cap_zero(base->dma_memcpy.cap_mask);
1541         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1542
1543         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1544         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1545         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1546         base->dma_memcpy.device_tx_status = coh901318_tx_status;
1547         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1548         base->dma_memcpy.device_control = coh901318_control;
1549         base->dma_memcpy.dev = &pdev->dev;
1550         /*
1551          * This controller can only access address at even 32bit boundaries,
1552          * i.e. 2^2
1553          */
1554         base->dma_memcpy.copy_align = 2;
1555         err = dma_async_device_register(&base->dma_memcpy);
1556
1557         if (err)
1558                 goto err_register_memcpy;
1559
1560         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1561                 (u32) base->virtbase);
1562
1563         return err;
1564
1565  err_register_memcpy:
1566         dma_async_device_unregister(&base->dma_slave);
1567  err_register_slave:
1568         coh901318_pool_destroy(&base->pool);
1569  err_pool_create:
1570         free_irq(platform_get_irq(pdev, 0), base);
1571  err_request_irq:
1572  err_no_irq:
1573         iounmap(base->virtbase);
1574  err_no_ioremap:
1575         kfree(base);
1576  err_alloc_coh_dma_channels:
1577  err_no_platformdata:
1578         release_mem_region(pdev->resource->start,
1579                            resource_size(pdev->resource));
1580  err_request_mem:
1581  err_get_resource:
1582         return err;
1583 }
1584
1585 static int __exit coh901318_remove(struct platform_device *pdev)
1586 {
1587         struct coh901318_base *base = platform_get_drvdata(pdev);
1588
1589         dma_async_device_unregister(&base->dma_memcpy);
1590         dma_async_device_unregister(&base->dma_slave);
1591         coh901318_pool_destroy(&base->pool);
1592         free_irq(platform_get_irq(pdev, 0), base);
1593         iounmap(base->virtbase);
1594         kfree(base);
1595         release_mem_region(pdev->resource->start,
1596                            resource_size(pdev->resource));
1597         return 0;
1598 }
1599
1600
1601 static struct platform_driver coh901318_driver = {
1602         .remove = __exit_p(coh901318_remove),
1603         .driver = {
1604                 .name   = "coh901318",
1605         },
1606 };
1607
1608 int __init coh901318_init(void)
1609 {
1610         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1611 }
1612 subsys_initcall(coh901318_init);
1613
1614 void __exit coh901318_exit(void)
1615 {
1616         platform_driver_unregister(&coh901318_driver);
1617 }
1618 module_exit(coh901318_exit);
1619
1620 MODULE_LICENSE("GPL");
1621 MODULE_AUTHOR("Per Friden");