2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/dmapool.h>
84 #include <linux/dmaengine.h>
85 #include <linux/amba/bus.h>
86 #include <linux/amba/pl08x.h>
87 #include <linux/debugfs.h>
88 #include <linux/seq_file.h>
90 #include <asm/hardware/pl080.h>
92 #define DRIVER_NAME "pl08xdmac"
95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters or not.
105 * PL08X private data structures
106 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
107 * start & end do not - their bus bit info is in cctl. Also note that these
108 * are fixed 32-bit quantities.
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
129 * @mem_buses: set to indicate memory transfers on AHB2.
130 * @lock: a spinlock for this struct
132 struct pl08x_driver_data {
133 struct dma_device slave;
134 struct dma_device memcpy;
136 struct amba_device *adev;
137 const struct vendor_data *vd;
138 struct pl08x_platform_data *pd;
139 struct pl08x_phy_chan *phy_chans;
140 struct dma_pool *pool;
148 * PL08X specific defines
152 * Memory boundaries: the manual for PL08x says that the controller
153 * cannot read past a 1KiB boundary, so these defines are used to
154 * create transfer LLIs that do not cross such boundaries.
156 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
157 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
159 /* Size (bytes) of each LLI buffer allocated for one transfer */
160 # define PL08X_LLI_TSFR_SIZE 0x2000
162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
163 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
164 #define PL08X_ALIGN 8
166 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
168 return container_of(chan, struct pl08x_dma_chan, chan);
171 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
173 return container_of(tx, struct pl08x_txd, tx);
177 * Physical channel handling
180 /* Whether a certain channel is busy or not */
181 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
185 val = readl(ch->base + PL080_CH_CONFIG);
186 return val & PL080_CONFIG_ACTIVE;
190 * Set the initial DMA register values i.e. those for the first LLI
191 * The next LLI pointer and the configuration interrupt bit have
192 * been set when the LLIs were constructed. Poke them into the hardware
193 * and start the transfer.
195 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
196 struct pl08x_txd *txd)
198 struct pl08x_driver_data *pl08x = plchan->host;
199 struct pl08x_phy_chan *phychan = plchan->phychan;
200 struct pl08x_lli *lli = &txd->llis_va[0];
205 /* Wait for channel inactive */
206 while (pl08x_phy_channel_busy(phychan))
209 dev_vdbg(&pl08x->adev->dev,
210 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
211 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
212 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
215 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
216 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
217 writel(lli->lli, phychan->base + PL080_CH_LLI);
218 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
219 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
221 /* Enable the DMA channel */
222 /* Do not access config register until channel shows as disabled */
223 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
226 /* Do not access config register until channel shows as inactive */
227 val = readl(phychan->base + PL080_CH_CONFIG);
228 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
229 val = readl(phychan->base + PL080_CH_CONFIG);
231 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
235 * Pause the channel by setting the HALT bit.
237 * For M->P transfers, pause the DMAC first and then stop the peripheral -
238 * the FIFO can only drain if the peripheral is still requesting data.
239 * (note: this can still timeout if the DMAC FIFO never drains of data.)
241 * For P->M transfers, disable the peripheral first to stop it filling
242 * the DMAC FIFO, and then pause the DMAC.
244 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
249 /* Set the HALT bit and wait for the FIFO to drain */
250 val = readl(ch->base + PL080_CH_CONFIG);
251 val |= PL080_CONFIG_HALT;
252 writel(val, ch->base + PL080_CH_CONFIG);
254 /* Wait for channel inactive */
255 for (timeout = 1000; timeout; timeout--) {
256 if (!pl08x_phy_channel_busy(ch))
260 if (pl08x_phy_channel_busy(ch))
261 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
264 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
268 /* Clear the HALT bit */
269 val = readl(ch->base + PL080_CH_CONFIG);
270 val &= ~PL080_CONFIG_HALT;
271 writel(val, ch->base + PL080_CH_CONFIG);
276 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
277 * clears any pending interrupt status. This should not be used for
278 * an on-going transfer, but as a method of shutting down a channel
279 * (eg, when it's no longer used) or terminating a transfer.
281 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
282 struct pl08x_phy_chan *ch)
284 u32 val = readl(ch->base + PL080_CH_CONFIG);
286 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
287 PL080_CONFIG_TC_IRQ_MASK);
289 writel(val, ch->base + PL080_CH_CONFIG);
291 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
292 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
295 static inline u32 get_bytes_in_cctl(u32 cctl)
297 /* The source width defines the number of bytes */
298 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
300 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
301 case PL080_WIDTH_8BIT:
303 case PL080_WIDTH_16BIT:
306 case PL080_WIDTH_32BIT:
313 /* The channel should be paused when calling this */
314 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
316 struct pl08x_phy_chan *ch;
317 struct pl08x_txd *txd;
321 spin_lock_irqsave(&plchan->lock, flags);
322 ch = plchan->phychan;
326 * Follow the LLIs to get the number of remaining
327 * bytes in the currently active transaction.
330 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
332 /* First get the remaining bytes in the active transfer */
333 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
336 struct pl08x_lli *llis_va = txd->llis_va;
337 dma_addr_t llis_bus = txd->llis_bus;
340 BUG_ON(clli < llis_bus || clli >= llis_bus +
341 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
344 * Locate the next LLI - as this is an array,
345 * it's simple maths to find.
347 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
349 for (; index < MAX_NUM_TSFR_LLIS; index++) {
350 bytes += get_bytes_in_cctl(llis_va[index].cctl);
353 * A LLI pointer of 0 terminates the LLI list
355 if (!llis_va[index].lli)
361 /* Sum up all queued transactions */
362 if (!list_empty(&plchan->pend_list)) {
363 struct pl08x_txd *txdi;
364 list_for_each_entry(txdi, &plchan->pend_list, node) {
369 spin_unlock_irqrestore(&plchan->lock, flags);
375 * Allocate a physical channel for a virtual channel
377 * Try to locate a physical channel to be used for this transfer. If all
378 * are taken return NULL and the requester will have to cope by using
379 * some fallback PIO mode or retrying later.
381 static struct pl08x_phy_chan *
382 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
383 struct pl08x_dma_chan *virt_chan)
385 struct pl08x_phy_chan *ch = NULL;
389 for (i = 0; i < pl08x->vd->channels; i++) {
390 ch = &pl08x->phy_chans[i];
392 spin_lock_irqsave(&ch->lock, flags);
395 ch->serving = virt_chan;
397 spin_unlock_irqrestore(&ch->lock, flags);
401 spin_unlock_irqrestore(&ch->lock, flags);
404 if (i == pl08x->vd->channels) {
405 /* No physical channel available, cope with it */
412 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
413 struct pl08x_phy_chan *ch)
417 spin_lock_irqsave(&ch->lock, flags);
419 /* Stop the channel and clear its interrupts */
420 pl08x_terminate_phy_chan(pl08x, ch);
422 /* Mark it as free */
424 spin_unlock_irqrestore(&ch->lock, flags);
431 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
434 case PL080_WIDTH_8BIT:
436 case PL080_WIDTH_16BIT:
438 case PL080_WIDTH_32BIT:
447 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
452 /* Remove all src, dst and transfer size bits */
453 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
454 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
455 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
457 /* Then set the bits according to the parameters */
460 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
463 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
466 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
475 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
478 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
481 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
488 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
492 struct pl08x_lli_build_data {
493 struct pl08x_txd *txd;
494 struct pl08x_driver_data *pl08x;
495 struct pl08x_bus_data srcbus;
496 struct pl08x_bus_data dstbus;
501 * Autoselect a master bus to use for the transfer this prefers the
502 * destination bus if both available if fixed address on one bus the
503 * other will be chosen
505 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
506 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
508 if (!(cctl & PL080_CONTROL_DST_INCR)) {
511 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
515 if (bd->dstbus.buswidth == 4) {
518 } else if (bd->srcbus.buswidth == 4) {
521 } else if (bd->dstbus.buswidth == 2) {
524 } else if (bd->srcbus.buswidth == 2) {
528 /* bd->srcbus.buswidth == 1 */
536 * Fills in one LLI for a certain transfer descriptor and advance the counter
538 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
539 int num_llis, int len, u32 cctl)
541 struct pl08x_lli *llis_va = bd->txd->llis_va;
542 dma_addr_t llis_bus = bd->txd->llis_bus;
544 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
546 llis_va[num_llis].cctl = cctl;
547 llis_va[num_llis].src = bd->srcbus.addr;
548 llis_va[num_llis].dst = bd->dstbus.addr;
549 llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
550 if (bd->pl08x->lli_buses & PL08X_AHB2)
551 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
553 if (cctl & PL080_CONTROL_SRC_INCR)
554 bd->srcbus.addr += len;
555 if (cctl & PL080_CONTROL_DST_INCR)
556 bd->dstbus.addr += len;
558 BUG_ON(bd->remainder < len);
560 bd->remainder -= len;
564 * Return number of bytes to fill to boundary, or len.
565 * This calculation works for any value of addr.
567 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
569 size_t boundary_len = PL08X_BOUNDARY_SIZE -
570 (addr & (PL08X_BOUNDARY_SIZE - 1));
572 return min(boundary_len, len);
576 * This fills in the table of LLIs for the transfer descriptor
577 * Note that we assume we never have to change the burst sizes
580 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
581 struct pl08x_txd *txd)
583 struct pl08x_bus_data *mbus, *sbus;
584 struct pl08x_lli_build_data bd;
587 size_t max_bytes_per_lli;
588 size_t total_bytes = 0;
589 struct pl08x_lli *llis_va;
591 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
594 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
600 /* Get the default CCTL */
605 bd.srcbus.addr = txd->src_addr;
606 bd.dstbus.addr = txd->dst_addr;
608 /* Find maximum width of the source bus */
610 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
611 PL080_CONTROL_SWIDTH_SHIFT);
613 /* Find maximum width of the destination bus */
615 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
616 PL080_CONTROL_DWIDTH_SHIFT);
618 /* Set up the bus widths to the maximum */
619 bd.srcbus.buswidth = bd.srcbus.maxwidth;
620 bd.dstbus.buswidth = bd.dstbus.maxwidth;
621 dev_vdbg(&pl08x->adev->dev,
622 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
623 __func__, bd.srcbus.buswidth, bd.dstbus.buswidth);
627 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
629 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
630 PL080_CONTROL_TRANSFER_SIZE_MASK;
631 dev_vdbg(&pl08x->adev->dev,
632 "%s max bytes per lli = %zu\n",
633 __func__, max_bytes_per_lli);
635 /* We need to count this down to zero */
636 bd.remainder = txd->len;
637 dev_vdbg(&pl08x->adev->dev,
638 "%s remainder = %zu\n",
639 __func__, bd.remainder);
642 * Choose bus to align to
643 * - prefers destination bus if both available
644 * - if fixed address on one bus chooses other
646 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
648 if (txd->len < mbus->buswidth) {
649 /* Less than a bus width available - send as single bytes */
650 while (bd.remainder) {
651 dev_vdbg(&pl08x->adev->dev,
652 "%s single byte LLIs for a transfer of "
653 "less than a bus width (remain 0x%08x)\n",
654 __func__, bd.remainder);
655 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
656 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
660 /* Make one byte LLIs until master bus is aligned */
661 while ((mbus->addr) % (mbus->buswidth)) {
662 dev_vdbg(&pl08x->adev->dev,
663 "%s adjustment lli for less than bus width "
665 __func__, bd.remainder);
666 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
667 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
673 * - if slave is not then we must set its width down
675 if (sbus->addr % sbus->buswidth) {
676 dev_dbg(&pl08x->adev->dev,
677 "%s set down bus width to one byte\n",
684 * Make largest possible LLIs until less than one bus
687 while (bd.remainder > (mbus->buswidth - 1)) {
688 size_t lli_len, target_len, tsize, odd_bytes;
691 * If enough left try to send max possible,
692 * otherwise try to send the remainder
694 target_len = min(bd.remainder, max_bytes_per_lli);
697 * Set bus lengths for incrementing buses to the
698 * number of bytes which fill to next memory boundary,
699 * limiting on the target length calculated above.
701 if (cctl & PL080_CONTROL_SRC_INCR)
702 bd.srcbus.fill_bytes =
703 pl08x_pre_boundary(bd.srcbus.addr,
706 bd.srcbus.fill_bytes = target_len;
708 if (cctl & PL080_CONTROL_DST_INCR)
709 bd.dstbus.fill_bytes =
710 pl08x_pre_boundary(bd.dstbus.addr,
713 bd.dstbus.fill_bytes = target_len;
715 /* Find the nearest */
716 lli_len = min(bd.srcbus.fill_bytes,
717 bd.dstbus.fill_bytes);
719 BUG_ON(lli_len > bd.remainder);
722 dev_err(&pl08x->adev->dev,
723 "%s lli_len is %zu, <= 0\n",
728 if (lli_len == target_len) {
730 * Can send what we wanted.
733 lli_len = (lli_len/mbus->buswidth) *
738 * So now we know how many bytes to transfer
739 * to get to the nearest boundary. The next
740 * LLI will past the boundary. However, we
741 * may be working to a boundary on the slave
742 * bus. We need to ensure the master stays
743 * aligned, and that we are working in
744 * multiples of the bus widths.
746 odd_bytes = lli_len % mbus->buswidth;
747 lli_len -= odd_bytes;
753 * Check against minimum bus alignment:
754 * Calculate actual transfer size in relation
755 * to bus width an get a maximum remainder of
756 * the smallest bus width - 1
758 /* FIXME: use round_down()? */
759 tsize = lli_len / min(mbus->buswidth,
761 lli_len = tsize * min(mbus->buswidth,
764 if (target_len != lli_len) {
765 dev_vdbg(&pl08x->adev->dev,
766 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
767 __func__, target_len, lli_len, txd->len);
770 cctl = pl08x_cctl_bits(cctl,
775 dev_vdbg(&pl08x->adev->dev,
776 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
777 __func__, lli_len, bd.remainder);
778 pl08x_fill_lli_for_desc(&bd, num_llis++,
780 total_bytes += lli_len;
786 * Creep past the boundary, maintaining
790 for (j = 0; (j < mbus->buswidth)
791 && (bd.remainder); j++) {
792 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
793 dev_vdbg(&pl08x->adev->dev,
794 "%s align with boundary, single byte (remain 0x%08zx)\n",
795 __func__, bd.remainder);
796 pl08x_fill_lli_for_desc(&bd,
797 num_llis++, 1, cctl);
806 while (bd.remainder) {
807 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
808 dev_vdbg(&pl08x->adev->dev,
809 "%s align with boundary, single odd byte (remain %zu)\n",
810 __func__, bd.remainder);
811 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
815 if (total_bytes != txd->len) {
816 dev_err(&pl08x->adev->dev,
817 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
818 __func__, total_bytes, txd->len);
822 if (num_llis >= MAX_NUM_TSFR_LLIS) {
823 dev_err(&pl08x->adev->dev,
824 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
825 __func__, (u32) MAX_NUM_TSFR_LLIS);
829 llis_va = txd->llis_va;
830 /* The final LLI terminates the LLI. */
831 llis_va[num_llis - 1].lli = 0;
832 /* The final LLI element shall also fire an interrupt. */
833 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
839 for (i = 0; i < num_llis; i++) {
840 dev_vdbg(&pl08x->adev->dev,
841 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
856 /* You should call this with the struct pl08x lock held */
857 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
858 struct pl08x_txd *txd)
861 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
868 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
869 struct pl08x_dma_chan *plchan)
871 struct pl08x_txd *txdi = NULL;
872 struct pl08x_txd *next;
874 if (!list_empty(&plchan->pend_list)) {
875 list_for_each_entry_safe(txdi,
876 next, &plchan->pend_list, node) {
877 list_del(&txdi->node);
878 pl08x_free_txd(pl08x, txdi);
886 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
891 static void pl08x_free_chan_resources(struct dma_chan *chan)
896 * This should be called with the channel plchan->lock held
898 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
899 struct pl08x_txd *txd)
901 struct pl08x_driver_data *pl08x = plchan->host;
902 struct pl08x_phy_chan *ch;
905 /* Check if we already have a channel */
909 ch = pl08x_get_phy_channel(pl08x, plchan);
911 /* No physical channel available, cope with it */
912 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
917 * OK we have a physical channel: for memcpy() this is all we
918 * need, but for slaves the physical signals may be muxed!
919 * Can the platform allow us to use this channel?
923 pl08x->pd->get_signal) {
924 ret = pl08x->pd->get_signal(plchan);
926 dev_dbg(&pl08x->adev->dev,
927 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
928 ch->id, plchan->name);
929 /* Release physical channel & return */
930 pl08x_put_phy_channel(pl08x, ch);
935 /* Assign the flow control signal to this channel */
936 if (txd->direction == DMA_TO_DEVICE)
937 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
938 else if (txd->direction == DMA_FROM_DEVICE)
939 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
942 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
947 plchan->phychan_hold++;
948 plchan->phychan = ch;
953 static void release_phy_channel(struct pl08x_dma_chan *plchan)
955 struct pl08x_driver_data *pl08x = plchan->host;
957 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
958 pl08x->pd->put_signal(plchan);
959 plchan->phychan->signal = -1;
961 pl08x_put_phy_channel(pl08x, plchan->phychan);
962 plchan->phychan = NULL;
965 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
967 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
968 struct pl08x_txd *txd = to_pl08x_txd(tx);
971 spin_lock_irqsave(&plchan->lock, flags);
973 plchan->chan.cookie += 1;
974 if (plchan->chan.cookie < 0)
975 plchan->chan.cookie = 1;
976 tx->cookie = plchan->chan.cookie;
978 /* Put this onto the pending list */
979 list_add_tail(&txd->node, &plchan->pend_list);
982 * If there was no physical channel available for this memcpy,
983 * stack the request up and indicate that the channel is waiting
984 * for a free physical channel.
986 if (!plchan->slave && !plchan->phychan) {
987 /* Do this memcpy whenever there is a channel ready */
988 plchan->state = PL08X_CHAN_WAITING;
989 plchan->waiting = txd;
991 plchan->phychan_hold--;
994 spin_unlock_irqrestore(&plchan->lock, flags);
999 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1000 struct dma_chan *chan, unsigned long flags)
1002 struct dma_async_tx_descriptor *retval = NULL;
1008 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1009 * If slaves are relying on interrupts to signal completion this function
1010 * must not be called with interrupts disabled.
1012 static enum dma_status
1013 pl08x_dma_tx_status(struct dma_chan *chan,
1014 dma_cookie_t cookie,
1015 struct dma_tx_state *txstate)
1017 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1018 dma_cookie_t last_used;
1019 dma_cookie_t last_complete;
1020 enum dma_status ret;
1023 last_used = plchan->chan.cookie;
1024 last_complete = plchan->lc;
1026 ret = dma_async_is_complete(cookie, last_complete, last_used);
1027 if (ret == DMA_SUCCESS) {
1028 dma_set_tx_state(txstate, last_complete, last_used, 0);
1033 * This cookie not complete yet
1035 last_used = plchan->chan.cookie;
1036 last_complete = plchan->lc;
1038 /* Get number of bytes left in the active transactions and queue */
1039 bytesleft = pl08x_getbytes_chan(plchan);
1041 dma_set_tx_state(txstate, last_complete, last_used,
1044 if (plchan->state == PL08X_CHAN_PAUSED)
1047 /* Whether waiting or running, we're in progress */
1048 return DMA_IN_PROGRESS;
1051 /* PrimeCell DMA extension */
1052 struct burst_table {
1057 static const struct burst_table burst_sizes[] = {
1060 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1061 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1065 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1066 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1070 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1071 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1075 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1076 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1080 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1081 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1085 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1086 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1090 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1091 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1095 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1096 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1100 static int dma_set_runtime_config(struct dma_chan *chan,
1101 struct dma_slave_config *config)
1103 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1104 struct pl08x_driver_data *pl08x = plchan->host;
1105 struct pl08x_channel_data *cd = plchan->cd;
1106 enum dma_slave_buswidth addr_width;
1115 /* Transfer direction */
1116 plchan->runtime_direction = config->direction;
1117 if (config->direction == DMA_TO_DEVICE) {
1118 addr = config->dst_addr;
1119 addr_width = config->dst_addr_width;
1120 maxburst = config->dst_maxburst;
1121 } else if (config->direction == DMA_FROM_DEVICE) {
1122 addr = config->src_addr;
1123 addr_width = config->src_addr_width;
1124 maxburst = config->src_maxburst;
1126 dev_err(&pl08x->adev->dev,
1127 "bad runtime_config: alien transfer direction\n");
1131 switch (addr_width) {
1132 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1133 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1134 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1136 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1137 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1138 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1140 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1141 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1142 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1145 dev_err(&pl08x->adev->dev,
1146 "bad runtime_config: alien address width\n");
1151 * Now decide on a maxburst:
1152 * If this channel will only request single transfers, set this
1153 * down to ONE element. Also select one element if no maxburst
1156 if (plchan->cd->single || maxburst == 0) {
1157 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1158 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1160 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1161 if (burst_sizes[i].burstwords <= maxburst)
1163 cctl |= burst_sizes[i].reg;
1166 plchan->runtime_addr = addr;
1168 /* Modify the default channel data to fit PrimeCell request */
1171 dev_dbg(&pl08x->adev->dev,
1172 "configured channel %s (%s) for %s, data width %d, "
1173 "maxburst %d words, LE, CCTL=0x%08x\n",
1174 dma_chan_name(chan), plchan->name,
1175 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1184 * Slave transactions callback to the slave device to allow
1185 * synchronization of slave DMA signals with the DMAC enable
1187 static void pl08x_issue_pending(struct dma_chan *chan)
1189 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1190 unsigned long flags;
1192 spin_lock_irqsave(&plchan->lock, flags);
1193 /* Something is already active, or we're waiting for a channel... */
1194 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1195 spin_unlock_irqrestore(&plchan->lock, flags);
1199 /* Take the first element in the queue and execute it */
1200 if (!list_empty(&plchan->pend_list)) {
1201 struct pl08x_txd *next;
1203 next = list_first_entry(&plchan->pend_list,
1206 list_del(&next->node);
1207 plchan->state = PL08X_CHAN_RUNNING;
1209 pl08x_start_txd(plchan, next);
1212 spin_unlock_irqrestore(&plchan->lock, flags);
1215 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1216 struct pl08x_txd *txd)
1218 struct pl08x_driver_data *pl08x = plchan->host;
1219 unsigned long flags;
1222 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1228 spin_lock_irqsave(&plchan->lock, flags);
1231 * See if we already have a physical channel allocated,
1232 * else this is the time to try to get one.
1234 ret = prep_phy_channel(plchan, txd);
1237 * No physical channel was available.
1239 * memcpy transfers can be sorted out at submission time.
1241 * Slave transfers may have been denied due to platform
1242 * channel muxing restrictions. Since there is no guarantee
1243 * that this will ever be resolved, and the signal must be
1244 * acquired AFTER acquiring the physical channel, we will let
1245 * them be NACK:ed with -EBUSY here. The drivers can retry
1246 * the prep() call if they are eager on doing this using DMA.
1248 if (plchan->slave) {
1249 pl08x_free_txd_list(pl08x, plchan);
1250 pl08x_free_txd(pl08x, txd);
1251 spin_unlock_irqrestore(&plchan->lock, flags);
1256 * Else we're all set, paused and ready to roll, status
1257 * will switch to PL08X_CHAN_RUNNING when we call
1258 * issue_pending(). If there is something running on the
1259 * channel already we don't change its state.
1261 if (plchan->state == PL08X_CHAN_IDLE)
1262 plchan->state = PL08X_CHAN_PAUSED;
1264 spin_unlock_irqrestore(&plchan->lock, flags);
1270 * Given the source and destination available bus masks, select which
1271 * will be routed to each port. We try to have source and destination
1272 * on separate ports, but always respect the allowable settings.
1274 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1278 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1279 cctl |= PL080_CONTROL_DST_AHB2;
1280 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1281 cctl |= PL080_CONTROL_SRC_AHB2;
1286 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1287 unsigned long flags)
1289 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1292 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1293 txd->tx.flags = flags;
1294 txd->tx.tx_submit = pl08x_tx_submit;
1295 INIT_LIST_HEAD(&txd->node);
1297 /* Always enable error and terminal interrupts */
1298 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1299 PL080_CONFIG_TC_IRQ_MASK;
1305 * Initialize a descriptor to be used by memcpy submit
1307 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1308 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1309 size_t len, unsigned long flags)
1311 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1312 struct pl08x_driver_data *pl08x = plchan->host;
1313 struct pl08x_txd *txd;
1316 txd = pl08x_get_txd(plchan, flags);
1318 dev_err(&pl08x->adev->dev,
1319 "%s no memory for descriptor\n", __func__);
1323 txd->direction = DMA_NONE;
1324 txd->src_addr = src;
1325 txd->dst_addr = dest;
1328 /* Set platform data for m2m */
1329 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1330 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1331 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1333 /* Both to be incremented or the code will break */
1334 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1336 if (pl08x->vd->dualmaster)
1337 txd->cctl |= pl08x_select_bus(pl08x,
1338 pl08x->mem_buses, pl08x->mem_buses);
1340 ret = pl08x_prep_channel_resources(plchan, txd);
1347 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1348 struct dma_chan *chan, struct scatterlist *sgl,
1349 unsigned int sg_len, enum dma_data_direction direction,
1350 unsigned long flags)
1352 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1353 struct pl08x_driver_data *pl08x = plchan->host;
1354 struct pl08x_txd *txd;
1355 u8 src_buses, dst_buses;
1359 * Current implementation ASSUMES only one sg
1362 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1367 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1368 __func__, sgl->length, plchan->name);
1370 txd = pl08x_get_txd(plchan, flags);
1372 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1376 if (direction != plchan->runtime_direction)
1377 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1378 "the direction configured for the PrimeCell\n",
1382 * Set up addresses, the PrimeCell configured address
1383 * will take precedence since this may configure the
1384 * channel target address dynamically at runtime.
1386 txd->direction = direction;
1387 txd->len = sgl->length;
1389 txd->cctl = plchan->cd->cctl &
1390 ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1391 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1392 PL080_CONTROL_PROT_MASK);
1394 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1395 txd->cctl |= PL080_CONTROL_PROT_SYS;
1397 if (direction == DMA_TO_DEVICE) {
1398 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1399 txd->cctl |= PL080_CONTROL_SRC_INCR;
1400 txd->src_addr = sgl->dma_address;
1401 if (plchan->runtime_addr)
1402 txd->dst_addr = plchan->runtime_addr;
1404 txd->dst_addr = plchan->cd->addr;
1405 src_buses = pl08x->mem_buses;
1406 dst_buses = plchan->cd->periph_buses;
1407 } else if (direction == DMA_FROM_DEVICE) {
1408 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1409 txd->cctl |= PL080_CONTROL_DST_INCR;
1410 if (plchan->runtime_addr)
1411 txd->src_addr = plchan->runtime_addr;
1413 txd->src_addr = plchan->cd->addr;
1414 txd->dst_addr = sgl->dma_address;
1415 src_buses = plchan->cd->periph_buses;
1416 dst_buses = pl08x->mem_buses;
1418 dev_err(&pl08x->adev->dev,
1419 "%s direction unsupported\n", __func__);
1423 txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1425 ret = pl08x_prep_channel_resources(plchan, txd);
1432 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1435 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1436 struct pl08x_driver_data *pl08x = plchan->host;
1437 unsigned long flags;
1440 /* Controls applicable to inactive channels */
1441 if (cmd == DMA_SLAVE_CONFIG) {
1442 return dma_set_runtime_config(chan,
1443 (struct dma_slave_config *)arg);
1447 * Anything succeeds on channels with no physical allocation and
1448 * no queued transfers.
1450 spin_lock_irqsave(&plchan->lock, flags);
1451 if (!plchan->phychan && !plchan->at) {
1452 spin_unlock_irqrestore(&plchan->lock, flags);
1457 case DMA_TERMINATE_ALL:
1458 plchan->state = PL08X_CHAN_IDLE;
1460 if (plchan->phychan) {
1461 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1464 * Mark physical channel as free and free any slave
1467 release_phy_channel(plchan);
1469 /* Dequeue jobs and free LLIs */
1471 pl08x_free_txd(pl08x, plchan->at);
1474 /* Dequeue jobs not yet fired as well */
1475 pl08x_free_txd_list(pl08x, plchan);
1478 pl08x_pause_phy_chan(plchan->phychan);
1479 plchan->state = PL08X_CHAN_PAUSED;
1482 pl08x_resume_phy_chan(plchan->phychan);
1483 plchan->state = PL08X_CHAN_RUNNING;
1486 /* Unknown command */
1491 spin_unlock_irqrestore(&plchan->lock, flags);
1496 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1498 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1499 char *name = chan_id;
1501 /* Check that the channel is not taken! */
1502 if (!strcmp(plchan->name, name))
1509 * Just check that the device is there and active
1510 * TODO: turn this bit on/off depending on the number of physical channels
1511 * actually used, if it is zero... well shut it off. That will save some
1512 * power. Cut the clock at the same time.
1514 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1518 val = readl(pl08x->base + PL080_CONFIG);
1519 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1520 /* We implicitly clear bit 1 and that means little-endian mode */
1521 val |= PL080_CONFIG_ENABLE;
1522 writel(val, pl08x->base + PL080_CONFIG);
1525 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1527 struct device *dev = txd->tx.chan->device->dev;
1529 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1530 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1531 dma_unmap_single(dev, txd->src_addr, txd->len,
1534 dma_unmap_page(dev, txd->src_addr, txd->len,
1537 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1538 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1539 dma_unmap_single(dev, txd->dst_addr, txd->len,
1542 dma_unmap_page(dev, txd->dst_addr, txd->len,
1547 static void pl08x_tasklet(unsigned long data)
1549 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1550 struct pl08x_driver_data *pl08x = plchan->host;
1551 struct pl08x_txd *txd;
1552 unsigned long flags;
1554 spin_lock_irqsave(&plchan->lock, flags);
1560 /* Update last completed */
1561 plchan->lc = txd->tx.cookie;
1564 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1565 if (!list_empty(&plchan->pend_list)) {
1566 struct pl08x_txd *next;
1568 next = list_first_entry(&plchan->pend_list,
1571 list_del(&next->node);
1573 pl08x_start_txd(plchan, next);
1574 } else if (plchan->phychan_hold) {
1576 * This channel is still in use - we have a new txd being
1577 * prepared and will soon be queued. Don't give up the
1581 struct pl08x_dma_chan *waiting = NULL;
1584 * No more jobs, so free up the physical channel
1585 * Free any allocated signal on slave transfers too
1587 release_phy_channel(plchan);
1588 plchan->state = PL08X_CHAN_IDLE;
1591 * And NOW before anyone else can grab that free:d up
1592 * physical channel, see if there is some memcpy pending
1593 * that seriously needs to start because of being stacked
1594 * up while we were choking the physical channels with data.
1596 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1598 if (waiting->state == PL08X_CHAN_WAITING &&
1599 waiting->waiting != NULL) {
1602 /* This should REALLY not fail now */
1603 ret = prep_phy_channel(waiting,
1606 waiting->phychan_hold--;
1607 waiting->state = PL08X_CHAN_RUNNING;
1608 waiting->waiting = NULL;
1609 pl08x_issue_pending(&waiting->chan);
1615 spin_unlock_irqrestore(&plchan->lock, flags);
1618 dma_async_tx_callback callback = txd->tx.callback;
1619 void *callback_param = txd->tx.callback_param;
1621 /* Don't try to unmap buffers on slave channels */
1623 pl08x_unmap_buffers(txd);
1625 /* Free the descriptor */
1626 spin_lock_irqsave(&plchan->lock, flags);
1627 pl08x_free_txd(pl08x, txd);
1628 spin_unlock_irqrestore(&plchan->lock, flags);
1630 /* Callback to signal completion */
1632 callback(callback_param);
1636 static irqreturn_t pl08x_irq(int irq, void *dev)
1638 struct pl08x_driver_data *pl08x = dev;
1643 val = readl(pl08x->base + PL080_ERR_STATUS);
1645 /* An error interrupt (on one or more channels) */
1646 dev_err(&pl08x->adev->dev,
1647 "%s error interrupt, register value 0x%08x\n",
1650 * Simply clear ALL PL08X error interrupts,
1651 * regardless of channel and cause
1652 * FIXME: should be 0x00000003 on PL081 really.
1654 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1656 val = readl(pl08x->base + PL080_INT_STATUS);
1657 for (i = 0; i < pl08x->vd->channels; i++) {
1658 if ((1 << i) & val) {
1659 /* Locate physical channel */
1660 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1661 struct pl08x_dma_chan *plchan = phychan->serving;
1663 /* Schedule tasklet on this channel */
1664 tasklet_schedule(&plchan->tasklet);
1669 /* Clear only the terminal interrupts on channels we processed */
1670 writel(mask, pl08x->base + PL080_TC_CLEAR);
1672 return mask ? IRQ_HANDLED : IRQ_NONE;
1676 * Initialise the DMAC memcpy/slave channels.
1677 * Make a local wrapper to hold required data
1679 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1680 struct dma_device *dmadev,
1681 unsigned int channels,
1684 struct pl08x_dma_chan *chan;
1687 INIT_LIST_HEAD(&dmadev->channels);
1690 * Register as many many memcpy as we have physical channels,
1691 * we won't always be able to use all but the code will have
1692 * to cope with that situation.
1694 for (i = 0; i < channels; i++) {
1695 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1697 dev_err(&pl08x->adev->dev,
1698 "%s no memory for channel\n", __func__);
1703 chan->state = PL08X_CHAN_IDLE;
1707 chan->name = pl08x->pd->slave_channels[i].bus_id;
1708 chan->cd = &pl08x->pd->slave_channels[i];
1710 chan->cd = &pl08x->pd->memcpy_channel;
1711 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1717 if (chan->cd->circular_buffer) {
1718 dev_err(&pl08x->adev->dev,
1719 "channel %s: circular buffers not supported\n",
1724 dev_info(&pl08x->adev->dev,
1725 "initialize virtual channel \"%s\"\n",
1728 chan->chan.device = dmadev;
1729 chan->chan.cookie = 0;
1732 spin_lock_init(&chan->lock);
1733 INIT_LIST_HEAD(&chan->pend_list);
1734 tasklet_init(&chan->tasklet, pl08x_tasklet,
1735 (unsigned long) chan);
1737 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1739 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1740 i, slave ? "slave" : "memcpy");
1744 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1746 struct pl08x_dma_chan *chan = NULL;
1747 struct pl08x_dma_chan *next;
1749 list_for_each_entry_safe(chan,
1750 next, &dmadev->channels, chan.device_node) {
1751 list_del(&chan->chan.device_node);
1756 #ifdef CONFIG_DEBUG_FS
1757 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1760 case PL08X_CHAN_IDLE:
1762 case PL08X_CHAN_RUNNING:
1764 case PL08X_CHAN_PAUSED:
1766 case PL08X_CHAN_WAITING:
1771 return "UNKNOWN STATE";
1774 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1776 struct pl08x_driver_data *pl08x = s->private;
1777 struct pl08x_dma_chan *chan;
1778 struct pl08x_phy_chan *ch;
1779 unsigned long flags;
1782 seq_printf(s, "PL08x physical channels:\n");
1783 seq_printf(s, "CHANNEL:\tUSER:\n");
1784 seq_printf(s, "--------\t-----\n");
1785 for (i = 0; i < pl08x->vd->channels; i++) {
1786 struct pl08x_dma_chan *virt_chan;
1788 ch = &pl08x->phy_chans[i];
1790 spin_lock_irqsave(&ch->lock, flags);
1791 virt_chan = ch->serving;
1793 seq_printf(s, "%d\t\t%s\n",
1794 ch->id, virt_chan ? virt_chan->name : "(none)");
1796 spin_unlock_irqrestore(&ch->lock, flags);
1799 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1800 seq_printf(s, "CHANNEL:\tSTATE:\n");
1801 seq_printf(s, "--------\t------\n");
1802 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1803 seq_printf(s, "%s\t\t%s\n", chan->name,
1804 pl08x_state_str(chan->state));
1807 seq_printf(s, "\nPL08x virtual slave channels:\n");
1808 seq_printf(s, "CHANNEL:\tSTATE:\n");
1809 seq_printf(s, "--------\t------\n");
1810 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1811 seq_printf(s, "%s\t\t%s\n", chan->name,
1812 pl08x_state_str(chan->state));
1818 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1820 return single_open(file, pl08x_debugfs_show, inode->i_private);
1823 static const struct file_operations pl08x_debugfs_operations = {
1824 .open = pl08x_debugfs_open,
1826 .llseek = seq_lseek,
1827 .release = single_release,
1830 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1832 /* Expose a simple debugfs interface to view all clocks */
1833 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1835 &pl08x_debugfs_operations);
1839 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1844 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1846 struct pl08x_driver_data *pl08x;
1847 const struct vendor_data *vd = id->data;
1851 ret = amba_request_regions(adev, NULL);
1855 /* Create the driver state holder */
1856 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1862 /* Initialize memcpy engine */
1863 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1864 pl08x->memcpy.dev = &adev->dev;
1865 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1866 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1867 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1868 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1869 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1870 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1871 pl08x->memcpy.device_control = pl08x_control;
1873 /* Initialize slave engine */
1874 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1875 pl08x->slave.dev = &adev->dev;
1876 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1877 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1878 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1879 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1880 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1881 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1882 pl08x->slave.device_control = pl08x_control;
1884 /* Get the platform data */
1885 pl08x->pd = dev_get_platdata(&adev->dev);
1887 dev_err(&adev->dev, "no platform data supplied\n");
1888 goto out_no_platdata;
1891 /* Assign useful pointers to the driver state */
1895 /* By default, AHB1 only. If dualmaster, from platform */
1896 pl08x->lli_buses = PL08X_AHB1;
1897 pl08x->mem_buses = PL08X_AHB1;
1898 if (pl08x->vd->dualmaster) {
1899 pl08x->lli_buses = pl08x->pd->lli_buses;
1900 pl08x->mem_buses = pl08x->pd->mem_buses;
1903 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1904 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1905 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1908 goto out_no_lli_pool;
1911 spin_lock_init(&pl08x->lock);
1913 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1916 goto out_no_ioremap;
1919 /* Turn on the PL08x */
1920 pl08x_ensure_on(pl08x);
1922 /* Attach the interrupt handler */
1923 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1924 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1926 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1927 DRIVER_NAME, pl08x);
1929 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1930 __func__, adev->irq[0]);
1934 /* Initialize physical channels */
1935 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1937 if (!pl08x->phy_chans) {
1938 dev_err(&adev->dev, "%s failed to allocate "
1939 "physical channel holders\n",
1941 goto out_no_phychans;
1944 for (i = 0; i < vd->channels; i++) {
1945 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1948 ch->base = pl08x->base + PL080_Cx_BASE(i);
1949 spin_lock_init(&ch->lock);
1952 dev_info(&adev->dev,
1953 "physical channel %d is %s\n", i,
1954 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1957 /* Register as many memcpy channels as there are physical channels */
1958 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1959 pl08x->vd->channels, false);
1961 dev_warn(&pl08x->adev->dev,
1962 "%s failed to enumerate memcpy channels - %d\n",
1966 pl08x->memcpy.chancnt = ret;
1968 /* Register slave channels */
1969 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1970 pl08x->pd->num_slave_channels,
1973 dev_warn(&pl08x->adev->dev,
1974 "%s failed to enumerate slave channels - %d\n",
1978 pl08x->slave.chancnt = ret;
1980 ret = dma_async_device_register(&pl08x->memcpy);
1982 dev_warn(&pl08x->adev->dev,
1983 "%s failed to register memcpy as an async device - %d\n",
1985 goto out_no_memcpy_reg;
1988 ret = dma_async_device_register(&pl08x->slave);
1990 dev_warn(&pl08x->adev->dev,
1991 "%s failed to register slave as an async device - %d\n",
1993 goto out_no_slave_reg;
1996 amba_set_drvdata(adev, pl08x);
1997 init_pl08x_debugfs(pl08x);
1998 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1999 amba_part(adev), amba_rev(adev),
2000 (unsigned long long)adev->res.start, adev->irq[0]);
2004 dma_async_device_unregister(&pl08x->memcpy);
2006 pl08x_free_virtual_channels(&pl08x->slave);
2008 pl08x_free_virtual_channels(&pl08x->memcpy);
2010 kfree(pl08x->phy_chans);
2012 free_irq(adev->irq[0], pl08x);
2014 iounmap(pl08x->base);
2016 dma_pool_destroy(pl08x->pool);
2021 amba_release_regions(adev);
2025 /* PL080 has 8 channels and the PL080 have just 2 */
2026 static struct vendor_data vendor_pl080 = {
2031 static struct vendor_data vendor_pl081 = {
2033 .dualmaster = false,
2036 static struct amba_id pl08x_ids[] = {
2041 .data = &vendor_pl080,
2047 .data = &vendor_pl081,
2049 /* Nomadik 8815 PL080 variant */
2053 .data = &vendor_pl080,
2058 static struct amba_driver pl08x_amba_driver = {
2059 .drv.name = DRIVER_NAME,
2060 .id_table = pl08x_ids,
2061 .probe = pl08x_probe,
2064 static int __init pl08x_init(void)
2067 retval = amba_driver_register(&pl08x_amba_driver);
2069 printk(KERN_WARNING DRIVER_NAME
2070 "failed to register as an AMBA device (%d)\n",
2074 subsys_initcall(pl08x_init);