2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/amba/bus.h>
78 #include <linux/amba/pl08x.h>
79 #include <linux/debugfs.h>
80 #include <linux/delay.h>
81 #include <linux/device.h>
82 #include <linux/dmaengine.h>
83 #include <linux/dmapool.h>
84 #include <linux/init.h>
85 #include <linux/interrupt.h>
86 #include <linux/module.h>
87 #include <linux/pm_runtime.h>
88 #include <linux/seq_file.h>
89 #include <linux/slab.h>
90 #include <asm/hardware/pl080.h>
92 #define DRIVER_NAME "pl08xdmac"
95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters or not.
105 * PL08X private data structures
106 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
107 * start & end do not - their bus bit info is in cctl. Also note that these
108 * are fixed 32-bit quantities.
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
130 * @mem_buses: set to indicate memory transfers on AHB2.
131 * @lock: a spinlock for this struct
133 struct pl08x_driver_data {
134 struct dma_device slave;
135 struct dma_device memcpy;
137 struct amba_device *adev;
138 const struct vendor_data *vd;
139 struct pl08x_platform_data *pd;
140 struct pl08x_phy_chan *phy_chans;
141 struct dma_pool *pool;
149 * PL08X specific defines
152 /* Size (bytes) of each LLI buffer allocated for one transfer */
153 # define PL08X_LLI_TSFR_SIZE 0x2000
155 /* Maximum times we call dma_pool_alloc on this pool without freeing */
156 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
157 #define PL08X_ALIGN 8
159 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
161 return container_of(chan, struct pl08x_dma_chan, chan);
164 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
166 return container_of(tx, struct pl08x_txd, tx);
170 * Physical channel handling
173 /* Whether a certain channel is busy or not */
174 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
178 val = readl(ch->base + PL080_CH_CONFIG);
179 return val & PL080_CONFIG_ACTIVE;
183 * Set the initial DMA register values i.e. those for the first LLI
184 * The next LLI pointer and the configuration interrupt bit have
185 * been set when the LLIs were constructed. Poke them into the hardware
186 * and start the transfer.
188 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
189 struct pl08x_txd *txd)
191 struct pl08x_driver_data *pl08x = plchan->host;
192 struct pl08x_phy_chan *phychan = plchan->phychan;
193 struct pl08x_lli *lli = &txd->llis_va[0];
198 /* Wait for channel inactive */
199 while (pl08x_phy_channel_busy(phychan))
202 dev_vdbg(&pl08x->adev->dev,
203 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
204 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
205 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
208 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
209 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
210 writel(lli->lli, phychan->base + PL080_CH_LLI);
211 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
212 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
214 /* Enable the DMA channel */
215 /* Do not access config register until channel shows as disabled */
216 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
219 /* Do not access config register until channel shows as inactive */
220 val = readl(phychan->base + PL080_CH_CONFIG);
221 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
222 val = readl(phychan->base + PL080_CH_CONFIG);
224 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
228 * Pause the channel by setting the HALT bit.
230 * For M->P transfers, pause the DMAC first and then stop the peripheral -
231 * the FIFO can only drain if the peripheral is still requesting data.
232 * (note: this can still timeout if the DMAC FIFO never drains of data.)
234 * For P->M transfers, disable the peripheral first to stop it filling
235 * the DMAC FIFO, and then pause the DMAC.
237 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
242 /* Set the HALT bit and wait for the FIFO to drain */
243 val = readl(ch->base + PL080_CH_CONFIG);
244 val |= PL080_CONFIG_HALT;
245 writel(val, ch->base + PL080_CH_CONFIG);
247 /* Wait for channel inactive */
248 for (timeout = 1000; timeout; timeout--) {
249 if (!pl08x_phy_channel_busy(ch))
253 if (pl08x_phy_channel_busy(ch))
254 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
257 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
261 /* Clear the HALT bit */
262 val = readl(ch->base + PL080_CH_CONFIG);
263 val &= ~PL080_CONFIG_HALT;
264 writel(val, ch->base + PL080_CH_CONFIG);
268 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
269 * clears any pending interrupt status. This should not be used for
270 * an on-going transfer, but as a method of shutting down a channel
271 * (eg, when it's no longer used) or terminating a transfer.
273 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
274 struct pl08x_phy_chan *ch)
276 u32 val = readl(ch->base + PL080_CH_CONFIG);
278 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
279 PL080_CONFIG_TC_IRQ_MASK);
281 writel(val, ch->base + PL080_CH_CONFIG);
283 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
284 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
287 static inline u32 get_bytes_in_cctl(u32 cctl)
289 /* The source width defines the number of bytes */
290 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
292 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
293 case PL080_WIDTH_8BIT:
295 case PL080_WIDTH_16BIT:
298 case PL080_WIDTH_32BIT:
305 /* The channel should be paused when calling this */
306 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
308 struct pl08x_phy_chan *ch;
309 struct pl08x_txd *txd;
313 spin_lock_irqsave(&plchan->lock, flags);
314 ch = plchan->phychan;
318 * Follow the LLIs to get the number of remaining
319 * bytes in the currently active transaction.
322 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
324 /* First get the remaining bytes in the active transfer */
325 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
328 struct pl08x_lli *llis_va = txd->llis_va;
329 dma_addr_t llis_bus = txd->llis_bus;
332 BUG_ON(clli < llis_bus || clli >= llis_bus +
333 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
336 * Locate the next LLI - as this is an array,
337 * it's simple maths to find.
339 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
341 for (; index < MAX_NUM_TSFR_LLIS; index++) {
342 bytes += get_bytes_in_cctl(llis_va[index].cctl);
345 * A LLI pointer of 0 terminates the LLI list
347 if (!llis_va[index].lli)
353 /* Sum up all queued transactions */
354 if (!list_empty(&plchan->pend_list)) {
355 struct pl08x_txd *txdi;
356 list_for_each_entry(txdi, &plchan->pend_list, node) {
361 spin_unlock_irqrestore(&plchan->lock, flags);
367 * Allocate a physical channel for a virtual channel
369 * Try to locate a physical channel to be used for this transfer. If all
370 * are taken return NULL and the requester will have to cope by using
371 * some fallback PIO mode or retrying later.
373 static struct pl08x_phy_chan *
374 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
375 struct pl08x_dma_chan *virt_chan)
377 struct pl08x_phy_chan *ch = NULL;
381 for (i = 0; i < pl08x->vd->channels; i++) {
382 ch = &pl08x->phy_chans[i];
384 spin_lock_irqsave(&ch->lock, flags);
387 ch->serving = virt_chan;
389 spin_unlock_irqrestore(&ch->lock, flags);
393 spin_unlock_irqrestore(&ch->lock, flags);
396 if (i == pl08x->vd->channels) {
397 /* No physical channel available, cope with it */
401 pm_runtime_get_sync(&pl08x->adev->dev);
405 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
406 struct pl08x_phy_chan *ch)
410 spin_lock_irqsave(&ch->lock, flags);
412 /* Stop the channel and clear its interrupts */
413 pl08x_terminate_phy_chan(pl08x, ch);
415 pm_runtime_put(&pl08x->adev->dev);
417 /* Mark it as free */
419 spin_unlock_irqrestore(&ch->lock, flags);
426 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
429 case PL080_WIDTH_8BIT:
431 case PL080_WIDTH_16BIT:
433 case PL080_WIDTH_32BIT:
442 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
447 /* Remove all src, dst and transfer size bits */
448 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
449 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
450 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
452 /* Then set the bits according to the parameters */
455 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
458 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
461 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
470 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
473 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
476 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
483 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
487 struct pl08x_lli_build_data {
488 struct pl08x_txd *txd;
489 struct pl08x_bus_data srcbus;
490 struct pl08x_bus_data dstbus;
496 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
497 * victim in case src & dest are not similarly aligned. i.e. If after aligning
498 * masters address with width requirements of transfer (by sending few byte by
499 * byte data), slave is still not aligned, then its width will be reduced to
501 * - prefers the destination bus if both available
502 * - if fixed address on one bus the other will be chosen
504 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
505 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
507 if (!(cctl & PL080_CONTROL_DST_INCR)) {
510 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
514 if (bd->dstbus.buswidth == 4) {
517 } else if (bd->srcbus.buswidth == 4) {
520 } else if (bd->dstbus.buswidth == 2) {
523 } else if (bd->srcbus.buswidth == 2) {
527 /* bd->srcbus.buswidth == 1 */
535 * Fills in one LLI for a certain transfer descriptor and advance the counter
537 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
538 int num_llis, int len, u32 cctl)
540 struct pl08x_lli *llis_va = bd->txd->llis_va;
541 dma_addr_t llis_bus = bd->txd->llis_bus;
543 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
545 llis_va[num_llis].cctl = cctl;
546 llis_va[num_llis].src = bd->srcbus.addr;
547 llis_va[num_llis].dst = bd->dstbus.addr;
548 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
549 sizeof(struct pl08x_lli);
550 llis_va[num_llis].lli |= bd->lli_bus;
552 if (cctl & PL080_CONTROL_SRC_INCR)
553 bd->srcbus.addr += len;
554 if (cctl & PL080_CONTROL_DST_INCR)
555 bd->dstbus.addr += len;
557 BUG_ON(bd->remainder < len);
559 bd->remainder -= len;
562 static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
563 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
565 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
566 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
567 (*total_bytes) += len;
571 * This fills in the table of LLIs for the transfer descriptor
572 * Note that we assume we never have to change the burst sizes
575 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
576 struct pl08x_txd *txd)
578 struct pl08x_bus_data *mbus, *sbus;
579 struct pl08x_lli_build_data bd;
581 u32 cctl, early_bytes = 0;
582 size_t max_bytes_per_lli, total_bytes = 0;
583 struct pl08x_lli *llis_va;
585 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
587 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
593 /* Get the default CCTL */
597 bd.srcbus.addr = txd->src_addr;
598 bd.dstbus.addr = txd->dst_addr;
599 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
601 /* Find maximum width of the source bus */
603 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
604 PL080_CONTROL_SWIDTH_SHIFT);
606 /* Find maximum width of the destination bus */
608 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
609 PL080_CONTROL_DWIDTH_SHIFT);
611 /* Set up the bus widths to the maximum */
612 bd.srcbus.buswidth = bd.srcbus.maxwidth;
613 bd.dstbus.buswidth = bd.dstbus.maxwidth;
615 /* We need to count this down to zero */
616 bd.remainder = txd->len;
618 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
620 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
621 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
623 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
626 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
627 mbus == &bd.srcbus ? "src" : "dst",
628 sbus == &bd.srcbus ? "src" : "dst");
631 * Send byte by byte for following cases
632 * - Less than a bus width available
633 * - until master bus is aligned
635 if (bd.remainder < mbus->buswidth)
636 early_bytes = bd.remainder;
637 else if ((mbus->addr) % (mbus->buswidth)) {
638 early_bytes = mbus->buswidth - (mbus->addr) % (mbus->buswidth);
639 if ((bd.remainder - early_bytes) < mbus->buswidth)
640 early_bytes = bd.remainder;
644 dev_vdbg(&pl08x->adev->dev, "%s byte width LLIs "
645 "(remain 0x%08x)\n", __func__, bd.remainder);
646 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
653 * - if slave is not then we must set its width down
655 if (sbus->addr % sbus->buswidth) {
656 dev_dbg(&pl08x->adev->dev,
657 "%s set down bus width to one byte\n",
663 /* Bytes transferred = tsize * src width, not MIN(buswidths) */
664 max_bytes_per_lli = bd.srcbus.buswidth *
665 PL080_CONTROL_TRANSFER_SIZE_MASK;
668 * Make largest possible LLIs until less than one bus
671 while (bd.remainder > (mbus->buswidth - 1)) {
672 size_t lli_len, tsize;
675 * If enough left try to send max possible,
676 * otherwise try to send the remainder
678 lli_len = min(bd.remainder, max_bytes_per_lli);
680 * Check against minimum bus alignment: Calculate actual
681 * transfer size in relation to bus width and get a
682 * maximum remainder of the smallest bus width - 1
684 tsize = lli_len / min(mbus->buswidth, sbus->buswidth);
685 lli_len = tsize * min(mbus->buswidth, sbus->buswidth);
687 dev_vdbg(&pl08x->adev->dev,
688 "%s fill lli with single lli chunk of "
689 "size 0x%08zx (remainder 0x%08zx)\n",
690 __func__, lli_len, bd.remainder);
692 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
693 bd.dstbus.buswidth, tsize);
694 pl08x_fill_lli_for_desc(&bd, num_llis++, lli_len, cctl);
695 total_bytes += lli_len;
702 dev_vdbg(&pl08x->adev->dev,
703 "%s align with boundary, send odd bytes (remain %zu)\n",
704 __func__, bd.remainder);
705 prep_byte_width_lli(&bd, &cctl, bd.remainder,
706 num_llis++, &total_bytes);
710 if (total_bytes != txd->len) {
711 dev_err(&pl08x->adev->dev,
712 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
713 __func__, total_bytes, txd->len);
717 if (num_llis >= MAX_NUM_TSFR_LLIS) {
718 dev_err(&pl08x->adev->dev,
719 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
720 __func__, (u32) MAX_NUM_TSFR_LLIS);
724 llis_va = txd->llis_va;
725 /* The final LLI terminates the LLI. */
726 llis_va[num_llis - 1].lli = 0;
727 /* The final LLI element shall also fire an interrupt. */
728 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
734 dev_vdbg(&pl08x->adev->dev,
735 "%-3s %-9s %-10s %-10s %-10s %s\n",
736 "lli", "", "csrc", "cdst", "clli", "cctl");
737 for (i = 0; i < num_llis; i++) {
738 dev_vdbg(&pl08x->adev->dev,
739 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
740 i, &llis_va[i], llis_va[i].src,
741 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
750 /* You should call this with the struct pl08x lock held */
751 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
752 struct pl08x_txd *txd)
755 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
762 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
763 struct pl08x_dma_chan *plchan)
765 struct pl08x_txd *txdi = NULL;
766 struct pl08x_txd *next;
768 if (!list_empty(&plchan->pend_list)) {
769 list_for_each_entry_safe(txdi,
770 next, &plchan->pend_list, node) {
771 list_del(&txdi->node);
772 pl08x_free_txd(pl08x, txdi);
780 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
785 static void pl08x_free_chan_resources(struct dma_chan *chan)
790 * This should be called with the channel plchan->lock held
792 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
793 struct pl08x_txd *txd)
795 struct pl08x_driver_data *pl08x = plchan->host;
796 struct pl08x_phy_chan *ch;
799 /* Check if we already have a channel */
803 ch = pl08x_get_phy_channel(pl08x, plchan);
805 /* No physical channel available, cope with it */
806 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
811 * OK we have a physical channel: for memcpy() this is all we
812 * need, but for slaves the physical signals may be muxed!
813 * Can the platform allow us to use this channel?
815 if (plchan->slave && pl08x->pd->get_signal) {
816 ret = pl08x->pd->get_signal(plchan);
818 dev_dbg(&pl08x->adev->dev,
819 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
820 ch->id, plchan->name);
821 /* Release physical channel & return */
822 pl08x_put_phy_channel(pl08x, ch);
827 /* Assign the flow control signal to this channel */
828 if (txd->direction == DMA_TO_DEVICE)
829 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
830 else if (txd->direction == DMA_FROM_DEVICE)
831 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
834 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
839 plchan->phychan_hold++;
840 plchan->phychan = ch;
845 static void release_phy_channel(struct pl08x_dma_chan *plchan)
847 struct pl08x_driver_data *pl08x = plchan->host;
849 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
850 pl08x->pd->put_signal(plchan);
851 plchan->phychan->signal = -1;
853 pl08x_put_phy_channel(pl08x, plchan->phychan);
854 plchan->phychan = NULL;
857 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
859 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
860 struct pl08x_txd *txd = to_pl08x_txd(tx);
863 spin_lock_irqsave(&plchan->lock, flags);
865 plchan->chan.cookie += 1;
866 if (plchan->chan.cookie < 0)
867 plchan->chan.cookie = 1;
868 tx->cookie = plchan->chan.cookie;
870 /* Put this onto the pending list */
871 list_add_tail(&txd->node, &plchan->pend_list);
874 * If there was no physical channel available for this memcpy,
875 * stack the request up and indicate that the channel is waiting
876 * for a free physical channel.
878 if (!plchan->slave && !plchan->phychan) {
879 /* Do this memcpy whenever there is a channel ready */
880 plchan->state = PL08X_CHAN_WAITING;
881 plchan->waiting = txd;
883 plchan->phychan_hold--;
886 spin_unlock_irqrestore(&plchan->lock, flags);
891 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
892 struct dma_chan *chan, unsigned long flags)
894 struct dma_async_tx_descriptor *retval = NULL;
900 * Code accessing dma_async_is_complete() in a tight loop may give problems.
901 * If slaves are relying on interrupts to signal completion this function
902 * must not be called with interrupts disabled.
904 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
905 dma_cookie_t cookie, struct dma_tx_state *txstate)
907 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
908 dma_cookie_t last_used;
909 dma_cookie_t last_complete;
913 last_used = plchan->chan.cookie;
914 last_complete = plchan->lc;
916 ret = dma_async_is_complete(cookie, last_complete, last_used);
917 if (ret == DMA_SUCCESS) {
918 dma_set_tx_state(txstate, last_complete, last_used, 0);
923 * This cookie not complete yet
925 last_used = plchan->chan.cookie;
926 last_complete = plchan->lc;
928 /* Get number of bytes left in the active transactions and queue */
929 bytesleft = pl08x_getbytes_chan(plchan);
931 dma_set_tx_state(txstate, last_complete, last_used,
934 if (plchan->state == PL08X_CHAN_PAUSED)
937 /* Whether waiting or running, we're in progress */
938 return DMA_IN_PROGRESS;
941 /* PrimeCell DMA extension */
947 static const struct burst_table burst_sizes[] = {
950 .reg = PL080_BSIZE_256,
954 .reg = PL080_BSIZE_128,
958 .reg = PL080_BSIZE_64,
962 .reg = PL080_BSIZE_32,
966 .reg = PL080_BSIZE_16,
970 .reg = PL080_BSIZE_8,
974 .reg = PL080_BSIZE_4,
978 .reg = PL080_BSIZE_1,
983 * Given the source and destination available bus masks, select which
984 * will be routed to each port. We try to have source and destination
985 * on separate ports, but always respect the allowable settings.
987 static u32 pl08x_select_bus(u8 src, u8 dst)
991 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
992 cctl |= PL080_CONTROL_DST_AHB2;
993 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
994 cctl |= PL080_CONTROL_SRC_AHB2;
999 static u32 pl08x_cctl(u32 cctl)
1001 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1002 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1003 PL080_CONTROL_PROT_MASK);
1005 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1006 return cctl | PL080_CONTROL_PROT_SYS;
1009 static u32 pl08x_width(enum dma_slave_buswidth width)
1012 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1013 return PL080_WIDTH_8BIT;
1014 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1015 return PL080_WIDTH_16BIT;
1016 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1017 return PL080_WIDTH_32BIT;
1023 static u32 pl08x_burst(u32 maxburst)
1027 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1028 if (burst_sizes[i].burstwords <= maxburst)
1031 return burst_sizes[i].reg;
1034 static int dma_set_runtime_config(struct dma_chan *chan,
1035 struct dma_slave_config *config)
1037 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1038 struct pl08x_driver_data *pl08x = plchan->host;
1039 enum dma_slave_buswidth addr_width;
1040 u32 width, burst, maxburst;
1046 /* Transfer direction */
1047 plchan->runtime_direction = config->direction;
1048 if (config->direction == DMA_TO_DEVICE) {
1049 addr_width = config->dst_addr_width;
1050 maxburst = config->dst_maxburst;
1051 } else if (config->direction == DMA_FROM_DEVICE) {
1052 addr_width = config->src_addr_width;
1053 maxburst = config->src_maxburst;
1055 dev_err(&pl08x->adev->dev,
1056 "bad runtime_config: alien transfer direction\n");
1060 width = pl08x_width(addr_width);
1062 dev_err(&pl08x->adev->dev,
1063 "bad runtime_config: alien address width\n");
1067 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1068 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1071 * If this channel will only request single transfers, set this
1072 * down to ONE element. Also select one element if no maxburst
1075 if (plchan->cd->single)
1078 burst = pl08x_burst(maxburst);
1079 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1080 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1082 if (plchan->runtime_direction == DMA_FROM_DEVICE) {
1083 plchan->src_addr = config->src_addr;
1084 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1085 pl08x_select_bus(plchan->cd->periph_buses,
1088 plchan->dst_addr = config->dst_addr;
1089 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1090 pl08x_select_bus(pl08x->mem_buses,
1091 plchan->cd->periph_buses);
1094 dev_dbg(&pl08x->adev->dev,
1095 "configured channel %s (%s) for %s, data width %d, "
1096 "maxburst %d words, LE, CCTL=0x%08x\n",
1097 dma_chan_name(chan), plchan->name,
1098 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1107 * Slave transactions callback to the slave device to allow
1108 * synchronization of slave DMA signals with the DMAC enable
1110 static void pl08x_issue_pending(struct dma_chan *chan)
1112 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1113 unsigned long flags;
1115 spin_lock_irqsave(&plchan->lock, flags);
1116 /* Something is already active, or we're waiting for a channel... */
1117 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1118 spin_unlock_irqrestore(&plchan->lock, flags);
1122 /* Take the first element in the queue and execute it */
1123 if (!list_empty(&plchan->pend_list)) {
1124 struct pl08x_txd *next;
1126 next = list_first_entry(&plchan->pend_list,
1129 list_del(&next->node);
1130 plchan->state = PL08X_CHAN_RUNNING;
1132 pl08x_start_txd(plchan, next);
1135 spin_unlock_irqrestore(&plchan->lock, flags);
1138 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1139 struct pl08x_txd *txd)
1141 struct pl08x_driver_data *pl08x = plchan->host;
1142 unsigned long flags;
1145 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1151 spin_lock_irqsave(&plchan->lock, flags);
1154 * See if we already have a physical channel allocated,
1155 * else this is the time to try to get one.
1157 ret = prep_phy_channel(plchan, txd);
1160 * No physical channel was available.
1162 * memcpy transfers can be sorted out at submission time.
1164 * Slave transfers may have been denied due to platform
1165 * channel muxing restrictions. Since there is no guarantee
1166 * that this will ever be resolved, and the signal must be
1167 * acquired AFTER acquiring the physical channel, we will let
1168 * them be NACK:ed with -EBUSY here. The drivers can retry
1169 * the prep() call if they are eager on doing this using DMA.
1171 if (plchan->slave) {
1172 pl08x_free_txd_list(pl08x, plchan);
1173 pl08x_free_txd(pl08x, txd);
1174 spin_unlock_irqrestore(&plchan->lock, flags);
1179 * Else we're all set, paused and ready to roll, status
1180 * will switch to PL08X_CHAN_RUNNING when we call
1181 * issue_pending(). If there is something running on the
1182 * channel already we don't change its state.
1184 if (plchan->state == PL08X_CHAN_IDLE)
1185 plchan->state = PL08X_CHAN_PAUSED;
1187 spin_unlock_irqrestore(&plchan->lock, flags);
1192 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1193 unsigned long flags)
1195 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1198 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1199 txd->tx.flags = flags;
1200 txd->tx.tx_submit = pl08x_tx_submit;
1201 INIT_LIST_HEAD(&txd->node);
1203 /* Always enable error and terminal interrupts */
1204 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1205 PL080_CONFIG_TC_IRQ_MASK;
1211 * Initialize a descriptor to be used by memcpy submit
1213 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1214 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1215 size_t len, unsigned long flags)
1217 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1218 struct pl08x_driver_data *pl08x = plchan->host;
1219 struct pl08x_txd *txd;
1222 txd = pl08x_get_txd(plchan, flags);
1224 dev_err(&pl08x->adev->dev,
1225 "%s no memory for descriptor\n", __func__);
1229 txd->direction = DMA_NONE;
1230 txd->src_addr = src;
1231 txd->dst_addr = dest;
1234 /* Set platform data for m2m */
1235 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1236 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1237 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1239 /* Both to be incremented or the code will break */
1240 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1242 if (pl08x->vd->dualmaster)
1243 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1246 ret = pl08x_prep_channel_resources(plchan, txd);
1253 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1254 struct dma_chan *chan, struct scatterlist *sgl,
1255 unsigned int sg_len, enum dma_data_direction direction,
1256 unsigned long flags)
1258 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1259 struct pl08x_driver_data *pl08x = plchan->host;
1260 struct pl08x_txd *txd;
1264 * Current implementation ASSUMES only one sg
1267 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1272 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1273 __func__, sgl->length, plchan->name);
1275 txd = pl08x_get_txd(plchan, flags);
1277 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1281 if (direction != plchan->runtime_direction)
1282 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1283 "the direction configured for the PrimeCell\n",
1287 * Set up addresses, the PrimeCell configured address
1288 * will take precedence since this may configure the
1289 * channel target address dynamically at runtime.
1291 txd->direction = direction;
1292 txd->len = sgl->length;
1294 if (direction == DMA_TO_DEVICE) {
1295 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1296 txd->cctl = plchan->dst_cctl;
1297 txd->src_addr = sgl->dma_address;
1298 txd->dst_addr = plchan->dst_addr;
1299 } else if (direction == DMA_FROM_DEVICE) {
1300 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1301 txd->cctl = plchan->src_cctl;
1302 txd->src_addr = plchan->src_addr;
1303 txd->dst_addr = sgl->dma_address;
1305 dev_err(&pl08x->adev->dev,
1306 "%s direction unsupported\n", __func__);
1310 ret = pl08x_prep_channel_resources(plchan, txd);
1317 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1320 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1321 struct pl08x_driver_data *pl08x = plchan->host;
1322 unsigned long flags;
1325 /* Controls applicable to inactive channels */
1326 if (cmd == DMA_SLAVE_CONFIG) {
1327 return dma_set_runtime_config(chan,
1328 (struct dma_slave_config *)arg);
1332 * Anything succeeds on channels with no physical allocation and
1333 * no queued transfers.
1335 spin_lock_irqsave(&plchan->lock, flags);
1336 if (!plchan->phychan && !plchan->at) {
1337 spin_unlock_irqrestore(&plchan->lock, flags);
1342 case DMA_TERMINATE_ALL:
1343 plchan->state = PL08X_CHAN_IDLE;
1345 if (plchan->phychan) {
1346 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1349 * Mark physical channel as free and free any slave
1352 release_phy_channel(plchan);
1354 /* Dequeue jobs and free LLIs */
1356 pl08x_free_txd(pl08x, plchan->at);
1359 /* Dequeue jobs not yet fired as well */
1360 pl08x_free_txd_list(pl08x, plchan);
1363 pl08x_pause_phy_chan(plchan->phychan);
1364 plchan->state = PL08X_CHAN_PAUSED;
1367 pl08x_resume_phy_chan(plchan->phychan);
1368 plchan->state = PL08X_CHAN_RUNNING;
1371 /* Unknown command */
1376 spin_unlock_irqrestore(&plchan->lock, flags);
1381 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1383 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1384 char *name = chan_id;
1386 /* Check that the channel is not taken! */
1387 if (!strcmp(plchan->name, name))
1394 * Just check that the device is there and active
1395 * TODO: turn this bit on/off depending on the number of physical channels
1396 * actually used, if it is zero... well shut it off. That will save some
1397 * power. Cut the clock at the same time.
1399 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1401 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1404 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1406 struct device *dev = txd->tx.chan->device->dev;
1408 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1409 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1410 dma_unmap_single(dev, txd->src_addr, txd->len,
1413 dma_unmap_page(dev, txd->src_addr, txd->len,
1416 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1417 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1418 dma_unmap_single(dev, txd->dst_addr, txd->len,
1421 dma_unmap_page(dev, txd->dst_addr, txd->len,
1426 static void pl08x_tasklet(unsigned long data)
1428 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1429 struct pl08x_driver_data *pl08x = plchan->host;
1430 struct pl08x_txd *txd;
1431 unsigned long flags;
1433 spin_lock_irqsave(&plchan->lock, flags);
1439 /* Update last completed */
1440 plchan->lc = txd->tx.cookie;
1443 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1444 if (!list_empty(&plchan->pend_list)) {
1445 struct pl08x_txd *next;
1447 next = list_first_entry(&plchan->pend_list,
1450 list_del(&next->node);
1452 pl08x_start_txd(plchan, next);
1453 } else if (plchan->phychan_hold) {
1455 * This channel is still in use - we have a new txd being
1456 * prepared and will soon be queued. Don't give up the
1460 struct pl08x_dma_chan *waiting = NULL;
1463 * No more jobs, so free up the physical channel
1464 * Free any allocated signal on slave transfers too
1466 release_phy_channel(plchan);
1467 plchan->state = PL08X_CHAN_IDLE;
1470 * And NOW before anyone else can grab that free:d up
1471 * physical channel, see if there is some memcpy pending
1472 * that seriously needs to start because of being stacked
1473 * up while we were choking the physical channels with data.
1475 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1477 if (waiting->state == PL08X_CHAN_WAITING &&
1478 waiting->waiting != NULL) {
1481 /* This should REALLY not fail now */
1482 ret = prep_phy_channel(waiting,
1485 waiting->phychan_hold--;
1486 waiting->state = PL08X_CHAN_RUNNING;
1487 waiting->waiting = NULL;
1488 pl08x_issue_pending(&waiting->chan);
1494 spin_unlock_irqrestore(&plchan->lock, flags);
1497 dma_async_tx_callback callback = txd->tx.callback;
1498 void *callback_param = txd->tx.callback_param;
1500 /* Don't try to unmap buffers on slave channels */
1502 pl08x_unmap_buffers(txd);
1504 /* Free the descriptor */
1505 spin_lock_irqsave(&plchan->lock, flags);
1506 pl08x_free_txd(pl08x, txd);
1507 spin_unlock_irqrestore(&plchan->lock, flags);
1509 /* Callback to signal completion */
1511 callback(callback_param);
1515 static irqreturn_t pl08x_irq(int irq, void *dev)
1517 struct pl08x_driver_data *pl08x = dev;
1518 u32 mask = 0, err, tc, i;
1520 /* check & clear - ERR & TC interrupts */
1521 err = readl(pl08x->base + PL080_ERR_STATUS);
1523 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1525 writel(err, pl08x->base + PL080_ERR_CLEAR);
1527 tc = readl(pl08x->base + PL080_INT_STATUS);
1529 writel(tc, pl08x->base + PL080_TC_CLEAR);
1534 for (i = 0; i < pl08x->vd->channels; i++) {
1535 if (((1 << i) & err) || ((1 << i) & tc)) {
1536 /* Locate physical channel */
1537 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1538 struct pl08x_dma_chan *plchan = phychan->serving;
1541 dev_err(&pl08x->adev->dev,
1542 "%s Error TC interrupt on unused channel: 0x%08x\n",
1547 /* Schedule tasklet on this channel */
1548 tasklet_schedule(&plchan->tasklet);
1553 return mask ? IRQ_HANDLED : IRQ_NONE;
1556 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1558 u32 cctl = pl08x_cctl(chan->cd->cctl);
1561 chan->name = chan->cd->bus_id;
1562 chan->src_addr = chan->cd->addr;
1563 chan->dst_addr = chan->cd->addr;
1564 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1565 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1566 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1567 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1571 * Initialise the DMAC memcpy/slave channels.
1572 * Make a local wrapper to hold required data
1574 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1575 struct dma_device *dmadev, unsigned int channels, bool slave)
1577 struct pl08x_dma_chan *chan;
1580 INIT_LIST_HEAD(&dmadev->channels);
1583 * Register as many many memcpy as we have physical channels,
1584 * we won't always be able to use all but the code will have
1585 * to cope with that situation.
1587 for (i = 0; i < channels; i++) {
1588 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1590 dev_err(&pl08x->adev->dev,
1591 "%s no memory for channel\n", __func__);
1596 chan->state = PL08X_CHAN_IDLE;
1599 chan->cd = &pl08x->pd->slave_channels[i];
1600 pl08x_dma_slave_init(chan);
1602 chan->cd = &pl08x->pd->memcpy_channel;
1603 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1609 if (chan->cd->circular_buffer) {
1610 dev_err(&pl08x->adev->dev,
1611 "channel %s: circular buffers not supported\n",
1616 dev_dbg(&pl08x->adev->dev,
1617 "initialize virtual channel \"%s\"\n",
1620 chan->chan.device = dmadev;
1621 chan->chan.cookie = 0;
1624 spin_lock_init(&chan->lock);
1625 INIT_LIST_HEAD(&chan->pend_list);
1626 tasklet_init(&chan->tasklet, pl08x_tasklet,
1627 (unsigned long) chan);
1629 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1631 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1632 i, slave ? "slave" : "memcpy");
1636 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1638 struct pl08x_dma_chan *chan = NULL;
1639 struct pl08x_dma_chan *next;
1641 list_for_each_entry_safe(chan,
1642 next, &dmadev->channels, chan.device_node) {
1643 list_del(&chan->chan.device_node);
1648 #ifdef CONFIG_DEBUG_FS
1649 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1652 case PL08X_CHAN_IDLE:
1654 case PL08X_CHAN_RUNNING:
1656 case PL08X_CHAN_PAUSED:
1658 case PL08X_CHAN_WAITING:
1663 return "UNKNOWN STATE";
1666 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1668 struct pl08x_driver_data *pl08x = s->private;
1669 struct pl08x_dma_chan *chan;
1670 struct pl08x_phy_chan *ch;
1671 unsigned long flags;
1674 seq_printf(s, "PL08x physical channels:\n");
1675 seq_printf(s, "CHANNEL:\tUSER:\n");
1676 seq_printf(s, "--------\t-----\n");
1677 for (i = 0; i < pl08x->vd->channels; i++) {
1678 struct pl08x_dma_chan *virt_chan;
1680 ch = &pl08x->phy_chans[i];
1682 spin_lock_irqsave(&ch->lock, flags);
1683 virt_chan = ch->serving;
1685 seq_printf(s, "%d\t\t%s\n",
1686 ch->id, virt_chan ? virt_chan->name : "(none)");
1688 spin_unlock_irqrestore(&ch->lock, flags);
1691 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1692 seq_printf(s, "CHANNEL:\tSTATE:\n");
1693 seq_printf(s, "--------\t------\n");
1694 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1695 seq_printf(s, "%s\t\t%s\n", chan->name,
1696 pl08x_state_str(chan->state));
1699 seq_printf(s, "\nPL08x virtual slave channels:\n");
1700 seq_printf(s, "CHANNEL:\tSTATE:\n");
1701 seq_printf(s, "--------\t------\n");
1702 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1703 seq_printf(s, "%s\t\t%s\n", chan->name,
1704 pl08x_state_str(chan->state));
1710 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1712 return single_open(file, pl08x_debugfs_show, inode->i_private);
1715 static const struct file_operations pl08x_debugfs_operations = {
1716 .open = pl08x_debugfs_open,
1718 .llseek = seq_lseek,
1719 .release = single_release,
1722 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1724 /* Expose a simple debugfs interface to view all clocks */
1725 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1726 S_IFREG | S_IRUGO, NULL, pl08x,
1727 &pl08x_debugfs_operations);
1731 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1736 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1738 struct pl08x_driver_data *pl08x;
1739 const struct vendor_data *vd = id->data;
1743 ret = amba_request_regions(adev, NULL);
1747 /* Create the driver state holder */
1748 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
1754 pm_runtime_set_active(&adev->dev);
1755 pm_runtime_enable(&adev->dev);
1757 /* Initialize memcpy engine */
1758 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1759 pl08x->memcpy.dev = &adev->dev;
1760 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1761 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1762 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1763 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1764 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1765 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1766 pl08x->memcpy.device_control = pl08x_control;
1768 /* Initialize slave engine */
1769 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1770 pl08x->slave.dev = &adev->dev;
1771 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1772 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1773 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1774 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1775 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1776 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1777 pl08x->slave.device_control = pl08x_control;
1779 /* Get the platform data */
1780 pl08x->pd = dev_get_platdata(&adev->dev);
1782 dev_err(&adev->dev, "no platform data supplied\n");
1783 goto out_no_platdata;
1786 /* Assign useful pointers to the driver state */
1790 /* By default, AHB1 only. If dualmaster, from platform */
1791 pl08x->lli_buses = PL08X_AHB1;
1792 pl08x->mem_buses = PL08X_AHB1;
1793 if (pl08x->vd->dualmaster) {
1794 pl08x->lli_buses = pl08x->pd->lli_buses;
1795 pl08x->mem_buses = pl08x->pd->mem_buses;
1798 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1799 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1800 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1803 goto out_no_lli_pool;
1806 spin_lock_init(&pl08x->lock);
1808 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1811 goto out_no_ioremap;
1814 /* Turn on the PL08x */
1815 pl08x_ensure_on(pl08x);
1817 /* Attach the interrupt handler */
1818 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1819 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1821 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1822 DRIVER_NAME, pl08x);
1824 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1825 __func__, adev->irq[0]);
1829 /* Initialize physical channels */
1830 pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)),
1832 if (!pl08x->phy_chans) {
1833 dev_err(&adev->dev, "%s failed to allocate "
1834 "physical channel holders\n",
1836 goto out_no_phychans;
1839 for (i = 0; i < vd->channels; i++) {
1840 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1843 ch->base = pl08x->base + PL080_Cx_BASE(i);
1844 spin_lock_init(&ch->lock);
1847 dev_dbg(&adev->dev, "physical channel %d is %s\n",
1848 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1851 /* Register as many memcpy channels as there are physical channels */
1852 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1853 pl08x->vd->channels, false);
1855 dev_warn(&pl08x->adev->dev,
1856 "%s failed to enumerate memcpy channels - %d\n",
1860 pl08x->memcpy.chancnt = ret;
1862 /* Register slave channels */
1863 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1864 pl08x->pd->num_slave_channels, true);
1866 dev_warn(&pl08x->adev->dev,
1867 "%s failed to enumerate slave channels - %d\n",
1871 pl08x->slave.chancnt = ret;
1873 ret = dma_async_device_register(&pl08x->memcpy);
1875 dev_warn(&pl08x->adev->dev,
1876 "%s failed to register memcpy as an async device - %d\n",
1878 goto out_no_memcpy_reg;
1881 ret = dma_async_device_register(&pl08x->slave);
1883 dev_warn(&pl08x->adev->dev,
1884 "%s failed to register slave as an async device - %d\n",
1886 goto out_no_slave_reg;
1889 amba_set_drvdata(adev, pl08x);
1890 init_pl08x_debugfs(pl08x);
1891 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1892 amba_part(adev), amba_rev(adev),
1893 (unsigned long long)adev->res.start, adev->irq[0]);
1895 pm_runtime_put(&adev->dev);
1899 dma_async_device_unregister(&pl08x->memcpy);
1901 pl08x_free_virtual_channels(&pl08x->slave);
1903 pl08x_free_virtual_channels(&pl08x->memcpy);
1905 kfree(pl08x->phy_chans);
1907 free_irq(adev->irq[0], pl08x);
1909 iounmap(pl08x->base);
1911 dma_pool_destroy(pl08x->pool);
1914 pm_runtime_put(&adev->dev);
1915 pm_runtime_disable(&adev->dev);
1919 amba_release_regions(adev);
1923 /* PL080 has 8 channels and the PL080 have just 2 */
1924 static struct vendor_data vendor_pl080 = {
1929 static struct vendor_data vendor_pl081 = {
1931 .dualmaster = false,
1934 static struct amba_id pl08x_ids[] = {
1939 .data = &vendor_pl080,
1945 .data = &vendor_pl081,
1947 /* Nomadik 8815 PL080 variant */
1951 .data = &vendor_pl080,
1956 static struct amba_driver pl08x_amba_driver = {
1957 .drv.name = DRIVER_NAME,
1958 .id_table = pl08x_ids,
1959 .probe = pl08x_probe,
1962 static int __init pl08x_init(void)
1965 retval = amba_driver_register(&pl08x_amba_driver);
1967 printk(KERN_WARNING DRIVER_NAME
1968 "failed to register as an AMBA device (%d)\n",
1972 subsys_initcall(pl08x_init);