drivers/clk/spear/spear1310_clock.c

   1 /*
   2  * arch/arm/mach-spear13xx/spear1310_clock.c
   3  *
   4  * SPEAr1310 machine clock framework source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/spinlock_types.h>
  20 #include <mach/spear.h>
  21 #include "clk.h"
  22
  23 /* PLL related registers and bit values */
  24 #define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
  25         /* PLL_CFG bit values */
  26         #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
  27         #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
  28         #define SPEAR1310_RAS_SYNT2_3_CLK_MASK          2
  29         #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT         29
  30         #define SPEAR1310_RAS_SYNT_CLK_MASK             2
  31         #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT         27
  32         #define SPEAR1310_PLL_CLK_MASK                  2
  33         #define SPEAR1310_PLL3_CLK_SHIFT                24
  34         #define SPEAR1310_PLL2_CLK_SHIFT                22
  35         #define SPEAR1310_PLL1_CLK_SHIFT                20
  36
  37 #define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
  38 #define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
  39 #define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
  40 #define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
  41 #define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
  42 #define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
  43 #define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
  44 #define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
  45 #define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
  46         /* PERIP_CLK_CFG bit values */
  47         #define SPEAR1310_GPT_OSC24_VAL                 0
  48         #define SPEAR1310_GPT_APB_VAL                   1
  49         #define SPEAR1310_GPT_CLK_MASK                  1
  50         #define SPEAR1310_GPT3_CLK_SHIFT                11
  51         #define SPEAR1310_GPT2_CLK_SHIFT                10
  52         #define SPEAR1310_GPT1_CLK_SHIFT                9
  53         #define SPEAR1310_GPT0_CLK_SHIFT                8
  54         #define SPEAR1310_UART_CLK_PLL5_VAL             0
  55         #define SPEAR1310_UART_CLK_OSC24_VAL            1
  56         #define SPEAR1310_UART_CLK_SYNT_VAL             2
  57         #define SPEAR1310_UART_CLK_MASK                 2
  58         #define SPEAR1310_UART_CLK_SHIFT                4
  59
  60         #define SPEAR1310_AUX_CLK_PLL5_VAL              0
  61         #define SPEAR1310_AUX_CLK_SYNT_VAL              1
  62         #define SPEAR1310_CLCD_CLK_MASK                 2
  63         #define SPEAR1310_CLCD_CLK_SHIFT                2
  64         #define SPEAR1310_C3_CLK_MASK                   1
  65         #define SPEAR1310_C3_CLK_SHIFT                  1
  66
  67 #define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
  68         #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
  69         #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
  70         #define SPEAR1310_GMAC_PHY_CLK_MASK             1
  71         #define SPEAR1310_GMAC_PHY_CLK_SHIFT            3
  72         #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
  73         #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
  74
  75 #define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
  76         /* I2S_CLK_CFG register mask */
  77         #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
  78         #define SPEAR1310_I2S_SCLK_X_SHIFT              27
  79         #define SPEAR1310_I2S_SCLK_Y_MASK               0x1F
  80         #define SPEAR1310_I2S_SCLK_Y_SHIFT              22
  81         #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT         21
  82         #define SPEAR1310_I2S_SCLK_SYNTH_ENB            20
  83         #define SPEAR1310_I2S_PRS1_CLK_X_MASK           0xFF
  84         #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT          12
  85         #define SPEAR1310_I2S_PRS1_CLK_Y_MASK           0xFF
  86         #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT          4
  87         #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT         3
  88         #define SPEAR1310_I2S_REF_SEL_MASK              1
  89         #define SPEAR1310_I2S_REF_SHIFT                 2
  90         #define SPEAR1310_I2S_SRC_CLK_MASK              2
  91         #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
  92
  93 #define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
  94 #define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
  95 #define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
  96 #define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
  97 #define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
  98 #define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
  99 #define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
 100 #define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
 101 #define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
 102 #define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
 103 #define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
 104 #define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
 105         /* Check Fractional synthesizer reg masks */
 106
 107 #define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
 108         /* PERIP1_CLK_ENB register masks */
 109         #define SPEAR1310_RTC_CLK_ENB                   31
 110         #define SPEAR1310_ADC_CLK_ENB                   30
 111         #define SPEAR1310_C3_CLK_ENB                    29
 112         #define SPEAR1310_JPEG_CLK_ENB                  28
 113         #define SPEAR1310_CLCD_CLK_ENB                  27
 114         #define SPEAR1310_DMA_CLK_ENB                   25
 115         #define SPEAR1310_GPIO1_CLK_ENB                 24
 116         #define SPEAR1310_GPIO0_CLK_ENB                 23
 117         #define SPEAR1310_GPT1_CLK_ENB                  22
 118         #define SPEAR1310_GPT0_CLK_ENB                  21
 119         #define SPEAR1310_I2S0_CLK_ENB                  20
 120         #define SPEAR1310_I2S1_CLK_ENB                  19
 121         #define SPEAR1310_I2C0_CLK_ENB                  18
 122         #define SPEAR1310_SSP_CLK_ENB                   17
 123         #define SPEAR1310_UART_CLK_ENB                  15
 124         #define SPEAR1310_PCIE_SATA_2_CLK_ENB           14
 125         #define SPEAR1310_PCIE_SATA_1_CLK_ENB           13
 126         #define SPEAR1310_PCIE_SATA_0_CLK_ENB           12
 127         #define SPEAR1310_UOC_CLK_ENB                   11
 128         #define SPEAR1310_UHC1_CLK_ENB                  10
 129         #define SPEAR1310_UHC0_CLK_ENB                  9
 130         #define SPEAR1310_GMAC_CLK_ENB                  8
 131         #define SPEAR1310_CFXD_CLK_ENB                  7
 132         #define SPEAR1310_SDHCI_CLK_ENB                 6
 133         #define SPEAR1310_SMI_CLK_ENB                   5
 134         #define SPEAR1310_FSMC_CLK_ENB                  4
 135         #define SPEAR1310_SYSRAM0_CLK_ENB               3
 136         #define SPEAR1310_SYSRAM1_CLK_ENB               2
 137         #define SPEAR1310_SYSROM_CLK_ENB                1
 138         #define SPEAR1310_BUS_CLK_ENB                   0
 139
 140 #define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
 141         /* PERIP2_CLK_ENB register masks */
 142         #define SPEAR1310_THSENS_CLK_ENB                8
 143         #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
 144         #define SPEAR1310_ACP_CLK_ENB                   6
 145         #define SPEAR1310_GPT3_CLK_ENB                  5
 146         #define SPEAR1310_GPT2_CLK_ENB                  4
 147         #define SPEAR1310_KBD_CLK_ENB                   3
 148         #define SPEAR1310_CPU_DBG_CLK_ENB               2
 149         #define SPEAR1310_DDR_CORE_CLK_ENB              1
 150         #define SPEAR1310_DDR_CTRL_CLK_ENB              0
 151
 152 #define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
 153         /* RAS_CLK_ENB register masks */
 154         #define SPEAR1310_SYNT3_CLK_ENB                 17
 155         #define SPEAR1310_SYNT2_CLK_ENB                 16
 156         #define SPEAR1310_SYNT1_CLK_ENB                 15
 157         #define SPEAR1310_SYNT0_CLK_ENB                 14
 158         #define SPEAR1310_PCLK3_CLK_ENB                 13
 159         #define SPEAR1310_PCLK2_CLK_ENB                 12
 160         #define SPEAR1310_PCLK1_CLK_ENB                 11
 161         #define SPEAR1310_PCLK0_CLK_ENB                 10
 162         #define SPEAR1310_PLL3_CLK_ENB                  9
 163         #define SPEAR1310_PLL2_CLK_ENB                  8
 164         #define SPEAR1310_C125M_PAD_CLK_ENB             7
 165         #define SPEAR1310_C30M_CLK_ENB                  6
 166         #define SPEAR1310_C48M_CLK_ENB                  5
 167         #define SPEAR1310_OSC_25M_CLK_ENB               4
 168         #define SPEAR1310_OSC_32K_CLK_ENB               3
 169         #define SPEAR1310_OSC_24M_CLK_ENB               2
 170         #define SPEAR1310_PCLK_CLK_ENB                  1
 171         #define SPEAR1310_ACLK_CLK_ENB                  0
 172
 173 /* RAS Area Control Register */
 174 #define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
 175         #define SPEAR1310_SSP1_CLK_MASK                 3
 176         #define SPEAR1310_SSP1_CLK_SHIFT                26
 177         #define SPEAR1310_TDM_CLK_MASK                  1
 178         #define SPEAR1310_TDM2_CLK_SHIFT                24
 179         #define SPEAR1310_TDM1_CLK_SHIFT                23
 180         #define SPEAR1310_I2C_CLK_MASK                  1
 181         #define SPEAR1310_I2C7_CLK_SHIFT                22
 182         #define SPEAR1310_I2C6_CLK_SHIFT                21
 183         #define SPEAR1310_I2C5_CLK_SHIFT                20
 184         #define SPEAR1310_I2C4_CLK_SHIFT                19
 185         #define SPEAR1310_I2C3_CLK_SHIFT                18
 186         #define SPEAR1310_I2C2_CLK_SHIFT                17
 187         #define SPEAR1310_I2C1_CLK_SHIFT                16
 188         #define SPEAR1310_GPT64_CLK_MASK                1
 189         #define SPEAR1310_GPT64_CLK_SHIFT               15
 190         #define SPEAR1310_RAS_UART_CLK_MASK             1
 191         #define SPEAR1310_UART5_CLK_SHIFT               14
 192         #define SPEAR1310_UART4_CLK_SHIFT               13
 193         #define SPEAR1310_UART3_CLK_SHIFT               12
 194         #define SPEAR1310_UART2_CLK_SHIFT               11
 195         #define SPEAR1310_UART1_CLK_SHIFT               10
 196         #define SPEAR1310_PCI_CLK_MASK                  1
 197         #define SPEAR1310_PCI_CLK_SHIFT                 0
 198
 199 #define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
 200         #define SPEAR1310_PHY_CLK_MASK                  0x3
 201         #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
 202         #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
 203
 204 #define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
 205         #define SPEAR1310_CAN1_CLK_ENB                  25
 206         #define SPEAR1310_CAN0_CLK_ENB                  24
 207         #define SPEAR1310_GPT64_CLK_ENB                 23
 208         #define SPEAR1310_SSP1_CLK_ENB                  22
 209         #define SPEAR1310_I2C7_CLK_ENB                  21
 210         #define SPEAR1310_I2C6_CLK_ENB                  20
 211         #define SPEAR1310_I2C5_CLK_ENB                  19
 212         #define SPEAR1310_I2C4_CLK_ENB                  18
 213         #define SPEAR1310_I2C3_CLK_ENB                  17
 214         #define SPEAR1310_I2C2_CLK_ENB                  16
 215         #define SPEAR1310_I2C1_CLK_ENB                  15
 216         #define SPEAR1310_UART5_CLK_ENB                 14
 217         #define SPEAR1310_UART4_CLK_ENB                 13
 218         #define SPEAR1310_UART3_CLK_ENB                 12
 219         #define SPEAR1310_UART2_CLK_ENB                 11
 220         #define SPEAR1310_UART1_CLK_ENB                 10
 221         #define SPEAR1310_RS485_1_CLK_ENB               9
 222         #define SPEAR1310_RS485_0_CLK_ENB               8
 223         #define SPEAR1310_TDM2_CLK_ENB                  7
 224         #define SPEAR1310_TDM1_CLK_ENB                  6
 225         #define SPEAR1310_PCI_CLK_ENB                   5
 226         #define SPEAR1310_GMII_CLK_ENB                  4
 227         #define SPEAR1310_MII2_CLK_ENB                  3
 228         #define SPEAR1310_MII1_CLK_ENB                  2
 229         #define SPEAR1310_MII0_CLK_ENB                  1
 230         #define SPEAR1310_ESRAM_CLK_ENB                 0
 231
 232 static DEFINE_SPINLOCK(_lock);
 233
 234 /* pll rate configuration table, in ascending order of rates */
 235 static struct pll_rate_tbl pll_rtbl[] = {
 236         /* PCLK 24MHz */
 237         {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
 238         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
 239         {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
 240         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
 241         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
 242         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
 243         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 244 };
 245
 246 /* vco-pll4 rate configuration table, in ascending order of rates */
 247 static struct pll_rate_tbl pll4_rtbl[] = {
 248         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
 249         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
 250         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
 251         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 252 };
 253
 254 /* aux rate configuration table, in ascending order of rates */
 255 static struct aux_rate_tbl aux_rtbl[] = {
 256         /* For VCO1div2 = 500 MHz */
 257         {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
 258         {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
 259         {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
 260         {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
 261         {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
 262         {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
 263 };
 264
 265 /* gmac rate configuration table, in ascending order of rates */
 266 static struct aux_rate_tbl gmac_rtbl[] = {
 267         /* For gmac phy input clk */
 268         {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
 269         {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
 270         {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
 271         {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
 272 };
 273
 274 /* clcd rate configuration table, in ascending order of rates */
 275 static struct frac_rate_tbl clcd_rtbl[] = {
 276         {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
 277         {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
 278         {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
 279         {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
 280         {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
 281         {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
 282         {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
 283         {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
 284         {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
 285         {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
 286 };
 287
 288 /* i2s prescaler1 masks */
 289 static struct aux_clk_masks i2s_prs1_masks = {
 290         .eq_sel_mask = AUX_EQ_SEL_MASK,
 291         .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
 292         .eq1_mask = AUX_EQ1_SEL,
 293         .eq2_mask = AUX_EQ2_SEL,
 294         .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
 295         .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
 296         .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
 297         .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
 298 };
 299
 300 /* i2s sclk (bit clock) syynthesizers masks */
 301 static struct aux_clk_masks i2s_sclk_masks = {
 302         .eq_sel_mask = AUX_EQ_SEL_MASK,
 303         .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
 304         .eq1_mask = AUX_EQ1_SEL,
 305         .eq2_mask = AUX_EQ2_SEL,
 306         .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
 307         .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
 308         .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
 309         .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
 310         .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
 311 };
 312
 313 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 314 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 315         /* For parent clk = 49.152 MHz */
 316         {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
 317 };
 318
 319 /* i2s sclk aux rate configuration table, in ascending order of rates */
 320 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
 321         /* For i2s_ref_clk = 12.288MHz */
 322         {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
 323         {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
 324 };
 325
 326 /* adc rate configuration table, in ascending order of rates */
 327 /* possible adc range is 2.5 MHz to 20 MHz. */
 328 static struct aux_rate_tbl adc_rtbl[] = {
 329         /* For ahb = 166.67 MHz */
 330         {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
 331         {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
 332         {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
 333         {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
 334 };
 335
 336 /* General synth rate configuration table, in ascending order of rates */
 337 static struct frac_rate_tbl gen_rtbl[] = {
 338         /* For vco1div4 = 250 MHz */
 339         {.div = 0x14000}, /* 25 MHz */
 340         {.div = 0x0A000}, /* 50 MHz */
 341         {.div = 0x05000}, /* 100 MHz */
 342         {.div = 0x02000}, /* 250 MHz */
 343 };
 344
 345 /* clock parents */
 346 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 347 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 348 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
 349 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
 350 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
 351         "osc_25m_clk", };
 352 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
 353 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
 354 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
 355 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
 356         "i2s_src_pad_clk", };
 357 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
 358 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 359         "pll3_clk", };
 360 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
 361         "pll2_clk", };
 362 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
 363         "ras_pll2_clk", "ras_syn0_clk", };
 364 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
 365         "ras_pll2_clk", "ras_syn0_clk", };
 366 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
 367 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
 368 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
 369         "ras_plclk0_clk", };
 370 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
 371 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
 372
 373 void __init spear1310_clk_init(void)
 374 {
 375         struct clk *clk, *clk1;
 376
 377         clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
 378         clk_register_clkdev(clk, "apb_pclk", NULL);
 379
 380         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 381                         32000);
 382         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 383
 384         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
 385                         24000000);
 386         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 387
 388         clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
 389                         25000000);
 390         clk_register_clkdev(clk, "osc_25m_clk", NULL);
 391
 392         clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
 393                         125000000);
 394         clk_register_clkdev(clk, "gmii_pad_clk", NULL);
 395
 396         clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
 397                         CLK_IS_ROOT, 12288000);
 398         clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
 399
 400         /* clock derived from 32 KHz osc clk */
 401         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 402                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
 403                         &_lock);
 404         clk_register_clkdev(clk, NULL, "fc900000.rtc");
 405
 406         /* clock derived from 24 or 25 MHz osc clk */
 407         /* vco-pll */
 408         clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
 409                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 410                         SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 411                         &_lock);
 412         clk_register_clkdev(clk, "vco1_mclk", NULL);
 413         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
 414                         0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
 415                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 416         clk_register_clkdev(clk, "vco1_clk", NULL);
 417         clk_register_clkdev(clk1, "pll1_clk", NULL);
 418
 419         clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
 420                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 421                         SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 422                         &_lock);
 423         clk_register_clkdev(clk, "vco2_mclk", NULL);
 424         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
 425                         0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
 426                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 427         clk_register_clkdev(clk, "vco2_clk", NULL);
 428         clk_register_clkdev(clk1, "pll2_clk", NULL);
 429
 430         clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
 431                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 432                         SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 433                         &_lock);
 434         clk_register_clkdev(clk, "vco3_mclk", NULL);
 435         clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
 436                         0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
 437                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 438         clk_register_clkdev(clk, "vco3_clk", NULL);
 439         clk_register_clkdev(clk1, "pll3_clk", NULL);
 440
 441         clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
 442                         0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
 443                         ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
 444         clk_register_clkdev(clk, "vco4_clk", NULL);
 445         clk_register_clkdev(clk1, "pll4_clk", NULL);
 446
 447         clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
 448                         48000000);
 449         clk_register_clkdev(clk, "pll5_clk", NULL);
 450
 451         clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
 452                         25000000);
 453         clk_register_clkdev(clk, "pll6_clk", NULL);
 454
 455         /* vco div n clocks */
 456         clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
 457                         2);
 458         clk_register_clkdev(clk, "vco1div2_clk", NULL);
 459
 460         clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
 461                         4);
 462         clk_register_clkdev(clk, "vco1div4_clk", NULL);
 463
 464         clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
 465                         2);
 466         clk_register_clkdev(clk, "vco2div2_clk", NULL);
 467
 468         clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
 469                         2);
 470         clk_register_clkdev(clk, "vco3div2_clk", NULL);
 471
 472         /* peripherals */
 473         clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
 474                         128);
 475         clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
 476                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
 477                         &_lock);
 478         clk_register_clkdev(clk, NULL, "spear_thermal");
 479
 480         /* clock derived from pll4 clk */
 481         clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
 482                         1);
 483         clk_register_clkdev(clk, "ddr_clk", NULL);
 484
 485         /* clock derived from pll1 clk */
 486         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
 487         clk_register_clkdev(clk, "cpu_clk", NULL);
 488
 489         clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
 490                         2);
 491         clk_register_clkdev(clk, NULL, "ec800620.wdt");
 492
 493         clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 494                         6);
 495         clk_register_clkdev(clk, "ahb_clk", NULL);
 496
 497         clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
 498                         12);
 499         clk_register_clkdev(clk, "apb_clk", NULL);
 500
 501         /* gpt clocks */
 502         clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
 503                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 504                         SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 505                         &_lock);
 506         clk_register_clkdev(clk, "gpt0_mclk", NULL);
 507         clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 508                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
 509                         &_lock);
 510         clk_register_clkdev(clk, NULL, "gpt0");
 511
 512         clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
 513                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 514                         SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 515                         &_lock);
 516         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 517         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 518                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
 519                         &_lock);
 520         clk_register_clkdev(clk, NULL, "gpt1");
 521
 522         clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
 523                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 524                         SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 525                         &_lock);
 526         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 527         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 528                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
 529                         &_lock);
 530         clk_register_clkdev(clk, NULL, "gpt2");
 531
 532         clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
 533                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 534                         SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 535                         &_lock);
 536         clk_register_clkdev(clk, "gpt3_mclk", NULL);
 537         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 538                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
 539                         &_lock);
 540         clk_register_clkdev(clk, NULL, "gpt3");
 541
 542         /* others */
 543         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
 544                         0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
 545                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 546         clk_register_clkdev(clk, "uart_syn_clk", NULL);
 547         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 548
 549         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
 550                         ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 551                         SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
 552                         &_lock);
 553         clk_register_clkdev(clk, "uart0_mclk", NULL);
 554
 555         clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0,
 556                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
 557                         &_lock);
 558         clk_register_clkdev(clk, NULL, "e0000000.serial");
 559
 560         clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
 561                         "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
 562                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 563         clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
 564         clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
 565
 566         clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0,
 567                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
 568                         &_lock);
 569         clk_register_clkdev(clk, NULL, "b3000000.sdhci");
 570
 571         clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
 572                         0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
 573                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 574         clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
 575         clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
 576
 577         clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0,
 578                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
 579                         &_lock);
 580         clk_register_clkdev(clk, NULL, "b2800000.cf");
 581         clk_register_clkdev(clk, NULL, "arasan_xd");
 582
 583         clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
 584                         0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
 585                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 586         clk_register_clkdev(clk, "c3_syn_clk", NULL);
 587         clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 588
 589         clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
 590                         ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 591                         SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
 592                         &_lock);
 593         clk_register_clkdev(clk, "c3_mclk", NULL);
 594
 595         clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
 596                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
 597                         &_lock);
 598         clk_register_clkdev(clk, NULL, "c3");
 599
 600         /* gmac */
 601         clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
 602                         ARRAY_SIZE(gmac_phy_input_parents), 0,
 603                         SPEAR1310_GMAC_CLK_CFG,
 604                         SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 605                         SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 606         clk_register_clkdev(clk, "phy_input_mclk", NULL);
 607
 608         clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
 609                         0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
 610                         ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
 611         clk_register_clkdev(clk, "phy_syn_clk", NULL);
 612         clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 613
 614         clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
 615                         ARRAY_SIZE(gmac_phy_parents), 0,
 616                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 617                         SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 618         clk_register_clkdev(clk, NULL, "stmmacphy.0");
 619
 620         /* clcd */
 621         clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
 622                         ARRAY_SIZE(clcd_synth_parents), 0,
 623                         SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 624                         SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 625         clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 626
 627         clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
 628                         SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
 629                         ARRAY_SIZE(clcd_rtbl), &_lock);
 630         clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 631
 632         clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
 633                         ARRAY_SIZE(clcd_pixel_parents), 0,
 634                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 635                         SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 636         clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
 637
 638         clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 639                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
 640                         &_lock);
 641         clk_register_clkdev(clk, "clcd_clk", NULL);
 642
 643         /* i2s */
 644         clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
 645                         ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
 646                         SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
 647                         0, &_lock);
 648         clk_register_clkdev(clk, "i2s_src_clk", NULL);
 649
 650         clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
 651                         SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
 652                         ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
 653         clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 654
 655         clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
 656                         ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
 657                         SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
 658                         &_lock);
 659         clk_register_clkdev(clk, "i2s_ref_clk", NULL);
 660
 661         clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
 662                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
 663                         0, &_lock);
 664         clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 665
 666         clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
 667                         "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
 668                         &i2s_sclk_masks, i2s_sclk_rtbl,
 669                         ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
 670         clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
 671         clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
 672
 673         /* clock derived from ahb clk */
 674         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
 675                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
 676                         &_lock);
 677         clk_register_clkdev(clk, NULL, "e0280000.i2c");
 678
 679         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
 680                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
 681                         &_lock);
 682         clk_register_clkdev(clk, NULL, "ea800000.dma");
 683         clk_register_clkdev(clk, NULL, "eb000000.dma");
 684
 685         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
 686                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
 687                         &_lock);
 688         clk_register_clkdev(clk, NULL, "b2000000.jpeg");
 689
 690         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
 691                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
 692                         &_lock);
 693         clk_register_clkdev(clk, NULL, "e2000000.eth");
 694
 695         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
 696                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
 697                         &_lock);
 698         clk_register_clkdev(clk, NULL, "b0000000.flash");
 699
 700         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
 701                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
 702                         &_lock);
 703         clk_register_clkdev(clk, NULL, "ea000000.flash");
 704
 705         clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 706                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
 707                         &_lock);
 708         clk_register_clkdev(clk, "usbh.0_clk", NULL);
 709
 710         clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 711                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
 712                         &_lock);
 713         clk_register_clkdev(clk, "usbh.1_clk", NULL);
 714
 715         clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 716                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
 717                         &_lock);
 718         clk_register_clkdev(clk, NULL, "uoc");
 719
 720         clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 721                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 722                         0, &_lock);
 723         clk_register_clkdev(clk, NULL, "dw_pcie.0");
 724         clk_register_clkdev(clk, NULL, "ahci.0");
 725
 726         clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 727                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 728                         0, &_lock);
 729         clk_register_clkdev(clk, NULL, "dw_pcie.1");
 730         clk_register_clkdev(clk, NULL, "ahci.1");
 731
 732         clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 733                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 734                         0, &_lock);
 735         clk_register_clkdev(clk, NULL, "dw_pcie.2");
 736         clk_register_clkdev(clk, NULL, "ahci.2");
 737
 738         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 739                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
 740                         &_lock);
 741         clk_register_clkdev(clk, "sysram0_clk", NULL);
 742
 743         clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
 744                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
 745                         &_lock);
 746         clk_register_clkdev(clk, "sysram1_clk", NULL);
 747
 748         clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
 749                         0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
 750                         ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
 751         clk_register_clkdev(clk, "adc_syn_clk", NULL);
 752         clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
 753
 754         clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0,
 755                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
 756                         &_lock);
 757         clk_register_clkdev(clk, NULL, "adc_clk");
 758
 759         /* clock derived from apb clk */
 760         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
 761                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
 762                         &_lock);
 763         clk_register_clkdev(clk, NULL, "e0100000.spi");
 764
 765         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
 766                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
 767                         &_lock);
 768         clk_register_clkdev(clk, NULL, "e0600000.gpio");
 769
 770         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
 771                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
 772                         &_lock);
 773         clk_register_clkdev(clk, NULL, "e0680000.gpio");
 774
 775         clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
 776                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
 777                         &_lock);
 778         clk_register_clkdev(clk, NULL, "e0180000.i2s");
 779
 780         clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
 781                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
 782                         &_lock);
 783         clk_register_clkdev(clk, NULL, "e0200000.i2s");
 784
 785         clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
 786                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
 787                         &_lock);
 788         clk_register_clkdev(clk, NULL, "e0300000.kbd");
 789
 790         /* RAS clks */
 791         clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
 792                         ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
 793                         SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 794                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 795         clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
 796
 797         clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
 798                         ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
 799                         SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 800                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 801         clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
 802
 803         clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
 804                         SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 805                         &_lock);
 806         clk_register_clkdev(clk, "gen_syn0_clk", NULL);
 807
 808         clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
 809                         SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 810                         &_lock);
 811         clk_register_clkdev(clk, "gen_syn1_clk", NULL);
 812
 813         clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
 814                         SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 815                         &_lock);
 816         clk_register_clkdev(clk, "gen_syn2_clk", NULL);
 817
 818         clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
 819                         SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 820                         &_lock);
 821         clk_register_clkdev(clk, "gen_syn3_clk", NULL);
 822
 823         clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
 824                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
 825                         &_lock);
 826         clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
 827
 828         clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
 829                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
 830                         &_lock);
 831         clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
 832
 833         clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
 834                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
 835                         &_lock);
 836         clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
 837
 838         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 839                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
 840                         &_lock);
 841         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 842
 843         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
 844                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
 845                         &_lock);
 846         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
 847
 848         clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
 849                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
 850                         &_lock);
 851         clk_register_clkdev(clk, "ras_tx125_clk", NULL);
 852
 853         clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
 854                         30000000);
 855         clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
 856                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
 857                         &_lock);
 858         clk_register_clkdev(clk, "ras_30m_clk", NULL);
 859
 860         clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
 861                         48000000);
 862         clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
 863                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
 864                         &_lock);
 865         clk_register_clkdev(clk, "ras_48m_clk", NULL);
 866
 867         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
 868                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
 869                         &_lock);
 870         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 871
 872         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
 873                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
 874                         &_lock);
 875         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 876
 877         clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
 878                         50000000);
 879
 880         clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
 881                         50000000);
 882
 883         clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
 884                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
 885                         &_lock);
 886         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 887
 888         clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
 889                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
 890                         &_lock);
 891         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 892
 893         clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
 894                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
 895                         &_lock);
 896         clk_register_clkdev(clk, NULL, "5c400000.eth");
 897
 898         clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
 899                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
 900                         &_lock);
 901         clk_register_clkdev(clk, NULL, "5c500000.eth");
 902
 903         clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
 904                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
 905                         &_lock);
 906         clk_register_clkdev(clk, NULL, "5c600000.eth");
 907
 908         clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
 909                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
 910                         &_lock);
 911         clk_register_clkdev(clk, NULL, "5c700000.eth");
 912
 913         clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
 914                         smii_rgmii_phy_parents,
 915                         ARRAY_SIZE(smii_rgmii_phy_parents), 0,
 916                         SPEAR1310_RAS_CTRL_REG1,
 917                         SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 918                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 919         clk_register_clkdev(clk, NULL, "stmmacphy.1");
 920         clk_register_clkdev(clk, NULL, "stmmacphy.2");
 921         clk_register_clkdev(clk, NULL, "stmmacphy.4");
 922
 923         clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
 924                         ARRAY_SIZE(rmii_phy_parents), 0,
 925                         SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 926                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 927         clk_register_clkdev(clk, NULL, "stmmacphy.3");
 928
 929         clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
 930                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 931                         SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 932                         0, &_lock);
 933         clk_register_clkdev(clk, "uart1_mclk", NULL);
 934
 935         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
 936                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
 937                         &_lock);
 938         clk_register_clkdev(clk, NULL, "5c800000.serial");
 939
 940         clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
 941                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 942                         SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 943                         0, &_lock);
 944         clk_register_clkdev(clk, "uart2_mclk", NULL);
 945
 946         clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
 947                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
 948                         &_lock);
 949         clk_register_clkdev(clk, NULL, "5c900000.serial");
 950
 951         clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
 952                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 953                         SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 954                         0, &_lock);
 955         clk_register_clkdev(clk, "uart3_mclk", NULL);
 956
 957         clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
 958                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
 959                         &_lock);
 960         clk_register_clkdev(clk, NULL, "5ca00000.serial");
 961
 962         clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
 963                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 964                         SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 965                         0, &_lock);
 966         clk_register_clkdev(clk, "uart4_mclk", NULL);
 967
 968         clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
 969                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
 970                         &_lock);
 971         clk_register_clkdev(clk, NULL, "5cb00000.serial");
 972
 973         clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
 974                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 975                         SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 976                         0, &_lock);
 977         clk_register_clkdev(clk, "uart5_mclk", NULL);
 978
 979         clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
 980                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
 981                         &_lock);
 982         clk_register_clkdev(clk, NULL, "5cc00000.serial");
 983
 984         clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
 985                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 986                         SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
 987                         &_lock);
 988         clk_register_clkdev(clk, "i2c1_mclk", NULL);
 989
 990         clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
 991                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
 992                         &_lock);
 993         clk_register_clkdev(clk, NULL, "5cd00000.i2c");
 994
 995         clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
 996                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 997                         SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
 998                         &_lock);
 999         clk_register_clkdev(clk, "i2c2_mclk", NULL);
1000
1001         clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1002                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1003                         &_lock);
1004         clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1005
1006         clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1007                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1008                         SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1009                         &_lock);
1010         clk_register_clkdev(clk, "i2c3_mclk", NULL);
1011
1012         clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1013                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1014                         &_lock);
1015         clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1016
1017         clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1018                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1019                         SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1020                         &_lock);
1021         clk_register_clkdev(clk, "i2c4_mclk", NULL);
1022
1023         clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1024                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1025                         &_lock);
1026         clk_register_clkdev(clk, NULL, "5d000000.i2c");
1027
1028         clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1029                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1030                         SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1031                         &_lock);
1032         clk_register_clkdev(clk, "i2c5_mclk", NULL);
1033
1034         clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1035                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1036                         &_lock);
1037         clk_register_clkdev(clk, NULL, "5d100000.i2c");
1038
1039         clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1040                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1041                         SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1042                         &_lock);
1043         clk_register_clkdev(clk, "i2c6_mclk", NULL);
1044
1045         clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1046                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1047                         &_lock);
1048         clk_register_clkdev(clk, NULL, "5d200000.i2c");
1049
1050         clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1051                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1052                         SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1053                         &_lock);
1054         clk_register_clkdev(clk, "i2c7_mclk", NULL);
1055
1056         clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1057                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1058                         &_lock);
1059         clk_register_clkdev(clk, NULL, "5d300000.i2c");
1060
1061         clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1062                         ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1063                         SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1064                         &_lock);
1065         clk_register_clkdev(clk, "ssp1_mclk", NULL);
1066
1067         clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1068                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1069                         &_lock);
1070         clk_register_clkdev(clk, NULL, "5d400000.spi");
1071
1072         clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1073                         ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1074                         SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1075                         &_lock);
1076         clk_register_clkdev(clk, "pci_mclk", NULL);
1077
1078         clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1079                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1080                         &_lock);
1081         clk_register_clkdev(clk, NULL, "pci");
1082
1083         clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1084                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1085                         SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1086                         &_lock);
1087         clk_register_clkdev(clk, "tdm1_mclk", NULL);
1088
1089         clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1090                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1091                         &_lock);
1092         clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1093
1094         clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1095                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1096                         SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1097                         &_lock);
1098         clk_register_clkdev(clk, "tdm2_mclk", NULL);
1099
1100         clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1101                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1102                         &_lock);
1103         clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1104 }