drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/slab.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/vmalloc.h>
  56 #include <linux/init.h>
  57 #include <linux/delay.h>
  58 #include <linux/ioctl.h>
  59
  60 #include <asm/system.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/dma.h>
  64 #include <linux/bitops.h>
  65 #include <asm/types.h>
  66 #include <linux/termios.h>
  67 #include <linux/workqueue.h>
  68 #include <linux/hdlc.h>
  69 #include <linux/synclink.h>
  70
  71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72 #define SYNCLINK_GENERIC_HDLC 1
  73 #else
  74 #define SYNCLINK_GENERIC_HDLC 0
  75 #endif
  76
  77 #define GET_USER(error,value,addr) error = get_user(value,addr)
  78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82 #include <asm/uaccess.h>
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 struct  _input_signal_events {
 138         int     ri_up;
 139         int     ri_down;
 140         int     dsr_up;
 141         int     dsr_down;
 142         int     dcd_up;
 143         int     dcd_down;
 144         int     cts_up;
 145         int     cts_down;
 146 };
 147
 148 /*
 149  * Device instance data structure
 150  */
 151 typedef struct _synclinkmp_info {
 152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153         int                     magic;
 154         int                     flags;
 155         int                     count;          /* count of opens */
 156         int                     line;
 157         unsigned short          close_delay;
 158         unsigned short          closing_wait;   /* time to wait before closing */
 159
 160         struct mgsl_icount      icount;
 161
 162         struct tty_struct       *tty;
 163         int                     timeout;
 164         int                     x_char;         /* xon/xoff character */
 165         int                     blocked_open;   /* # of blocked opens */
 166         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 167         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 168         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 169         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           *tx_buf;
 171         int                     tx_put;
 172         int                     tx_get;
 173         int                     tx_count;
 174
 175         wait_queue_head_t       open_wait;
 176         wait_queue_head_t       close_wait;
 177
 178         wait_queue_head_t       status_event_wait_q;
 179         wait_queue_head_t       event_wait_q;
 180         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 181         struct _synclinkmp_info *next_device;   /* device list link */
 182         struct timer_list       status_timer;   /* input signal status check timer */
 183
 184         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 185         struct work_struct task;                        /* task structure for scheduling bh */
 186
 187         u32 max_frame_size;                     /* as set by device config */
 188
 189         u32 pending_bh;
 190
 191         bool bh_running;                                /* Protection from multiple */
 192         int isr_overflow;
 193         bool bh_requested;
 194
 195         int dcd_chkcount;                       /* check counts to prevent */
 196         int cts_chkcount;                       /* too many IRQs if a signal */
 197         int dsr_chkcount;                       /* is floating */
 198         int ri_chkcount;
 199
 200         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 201         unsigned long buffer_list_phys;
 202
 203         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 204         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 205         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 206         unsigned int current_rx_buf;
 207
 208         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 209         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 210         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 211         unsigned int last_tx_buf;
 212
 213         unsigned char *tmp_rx_buf;
 214         unsigned int tmp_rx_buf_count;
 215
 216         bool rx_enabled;
 217         bool rx_overflow;
 218
 219         bool tx_enabled;
 220         bool tx_active;
 221         u32 idle_mode;
 222
 223         unsigned char ie0_value;
 224         unsigned char ie1_value;
 225         unsigned char ie2_value;
 226         unsigned char ctrlreg_value;
 227         unsigned char old_signals;
 228
 229         char device_name[25];                   /* device instance name */
 230
 231         int port_count;
 232         int adapter_num;
 233         int port_num;
 234
 235         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 236
 237         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 238
 239         unsigned int irq_level;                 /* interrupt level */
 240         unsigned long irq_flags;
 241         bool irq_requested;                     /* true if IRQ requested */
 242
 243         MGSL_PARAMS params;                     /* communications parameters */
 244
 245         unsigned char serial_signals;           /* current serial signal states */
 246
 247         bool irq_occurred;                      /* for diagnostics use */
 248         unsigned int init_error;                /* Initialization startup error */
 249
 250         u32 last_mem_alloc;
 251         unsigned char* memory_base;             /* shared memory address (PCI only) */
 252         u32 phys_memory_base;
 253         int shared_mem_requested;
 254
 255         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 256         u32 phys_sca_base;
 257         u32 sca_offset;
 258         bool sca_base_requested;
 259
 260         unsigned char* lcr_base;                /* local config registers (PCI only) */
 261         u32 phys_lcr_base;
 262         u32 lcr_offset;
 263         int lcr_mem_requested;
 264
 265         unsigned char* statctrl_base;           /* status/control register memory */
 266         u32 phys_statctrl_base;
 267         u32 statctrl_offset;
 268         bool sca_statctrl_requested;
 269
 270         u32 misc_ctrl_value;
 271         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 272         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 273         bool drop_rts_on_tx_done;
 274
 275         struct  _input_signal_events    input_signal_events;
 276
 277         /* SPPP/Cisco HDLC device parts */
 278         int netcount;
 279         int dosyncppp;
 280         spinlock_t netlock;
 281
 282 #if SYNCLINK_GENERIC_HDLC
 283         struct net_device *netdev;
 284 #endif
 285
 286 } SLMP_INFO;
 287
 288 #define MGSL_MAGIC 0x5401
 289
 290 /*
 291  * define serial signal status change macros
 292  */
 293 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 294 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 295 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 296 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 297
 298 /* Common Register macros */
 299 #define LPR     0x00
 300 #define PABR0   0x02
 301 #define PABR1   0x03
 302 #define WCRL    0x04
 303 #define WCRM    0x05
 304 #define WCRH    0x06
 305 #define DPCR    0x08
 306 #define DMER    0x09
 307 #define ISR0    0x10
 308 #define ISR1    0x11
 309 #define ISR2    0x12
 310 #define IER0    0x14
 311 #define IER1    0x15
 312 #define IER2    0x16
 313 #define ITCR    0x18
 314 #define INTVR   0x1a
 315 #define IMVR    0x1c
 316
 317 /* MSCI Register macros */
 318 #define TRB     0x20
 319 #define TRBL    0x20
 320 #define TRBH    0x21
 321 #define SR0     0x22
 322 #define SR1     0x23
 323 #define SR2     0x24
 324 #define SR3     0x25
 325 #define FST     0x26
 326 #define IE0     0x28
 327 #define IE1     0x29
 328 #define IE2     0x2a
 329 #define FIE     0x2b
 330 #define CMD     0x2c
 331 #define MD0     0x2e
 332 #define MD1     0x2f
 333 #define MD2     0x30
 334 #define CTL     0x31
 335 #define SA0     0x32
 336 #define SA1     0x33
 337 #define IDL     0x34
 338 #define TMC     0x35
 339 #define RXS     0x36
 340 #define TXS     0x37
 341 #define TRC0    0x38
 342 #define TRC1    0x39
 343 #define RRC     0x3a
 344 #define CST0    0x3c
 345 #define CST1    0x3d
 346
 347 /* Timer Register Macros */
 348 #define TCNT    0x60
 349 #define TCNTL   0x60
 350 #define TCNTH   0x61
 351 #define TCONR   0x62
 352 #define TCONRL  0x62
 353 #define TCONRH  0x63
 354 #define TMCS    0x64
 355 #define TEPR    0x65
 356
 357 /* DMA Controller Register macros */
 358 #define DARL    0x80
 359 #define DARH    0x81
 360 #define DARB    0x82
 361 #define BAR     0x80
 362 #define BARL    0x80
 363 #define BARH    0x81
 364 #define BARB    0x82
 365 #define SAR     0x84
 366 #define SARL    0x84
 367 #define SARH    0x85
 368 #define SARB    0x86
 369 #define CPB     0x86
 370 #define CDA     0x88
 371 #define CDAL    0x88
 372 #define CDAH    0x89
 373 #define EDA     0x8a
 374 #define EDAL    0x8a
 375 #define EDAH    0x8b
 376 #define BFL     0x8c
 377 #define BFLL    0x8c
 378 #define BFLH    0x8d
 379 #define BCR     0x8e
 380 #define BCRL    0x8e
 381 #define BCRH    0x8f
 382 #define DSR     0x90
 383 #define DMR     0x91
 384 #define FCT     0x93
 385 #define DIR     0x94
 386 #define DCMD    0x95
 387
 388 /* combine with timer or DMA register address */
 389 #define TIMER0  0x00
 390 #define TIMER1  0x08
 391 #define TIMER2  0x10
 392 #define TIMER3  0x18
 393 #define RXDMA   0x00
 394 #define TXDMA   0x20
 395
 396 /* SCA Command Codes */
 397 #define NOOP            0x00
 398 #define TXRESET         0x01
 399 #define TXENABLE        0x02
 400 #define TXDISABLE       0x03
 401 #define TXCRCINIT       0x04
 402 #define TXCRCEXCL       0x05
 403 #define TXEOM           0x06
 404 #define TXABORT         0x07
 405 #define MPON            0x08
 406 #define TXBUFCLR        0x09
 407 #define RXRESET         0x11
 408 #define RXENABLE        0x12
 409 #define RXDISABLE       0x13
 410 #define RXCRCINIT       0x14
 411 #define RXREJECT        0x15
 412 #define SEARCHMP        0x16
 413 #define RXCRCEXCL       0x17
 414 #define RXCRCCALC       0x18
 415 #define CHRESET         0x21
 416 #define HUNT            0x31
 417
 418 /* DMA command codes */
 419 #define SWABORT         0x01
 420 #define FEICLEAR        0x02
 421
 422 /* IE0 */
 423 #define TXINTE          BIT7
 424 #define RXINTE          BIT6
 425 #define TXRDYE          BIT1
 426 #define RXRDYE          BIT0
 427
 428 /* IE1 & SR1 */
 429 #define UDRN    BIT7
 430 #define IDLE    BIT6
 431 #define SYNCD   BIT4
 432 #define FLGD    BIT4
 433 #define CCTS    BIT3
 434 #define CDCD    BIT2
 435 #define BRKD    BIT1
 436 #define ABTD    BIT1
 437 #define GAPD    BIT1
 438 #define BRKE    BIT0
 439 #define IDLD    BIT0
 440
 441 /* IE2 & SR2 */
 442 #define EOM     BIT7
 443 #define PMP     BIT6
 444 #define SHRT    BIT6
 445 #define PE      BIT5
 446 #define ABT     BIT5
 447 #define FRME    BIT4
 448 #define RBIT    BIT4
 449 #define OVRN    BIT3
 450 #define CRCE    BIT2
 451
 452
 453 /*
 454  * Global linked list of SyncLink devices
 455  */
 456 static SLMP_INFO *synclinkmp_device_list = NULL;
 457 static int synclinkmp_adapter_count = -1;
 458 static int synclinkmp_device_count = 0;
 459
 460 /*
 461  * Set this param to non-zero to load eax with the
 462  * .text section address and breakpoint on module load.
 463  * This is useful for use with gdb and add-symbol-file command.
 464  */
 465 static int break_on_load=0;
 466
 467 /*
 468  * Driver major number, defaults to zero to get auto
 469  * assigned major number. May be forced as module parameter.
 470  */
 471 static int ttymajor=0;
 472
 473 /*
 474  * Array of user specified options for ISA adapters.
 475  */
 476 static int debug_level = 0;
 477 static int maxframe[MAX_DEVICES] = {0,};
 478 static int dosyncppp[MAX_DEVICES] = {0,};
 479
 480 module_param(break_on_load, bool, 0);
 481 module_param(ttymajor, int, 0);
 482 module_param(debug_level, int, 0);
 483 module_param_array(maxframe, int, NULL, 0);
 484 module_param_array(dosyncppp, int, NULL, 0);
 485
 486 static char *driver_name = "SyncLink MultiPort driver";
 487 static char *driver_version = "$Revision: 4.38 $";
 488
 489 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 490 static void synclinkmp_remove_one(struct pci_dev *dev);
 491
 492 static struct pci_device_id synclinkmp_pci_tbl[] = {
 493         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 494         { 0, }, /* terminate list */
 495 };
 496 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 497
 498 MODULE_LICENSE("GPL");
 499
 500 static struct pci_driver synclinkmp_pci_driver = {
 501         .name           = "synclinkmp",
 502         .id_table       = synclinkmp_pci_tbl,
 503         .probe          = synclinkmp_init_one,
 504         .remove         = __devexit_p(synclinkmp_remove_one),
 505 };
 506
 507
 508 static struct tty_driver *serial_driver;
 509
 510 /* number of characters left in xmit buffer before we ask for more */
 511 #define WAKEUP_CHARS 256
 512
 513
 514 /* tty callbacks */
 515
 516 static int  open(struct tty_struct *tty, struct file * filp);
 517 static void close(struct tty_struct *tty, struct file * filp);
 518 static void hangup(struct tty_struct *tty);
 519 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 520
 521 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 522 static int put_char(struct tty_struct *tty, unsigned char ch);
 523 static void send_xchar(struct tty_struct *tty, char ch);
 524 static void wait_until_sent(struct tty_struct *tty, int timeout);
 525 static int  write_room(struct tty_struct *tty);
 526 static void flush_chars(struct tty_struct *tty);
 527 static void flush_buffer(struct tty_struct *tty);
 528 static void tx_hold(struct tty_struct *tty);
 529 static void tx_release(struct tty_struct *tty);
 530
 531 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 532 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 533 static int  chars_in_buffer(struct tty_struct *tty);
 534 static void throttle(struct tty_struct * tty);
 535 static void unthrottle(struct tty_struct * tty);
 536 static void set_break(struct tty_struct *tty, int break_state);
 537
 538 #if SYNCLINK_GENERIC_HDLC
 539 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 540 static void hdlcdev_tx_done(SLMP_INFO *info);
 541 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 542 static int  hdlcdev_init(SLMP_INFO *info);
 543 static void hdlcdev_exit(SLMP_INFO *info);
 544 #endif
 545
 546 /* ioctl handlers */
 547
 548 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 549 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 550 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 551 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 552 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 553 static int  tx_enable(SLMP_INFO *info, int enable);
 554 static int  tx_abort(SLMP_INFO *info);
 555 static int  rx_enable(SLMP_INFO *info, int enable);
 556 static int  modem_input_wait(SLMP_INFO *info,int arg);
 557 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 558 static int  tiocmget(struct tty_struct *tty, struct file *file);
 559 static int  tiocmset(struct tty_struct *tty, struct file *file,
 560                      unsigned int set, unsigned int clear);
 561 static void set_break(struct tty_struct *tty, int break_state);
 562
 563 static void add_device(SLMP_INFO *info);
 564 static void device_init(int adapter_num, struct pci_dev *pdev);
 565 static int  claim_resources(SLMP_INFO *info);
 566 static void release_resources(SLMP_INFO *info);
 567
 568 static int  startup(SLMP_INFO *info);
 569 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 570 static void shutdown(SLMP_INFO *info);
 571 static void program_hw(SLMP_INFO *info);
 572 static void change_params(SLMP_INFO *info);
 573
 574 static bool init_adapter(SLMP_INFO *info);
 575 static bool register_test(SLMP_INFO *info);
 576 static bool irq_test(SLMP_INFO *info);
 577 static bool loopback_test(SLMP_INFO *info);
 578 static int  adapter_test(SLMP_INFO *info);
 579 static bool memory_test(SLMP_INFO *info);
 580
 581 static void reset_adapter(SLMP_INFO *info);
 582 static void reset_port(SLMP_INFO *info);
 583 static void async_mode(SLMP_INFO *info);
 584 static void hdlc_mode(SLMP_INFO *info);
 585
 586 static void rx_stop(SLMP_INFO *info);
 587 static void rx_start(SLMP_INFO *info);
 588 static void rx_reset_buffers(SLMP_INFO *info);
 589 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 590 static bool rx_get_frame(SLMP_INFO *info);
 591
 592 static void tx_start(SLMP_INFO *info);
 593 static void tx_stop(SLMP_INFO *info);
 594 static void tx_load_fifo(SLMP_INFO *info);
 595 static void tx_set_idle(SLMP_INFO *info);
 596 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 597
 598 static void get_signals(SLMP_INFO *info);
 599 static void set_signals(SLMP_INFO *info);
 600 static void enable_loopback(SLMP_INFO *info, int enable);
 601 static void set_rate(SLMP_INFO *info, u32 data_rate);
 602
 603 static int  bh_action(SLMP_INFO *info);
 604 static void bh_handler(struct work_struct *work);
 605 static void bh_receive(SLMP_INFO *info);
 606 static void bh_transmit(SLMP_INFO *info);
 607 static void bh_status(SLMP_INFO *info);
 608 static void isr_timer(SLMP_INFO *info);
 609 static void isr_rxint(SLMP_INFO *info);
 610 static void isr_rxrdy(SLMP_INFO *info);
 611 static void isr_txint(SLMP_INFO *info);
 612 static void isr_txrdy(SLMP_INFO *info);
 613 static void isr_rxdmaok(SLMP_INFO *info);
 614 static void isr_rxdmaerror(SLMP_INFO *info);
 615 static void isr_txdmaok(SLMP_INFO *info);
 616 static void isr_txdmaerror(SLMP_INFO *info);
 617 static void isr_io_pin(SLMP_INFO *info, u16 status);
 618
 619 static int  alloc_dma_bufs(SLMP_INFO *info);
 620 static void free_dma_bufs(SLMP_INFO *info);
 621 static int  alloc_buf_list(SLMP_INFO *info);
 622 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 623 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 624 static void free_tmp_rx_buf(SLMP_INFO *info);
 625
 626 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 627 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 628 static void tx_timeout(unsigned long context);
 629 static void status_timeout(unsigned long context);
 630
 631 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 632 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 633 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 634 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 635 static unsigned char read_status_reg(SLMP_INFO * info);
 636 static void write_control_reg(SLMP_INFO * info);
 637
 638
 639 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 640 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 641 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 642
 643 static u32 misc_ctrl_value = 0x007e4040;
 644 static u32 lcr1_brdr_value = 0x00800028;
 645
 646 static u32 read_ahead_count = 8;
 647
 648 /* DPCR, DMA Priority Control
 649  *
 650  * 07..05  Not used, must be 0
 651  * 04      BRC, bus release condition: 0=all transfers complete
 652  *              1=release after 1 xfer on all channels
 653  * 03      CCC, channel change condition: 0=every cycle
 654  *              1=after each channel completes all xfers
 655  * 02..00  PR<2..0>, priority 100=round robin
 656  *
 657  * 00000100 = 0x00
 658  */
 659 static unsigned char dma_priority = 0x04;
 660
 661 // Number of bytes that can be written to shared RAM
 662 // in a single write operation
 663 static u32 sca_pci_load_interval = 64;
 664
 665 /*
 666  * 1st function defined in .text section. Calling this function in
 667  * init_module() followed by a breakpoint allows a remote debugger
 668  * (gdb) to get the .text address for the add-symbol-file command.
 669  * This allows remote debugging of dynamically loadable modules.
 670  */
 671 static void* synclinkmp_get_text_ptr(void);
 672 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 673
 674 static inline int sanity_check(SLMP_INFO *info,
 675                                char *name, const char *routine)
 676 {
 677 #ifdef SANITY_CHECK
 678         static const char *badmagic =
 679                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 680         static const char *badinfo =
 681                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 682
 683         if (!info) {
 684                 printk(badinfo, name, routine);
 685                 return 1;
 686         }
 687         if (info->magic != MGSL_MAGIC) {
 688                 printk(badmagic, name, routine);
 689                 return 1;
 690         }
 691 #else
 692         if (!info)
 693                 return 1;
 694 #endif
 695         return 0;
 696 }
 697
 698 /**
 699  * line discipline callback wrappers
 700  *
 701  * The wrappers maintain line discipline references
 702  * while calling into the line discipline.
 703  *
 704  * ldisc_receive_buf  - pass receive data to line discipline
 705  */
 706
 707 static void ldisc_receive_buf(struct tty_struct *tty,
 708                               const __u8 *data, char *flags, int count)
 709 {
 710         struct tty_ldisc *ld;
 711         if (!tty)
 712                 return;
 713         ld = tty_ldisc_ref(tty);
 714         if (ld) {
 715                 if (ld->receive_buf)
 716                         ld->receive_buf(tty, data, flags, count);
 717                 tty_ldisc_deref(ld);
 718         }
 719 }
 720
 721 /* tty callbacks */
 722
 723 /* Called when a port is opened.  Init and enable port.
 724  */
 725 static int open(struct tty_struct *tty, struct file *filp)
 726 {
 727         SLMP_INFO *info;
 728         int retval, line;
 729         unsigned long flags;
 730
 731         line = tty->index;
 732         if ((line < 0) || (line >= synclinkmp_device_count)) {
 733                 printk("%s(%d): open with invalid line #%d.\n",
 734                         __FILE__,__LINE__,line);
 735                 return -ENODEV;
 736         }
 737
 738         info = synclinkmp_device_list;
 739         while(info && info->line != line)
 740                 info = info->next_device;
 741         if (sanity_check(info, tty->name, "open"))
 742                 return -ENODEV;
 743         if ( info->init_error ) {
 744                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 745                         __FILE__,__LINE__,info->device_name,info->init_error);
 746                 return -ENODEV;
 747         }
 748
 749         tty->driver_data = info;
 750         info->tty = tty;
 751
 752         if (debug_level >= DEBUG_LEVEL_INFO)
 753                 printk("%s(%d):%s open(), old ref count = %d\n",
 754                          __FILE__,__LINE__,tty->driver->name, info->count);
 755
 756         /* If port is closing, signal caller to try again */
 757         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 758                 if (info->flags & ASYNC_CLOSING)
 759                         interruptible_sleep_on(&info->close_wait);
 760                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 761                         -EAGAIN : -ERESTARTSYS);
 762                 goto cleanup;
 763         }
 764
 765         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 766
 767         spin_lock_irqsave(&info->netlock, flags);
 768         if (info->netcount) {
 769                 retval = -EBUSY;
 770                 spin_unlock_irqrestore(&info->netlock, flags);
 771                 goto cleanup;
 772         }
 773         info->count++;
 774         spin_unlock_irqrestore(&info->netlock, flags);
 775
 776         if (info->count == 1) {
 777                 /* 1st open on this device, init hardware */
 778                 retval = startup(info);
 779                 if (retval < 0)
 780                         goto cleanup;
 781         }
 782
 783         retval = block_til_ready(tty, filp, info);
 784         if (retval) {
 785                 if (debug_level >= DEBUG_LEVEL_INFO)
 786                         printk("%s(%d):%s block_til_ready() returned %d\n",
 787                                  __FILE__,__LINE__, info->device_name, retval);
 788                 goto cleanup;
 789         }
 790
 791         if (debug_level >= DEBUG_LEVEL_INFO)
 792                 printk("%s(%d):%s open() success\n",
 793                          __FILE__,__LINE__, info->device_name);
 794         retval = 0;
 795
 796 cleanup:
 797         if (retval) {
 798                 if (tty->count == 1)
 799                         info->tty = NULL; /* tty layer will release tty struct */
 800                 if(info->count)
 801                         info->count--;
 802         }
 803
 804         return retval;
 805 }
 806
 807 /* Called when port is closed. Wait for remaining data to be
 808  * sent. Disable port and free resources.
 809  */
 810 static void close(struct tty_struct *tty, struct file *filp)
 811 {
 812         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 813
 814         if (sanity_check(info, tty->name, "close"))
 815                 return;
 816
 817         if (debug_level >= DEBUG_LEVEL_INFO)
 818                 printk("%s(%d):%s close() entry, count=%d\n",
 819                          __FILE__,__LINE__, info->device_name, info->count);
 820
 821         if (!info->count)
 822                 return;
 823
 824         if (tty_hung_up_p(filp))
 825                 goto cleanup;
 826
 827         if ((tty->count == 1) && (info->count != 1)) {
 828                 /*
 829                  * tty->count is 1 and the tty structure will be freed.
 830                  * info->count should be one in this case.
 831                  * if it's not, correct it so that the port is shutdown.
 832                  */
 833                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 834                        "info->count is %d\n",
 835                          __FILE__,__LINE__, info->device_name, info->count);
 836                 info->count = 1;
 837         }
 838
 839         info->count--;
 840
 841         /* if at least one open remaining, leave hardware active */
 842         if (info->count)
 843                 goto cleanup;
 844
 845         info->flags |= ASYNC_CLOSING;
 846
 847         /* set tty->closing to notify line discipline to
 848          * only process XON/XOFF characters. Only the N_TTY
 849          * discipline appears to use this (ppp does not).
 850          */
 851         tty->closing = 1;
 852
 853         /* wait for transmit data to clear all layers */
 854
 855         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 856                 if (debug_level >= DEBUG_LEVEL_INFO)
 857                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 858                                  __FILE__,__LINE__, info->device_name );
 859                 tty_wait_until_sent(tty, info->closing_wait);
 860         }
 861
 862         if (info->flags & ASYNC_INITIALIZED)
 863                 wait_until_sent(tty, info->timeout);
 864
 865         flush_buffer(tty);
 866
 867         tty_ldisc_flush(tty);
 868
 869         shutdown(info);
 870
 871         tty->closing = 0;
 872         info->tty = NULL;
 873
 874         if (info->blocked_open) {
 875                 if (info->close_delay) {
 876                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 877                 }
 878                 wake_up_interruptible(&info->open_wait);
 879         }
 880
 881         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 882
 883         wake_up_interruptible(&info->close_wait);
 884
 885 cleanup:
 886         if (debug_level >= DEBUG_LEVEL_INFO)
 887                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 888                         tty->driver->name, info->count);
 889 }
 890
 891 /* Called by tty_hangup() when a hangup is signaled.
 892  * This is the same as closing all open descriptors for the port.
 893  */
 894 static void hangup(struct tty_struct *tty)
 895 {
 896         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 897
 898         if (debug_level >= DEBUG_LEVEL_INFO)
 899                 printk("%s(%d):%s hangup()\n",
 900                          __FILE__,__LINE__, info->device_name );
 901
 902         if (sanity_check(info, tty->name, "hangup"))
 903                 return;
 904
 905         flush_buffer(tty);
 906         shutdown(info);
 907
 908         info->count = 0;
 909         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 910         info->tty = NULL;
 911
 912         wake_up_interruptible(&info->open_wait);
 913 }
 914
 915 /* Set new termios settings
 916  */
 917 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 918 {
 919         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 920         unsigned long flags;
 921
 922         if (debug_level >= DEBUG_LEVEL_INFO)
 923                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 924                         tty->driver->name );
 925
 926         change_params(info);
 927
 928         /* Handle transition to B0 status */
 929         if (old_termios->c_cflag & CBAUD &&
 930             !(tty->termios->c_cflag & CBAUD)) {
 931                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 932                 spin_lock_irqsave(&info->lock,flags);
 933                 set_signals(info);
 934                 spin_unlock_irqrestore(&info->lock,flags);
 935         }
 936
 937         /* Handle transition away from B0 status */
 938         if (!(old_termios->c_cflag & CBAUD) &&
 939             tty->termios->c_cflag & CBAUD) {
 940                 info->serial_signals |= SerialSignal_DTR;
 941                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 942                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 943                         info->serial_signals |= SerialSignal_RTS;
 944                 }
 945                 spin_lock_irqsave(&info->lock,flags);
 946                 set_signals(info);
 947                 spin_unlock_irqrestore(&info->lock,flags);
 948         }
 949
 950         /* Handle turning off CRTSCTS */
 951         if (old_termios->c_cflag & CRTSCTS &&
 952             !(tty->termios->c_cflag & CRTSCTS)) {
 953                 tty->hw_stopped = 0;
 954                 tx_release(tty);
 955         }
 956 }
 957
 958 /* Send a block of data
 959  *
 960  * Arguments:
 961  *
 962  *      tty             pointer to tty information structure
 963  *      buf             pointer to buffer containing send data
 964  *      count           size of send data in bytes
 965  *
 966  * Return Value:        number of characters written
 967  */
 968 static int write(struct tty_struct *tty,
 969                  const unsigned char *buf, int count)
 970 {
 971         int     c, ret = 0;
 972         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 973         unsigned long flags;
 974
 975         if (debug_level >= DEBUG_LEVEL_INFO)
 976                 printk("%s(%d):%s write() count=%d\n",
 977                        __FILE__,__LINE__,info->device_name,count);
 978
 979         if (sanity_check(info, tty->name, "write"))
 980                 goto cleanup;
 981
 982         if (!info->tx_buf)
 983                 goto cleanup;
 984
 985         if (info->params.mode == MGSL_MODE_HDLC) {
 986                 if (count > info->max_frame_size) {
 987                         ret = -EIO;
 988                         goto cleanup;
 989                 }
 990                 if (info->tx_active)
 991                         goto cleanup;
 992                 if (info->tx_count) {
 993                         /* send accumulated data from send_char() calls */
 994                         /* as frame and wait before accepting more data. */
 995                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 996                         goto start;
 997                 }
 998                 ret = info->tx_count = count;
 999                 tx_load_dma_buffer(info, buf, count);
1000                 goto start;
1001         }
1002
1003         for (;;) {
1004                 c = min_t(int, count,
1005                         min(info->max_frame_size - info->tx_count - 1,
1006                             info->max_frame_size - info->tx_put));
1007                 if (c <= 0)
1008                         break;
1009
1010                 memcpy(info->tx_buf + info->tx_put, buf, c);
1011
1012                 spin_lock_irqsave(&info->lock,flags);
1013                 info->tx_put += c;
1014                 if (info->tx_put >= info->max_frame_size)
1015                         info->tx_put -= info->max_frame_size;
1016                 info->tx_count += c;
1017                 spin_unlock_irqrestore(&info->lock,flags);
1018
1019                 buf += c;
1020                 count -= c;
1021                 ret += c;
1022         }
1023
1024         if (info->params.mode == MGSL_MODE_HDLC) {
1025                 if (count) {
1026                         ret = info->tx_count = 0;
1027                         goto cleanup;
1028                 }
1029                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1030         }
1031 start:
1032         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1033                 spin_lock_irqsave(&info->lock,flags);
1034                 if (!info->tx_active)
1035                         tx_start(info);
1036                 spin_unlock_irqrestore(&info->lock,flags);
1037         }
1038
1039 cleanup:
1040         if (debug_level >= DEBUG_LEVEL_INFO)
1041                 printk( "%s(%d):%s write() returning=%d\n",
1042                         __FILE__,__LINE__,info->device_name,ret);
1043         return ret;
1044 }
1045
1046 /* Add a character to the transmit buffer.
1047  */
1048 static int put_char(struct tty_struct *tty, unsigned char ch)
1049 {
1050         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1051         unsigned long flags;
1052         int ret = 0;
1053
1054         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1055                 printk( "%s(%d):%s put_char(%d)\n",
1056                         __FILE__,__LINE__,info->device_name,ch);
1057         }
1058
1059         if (sanity_check(info, tty->name, "put_char"))
1060                 return 0;
1061
1062         if (!info->tx_buf)
1063                 return 0;
1064
1065         spin_lock_irqsave(&info->lock,flags);
1066
1067         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1068              !info->tx_active ) {
1069
1070                 if (info->tx_count < info->max_frame_size - 1) {
1071                         info->tx_buf[info->tx_put++] = ch;
1072                         if (info->tx_put >= info->max_frame_size)
1073                                 info->tx_put -= info->max_frame_size;
1074                         info->tx_count++;
1075                         ret = 1;
1076                 }
1077         }
1078
1079         spin_unlock_irqrestore(&info->lock,flags);
1080         return ret;
1081 }
1082
1083 /* Send a high-priority XON/XOFF character
1084  */
1085 static void send_xchar(struct tty_struct *tty, char ch)
1086 {
1087         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1088         unsigned long flags;
1089
1090         if (debug_level >= DEBUG_LEVEL_INFO)
1091                 printk("%s(%d):%s send_xchar(%d)\n",
1092                          __FILE__,__LINE__, info->device_name, ch );
1093
1094         if (sanity_check(info, tty->name, "send_xchar"))
1095                 return;
1096
1097         info->x_char = ch;
1098         if (ch) {
1099                 /* Make sure transmit interrupts are on */
1100                 spin_lock_irqsave(&info->lock,flags);
1101                 if (!info->tx_enabled)
1102                         tx_start(info);
1103                 spin_unlock_irqrestore(&info->lock,flags);
1104         }
1105 }
1106
1107 /* Wait until the transmitter is empty.
1108  */
1109 static void wait_until_sent(struct tty_struct *tty, int timeout)
1110 {
1111         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1112         unsigned long orig_jiffies, char_time;
1113
1114         if (!info )
1115                 return;
1116
1117         if (debug_level >= DEBUG_LEVEL_INFO)
1118                 printk("%s(%d):%s wait_until_sent() entry\n",
1119                          __FILE__,__LINE__, info->device_name );
1120
1121         if (sanity_check(info, tty->name, "wait_until_sent"))
1122                 return;
1123
1124         lock_kernel();
1125
1126         if (!(info->flags & ASYNC_INITIALIZED))
1127                 goto exit;
1128
1129         orig_jiffies = jiffies;
1130
1131         /* Set check interval to 1/5 of estimated time to
1132          * send a character, and make it at least 1. The check
1133          * interval should also be less than the timeout.
1134          * Note: use tight timings here to satisfy the NIST-PCTS.
1135          */
1136
1137         if ( info->params.data_rate ) {
1138                 char_time = info->timeout/(32 * 5);
1139                 if (!char_time)
1140                         char_time++;
1141         } else
1142                 char_time = 1;
1143
1144         if (timeout)
1145                 char_time = min_t(unsigned long, char_time, timeout);
1146
1147         if ( info->params.mode == MGSL_MODE_HDLC ) {
1148                 while (info->tx_active) {
1149                         msleep_interruptible(jiffies_to_msecs(char_time));
1150                         if (signal_pending(current))
1151                                 break;
1152                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1153                                 break;
1154                 }
1155         } else {
1156                 //TODO: determine if there is something similar to USC16C32
1157                 //      TXSTATUS_ALL_SENT status
1158                 while ( info->tx_active && info->tx_enabled) {
1159                         msleep_interruptible(jiffies_to_msecs(char_time));
1160                         if (signal_pending(current))
1161                                 break;
1162                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1163                                 break;
1164                 }
1165         }
1166
1167 exit:
1168         unlock_kernel();
1169         if (debug_level >= DEBUG_LEVEL_INFO)
1170                 printk("%s(%d):%s wait_until_sent() exit\n",
1171                          __FILE__,__LINE__, info->device_name );
1172 }
1173
1174 /* Return the count of free bytes in transmit buffer
1175  */
1176 static int write_room(struct tty_struct *tty)
1177 {
1178         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1179         int ret;
1180
1181         if (sanity_check(info, tty->name, "write_room"))
1182                 return 0;
1183
1184         lock_kernel();
1185         if (info->params.mode == MGSL_MODE_HDLC) {
1186                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1187         } else {
1188                 ret = info->max_frame_size - info->tx_count - 1;
1189                 if (ret < 0)
1190                         ret = 0;
1191         }
1192         unlock_kernel();
1193
1194         if (debug_level >= DEBUG_LEVEL_INFO)
1195                 printk("%s(%d):%s write_room()=%d\n",
1196                        __FILE__, __LINE__, info->device_name, ret);
1197
1198         return ret;
1199 }
1200
1201 /* enable transmitter and send remaining buffered characters
1202  */
1203 static void flush_chars(struct tty_struct *tty)
1204 {
1205         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1206         unsigned long flags;
1207
1208         if ( debug_level >= DEBUG_LEVEL_INFO )
1209                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1210                         __FILE__,__LINE__,info->device_name,info->tx_count);
1211
1212         if (sanity_check(info, tty->name, "flush_chars"))
1213                 return;
1214
1215         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1216             !info->tx_buf)
1217                 return;
1218
1219         if ( debug_level >= DEBUG_LEVEL_INFO )
1220                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1221                         __FILE__,__LINE__,info->device_name );
1222
1223         spin_lock_irqsave(&info->lock,flags);
1224
1225         if (!info->tx_active) {
1226                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1227                         info->tx_count ) {
1228                         /* operating in synchronous (frame oriented) mode */
1229                         /* copy data from circular tx_buf to */
1230                         /* transmit DMA buffer. */
1231                         tx_load_dma_buffer(info,
1232                                  info->tx_buf,info->tx_count);
1233                 }
1234                 tx_start(info);
1235         }
1236
1237         spin_unlock_irqrestore(&info->lock,flags);
1238 }
1239
1240 /* Discard all data in the send buffer
1241  */
1242 static void flush_buffer(struct tty_struct *tty)
1243 {
1244         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1245         unsigned long flags;
1246
1247         if (debug_level >= DEBUG_LEVEL_INFO)
1248                 printk("%s(%d):%s flush_buffer() entry\n",
1249                          __FILE__,__LINE__, info->device_name );
1250
1251         if (sanity_check(info, tty->name, "flush_buffer"))
1252                 return;
1253
1254         spin_lock_irqsave(&info->lock,flags);
1255         info->tx_count = info->tx_put = info->tx_get = 0;
1256         del_timer(&info->tx_timer);
1257         spin_unlock_irqrestore(&info->lock,flags);
1258
1259         tty_wakeup(tty);
1260 }
1261
1262 /* throttle (stop) transmitter
1263  */
1264 static void tx_hold(struct tty_struct *tty)
1265 {
1266         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1267         unsigned long flags;
1268
1269         if (sanity_check(info, tty->name, "tx_hold"))
1270                 return;
1271
1272         if ( debug_level >= DEBUG_LEVEL_INFO )
1273                 printk("%s(%d):%s tx_hold()\n",
1274                         __FILE__,__LINE__,info->device_name);
1275
1276         spin_lock_irqsave(&info->lock,flags);
1277         if (info->tx_enabled)
1278                 tx_stop(info);
1279         spin_unlock_irqrestore(&info->lock,flags);
1280 }
1281
1282 /* release (start) transmitter
1283  */
1284 static void tx_release(struct tty_struct *tty)
1285 {
1286         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1287         unsigned long flags;
1288
1289         if (sanity_check(info, tty->name, "tx_release"))
1290                 return;
1291
1292         if ( debug_level >= DEBUG_LEVEL_INFO )
1293                 printk("%s(%d):%s tx_release()\n",
1294                         __FILE__,__LINE__,info->device_name);
1295
1296         spin_lock_irqsave(&info->lock,flags);
1297         if (!info->tx_enabled)
1298                 tx_start(info);
1299         spin_unlock_irqrestore(&info->lock,flags);
1300 }
1301
1302 /* Service an IOCTL request
1303  *
1304  * Arguments:
1305  *
1306  *      tty     pointer to tty instance data
1307  *      file    pointer to associated file object for device
1308  *      cmd     IOCTL command code
1309  *      arg     command argument/context
1310  *
1311  * Return Value:        0 if success, otherwise error code
1312  */
1313 static int do_ioctl(struct tty_struct *tty, struct file *file,
1314                  unsigned int cmd, unsigned long arg)
1315 {
1316         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1317         int error;
1318         struct mgsl_icount cnow;        /* kernel counter temps */
1319         struct serial_icounter_struct __user *p_cuser;  /* user space */
1320         unsigned long flags;
1321         void __user *argp = (void __user *)arg;
1322
1323         if (debug_level >= DEBUG_LEVEL_INFO)
1324                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1325                         info->device_name, cmd );
1326
1327         if (sanity_check(info, tty->name, "ioctl"))
1328                 return -ENODEV;
1329
1330         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1331             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1332                 if (tty->flags & (1 << TTY_IO_ERROR))
1333                     return -EIO;
1334         }
1335
1336         switch (cmd) {
1337         case MGSL_IOCGPARAMS:
1338                 return get_params(info, argp);
1339         case MGSL_IOCSPARAMS:
1340                 return set_params(info, argp);
1341         case MGSL_IOCGTXIDLE:
1342                 return get_txidle(info, argp);
1343         case MGSL_IOCSTXIDLE:
1344                 return set_txidle(info, (int)arg);
1345         case MGSL_IOCTXENABLE:
1346                 return tx_enable(info, (int)arg);
1347         case MGSL_IOCRXENABLE:
1348                 return rx_enable(info, (int)arg);
1349         case MGSL_IOCTXABORT:
1350                 return tx_abort(info);
1351         case MGSL_IOCGSTATS:
1352                 return get_stats(info, argp);
1353         case MGSL_IOCWAITEVENT:
1354                 return wait_mgsl_event(info, argp);
1355         case MGSL_IOCLOOPTXDONE:
1356                 return 0; // TODO: Not supported, need to document
1357                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1358                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1359                  */
1360         case TIOCMIWAIT:
1361                 return modem_input_wait(info,(int)arg);
1362
1363                 /*
1364                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1365                  * Return: write counters to the user passed counter struct
1366                  * NB: both 1->0 and 0->1 transitions are counted except for
1367                  *     RI where only 0->1 is counted.
1368                  */
1369         case TIOCGICOUNT:
1370                 spin_lock_irqsave(&info->lock,flags);
1371                 cnow = info->icount;
1372                 spin_unlock_irqrestore(&info->lock,flags);
1373                 p_cuser = argp;
1374                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1375                 if (error) return error;
1376                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1377                 if (error) return error;
1378                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1379                 if (error) return error;
1380                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1381                 if (error) return error;
1382                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1383                 if (error) return error;
1384                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1385                 if (error) return error;
1386                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1387                 if (error) return error;
1388                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1389                 if (error) return error;
1390                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1391                 if (error) return error;
1392                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1395                 if (error) return error;
1396                 return 0;
1397         default:
1398                 return -ENOIOCTLCMD;
1399         }
1400         return 0;
1401 }
1402
1403 static int ioctl(struct tty_struct *tty, struct file *file,
1404                  unsigned int cmd, unsigned long arg)
1405 {
1406         int ret;
1407         lock_kernel();
1408         ret = do_ioctl(tty, file, cmd, arg);
1409         unlock_kernel();
1410         return ret;
1411 }
1412
1413 /*
1414  * /proc fs routines....
1415  */
1416
1417 static inline int line_info(char *buf, SLMP_INFO *info)
1418 {
1419         char    stat_buf[30];
1420         int     ret;
1421         unsigned long flags;
1422
1423         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1424                        "\tIRQ=%d MaxFrameSize=%u\n",
1425                 info->device_name,
1426                 info->phys_sca_base,
1427                 info->phys_memory_base,
1428                 info->phys_statctrl_base,
1429                 info->phys_lcr_base,
1430                 info->irq_level,
1431                 info->max_frame_size );
1432
1433         /* output current serial signal states */
1434         spin_lock_irqsave(&info->lock,flags);
1435         get_signals(info);
1436         spin_unlock_irqrestore(&info->lock,flags);
1437
1438         stat_buf[0] = 0;
1439         stat_buf[1] = 0;
1440         if (info->serial_signals & SerialSignal_RTS)
1441                 strcat(stat_buf, "|RTS");
1442         if (info->serial_signals & SerialSignal_CTS)
1443                 strcat(stat_buf, "|CTS");
1444         if (info->serial_signals & SerialSignal_DTR)
1445                 strcat(stat_buf, "|DTR");
1446         if (info->serial_signals & SerialSignal_DSR)
1447                 strcat(stat_buf, "|DSR");
1448         if (info->serial_signals & SerialSignal_DCD)
1449                 strcat(stat_buf, "|CD");
1450         if (info->serial_signals & SerialSignal_RI)
1451                 strcat(stat_buf, "|RI");
1452
1453         if (info->params.mode == MGSL_MODE_HDLC) {
1454                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1455                               info->icount.txok, info->icount.rxok);
1456                 if (info->icount.txunder)
1457                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1458                 if (info->icount.txabort)
1459                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1460                 if (info->icount.rxshort)
1461                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1462                 if (info->icount.rxlong)
1463                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1464                 if (info->icount.rxover)
1465                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1466                 if (info->icount.rxcrc)
1467                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1468         } else {
1469                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1470                               info->icount.tx, info->icount.rx);
1471                 if (info->icount.frame)
1472                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1473                 if (info->icount.parity)
1474                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1475                 if (info->icount.brk)
1476                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1477                 if (info->icount.overrun)
1478                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1479         }
1480
1481         /* Append serial signal status to end */
1482         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1483
1484         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1485          info->tx_active,info->bh_requested,info->bh_running,
1486          info->pending_bh);
1487
1488         return ret;
1489 }
1490
1491 /* Called to print information about devices
1492  */
1493 static int read_proc(char *page, char **start, off_t off, int count,
1494               int *eof, void *data)
1495 {
1496         int len = 0, l;
1497         off_t   begin = 0;
1498         SLMP_INFO *info;
1499
1500         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1501
1502         info = synclinkmp_device_list;
1503         while( info ) {
1504                 l = line_info(page + len, info);
1505                 len += l;
1506                 if (len+begin > off+count)
1507                         goto done;
1508                 if (len+begin < off) {
1509                         begin += len;
1510                         len = 0;
1511                 }
1512                 info = info->next_device;
1513         }
1514
1515         *eof = 1;
1516 done:
1517         if (off >= len+begin)
1518                 return 0;
1519         *start = page + (off-begin);
1520         return ((count < begin+len-off) ? count : begin+len-off);
1521 }
1522
1523 /* Return the count of bytes in transmit buffer
1524  */
1525 static int chars_in_buffer(struct tty_struct *tty)
1526 {
1527         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1528
1529         if (sanity_check(info, tty->name, "chars_in_buffer"))
1530                 return 0;
1531
1532         if (debug_level >= DEBUG_LEVEL_INFO)
1533                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1534                        __FILE__, __LINE__, info->device_name, info->tx_count);
1535
1536         return info->tx_count;
1537 }
1538
1539 /* Signal remote device to throttle send data (our receive data)
1540  */
1541 static void throttle(struct tty_struct * tty)
1542 {
1543         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1544         unsigned long flags;
1545
1546         if (debug_level >= DEBUG_LEVEL_INFO)
1547                 printk("%s(%d):%s throttle() entry\n",
1548                          __FILE__,__LINE__, info->device_name );
1549
1550         if (sanity_check(info, tty->name, "throttle"))
1551                 return;
1552
1553         if (I_IXOFF(tty))
1554                 send_xchar(tty, STOP_CHAR(tty));
1555
1556         if (tty->termios->c_cflag & CRTSCTS) {
1557                 spin_lock_irqsave(&info->lock,flags);
1558                 info->serial_signals &= ~SerialSignal_RTS;
1559                 set_signals(info);
1560                 spin_unlock_irqrestore(&info->lock,flags);
1561         }
1562 }
1563
1564 /* Signal remote device to stop throttling send data (our receive data)
1565  */
1566 static void unthrottle(struct tty_struct * tty)
1567 {
1568         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1569         unsigned long flags;
1570
1571         if (debug_level >= DEBUG_LEVEL_INFO)
1572                 printk("%s(%d):%s unthrottle() entry\n",
1573                          __FILE__,__LINE__, info->device_name );
1574
1575         if (sanity_check(info, tty->name, "unthrottle"))
1576                 return;
1577
1578         if (I_IXOFF(tty)) {
1579                 if (info->x_char)
1580                         info->x_char = 0;
1581                 else
1582                         send_xchar(tty, START_CHAR(tty));
1583         }
1584
1585         if (tty->termios->c_cflag & CRTSCTS) {
1586                 spin_lock_irqsave(&info->lock,flags);
1587                 info->serial_signals |= SerialSignal_RTS;
1588                 set_signals(info);
1589                 spin_unlock_irqrestore(&info->lock,flags);
1590         }
1591 }
1592
1593 /* set or clear transmit break condition
1594  * break_state  -1=set break condition, 0=clear
1595  */
1596 static void set_break(struct tty_struct *tty, int break_state)
1597 {
1598         unsigned char RegValue;
1599         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1600         unsigned long flags;
1601
1602         if (debug_level >= DEBUG_LEVEL_INFO)
1603                 printk("%s(%d):%s set_break(%d)\n",
1604                          __FILE__,__LINE__, info->device_name, break_state);
1605
1606         if (sanity_check(info, tty->name, "set_break"))
1607                 return;
1608
1609         spin_lock_irqsave(&info->lock,flags);
1610         RegValue = read_reg(info, CTL);
1611         if (break_state == -1)
1612                 RegValue |= BIT3;
1613         else
1614                 RegValue &= ~BIT3;
1615         write_reg(info, CTL, RegValue);
1616         spin_unlock_irqrestore(&info->lock,flags);
1617 }
1618
1619 #if SYNCLINK_GENERIC_HDLC
1620
1621 /**
1622  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1623  * set encoding and frame check sequence (FCS) options
1624  *
1625  * dev       pointer to network device structure
1626  * encoding  serial encoding setting
1627  * parity    FCS setting
1628  *
1629  * returns 0 if success, otherwise error code
1630  */
1631 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1632                           unsigned short parity)
1633 {
1634         SLMP_INFO *info = dev_to_port(dev);
1635         unsigned char  new_encoding;
1636         unsigned short new_crctype;
1637
1638         /* return error if TTY interface open */
1639         if (info->count)
1640                 return -EBUSY;
1641
1642         switch (encoding)
1643         {
1644         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1645         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1646         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1647         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1648         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1649         default: return -EINVAL;
1650         }
1651
1652         switch (parity)
1653         {
1654         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1655         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1656         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1657         default: return -EINVAL;
1658         }
1659
1660         info->params.encoding = new_encoding;
1661         info->params.crc_type = new_crctype;
1662
1663         /* if network interface up, reprogram hardware */
1664         if (info->netcount)
1665                 program_hw(info);
1666
1667         return 0;
1668 }
1669
1670 /**
1671  * called by generic HDLC layer to send frame
1672  *
1673  * skb  socket buffer containing HDLC frame
1674  * dev  pointer to network device structure
1675  *
1676  * returns 0 if success, otherwise error code
1677  */
1678 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1679 {
1680         SLMP_INFO *info = dev_to_port(dev);
1681         struct net_device_stats *stats = hdlc_stats(dev);
1682         unsigned long flags;
1683
1684         if (debug_level >= DEBUG_LEVEL_INFO)
1685                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1686
1687         /* stop sending until this frame completes */
1688         netif_stop_queue(dev);
1689
1690         /* copy data to device buffers */
1691         info->tx_count = skb->len;
1692         tx_load_dma_buffer(info, skb->data, skb->len);
1693
1694         /* update network statistics */
1695         stats->tx_packets++;
1696         stats->tx_bytes += skb->len;
1697
1698         /* done with socket buffer, so free it */
1699         dev_kfree_skb(skb);
1700
1701         /* save start time for transmit timeout detection */
1702         dev->trans_start = jiffies;
1703
1704         /* start hardware transmitter if necessary */
1705         spin_lock_irqsave(&info->lock,flags);
1706         if (!info->tx_active)
1707                 tx_start(info);
1708         spin_unlock_irqrestore(&info->lock,flags);
1709
1710         return 0;
1711 }
1712
1713 /**
1714  * called by network layer when interface enabled
1715  * claim resources and initialize hardware
1716  *
1717  * dev  pointer to network device structure
1718  *
1719  * returns 0 if success, otherwise error code
1720  */
1721 static int hdlcdev_open(struct net_device *dev)
1722 {
1723         SLMP_INFO *info = dev_to_port(dev);
1724         int rc;
1725         unsigned long flags;
1726
1727         if (debug_level >= DEBUG_LEVEL_INFO)
1728                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1729
1730         /* generic HDLC layer open processing */
1731         if ((rc = hdlc_open(dev)))
1732                 return rc;
1733
1734         /* arbitrate between network and tty opens */
1735         spin_lock_irqsave(&info->netlock, flags);
1736         if (info->count != 0 || info->netcount != 0) {
1737                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1738                 spin_unlock_irqrestore(&info->netlock, flags);
1739                 return -EBUSY;
1740         }
1741         info->netcount=1;
1742         spin_unlock_irqrestore(&info->netlock, flags);
1743
1744         /* claim resources and init adapter */
1745         if ((rc = startup(info)) != 0) {
1746                 spin_lock_irqsave(&info->netlock, flags);
1747                 info->netcount=0;
1748                 spin_unlock_irqrestore(&info->netlock, flags);
1749                 return rc;
1750         }
1751
1752         /* assert DTR and RTS, apply hardware settings */
1753         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1754         program_hw(info);
1755
1756         /* enable network layer transmit */
1757         dev->trans_start = jiffies;
1758         netif_start_queue(dev);
1759
1760         /* inform generic HDLC layer of current DCD status */
1761         spin_lock_irqsave(&info->lock, flags);
1762         get_signals(info);
1763         spin_unlock_irqrestore(&info->lock, flags);
1764         if (info->serial_signals & SerialSignal_DCD)
1765                 netif_carrier_on(dev);
1766         else
1767                 netif_carrier_off(dev);
1768         return 0;
1769 }
1770
1771 /**
1772  * called by network layer when interface is disabled
1773  * shutdown hardware and release resources
1774  *
1775  * dev  pointer to network device structure
1776  *
1777  * returns 0 if success, otherwise error code
1778  */
1779 static int hdlcdev_close(struct net_device *dev)
1780 {
1781         SLMP_INFO *info = dev_to_port(dev);
1782         unsigned long flags;
1783
1784         if (debug_level >= DEBUG_LEVEL_INFO)
1785                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1786
1787         netif_stop_queue(dev);
1788
1789         /* shutdown adapter and release resources */
1790         shutdown(info);
1791
1792         hdlc_close(dev);
1793
1794         spin_lock_irqsave(&info->netlock, flags);
1795         info->netcount=0;
1796         spin_unlock_irqrestore(&info->netlock, flags);
1797
1798         return 0;
1799 }
1800
1801 /**
1802  * called by network layer to process IOCTL call to network device
1803  *
1804  * dev  pointer to network device structure
1805  * ifr  pointer to network interface request structure
1806  * cmd  IOCTL command code
1807  *
1808  * returns 0 if success, otherwise error code
1809  */
1810 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1811 {
1812         const size_t size = sizeof(sync_serial_settings);
1813         sync_serial_settings new_line;
1814         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1815         SLMP_INFO *info = dev_to_port(dev);
1816         unsigned int flags;
1817
1818         if (debug_level >= DEBUG_LEVEL_INFO)
1819                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1820
1821         /* return error if TTY interface open */
1822         if (info->count)
1823                 return -EBUSY;
1824
1825         if (cmd != SIOCWANDEV)
1826                 return hdlc_ioctl(dev, ifr, cmd);
1827
1828         switch(ifr->ifr_settings.type) {
1829         case IF_GET_IFACE: /* return current sync_serial_settings */
1830
1831                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1832                 if (ifr->ifr_settings.size < size) {
1833                         ifr->ifr_settings.size = size; /* data size wanted */
1834                         return -ENOBUFS;
1835                 }
1836
1837                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1838                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1839                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1840                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1841
1842                 switch (flags){
1843                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1844                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1845                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1846                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1847                 default: new_line.clock_type = CLOCK_DEFAULT;
1848                 }
1849
1850                 new_line.clock_rate = info->params.clock_speed;
1851                 new_line.loopback   = info->params.loopback ? 1:0;
1852
1853                 if (copy_to_user(line, &new_line, size))
1854                         return -EFAULT;
1855                 return 0;
1856
1857         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1858
1859                 if(!capable(CAP_NET_ADMIN))
1860                         return -EPERM;
1861                 if (copy_from_user(&new_line, line, size))
1862                         return -EFAULT;
1863
1864                 switch (new_line.clock_type)
1865                 {
1866                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1867                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1868                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1869                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1870                 case CLOCK_DEFAULT:  flags = info->params.flags &
1871                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1872                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1873                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1874                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1875                 default: return -EINVAL;
1876                 }
1877
1878                 if (new_line.loopback != 0 && new_line.loopback != 1)
1879                         return -EINVAL;
1880
1881                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1882                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1883                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1884                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1885                 info->params.flags |= flags;
1886
1887                 info->params.loopback = new_line.loopback;
1888
1889                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1890                         info->params.clock_speed = new_line.clock_rate;
1891                 else
1892                         info->params.clock_speed = 0;
1893
1894                 /* if network interface up, reprogram hardware */
1895                 if (info->netcount)
1896                         program_hw(info);
1897                 return 0;
1898
1899         default:
1900                 return hdlc_ioctl(dev, ifr, cmd);
1901         }
1902 }
1903
1904 /**
1905  * called by network layer when transmit timeout is detected
1906  *
1907  * dev  pointer to network device structure
1908  */
1909 static void hdlcdev_tx_timeout(struct net_device *dev)
1910 {
1911         SLMP_INFO *info = dev_to_port(dev);
1912         struct net_device_stats *stats = hdlc_stats(dev);
1913         unsigned long flags;
1914
1915         if (debug_level >= DEBUG_LEVEL_INFO)
1916                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1917
1918         stats->tx_errors++;
1919         stats->tx_aborted_errors++;
1920
1921         spin_lock_irqsave(&info->lock,flags);
1922         tx_stop(info);
1923         spin_unlock_irqrestore(&info->lock,flags);
1924
1925         netif_wake_queue(dev);
1926 }
1927
1928 /**
1929  * called by device driver when transmit completes
1930  * reenable network layer transmit if stopped
1931  *
1932  * info  pointer to device instance information
1933  */
1934 static void hdlcdev_tx_done(SLMP_INFO *info)
1935 {
1936         if (netif_queue_stopped(info->netdev))
1937                 netif_wake_queue(info->netdev);
1938 }
1939
1940 /**
1941  * called by device driver when frame received
1942  * pass frame to network layer
1943  *
1944  * info  pointer to device instance information
1945  * buf   pointer to buffer contianing frame data
1946  * size  count of data bytes in buf
1947  */
1948 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1949 {
1950         struct sk_buff *skb = dev_alloc_skb(size);
1951         struct net_device *dev = info->netdev;
1952         struct net_device_stats *stats = hdlc_stats(dev);
1953
1954         if (debug_level >= DEBUG_LEVEL_INFO)
1955                 printk("hdlcdev_rx(%s)\n",dev->name);
1956
1957         if (skb == NULL) {
1958                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1959                 stats->rx_dropped++;
1960                 return;
1961         }
1962
1963         memcpy(skb_put(skb, size),buf,size);
1964
1965         skb->protocol = hdlc_type_trans(skb, info->netdev);
1966
1967         stats->rx_packets++;
1968         stats->rx_bytes += size;
1969
1970         netif_rx(skb);
1971
1972         info->netdev->last_rx = jiffies;
1973 }
1974
1975 /**
1976  * called by device driver when adding device instance
1977  * do generic HDLC initialization
1978  *
1979  * info  pointer to device instance information
1980  *
1981  * returns 0 if success, otherwise error code
1982  */
1983 static int hdlcdev_init(SLMP_INFO *info)
1984 {
1985         int rc;
1986         struct net_device *dev;
1987         hdlc_device *hdlc;
1988
1989         /* allocate and initialize network and HDLC layer objects */
1990
1991         if (!(dev = alloc_hdlcdev(info))) {
1992                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1993                 return -ENOMEM;
1994         }
1995
1996         /* for network layer reporting purposes only */
1997         dev->mem_start = info->phys_sca_base;
1998         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1999         dev->irq       = info->irq_level;
2000
2001         /* network layer callbacks and settings */
2002         dev->do_ioctl       = hdlcdev_ioctl;
2003         dev->open           = hdlcdev_open;
2004         dev->stop           = hdlcdev_close;
2005         dev->tx_timeout     = hdlcdev_tx_timeout;
2006         dev->watchdog_timeo = 10*HZ;
2007         dev->tx_queue_len   = 50;
2008
2009         /* generic HDLC layer callbacks and settings */
2010         hdlc         = dev_to_hdlc(dev);
2011         hdlc->attach = hdlcdev_attach;
2012         hdlc->xmit   = hdlcdev_xmit;
2013
2014         /* register objects with HDLC layer */
2015         if ((rc = register_hdlc_device(dev))) {
2016                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2017                 free_netdev(dev);
2018                 return rc;
2019         }
2020
2021         info->netdev = dev;
2022         return 0;
2023 }
2024
2025 /**
2026  * called by device driver when removing device instance
2027  * do generic HDLC cleanup
2028  *
2029  * info  pointer to device instance information
2030  */
2031 static void hdlcdev_exit(SLMP_INFO *info)
2032 {
2033         unregister_hdlc_device(info->netdev);
2034         free_netdev(info->netdev);
2035         info->netdev = NULL;
2036 }
2037
2038 #endif /* CONFIG_HDLC */
2039
2040
2041 /* Return next bottom half action to perform.
2042  * Return Value:        BH action code or 0 if nothing to do.
2043  */
2044 static int bh_action(SLMP_INFO *info)
2045 {
2046         unsigned long flags;
2047         int rc = 0;
2048
2049         spin_lock_irqsave(&info->lock,flags);
2050
2051         if (info->pending_bh & BH_RECEIVE) {
2052                 info->pending_bh &= ~BH_RECEIVE;
2053                 rc = BH_RECEIVE;
2054         } else if (info->pending_bh & BH_TRANSMIT) {
2055                 info->pending_bh &= ~BH_TRANSMIT;
2056                 rc = BH_TRANSMIT;
2057         } else if (info->pending_bh & BH_STATUS) {
2058                 info->pending_bh &= ~BH_STATUS;
2059                 rc = BH_STATUS;
2060         }
2061
2062         if (!rc) {
2063                 /* Mark BH routine as complete */
2064                 info->bh_running = false;
2065                 info->bh_requested = false;
2066         }
2067
2068         spin_unlock_irqrestore(&info->lock,flags);
2069
2070         return rc;
2071 }
2072
2073 /* Perform bottom half processing of work items queued by ISR.
2074  */
2075 static void bh_handler(struct work_struct *work)
2076 {
2077         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2078         int action;
2079
2080         if (!info)
2081                 return;
2082
2083         if ( debug_level >= DEBUG_LEVEL_BH )
2084                 printk( "%s(%d):%s bh_handler() entry\n",
2085                         __FILE__,__LINE__,info->device_name);
2086
2087         info->bh_running = true;
2088
2089         while((action = bh_action(info)) != 0) {
2090
2091                 /* Process work item */
2092                 if ( debug_level >= DEBUG_LEVEL_BH )
2093                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2094                                 __FILE__,__LINE__,info->device_name, action);
2095
2096                 switch (action) {
2097
2098                 case BH_RECEIVE:
2099                         bh_receive(info);
2100                         break;
2101                 case BH_TRANSMIT:
2102                         bh_transmit(info);
2103                         break;
2104                 case BH_STATUS:
2105                         bh_status(info);
2106                         break;
2107                 default:
2108                         /* unknown work item ID */
2109                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2110                                 __FILE__,__LINE__,info->device_name,action);
2111                         break;
2112                 }
2113         }
2114
2115         if ( debug_level >= DEBUG_LEVEL_BH )
2116                 printk( "%s(%d):%s bh_handler() exit\n",
2117                         __FILE__,__LINE__,info->device_name);
2118 }
2119
2120 static void bh_receive(SLMP_INFO *info)
2121 {
2122         if ( debug_level >= DEBUG_LEVEL_BH )
2123                 printk( "%s(%d):%s bh_receive()\n",
2124                         __FILE__,__LINE__,info->device_name);
2125
2126         while( rx_get_frame(info) );
2127 }
2128
2129 static void bh_transmit(SLMP_INFO *info)
2130 {
2131         struct tty_struct *tty = info->tty;
2132
2133         if ( debug_level >= DEBUG_LEVEL_BH )
2134                 printk( "%s(%d):%s bh_transmit() entry\n",
2135                         __FILE__,__LINE__,info->device_name);
2136
2137         if (tty)
2138                 tty_wakeup(tty);
2139 }
2140
2141 static void bh_status(SLMP_INFO *info)
2142 {
2143         if ( debug_level >= DEBUG_LEVEL_BH )
2144                 printk( "%s(%d):%s bh_status() entry\n",
2145                         __FILE__,__LINE__,info->device_name);
2146
2147         info->ri_chkcount = 0;
2148         info->dsr_chkcount = 0;
2149         info->dcd_chkcount = 0;
2150         info->cts_chkcount = 0;
2151 }
2152
2153 static void isr_timer(SLMP_INFO * info)
2154 {
2155         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2156
2157         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2158         write_reg(info, IER2, 0);
2159
2160         /* TMCS, Timer Control/Status Register
2161          *
2162          * 07      CMF, Compare match flag (read only) 1=match
2163          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2164          * 05      Reserved, must be 0
2165          * 04      TME, Timer Enable
2166          * 03..00  Reserved, must be 0
2167          *
2168          * 0000 0000
2169          */
2170         write_reg(info, (unsigned char)(timer + TMCS), 0);
2171
2172         info->irq_occurred = true;
2173
2174         if ( debug_level >= DEBUG_LEVEL_ISR )
2175                 printk("%s(%d):%s isr_timer()\n",
2176                         __FILE__,__LINE__,info->device_name);
2177 }
2178
2179 static void isr_rxint(SLMP_INFO * info)
2180 {
2181         struct tty_struct *tty = info->tty;
2182         struct  mgsl_icount *icount = &info->icount;
2183         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2184         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2185
2186         /* clear status bits */
2187         if (status)
2188                 write_reg(info, SR1, status);
2189
2190         if (status2)
2191                 write_reg(info, SR2, status2);
2192
2193         if ( debug_level >= DEBUG_LEVEL_ISR )
2194                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2195                         __FILE__,__LINE__,info->device_name,status,status2);
2196
2197         if (info->params.mode == MGSL_MODE_ASYNC) {
2198                 if (status & BRKD) {
2199                         icount->brk++;
2200
2201                         /* process break detection if tty control
2202                          * is not set to ignore it
2203                          */
2204                         if ( tty ) {
2205                                 if (!(status & info->ignore_status_mask1)) {
2206                                         if (info->read_status_mask1 & BRKD) {
2207                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2208                                                 if (info->flags & ASYNC_SAK)
2209                                                         do_SAK(tty);
2210                                         }
2211                                 }
2212                         }
2213                 }
2214         }
2215         else {
2216                 if (status & (FLGD|IDLD)) {
2217                         if (status & FLGD)
2218                                 info->icount.exithunt++;
2219                         else if (status & IDLD)
2220                                 info->icount.rxidle++;
2221                         wake_up_interruptible(&info->event_wait_q);
2222                 }
2223         }
2224
2225         if (status & CDCD) {
2226                 /* simulate a common modem status change interrupt
2227                  * for our handler
2228                  */
2229                 get_signals( info );
2230                 isr_io_pin(info,
2231                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2232         }
2233 }
2234
2235 /*
2236  * handle async rx data interrupts
2237  */
2238 static void isr_rxrdy(SLMP_INFO * info)
2239 {
2240         u16 status;
2241         unsigned char DataByte;
2242         struct tty_struct *tty = info->tty;
2243         struct  mgsl_icount *icount = &info->icount;
2244
2245         if ( debug_level >= DEBUG_LEVEL_ISR )
2246                 printk("%s(%d):%s isr_rxrdy\n",
2247                         __FILE__,__LINE__,info->device_name);
2248
2249         while((status = read_reg(info,CST0)) & BIT0)
2250         {
2251                 int flag = 0;
2252                 bool over = false;
2253                 DataByte = read_reg(info,TRB);
2254
2255                 icount->rx++;
2256
2257                 if ( status & (PE + FRME + OVRN) ) {
2258                         printk("%s(%d):%s rxerr=%04X\n",
2259                                 __FILE__,__LINE__,info->device_name,status);
2260
2261                         /* update error statistics */
2262                         if (status & PE)
2263                                 icount->parity++;
2264                         else if (status & FRME)
2265                                 icount->frame++;
2266                         else if (status & OVRN)
2267                                 icount->overrun++;
2268
2269                         /* discard char if tty control flags say so */
2270                         if (status & info->ignore_status_mask2)
2271                                 continue;
2272
2273                         status &= info->read_status_mask2;
2274
2275                         if ( tty ) {
2276                                 if (status & PE)
2277                                         flag = TTY_PARITY;
2278                                 else if (status & FRME)
2279                                         flag = TTY_FRAME;
2280                                 if (status & OVRN) {
2281                                         /* Overrun is special, since it's
2282                                          * reported immediately, and doesn't
2283                                          * affect the current character
2284                                          */
2285                                         over = true;
2286                                 }
2287                         }
2288                 }       /* end of if (error) */
2289
2290                 if ( tty ) {
2291                         tty_insert_flip_char(tty, DataByte, flag);
2292                         if (over)
2293                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2294                 }
2295         }
2296
2297         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2298                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2299                         __FILE__,__LINE__,info->device_name,
2300                         icount->rx,icount->brk,icount->parity,
2301                         icount->frame,icount->overrun);
2302         }
2303
2304         if ( tty )
2305                 tty_flip_buffer_push(tty);
2306 }
2307
2308 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2309 {
2310         if ( debug_level >= DEBUG_LEVEL_ISR )
2311                 printk("%s(%d):%s isr_txeom status=%02x\n",
2312                         __FILE__,__LINE__,info->device_name,status);
2313
2314         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2315         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2316         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2317
2318         if (status & UDRN) {
2319                 write_reg(info, CMD, TXRESET);
2320                 write_reg(info, CMD, TXENABLE);
2321         } else
2322                 write_reg(info, CMD, TXBUFCLR);
2323
2324         /* disable and clear tx interrupts */
2325         info->ie0_value &= ~TXRDYE;
2326         info->ie1_value &= ~(IDLE + UDRN);
2327         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2328         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2329
2330         if ( info->tx_active ) {
2331                 if (info->params.mode != MGSL_MODE_ASYNC) {
2332                         if (status & UDRN)
2333                                 info->icount.txunder++;
2334                         else if (status & IDLE)
2335                                 info->icount.txok++;
2336                 }
2337
2338                 info->tx_active = false;
2339                 info->tx_count = info->tx_put = info->tx_get = 0;
2340
2341                 del_timer(&info->tx_timer);
2342
2343                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2344                         info->serial_signals &= ~SerialSignal_RTS;
2345                         info->drop_rts_on_tx_done = false;
2346                         set_signals(info);
2347                 }
2348
2349 #if SYNCLINK_GENERIC_HDLC
2350                 if (info->netcount)
2351                         hdlcdev_tx_done(info);
2352                 else
2353 #endif
2354                 {
2355                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2356                                 tx_stop(info);
2357                                 return;
2358                         }
2359                         info->pending_bh |= BH_TRANSMIT;
2360                 }
2361         }
2362 }
2363
2364
2365 /*
2366  * handle tx status interrupts
2367  */
2368 static void isr_txint(SLMP_INFO * info)
2369 {
2370         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2371
2372         /* clear status bits */
2373         write_reg(info, SR1, status);
2374
2375         if ( debug_level >= DEBUG_LEVEL_ISR )
2376                 printk("%s(%d):%s isr_txint status=%02x\n",
2377                         __FILE__,__LINE__,info->device_name,status);
2378
2379         if (status & (UDRN + IDLE))
2380                 isr_txeom(info, status);
2381
2382         if (status & CCTS) {
2383                 /* simulate a common modem status change interrupt
2384                  * for our handler
2385                  */
2386                 get_signals( info );
2387                 isr_io_pin(info,
2388                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2389
2390         }
2391 }
2392
2393 /*
2394  * handle async tx data interrupts
2395  */
2396 static void isr_txrdy(SLMP_INFO * info)
2397 {
2398         if ( debug_level >= DEBUG_LEVEL_ISR )
2399                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2400                         __FILE__,__LINE__,info->device_name,info->tx_count);
2401
2402         if (info->params.mode != MGSL_MODE_ASYNC) {
2403                 /* disable TXRDY IRQ, enable IDLE IRQ */
2404                 info->ie0_value &= ~TXRDYE;
2405                 info->ie1_value |= IDLE;
2406                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2407                 return;
2408         }
2409
2410         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2411                 tx_stop(info);
2412                 return;
2413         }
2414
2415         if ( info->tx_count )
2416                 tx_load_fifo( info );
2417         else {
2418                 info->tx_active = false;
2419                 info->ie0_value &= ~TXRDYE;
2420                 write_reg(info, IE0, info->ie0_value);
2421         }
2422
2423         if (info->tx_count < WAKEUP_CHARS)
2424                 info->pending_bh |= BH_TRANSMIT;
2425 }
2426
2427 static void isr_rxdmaok(SLMP_INFO * info)
2428 {
2429         /* BIT7 = EOT (end of transfer)
2430          * BIT6 = EOM (end of message/frame)
2431          */
2432         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2433
2434         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2435         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2436
2437         if ( debug_level >= DEBUG_LEVEL_ISR )
2438                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2439                         __FILE__,__LINE__,info->device_name,status);
2440
2441         info->pending_bh |= BH_RECEIVE;
2442 }
2443
2444 static void isr_rxdmaerror(SLMP_INFO * info)
2445 {
2446         /* BIT5 = BOF (buffer overflow)
2447          * BIT4 = COF (counter overflow)
2448          */
2449         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2450
2451         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2452         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2453
2454         if ( debug_level >= DEBUG_LEVEL_ISR )
2455                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2456                         __FILE__,__LINE__,info->device_name,status);
2457
2458         info->rx_overflow = true;
2459         info->pending_bh |= BH_RECEIVE;
2460 }
2461
2462 static void isr_txdmaok(SLMP_INFO * info)
2463 {
2464         unsigned char status_reg1 = read_reg(info, SR1);
2465
2466         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2467         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2468         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2469
2470         if ( debug_level >= DEBUG_LEVEL_ISR )
2471                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2472                         __FILE__,__LINE__,info->device_name,status_reg1);
2473
2474         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2475         write_reg16(info, TRC0, 0);
2476         info->ie0_value |= TXRDYE;
2477         write_reg(info, IE0, info->ie0_value);
2478 }
2479
2480 static void isr_txdmaerror(SLMP_INFO * info)
2481 {
2482         /* BIT5 = BOF (buffer overflow)
2483          * BIT4 = COF (counter overflow)
2484          */
2485         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2486
2487         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2488         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2489
2490         if ( debug_level >= DEBUG_LEVEL_ISR )
2491                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2492                         __FILE__,__LINE__,info->device_name,status);
2493 }
2494
2495 /* handle input serial signal changes
2496  */
2497 static void isr_io_pin( SLMP_INFO *info, u16 status )
2498 {
2499         struct  mgsl_icount *icount;
2500
2501         if ( debug_level >= DEBUG_LEVEL_ISR )
2502                 printk("%s(%d):isr_io_pin status=%04X\n",
2503                         __FILE__,__LINE__,status);
2504
2505         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2506                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2507                 icount = &info->icount;
2508                 /* update input line counters */
2509                 if (status & MISCSTATUS_RI_LATCHED) {
2510                         icount->rng++;
2511                         if ( status & SerialSignal_RI )
2512                                 info->input_signal_events.ri_up++;
2513                         else
2514                                 info->input_signal_events.ri_down++;
2515                 }
2516                 if (status & MISCSTATUS_DSR_LATCHED) {
2517                         icount->dsr++;
2518                         if ( status & SerialSignal_DSR )
2519                                 info->input_signal_events.dsr_up++;
2520                         else
2521                                 info->input_signal_events.dsr_down++;
2522                 }
2523                 if (status & MISCSTATUS_DCD_LATCHED) {
2524                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2525                                 info->ie1_value &= ~CDCD;
2526                                 write_reg(info, IE1, info->ie1_value);
2527                         }
2528                         icount->dcd++;
2529                         if (status & SerialSignal_DCD) {
2530                                 info->input_signal_events.dcd_up++;
2531                         } else
2532                                 info->input_signal_events.dcd_down++;
2533 #if SYNCLINK_GENERIC_HDLC
2534                         if (info->netcount) {
2535                                 if (status & SerialSignal_DCD)
2536                                         netif_carrier_on(info->netdev);
2537                                 else
2538                                         netif_carrier_off(info->netdev);
2539                         }
2540 #endif
2541                 }
2542                 if (status & MISCSTATUS_CTS_LATCHED)
2543                 {
2544                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2545                                 info->ie1_value &= ~CCTS;
2546                                 write_reg(info, IE1, info->ie1_value);
2547                         }
2548                         icount->cts++;
2549                         if ( status & SerialSignal_CTS )
2550                                 info->input_signal_events.cts_up++;
2551                         else
2552                                 info->input_signal_events.cts_down++;
2553                 }
2554                 wake_up_interruptible(&info->status_event_wait_q);
2555                 wake_up_interruptible(&info->event_wait_q);
2556
2557                 if ( (info->flags & ASYNC_CHECK_CD) &&
2558                      (status & MISCSTATUS_DCD_LATCHED) ) {
2559                         if ( debug_level >= DEBUG_LEVEL_ISR )
2560                                 printk("%s CD now %s...", info->device_name,
2561                                        (status & SerialSignal_DCD) ? "on" : "off");
2562                         if (status & SerialSignal_DCD)
2563                                 wake_up_interruptible(&info->open_wait);
2564                         else {
2565                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2566                                         printk("doing serial hangup...");
2567                                 if (info->tty)
2568                                         tty_hangup(info->tty);
2569                         }
2570                 }
2571
2572                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2573                      (status & MISCSTATUS_CTS_LATCHED) ) {
2574                         if ( info->tty ) {
2575                                 if (info->tty->hw_stopped) {
2576                                         if (status & SerialSignal_CTS) {
2577                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2578                                                         printk("CTS tx start...");
2579                                                 info->tty->hw_stopped = 0;
2580                                                 tx_start(info);
2581                                                 info->pending_bh |= BH_TRANSMIT;
2582                                                 return;
2583                                         }
2584                                 } else {
2585                                         if (!(status & SerialSignal_CTS)) {
2586                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2587                                                         printk("CTS tx stop...");
2588                                                 info->tty->hw_stopped = 1;
2589                                                 tx_stop(info);
2590                                         }
2591                                 }
2592                         }
2593                 }
2594         }
2595
2596         info->pending_bh |= BH_STATUS;
2597 }
2598
2599 /* Interrupt service routine entry point.
2600  *
2601  * Arguments:
2602  *      irq             interrupt number that caused interrupt
2603  *      dev_id          device ID supplied during interrupt registration
2604  *      regs            interrupted processor context
2605  */
2606 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2607 {
2608         SLMP_INFO *info = dev_id;
2609         unsigned char status, status0, status1=0;
2610         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2611         unsigned char timerstatus0, timerstatus1=0;
2612         unsigned char shift;
2613         unsigned int i;
2614         unsigned short tmp;
2615
2616         if ( debug_level >= DEBUG_LEVEL_ISR )
2617                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2618                         __FILE__, __LINE__, info->irq_level);
2619
2620         spin_lock(&info->lock);
2621
2622         for(;;) {
2623
2624                 /* get status for SCA0 (ports 0-1) */
2625                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2626                 status0 = (unsigned char)tmp;
2627                 dmastatus0 = (unsigned char)(tmp>>8);
2628                 timerstatus0 = read_reg(info, ISR2);
2629
2630                 if ( debug_level >= DEBUG_LEVEL_ISR )
2631                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2632                                 __FILE__, __LINE__, info->device_name,
2633                                 status0, dmastatus0, timerstatus0);
2634
2635                 if (info->port_count == 4) {
2636                         /* get status for SCA1 (ports 2-3) */
2637                         tmp = read_reg16(info->port_array[2], ISR0);
2638                         status1 = (unsigned char)tmp;
2639                         dmastatus1 = (unsigned char)(tmp>>8);
2640                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2641
2642                         if ( debug_level >= DEBUG_LEVEL_ISR )
2643                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2644                                         __FILE__,__LINE__,info->device_name,
2645                                         status1,dmastatus1,timerstatus1);
2646                 }
2647
2648                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2649                          !status1 && !dmastatus1 && !timerstatus1)
2650                         break;
2651
2652                 for(i=0; i < info->port_count ; i++) {
2653                         if (info->port_array[i] == NULL)
2654                                 continue;
2655                         if (i < 2) {
2656                                 status = status0;
2657                                 dmastatus = dmastatus0;
2658                         } else {
2659                                 status = status1;
2660                                 dmastatus = dmastatus1;
2661                         }
2662
2663                         shift = i & 1 ? 4 :0;
2664
2665                         if (status & BIT0 << shift)
2666                                 isr_rxrdy(info->port_array[i]);
2667                         if (status & BIT1 << shift)
2668                                 isr_txrdy(info->port_array[i]);
2669                         if (status & BIT2 << shift)
2670                                 isr_rxint(info->port_array[i]);
2671                         if (status & BIT3 << shift)
2672                                 isr_txint(info->port_array[i]);
2673
2674                         if (dmastatus & BIT0 << shift)
2675                                 isr_rxdmaerror(info->port_array[i]);
2676                         if (dmastatus & BIT1 << shift)
2677                                 isr_rxdmaok(info->port_array[i]);
2678                         if (dmastatus & BIT2 << shift)
2679                                 isr_txdmaerror(info->port_array[i]);
2680                         if (dmastatus & BIT3 << shift)
2681                                 isr_txdmaok(info->port_array[i]);
2682                 }
2683
2684                 if (timerstatus0 & (BIT5 | BIT4))
2685                         isr_timer(info->port_array[0]);
2686                 if (timerstatus0 & (BIT7 | BIT6))
2687                         isr_timer(info->port_array[1]);
2688                 if (timerstatus1 & (BIT5 | BIT4))
2689                         isr_timer(info->port_array[2]);
2690                 if (timerstatus1 & (BIT7 | BIT6))
2691                         isr_timer(info->port_array[3]);
2692         }
2693
2694         for(i=0; i < info->port_count ; i++) {
2695                 SLMP_INFO * port = info->port_array[i];
2696
2697                 /* Request bottom half processing if there's something
2698                  * for it to do and the bh is not already running.
2699                  *
2700                  * Note: startup adapter diags require interrupts.
2701                  * do not request bottom half processing if the
2702                  * device is not open in a normal mode.
2703                  */
2704                 if ( port && (port->count || port->netcount) &&
2705                      port->pending_bh && !port->bh_running &&
2706                      !port->bh_requested ) {
2707                         if ( debug_level >= DEBUG_LEVEL_ISR )
2708                                 printk("%s(%d):%s queueing bh task.\n",
2709                                         __FILE__,__LINE__,port->device_name);
2710                         schedule_work(&port->task);
2711                         port->bh_requested = true;
2712                 }
2713         }
2714
2715         spin_unlock(&info->lock);
2716
2717         if ( debug_level >= DEBUG_LEVEL_ISR )
2718                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2719                         __FILE__, __LINE__, info->irq_level);
2720         return IRQ_HANDLED;
2721 }
2722
2723 /* Initialize and start device.
2724  */
2725 static int startup(SLMP_INFO * info)
2726 {
2727         if ( debug_level >= DEBUG_LEVEL_INFO )
2728                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2729
2730         if (info->flags & ASYNC_INITIALIZED)
2731                 return 0;
2732
2733         if (!info->tx_buf) {
2734                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2735                 if (!info->tx_buf) {
2736                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2737                                 __FILE__,__LINE__,info->device_name);
2738                         return -ENOMEM;
2739                 }
2740         }
2741
2742         info->pending_bh = 0;
2743
2744         memset(&info->icount, 0, sizeof(info->icount));
2745
2746         /* program hardware for current parameters */
2747         reset_port(info);
2748
2749         change_params(info);
2750
2751         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2752
2753         if (info->tty)
2754                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2755
2756         info->flags |= ASYNC_INITIALIZED;
2757
2758         return 0;
2759 }
2760
2761 /* Called by close() and hangup() to shutdown hardware
2762  */
2763 static void shutdown(SLMP_INFO * info)
2764 {
2765         unsigned long flags;
2766
2767         if (!(info->flags & ASYNC_INITIALIZED))
2768                 return;
2769
2770         if (debug_level >= DEBUG_LEVEL_INFO)
2771                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2772                          __FILE__,__LINE__, info->device_name );
2773
2774         /* clear status wait queue because status changes */
2775         /* can't happen after shutting down the hardware */
2776         wake_up_interruptible(&info->status_event_wait_q);
2777         wake_up_interruptible(&info->event_wait_q);
2778
2779         del_timer(&info->tx_timer);
2780         del_timer(&info->status_timer);
2781
2782         kfree(info->tx_buf);
2783         info->tx_buf = NULL;
2784
2785         spin_lock_irqsave(&info->lock,flags);
2786
2787         reset_port(info);
2788
2789         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2790                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2791                 set_signals(info);
2792         }
2793
2794         spin_unlock_irqrestore(&info->lock,flags);
2795
2796         if (info->tty)
2797                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2798
2799         info->flags &= ~ASYNC_INITIALIZED;
2800 }
2801
2802 static void program_hw(SLMP_INFO *info)
2803 {
2804         unsigned long flags;
2805
2806         spin_lock_irqsave(&info->lock,flags);
2807
2808         rx_stop(info);
2809         tx_stop(info);
2810
2811         info->tx_count = info->tx_put = info->tx_get = 0;
2812
2813         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2814                 hdlc_mode(info);
2815         else
2816                 async_mode(info);
2817
2818         set_signals(info);
2819
2820         info->dcd_chkcount = 0;
2821         info->cts_chkcount = 0;
2822         info->ri_chkcount = 0;
2823         info->dsr_chkcount = 0;
2824
2825         info->ie1_value |= (CDCD|CCTS);
2826         write_reg(info, IE1, info->ie1_value);
2827
2828         get_signals(info);
2829
2830         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2831                 rx_start(info);
2832
2833         spin_unlock_irqrestore(&info->lock,flags);
2834 }
2835
2836 /* Reconfigure adapter based on new parameters
2837  */
2838 static void change_params(SLMP_INFO *info)
2839 {
2840         unsigned cflag;
2841         int bits_per_char;
2842
2843         if (!info->tty || !info->tty->termios)
2844                 return;
2845
2846         if (debug_level >= DEBUG_LEVEL_INFO)
2847                 printk("%s(%d):%s change_params()\n",
2848                          __FILE__,__LINE__, info->device_name );
2849
2850         cflag = info->tty->termios->c_cflag;
2851
2852         /* if B0 rate (hangup) specified then negate DTR and RTS */
2853         /* otherwise assert DTR and RTS */
2854         if (cflag & CBAUD)
2855                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2856         else
2857                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2858
2859         /* byte size and parity */
2860
2861         switch (cflag & CSIZE) {
2862               case CS5: info->params.data_bits = 5; break;
2863               case CS6: info->params.data_bits = 6; break;
2864               case CS7: info->params.data_bits = 7; break;
2865               case CS8: info->params.data_bits = 8; break;
2866               /* Never happens, but GCC is too dumb to figure it out */
2867               default:  info->params.data_bits = 7; break;
2868               }
2869
2870         if (cflag & CSTOPB)
2871                 info->params.stop_bits = 2;
2872         else
2873                 info->params.stop_bits = 1;
2874
2875         info->params.parity = ASYNC_PARITY_NONE;
2876         if (cflag & PARENB) {
2877                 if (cflag & PARODD)
2878                         info->params.parity = ASYNC_PARITY_ODD;
2879                 else
2880                         info->params.parity = ASYNC_PARITY_EVEN;
2881 #ifdef CMSPAR
2882                 if (cflag & CMSPAR)
2883                         info->params.parity = ASYNC_PARITY_SPACE;
2884 #endif
2885         }
2886
2887         /* calculate number of jiffies to transmit a full
2888          * FIFO (32 bytes) at specified data rate
2889          */
2890         bits_per_char = info->params.data_bits +
2891                         info->params.stop_bits + 1;
2892
2893         /* if port data rate is set to 460800 or less then
2894          * allow tty settings to override, otherwise keep the
2895          * current data rate.
2896          */
2897         if (info->params.data_rate <= 460800) {
2898                 info->params.data_rate = tty_get_baud_rate(info->tty);
2899         }
2900
2901         if ( info->params.data_rate ) {
2902                 info->timeout = (32*HZ*bits_per_char) /
2903                                 info->params.data_rate;
2904         }
2905         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2906
2907         if (cflag & CRTSCTS)
2908                 info->flags |= ASYNC_CTS_FLOW;
2909         else
2910                 info->flags &= ~ASYNC_CTS_FLOW;
2911
2912         if (cflag & CLOCAL)
2913                 info->flags &= ~ASYNC_CHECK_CD;
2914         else
2915                 info->flags |= ASYNC_CHECK_CD;
2916
2917         /* process tty input control flags */
2918
2919         info->read_status_mask2 = OVRN;
2920         if (I_INPCK(info->tty))
2921                 info->read_status_mask2 |= PE | FRME;
2922         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2923                 info->read_status_mask1 |= BRKD;
2924         if (I_IGNPAR(info->tty))
2925                 info->ignore_status_mask2 |= PE | FRME;
2926         if (I_IGNBRK(info->tty)) {
2927                 info->ignore_status_mask1 |= BRKD;
2928                 /* If ignoring parity and break indicators, ignore
2929                  * overruns too.  (For real raw support).
2930                  */
2931                 if (I_IGNPAR(info->tty))
2932                         info->ignore_status_mask2 |= OVRN;
2933         }
2934
2935         program_hw(info);
2936 }
2937
2938 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2939 {
2940         int err;
2941
2942         if (debug_level >= DEBUG_LEVEL_INFO)
2943                 printk("%s(%d):%s get_params()\n",
2944                          __FILE__,__LINE__, info->device_name);
2945
2946         if (!user_icount) {
2947                 memset(&info->icount, 0, sizeof(info->icount));
2948         } else {
2949                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2950                 if (err)
2951                         return -EFAULT;
2952         }
2953
2954         return 0;
2955 }
2956
2957 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2958 {
2959         int err;
2960         if (debug_level >= DEBUG_LEVEL_INFO)
2961                 printk("%s(%d):%s get_params()\n",
2962                          __FILE__,__LINE__, info->device_name);
2963
2964         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2965         if (err) {
2966                 if ( debug_level >= DEBUG_LEVEL_INFO )
2967                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2968                                 __FILE__,__LINE__,info->device_name);
2969                 return -EFAULT;
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2976 {
2977         unsigned long flags;
2978         MGSL_PARAMS tmp_params;
2979         int err;
2980
2981         if (debug_level >= DEBUG_LEVEL_INFO)
2982                 printk("%s(%d):%s set_params\n",
2983                         __FILE__,__LINE__,info->device_name );
2984         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2985         if (err) {
2986                 if ( debug_level >= DEBUG_LEVEL_INFO )
2987                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2988                                 __FILE__,__LINE__,info->device_name);
2989                 return -EFAULT;
2990         }
2991
2992         spin_lock_irqsave(&info->lock,flags);
2993         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2994         spin_unlock_irqrestore(&info->lock,flags);
2995
2996         change_params(info);
2997
2998         return 0;
2999 }
3000
3001 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3002 {
3003         int err;
3004
3005         if (debug_level >= DEBUG_LEVEL_INFO)
3006                 printk("%s(%d):%s get_txidle()=%d\n",
3007                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3008
3009         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3010         if (err) {
3011                 if ( debug_level >= DEBUG_LEVEL_INFO )
3012                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3013                                 __FILE__,__LINE__,info->device_name);
3014                 return -EFAULT;
3015         }
3016
3017         return 0;
3018 }
3019
3020 static int set_txidle(SLMP_INFO * info, int idle_mode)
3021 {
3022         unsigned long flags;
3023
3024         if (debug_level >= DEBUG_LEVEL_INFO)
3025                 printk("%s(%d):%s set_txidle(%d)\n",
3026                         __FILE__,__LINE__,info->device_name, idle_mode );
3027
3028         spin_lock_irqsave(&info->lock,flags);
3029         info->idle_mode = idle_mode;
3030         tx_set_idle( info );
3031         spin_unlock_irqrestore(&info->lock,flags);
3032         return 0;
3033 }
3034
3035 static int tx_enable(SLMP_INFO * info, int enable)
3036 {
3037         unsigned long flags;
3038
3039         if (debug_level >= DEBUG_LEVEL_INFO)
3040                 printk("%s(%d):%s tx_enable(%d)\n",
3041                         __FILE__,__LINE__,info->device_name, enable);
3042
3043         spin_lock_irqsave(&info->lock,flags);
3044         if ( enable ) {
3045                 if ( !info->tx_enabled ) {
3046                         tx_start(info);
3047                 }
3048         } else {
3049                 if ( info->tx_enabled )
3050                         tx_stop(info);
3051         }
3052         spin_unlock_irqrestore(&info->lock,flags);
3053         return 0;
3054 }
3055
3056 /* abort send HDLC frame
3057  */
3058 static int tx_abort(SLMP_INFO * info)
3059 {
3060         unsigned long flags;
3061
3062         if (debug_level >= DEBUG_LEVEL_INFO)
3063                 printk("%s(%d):%s tx_abort()\n",
3064                         __FILE__,__LINE__,info->device_name);
3065
3066         spin_lock_irqsave(&info->lock,flags);
3067         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3068                 info->ie1_value &= ~UDRN;
3069                 info->ie1_value |= IDLE;
3070                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3071                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3072
3073                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3074                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3075
3076                 write_reg(info, CMD, TXABORT);
3077         }
3078         spin_unlock_irqrestore(&info->lock,flags);
3079         return 0;
3080 }
3081
3082 static int rx_enable(SLMP_INFO * info, int enable)
3083 {
3084         unsigned long flags;
3085
3086         if (debug_level >= DEBUG_LEVEL_INFO)
3087                 printk("%s(%d):%s rx_enable(%d)\n",
3088                         __FILE__,__LINE__,info->device_name,enable);
3089
3090         spin_lock_irqsave(&info->lock,flags);
3091         if ( enable ) {
3092                 if ( !info->rx_enabled )
3093                         rx_start(info);
3094         } else {
3095                 if ( info->rx_enabled )
3096                         rx_stop(info);
3097         }
3098         spin_unlock_irqrestore(&info->lock,flags);
3099         return 0;
3100 }
3101
3102 /* wait for specified event to occur
3103  */
3104 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3105 {
3106         unsigned long flags;
3107         int s;
3108         int rc=0;
3109         struct mgsl_icount cprev, cnow;
3110         int events;
3111         int mask;
3112         struct  _input_signal_events oldsigs, newsigs;
3113         DECLARE_WAITQUEUE(wait, current);
3114
3115         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3116         if (rc) {
3117                 return  -EFAULT;
3118         }
3119
3120         if (debug_level >= DEBUG_LEVEL_INFO)
3121                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3122                         __FILE__,__LINE__,info->device_name,mask);
3123
3124         spin_lock_irqsave(&info->lock,flags);
3125
3126         /* return immediately if state matches requested events */
3127         get_signals(info);
3128         s = info->serial_signals;
3129
3130         events = mask &
3131                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3132                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3133                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3134                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3135         if (events) {
3136                 spin_unlock_irqrestore(&info->lock,flags);
3137                 goto exit;
3138         }
3139
3140         /* save current irq counts */
3141         cprev = info->icount;
3142         oldsigs = info->input_signal_events;
3143
3144         /* enable hunt and idle irqs if needed */
3145         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3146                 unsigned char oldval = info->ie1_value;
3147                 unsigned char newval = oldval +
3148                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3149                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3150                 if ( oldval != newval ) {
3151                         info->ie1_value = newval;
3152                         write_reg(info, IE1, info->ie1_value);
3153                 }
3154         }
3155
3156         set_current_state(TASK_INTERRUPTIBLE);
3157         add_wait_queue(&info->event_wait_q, &wait);
3158
3159         spin_unlock_irqrestore(&info->lock,flags);
3160
3161         for(;;) {
3162                 schedule();
3163                 if (signal_pending(current)) {
3164                         rc = -ERESTARTSYS;
3165                         break;
3166                 }
3167
3168                 /* get current irq counts */
3169                 spin_lock_irqsave(&info->lock,flags);
3170                 cnow = info->icount;
3171                 newsigs = info->input_signal_events;
3172                 set_current_state(TASK_INTERRUPTIBLE);
3173                 spin_unlock_irqrestore(&info->lock,flags);
3174
3175                 /* if no change, wait aborted for some reason */
3176                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3177                     newsigs.dsr_down == oldsigs.dsr_down &&
3178                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3179                     newsigs.dcd_down == oldsigs.dcd_down &&
3180                     newsigs.cts_up   == oldsigs.cts_up   &&
3181                     newsigs.cts_down == oldsigs.cts_down &&
3182                     newsigs.ri_up    == oldsigs.ri_up    &&
3183                     newsigs.ri_down  == oldsigs.ri_down  &&
3184                     cnow.exithunt    == cprev.exithunt   &&
3185                     cnow.rxidle      == cprev.rxidle) {
3186                         rc = -EIO;
3187                         break;
3188                 }
3189
3190                 events = mask &
3191                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3192                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3193                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3194                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3195                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3196                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3197                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3198                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3199                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3200                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3201                 if (events)
3202                         break;
3203
3204                 cprev = cnow;
3205                 oldsigs = newsigs;
3206         }
3207
3208         remove_wait_queue(&info->event_wait_q, &wait);
3209         set_current_state(TASK_RUNNING);
3210
3211
3212         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3213                 spin_lock_irqsave(&info->lock,flags);
3214                 if (!waitqueue_active(&info->event_wait_q)) {
3215                         /* disable enable exit hunt mode/idle rcvd IRQs */
3216                         info->ie1_value &= ~(FLGD|IDLD);
3217                         write_reg(info, IE1, info->ie1_value);
3218                 }
3219                 spin_unlock_irqrestore(&info->lock,flags);
3220         }
3221 exit:
3222         if ( rc == 0 )
3223                 PUT_USER(rc, events, mask_ptr);
3224
3225         return rc;
3226 }
3227
3228 static int modem_input_wait(SLMP_INFO *info,int arg)
3229 {
3230         unsigned long flags;
3231         int rc;
3232         struct mgsl_icount cprev, cnow;
3233         DECLARE_WAITQUEUE(wait, current);
3234
3235         /* save current irq counts */
3236         spin_lock_irqsave(&info->lock,flags);
3237         cprev = info->icount;
3238         add_wait_queue(&info->status_event_wait_q, &wait);
3239         set_current_state(TASK_INTERRUPTIBLE);
3240         spin_unlock_irqrestore(&info->lock,flags);
3241
3242         for(;;) {
3243                 schedule();
3244                 if (signal_pending(current)) {
3245                         rc = -ERESTARTSYS;
3246                         break;
3247                 }
3248
3249                 /* get new irq counts */
3250                 spin_lock_irqsave(&info->lock,flags);
3251                 cnow = info->icount;
3252                 set_current_state(TASK_INTERRUPTIBLE);
3253                 spin_unlock_irqrestore(&info->lock,flags);
3254
3255                 /* if no change, wait aborted for some reason */
3256                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3257                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3258                         rc = -EIO;
3259                         break;
3260                 }
3261
3262                 /* check for change in caller specified modem input */
3263                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3264                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3265                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3266                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3267                         rc = 0;
3268                         break;
3269                 }
3270
3271                 cprev = cnow;
3272         }
3273         remove_wait_queue(&info->status_event_wait_q, &wait);
3274         set_current_state(TASK_RUNNING);
3275         return rc;
3276 }
3277
3278 /* return the state of the serial control and status signals
3279  */
3280 static int tiocmget(struct tty_struct *tty, struct file *file)
3281 {
3282         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3283         unsigned int result;
3284         unsigned long flags;
3285
3286         spin_lock_irqsave(&info->lock,flags);
3287         get_signals(info);
3288         spin_unlock_irqrestore(&info->lock,flags);
3289
3290         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3291                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3292                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3293                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3294                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3295                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3296
3297         if (debug_level >= DEBUG_LEVEL_INFO)
3298                 printk("%s(%d):%s tiocmget() value=%08X\n",
3299                          __FILE__,__LINE__, info->device_name, result );
3300         return result;
3301 }
3302
3303 /* set modem control signals (DTR/RTS)
3304  */
3305 static int tiocmset(struct tty_struct *tty, struct file *file,
3306                     unsigned int set, unsigned int clear)
3307 {
3308         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3309         unsigned long flags;
3310
3311         if (debug_level >= DEBUG_LEVEL_INFO)
3312                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3313                         __FILE__,__LINE__,info->device_name, set, clear);
3314
3315         if (set & TIOCM_RTS)
3316                 info->serial_signals |= SerialSignal_RTS;
3317         if (set & TIOCM_DTR)
3318                 info->serial_signals |= SerialSignal_DTR;
3319         if (clear & TIOCM_RTS)
3320                 info->serial_signals &= ~SerialSignal_RTS;
3321         if (clear & TIOCM_DTR)
3322                 info->serial_signals &= ~SerialSignal_DTR;
3323
3324         spin_lock_irqsave(&info->lock,flags);
3325         set_signals(info);
3326         spin_unlock_irqrestore(&info->lock,flags);
3327
3328         return 0;
3329 }
3330
3331
3332
3333 /* Block the current process until the specified port is ready to open.
3334  */
3335 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3336                            SLMP_INFO *info)
3337 {
3338         DECLARE_WAITQUEUE(wait, current);
3339         int             retval;
3340         bool            do_clocal = false;
3341         bool            extra_count = false;
3342         unsigned long   flags;
3343
3344         if (debug_level >= DEBUG_LEVEL_INFO)
3345                 printk("%s(%d):%s block_til_ready()\n",
3346                          __FILE__,__LINE__, tty->driver->name );
3347
3348         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3349                 /* nonblock mode is set or port is not enabled */
3350                 /* just verify that callout device is not active */
3351                 info->flags |= ASYNC_NORMAL_ACTIVE;
3352                 return 0;
3353         }
3354
3355         if (tty->termios->c_cflag & CLOCAL)
3356                 do_clocal = true;
3357
3358         /* Wait for carrier detect and the line to become
3359          * free (i.e., not in use by the callout).  While we are in
3360          * this loop, info->count is dropped by one, so that
3361          * close() knows when to free things.  We restore it upon
3362          * exit, either normal or abnormal.
3363          */
3364
3365         retval = 0;
3366         add_wait_queue(&info->open_wait, &wait);
3367
3368         if (debug_level >= DEBUG_LEVEL_INFO)
3369                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3370                          __FILE__,__LINE__, tty->driver->name, info->count );
3371
3372         spin_lock_irqsave(&info->lock, flags);
3373         if (!tty_hung_up_p(filp)) {
3374                 extra_count = true;
3375                 info->count--;
3376         }
3377         spin_unlock_irqrestore(&info->lock, flags);
3378         info->blocked_open++;
3379
3380         while (1) {
3381                 if ((tty->termios->c_cflag & CBAUD)) {
3382                         spin_lock_irqsave(&info->lock,flags);
3383                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3384                         set_signals(info);
3385                         spin_unlock_irqrestore(&info->lock,flags);
3386                 }
3387
3388                 set_current_state(TASK_INTERRUPTIBLE);
3389
3390                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3391                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3392                                         -EAGAIN : -ERESTARTSYS;
3393                         break;
3394                 }
3395
3396                 spin_lock_irqsave(&info->lock,flags);
3397                 get_signals(info);
3398                 spin_unlock_irqrestore(&info->lock,flags);
3399
3400                 if (!(info->flags & ASYNC_CLOSING) &&
3401                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3402                         break;
3403                 }
3404
3405                 if (signal_pending(current)) {
3406                         retval = -ERESTARTSYS;
3407                         break;
3408                 }
3409
3410                 if (debug_level >= DEBUG_LEVEL_INFO)
3411                         printk("%s(%d):%s block_til_ready() count=%d\n",
3412                                  __FILE__,__LINE__, tty->driver->name, info->count );
3413
3414                 schedule();
3415         }
3416
3417         set_current_state(TASK_RUNNING);
3418         remove_wait_queue(&info->open_wait, &wait);
3419
3420         if (extra_count)
3421                 info->count++;
3422         info->blocked_open--;
3423
3424         if (debug_level >= DEBUG_LEVEL_INFO)
3425                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3426                          __FILE__,__LINE__, tty->driver->name, info->count );
3427
3428         if (!retval)
3429                 info->flags |= ASYNC_NORMAL_ACTIVE;
3430
3431         return retval;
3432 }
3433
3434 static int alloc_dma_bufs(SLMP_INFO *info)
3435 {
3436         unsigned short BuffersPerFrame;
3437         unsigned short BufferCount;
3438
3439         // Force allocation to start at 64K boundary for each port.
3440         // This is necessary because *all* buffer descriptors for a port
3441         // *must* be in the same 64K block. All descriptors on a port
3442         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3443         // into the CBP register.
3444         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3445
3446         /* Calculate the number of DMA buffers necessary to hold the */
3447         /* largest allowable frame size. Note: If the max frame size is */
3448         /* not an even multiple of the DMA buffer size then we need to */
3449         /* round the buffer count per frame up one. */
3450
3451         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3452         if ( info->max_frame_size % SCABUFSIZE )
3453                 BuffersPerFrame++;
3454
3455         /* calculate total number of data buffers (SCABUFSIZE) possible
3456          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3457          * for the descriptor list (BUFFERLISTSIZE).
3458          */
3459         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3460
3461         /* limit number of buffers to maximum amount of descriptors */
3462         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3463                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3464
3465         /* use enough buffers to transmit one max size frame */
3466         info->tx_buf_count = BuffersPerFrame + 1;
3467
3468         /* never use more than half the available buffers for transmit */
3469         if (info->tx_buf_count > (BufferCount/2))
3470                 info->tx_buf_count = BufferCount/2;
3471
3472         if (info->tx_buf_count > SCAMAXDESC)
3473                 info->tx_buf_count = SCAMAXDESC;
3474
3475         /* use remaining buffers for receive */
3476         info->rx_buf_count = BufferCount - info->tx_buf_count;
3477
3478         if (info->rx_buf_count > SCAMAXDESC)
3479                 info->rx_buf_count = SCAMAXDESC;
3480
3481         if ( debug_level >= DEBUG_LEVEL_INFO )
3482                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3483                         __FILE__,__LINE__, info->device_name,
3484                         info->tx_buf_count,info->rx_buf_count);
3485
3486         if ( alloc_buf_list( info ) < 0 ||
3487                 alloc_frame_bufs(info,
3488                                         info->rx_buf_list,
3489                                         info->rx_buf_list_ex,
3490                                         info->rx_buf_count) < 0 ||
3491                 alloc_frame_bufs(info,
3492                                         info->tx_buf_list,
3493                                         info->tx_buf_list_ex,
3494                                         info->tx_buf_count) < 0 ||
3495                 alloc_tmp_rx_buf(info) < 0 ) {
3496                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3497                         __FILE__,__LINE__, info->device_name);
3498                 return -ENOMEM;
3499         }
3500
3501         rx_reset_buffers( info );
3502
3503         return 0;
3504 }
3505
3506 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3507  */
3508 static int alloc_buf_list(SLMP_INFO *info)
3509 {
3510         unsigned int i;
3511
3512         /* build list in adapter shared memory */
3513         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3514         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3515         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3516
3517         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3518
3519         /* Save virtual address pointers to the receive and */
3520         /* transmit buffer lists. (Receive 1st). These pointers will */
3521         /* be used by the processor to access the lists. */
3522         info->rx_buf_list = (SCADESC *)info->buffer_list;
3523
3524         info->tx_buf_list = (SCADESC *)info->buffer_list;
3525         info->tx_buf_list += info->rx_buf_count;
3526
3527         /* Build links for circular buffer entry lists (tx and rx)
3528          *
3529          * Note: links are physical addresses read by the SCA device
3530          * to determine the next buffer entry to use.
3531          */
3532
3533         for ( i = 0; i < info->rx_buf_count; i++ ) {
3534                 /* calculate and store physical address of this buffer entry */
3535                 info->rx_buf_list_ex[i].phys_entry =
3536                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3537
3538                 /* calculate and store physical address of */
3539                 /* next entry in cirular list of entries */
3540                 info->rx_buf_list[i].next = info->buffer_list_phys;
3541                 if ( i < info->rx_buf_count - 1 )
3542                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3543
3544                 info->rx_buf_list[i].length = SCABUFSIZE;
3545         }
3546
3547         for ( i = 0; i < info->tx_buf_count; i++ ) {
3548                 /* calculate and store physical address of this buffer entry */
3549                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3550                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3551
3552                 /* calculate and store physical address of */
3553                 /* next entry in cirular list of entries */
3554
3555                 info->tx_buf_list[i].next = info->buffer_list_phys +
3556                         info->rx_buf_count * sizeof(SCADESC);
3557
3558                 if ( i < info->tx_buf_count - 1 )
3559                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3560         }
3561
3562         return 0;
3563 }
3564
3565 /* Allocate the frame DMA buffers used by the specified buffer list.
3566  */
3567 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3568 {
3569         int i;
3570         unsigned long phys_addr;
3571
3572         for ( i = 0; i < count; i++ ) {
3573                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3574                 phys_addr = info->port_array[0]->last_mem_alloc;
3575                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3576
3577                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3578                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3579         }
3580
3581         return 0;
3582 }
3583
3584 static void free_dma_bufs(SLMP_INFO *info)
3585 {
3586         info->buffer_list = NULL;
3587         info->rx_buf_list = NULL;
3588         info->tx_buf_list = NULL;
3589 }
3590
3591 /* allocate buffer large enough to hold max_frame_size.
3592  * This buffer is used to pass an assembled frame to the line discipline.
3593  */
3594 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3595 {
3596         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3597         if (info->tmp_rx_buf == NULL)
3598                 return -ENOMEM;
3599         return 0;
3600 }
3601
3602 static void free_tmp_rx_buf(SLMP_INFO *info)
3603 {
3604         kfree(info->tmp_rx_buf);
3605         info->tmp_rx_buf = NULL;
3606 }
3607
3608 static int claim_resources(SLMP_INFO *info)
3609 {
3610         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3611                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3612                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3613                 info->init_error = DiagStatus_AddressConflict;
3614                 goto errout;
3615         }
3616         else
3617                 info->shared_mem_requested = true;
3618
3619         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3620                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3621                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3622                 info->init_error = DiagStatus_AddressConflict;
3623                 goto errout;
3624         }
3625         else
3626                 info->lcr_mem_requested = true;
3627
3628         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3629                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3630                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3631                 info->init_error = DiagStatus_AddressConflict;
3632                 goto errout;
3633         }
3634         else
3635                 info->sca_base_requested = true;
3636
3637         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3638                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3639                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3640                 info->init_error = DiagStatus_AddressConflict;
3641                 goto errout;
3642         }
3643         else
3644                 info->sca_statctrl_requested = true;
3645
3646         info->memory_base = ioremap_nocache(info->phys_memory_base,
3647                                                                 SCA_MEM_SIZE);
3648         if (!info->memory_base) {
3649                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3650                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3651                 info->init_error = DiagStatus_CantAssignPciResources;
3652                 goto errout;
3653         }
3654
3655         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3656         if (!info->lcr_base) {
3657                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3658                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3659                 info->init_error = DiagStatus_CantAssignPciResources;
3660                 goto errout;
3661         }
3662         info->lcr_base += info->lcr_offset;
3663
3664         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3665         if (!info->sca_base) {
3666                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3667                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3668                 info->init_error = DiagStatus_CantAssignPciResources;
3669                 goto errout;
3670         }
3671         info->sca_base += info->sca_offset;
3672
3673         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3674                                                                 PAGE_SIZE);
3675         if (!info->statctrl_base) {
3676                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3677                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3678                 info->init_error = DiagStatus_CantAssignPciResources;
3679                 goto errout;
3680         }
3681         info->statctrl_base += info->statctrl_offset;
3682
3683         if ( !memory_test(info) ) {
3684                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3685                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3686                 info->init_error = DiagStatus_MemoryError;
3687                 goto errout;
3688         }
3689
3690         return 0;
3691
3692 errout:
3693         release_resources( info );
3694         return -ENODEV;
3695 }
3696
3697 static void release_resources(SLMP_INFO *info)
3698 {
3699         if ( debug_level >= DEBUG_LEVEL_INFO )
3700                 printk( "%s(%d):%s release_resources() entry\n",
3701                         __FILE__,__LINE__,info->device_name );
3702
3703         if ( info->irq_requested ) {
3704                 free_irq(info->irq_level, info);
3705                 info->irq_requested = false;
3706         }
3707
3708         if ( info->shared_mem_requested ) {
3709                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3710                 info->shared_mem_requested = false;
3711         }
3712         if ( info->lcr_mem_requested ) {
3713                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3714                 info->lcr_mem_requested = false;
3715         }
3716         if ( info->sca_base_requested ) {
3717                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3718                 info->sca_base_requested = false;
3719         }
3720         if ( info->sca_statctrl_requested ) {
3721                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3722                 info->sca_statctrl_requested = false;
3723         }
3724
3725         if (info->memory_base){
3726                 iounmap(info->memory_base);
3727                 info->memory_base = NULL;
3728         }
3729
3730         if (info->sca_base) {
3731                 iounmap(info->sca_base - info->sca_offset);
3732                 info->sca_base=NULL;
3733         }
3734
3735         if (info->statctrl_base) {
3736                 iounmap(info->statctrl_base - info->statctrl_offset);
3737                 info->statctrl_base=NULL;
3738         }
3739
3740         if (info->lcr_base){
3741                 iounmap(info->lcr_base - info->lcr_offset);
3742                 info->lcr_base = NULL;
3743         }
3744
3745         if ( debug_level >= DEBUG_LEVEL_INFO )
3746                 printk( "%s(%d):%s release_resources() exit\n",
3747                         __FILE__,__LINE__,info->device_name );
3748 }
3749
3750 /* Add the specified device instance data structure to the
3751  * global linked list of devices and increment the device count.
3752  */
3753 static void add_device(SLMP_INFO *info)
3754 {
3755         info->next_device = NULL;
3756         info->line = synclinkmp_device_count;
3757         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3758
3759         if (info->line < MAX_DEVICES) {
3760                 if (maxframe[info->line])
3761                         info->max_frame_size = maxframe[info->line];
3762                 info->dosyncppp = dosyncppp[info->line];
3763         }
3764
3765         synclinkmp_device_count++;
3766
3767         if ( !synclinkmp_device_list )
3768                 synclinkmp_device_list = info;
3769         else {
3770                 SLMP_INFO *current_dev = synclinkmp_device_list;
3771                 while( current_dev->next_device )
3772                         current_dev = current_dev->next_device;
3773                 current_dev->next_device = info;
3774         }
3775
3776         if ( info->max_frame_size < 4096 )
3777                 info->max_frame_size = 4096;
3778         else if ( info->max_frame_size > 65535 )
3779                 info->max_frame_size = 65535;
3780
3781         printk( "SyncLink MultiPort %s: "
3782                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3783                 info->device_name,
3784                 info->phys_sca_base,
3785                 info->phys_memory_base,
3786                 info->phys_statctrl_base,
3787                 info->phys_lcr_base,
3788                 info->irq_level,
3789                 info->max_frame_size );
3790
3791 #if SYNCLINK_GENERIC_HDLC
3792         hdlcdev_init(info);
3793 #endif
3794 }
3795
3796 /* Allocate and initialize a device instance structure
3797  *
3798  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3799  */
3800 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3801 {
3802         SLMP_INFO *info;
3803
3804         info = kzalloc(sizeof(SLMP_INFO),
3805                  GFP_KERNEL);
3806
3807         if (!info) {
3808                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3809                         __FILE__,__LINE__, adapter_num, port_num);
3810         } else {
3811                 info->magic = MGSL_MAGIC;
3812                 INIT_WORK(&info->task, bh_handler);
3813                 info->max_frame_size = 4096;
3814                 info->close_delay = 5*HZ/10;
3815                 info->closing_wait = 30*HZ;
3816                 init_waitqueue_head(&info->open_wait);
3817                 init_waitqueue_head(&info->close_wait);
3818                 init_waitqueue_head(&info->status_event_wait_q);
3819                 init_waitqueue_head(&info->event_wait_q);
3820                 spin_lock_init(&info->netlock);
3821                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3822                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3823                 info->adapter_num = adapter_num;
3824                 info->port_num = port_num;
3825
3826                 /* Copy configuration info to device instance data */
3827                 info->irq_level = pdev->irq;
3828                 info->phys_lcr_base = pci_resource_start(pdev,0);
3829                 info->phys_sca_base = pci_resource_start(pdev,2);
3830                 info->phys_memory_base = pci_resource_start(pdev,3);
3831                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3832
3833                 /* Because veremap only works on page boundaries we must map
3834                  * a larger area than is actually implemented for the LCR
3835                  * memory range. We map a full page starting at the page boundary.
3836                  */
3837                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3838                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3839
3840                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3841                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3842
3843                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3844                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3845
3846                 info->bus_type = MGSL_BUS_TYPE_PCI;
3847                 info->irq_flags = IRQF_SHARED;
3848
3849                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3850                 setup_timer(&info->status_timer, status_timeout,
3851                                 (unsigned long)info);
3852
3853                 /* Store the PCI9050 misc control register value because a flaw
3854                  * in the PCI9050 prevents LCR registers from being read if
3855                  * BIOS assigns an LCR base address with bit 7 set.
3856                  *
3857                  * Only the misc control register is accessed for which only
3858                  * write access is needed, so set an initial value and change
3859                  * bits to the device instance data as we write the value
3860                  * to the actual misc control register.
3861                  */
3862                 info->misc_ctrl_value = 0x087e4546;
3863
3864                 /* initial port state is unknown - if startup errors
3865                  * occur, init_error will be set to indicate the
3866                  * problem. Once the port is fully initialized,
3867                  * this value will be set to 0 to indicate the
3868                  * port is available.
3869                  */
3870                 info->init_error = -1;
3871         }
3872
3873         return info;
3874 }
3875
3876 static void device_init(int adapter_num, struct pci_dev *pdev)
3877 {
3878         SLMP_INFO *port_array[SCA_MAX_PORTS];
3879         int port;
3880
3881         /* allocate device instances for up to SCA_MAX_PORTS devices */
3882         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3883                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3884                 if( port_array[port] == NULL ) {
3885                         for ( --port; port >= 0; --port )
3886                                 kfree(port_array[port]);
3887                         return;
3888                 }
3889         }
3890
3891         /* give copy of port_array to all ports and add to device list  */
3892         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3893                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3894                 add_device( port_array[port] );
3895                 spin_lock_init(&port_array[port]->lock);
3896         }
3897
3898         /* Allocate and claim adapter resources */
3899         if ( !claim_resources(port_array[0]) ) {
3900
3901                 alloc_dma_bufs(port_array[0]);
3902
3903                 /* copy resource information from first port to others */
3904                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3905                         port_array[port]->lock  = port_array[0]->lock;
3906                         port_array[port]->irq_level     = port_array[0]->irq_level;
3907                         port_array[port]->memory_base   = port_array[0]->memory_base;
3908                         port_array[port]->sca_base      = port_array[0]->sca_base;
3909                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3910                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3911                         alloc_dma_bufs(port_array[port]);
3912                 }
3913
3914                 if ( request_irq(port_array[0]->irq_level,
3915                                         synclinkmp_interrupt,
3916                                         port_array[0]->irq_flags,
3917                                         port_array[0]->device_name,
3918                                         port_array[0]) < 0 ) {
3919                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3920                                 __FILE__,__LINE__,
3921                                 port_array[0]->device_name,
3922                                 port_array[0]->irq_level );
3923                 }
3924                 else {
3925                         port_array[0]->irq_requested = true;
3926                         adapter_test(port_array[0]);
3927                 }
3928         }
3929 }
3930
3931 static const struct tty_operations ops = {
3932         .open = open,
3933         .close = close,
3934         .write = write,
3935         .put_char = put_char,
3936         .flush_chars = flush_chars,
3937         .write_room = write_room,
3938         .chars_in_buffer = chars_in_buffer,
3939         .flush_buffer = flush_buffer,
3940         .ioctl = ioctl,
3941         .throttle = throttle,
3942         .unthrottle = unthrottle,
3943         .send_xchar = send_xchar,
3944         .break_ctl = set_break,
3945         .wait_until_sent = wait_until_sent,
3946         .read_proc = read_proc,
3947         .set_termios = set_termios,
3948         .stop = tx_hold,
3949         .start = tx_release,
3950         .hangup = hangup,
3951         .tiocmget = tiocmget,
3952         .tiocmset = tiocmset,
3953 };
3954
3955 static void synclinkmp_cleanup(void)
3956 {
3957         int rc;
3958         SLMP_INFO *info;
3959         SLMP_INFO *tmp;
3960
3961         printk("Unloading %s %s\n", driver_name, driver_version);
3962
3963         if (serial_driver) {
3964                 if ((rc = tty_unregister_driver(serial_driver)))
3965                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3966                                __FILE__,__LINE__,rc);
3967                 put_tty_driver(serial_driver);
3968         }
3969
3970         /* reset devices */
3971         info = synclinkmp_device_list;
3972         while(info) {
3973                 reset_port(info);
3974                 info = info->next_device;
3975         }
3976
3977         /* release devices */
3978         info = synclinkmp_device_list;
3979         while(info) {
3980 #if SYNCLINK_GENERIC_HDLC
3981                 hdlcdev_exit(info);
3982 #endif
3983                 free_dma_bufs(info);
3984                 free_tmp_rx_buf(info);
3985                 if ( info->port_num == 0 ) {
3986                         if (info->sca_base)
3987                                 write_reg(info, LPR, 1); /* set low power mode */
3988                         release_resources(info);
3989                 }
3990                 tmp = info;
3991                 info = info->next_device;
3992                 kfree(tmp);
3993         }
3994
3995         pci_unregister_driver(&synclinkmp_pci_driver);
3996 }
3997
3998 /* Driver initialization entry point.
3999  */
4000
4001 static int __init synclinkmp_init(void)
4002 {
4003         int rc;
4004
4005         if (break_on_load) {
4006                 synclinkmp_get_text_ptr();
4007                 BREAKPOINT();
4008         }
4009
4010         printk("%s %s\n", driver_name, driver_version);
4011
4012         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4013                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4014                 return rc;
4015         }
4016
4017         serial_driver = alloc_tty_driver(128);
4018         if (!serial_driver) {
4019                 rc = -ENOMEM;
4020                 goto error;
4021         }
4022
4023         /* Initialize the tty_driver structure */
4024
4025         serial_driver->owner = THIS_MODULE;
4026         serial_driver->driver_name = "synclinkmp";
4027         serial_driver->name = "ttySLM";
4028         serial_driver->major = ttymajor;
4029         serial_driver->minor_start = 64;
4030         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4031         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4032         serial_driver->init_termios = tty_std_termios;
4033         serial_driver->init_termios.c_cflag =
4034                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4035         serial_driver->init_termios.c_ispeed = 9600;
4036         serial_driver->init_termios.c_ospeed = 9600;
4037         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4038         tty_set_operations(serial_driver, &ops);
4039         if ((rc = tty_register_driver(serial_driver)) < 0) {
4040                 printk("%s(%d):Couldn't register serial driver\n",
4041                         __FILE__,__LINE__);
4042                 put_tty_driver(serial_driver);
4043                 serial_driver = NULL;
4044                 goto error;
4045         }
4046
4047         printk("%s %s, tty major#%d\n",
4048                 driver_name, driver_version,
4049                 serial_driver->major);
4050
4051         return 0;
4052
4053 error:
4054         synclinkmp_cleanup();
4055         return rc;
4056 }
4057
4058 static void __exit synclinkmp_exit(void)
4059 {
4060         synclinkmp_cleanup();
4061 }
4062
4063 module_init(synclinkmp_init);
4064 module_exit(synclinkmp_exit);
4065
4066 /* Set the port for internal loopback mode.
4067  * The TxCLK and RxCLK signals are generated from the BRG and
4068  * the TxD is looped back to the RxD internally.
4069  */
4070 static void enable_loopback(SLMP_INFO *info, int enable)
4071 {
4072         if (enable) {
4073                 /* MD2 (Mode Register 2)
4074                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4075                  */
4076                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4077
4078                 /* degate external TxC clock source */
4079                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4080                 write_control_reg(info);
4081
4082                 /* RXS/TXS (Rx/Tx clock source)
4083                  * 07      Reserved, must be 0
4084                  * 06..04  Clock Source, 100=BRG
4085                  * 03..00  Clock Divisor, 0000=1
4086                  */
4087                 write_reg(info, RXS, 0x40);
4088                 write_reg(info, TXS, 0x40);
4089
4090         } else {
4091                 /* MD2 (Mode Register 2)
4092                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4093                  */
4094                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4095
4096                 /* RXS/TXS (Rx/Tx clock source)
4097                  * 07      Reserved, must be 0
4098                  * 06..04  Clock Source, 000=RxC/TxC Pin
4099                  * 03..00  Clock Divisor, 0000=1
4100                  */
4101                 write_reg(info, RXS, 0x00);
4102                 write_reg(info, TXS, 0x00);
4103         }
4104
4105         /* set LinkSpeed if available, otherwise default to 2Mbps */
4106         if (info->params.clock_speed)
4107                 set_rate(info, info->params.clock_speed);
4108         else
4109                 set_rate(info, 3686400);
4110 }
4111
4112 /* Set the baud rate register to the desired speed
4113  *
4114  *      data_rate       data rate of clock in bits per second
4115  *                      A data rate of 0 disables the AUX clock.
4116  */
4117 static void set_rate( SLMP_INFO *info, u32 data_rate )
4118 {
4119         u32 TMCValue;
4120         unsigned char BRValue;
4121         u32 Divisor=0;
4122
4123         /* fBRG = fCLK/(TMC * 2^BR)
4124          */
4125         if (data_rate != 0) {
4126                 Divisor = 14745600/data_rate;
4127                 if (!Divisor)
4128                         Divisor = 1;
4129
4130                 TMCValue = Divisor;
4131
4132                 BRValue = 0;
4133                 if (TMCValue != 1 && TMCValue != 2) {
4134                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4135                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4136                          * 50/50 duty cycle.
4137                          */
4138                         BRValue = 1;
4139                         TMCValue >>= 1;
4140                 }
4141
4142                 /* while TMCValue is too big for TMC register, divide
4143                  * by 2 and increment BR exponent.
4144                  */
4145                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4146                         TMCValue >>= 1;
4147
4148                 write_reg(info, TXS,
4149                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4150                 write_reg(info, RXS,
4151                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4152                 write_reg(info, TMC, (unsigned char)TMCValue);
4153         }
4154         else {
4155                 write_reg(info, TXS,0);
4156                 write_reg(info, RXS,0);
4157                 write_reg(info, TMC, 0);
4158         }
4159 }
4160
4161 /* Disable receiver
4162  */
4163 static void rx_stop(SLMP_INFO *info)
4164 {
4165         if (debug_level >= DEBUG_LEVEL_ISR)
4166                 printk("%s(%d):%s rx_stop()\n",
4167                          __FILE__,__LINE__, info->device_name );
4168
4169         write_reg(info, CMD, RXRESET);
4170
4171         info->ie0_value &= ~RXRDYE;
4172         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4173
4174         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4175         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4176         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4177
4178         info->rx_enabled = false;
4179         info->rx_overflow = false;
4180 }
4181
4182 /* enable the receiver
4183  */
4184 static void rx_start(SLMP_INFO *info)
4185 {
4186         int i;
4187
4188         if (debug_level >= DEBUG_LEVEL_ISR)
4189                 printk("%s(%d):%s rx_start()\n",
4190                          __FILE__,__LINE__, info->device_name );
4191
4192         write_reg(info, CMD, RXRESET);
4193
4194         if ( info->params.mode == MGSL_MODE_HDLC ) {
4195                 /* HDLC, disabe IRQ on rxdata */
4196                 info->ie0_value &= ~RXRDYE;
4197                 write_reg(info, IE0, info->ie0_value);
4198
4199                 /* Reset all Rx DMA buffers and program rx dma */
4200                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4201                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4202
4203                 for (i = 0; i < info->rx_buf_count; i++) {
4204                         info->rx_buf_list[i].status = 0xff;
4205
4206                         // throttle to 4 shared memory writes at a time to prevent
4207                         // hogging local bus (keep latency time for DMA requests low).
4208                         if (!(i % 4))
4209                                 read_status_reg(info);
4210                 }
4211                 info->current_rx_buf = 0;
4212
4213                 /* set current/1st descriptor address */
4214                 write_reg16(info, RXDMA + CDA,
4215                         info->rx_buf_list_ex[0].phys_entry);
4216
4217                 /* set new last rx descriptor address */
4218                 write_reg16(info, RXDMA + EDA,
4219                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4220
4221                 /* set buffer length (shared by all rx dma data buffers) */
4222                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4223
4224                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4225                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4226         } else {
4227                 /* async, enable IRQ on rxdata */
4228                 info->ie0_value |= RXRDYE;
4229                 write_reg(info, IE0, info->ie0_value);
4230         }
4231
4232         write_reg(info, CMD, RXENABLE);
4233
4234         info->rx_overflow = false;
4235         info->rx_enabled = true;
4236 }
4237
4238 /* Enable the transmitter and send a transmit frame if
4239  * one is loaded in the DMA buffers.
4240  */
4241 static void tx_start(SLMP_INFO *info)
4242 {
4243         if (debug_level >= DEBUG_LEVEL_ISR)
4244                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4245                          __FILE__,__LINE__, info->device_name,info->tx_count );
4246
4247         if (!info->tx_enabled ) {
4248                 write_reg(info, CMD, TXRESET);
4249                 write_reg(info, CMD, TXENABLE);
4250                 info->tx_enabled = true;
4251         }
4252
4253         if ( info->tx_count ) {
4254
4255                 /* If auto RTS enabled and RTS is inactive, then assert */
4256                 /* RTS and set a flag indicating that the driver should */
4257                 /* negate RTS when the transmission completes. */
4258
4259                 info->drop_rts_on_tx_done = false;
4260
4261                 if (info->params.mode != MGSL_MODE_ASYNC) {
4262
4263                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4264                                 get_signals( info );
4265                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4266                                         info->serial_signals |= SerialSignal_RTS;
4267                                         set_signals( info );
4268                                         info->drop_rts_on_tx_done = true;
4269                                 }
4270                         }
4271
4272                         write_reg16(info, TRC0,
4273                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4274
4275                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4276                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4277
4278                         /* set TX CDA (current descriptor address) */
4279                         write_reg16(info, TXDMA + CDA,
4280                                 info->tx_buf_list_ex[0].phys_entry);
4281
4282                         /* set TX EDA (last descriptor address) */
4283                         write_reg16(info, TXDMA + EDA,
4284                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4285
4286                         /* enable underrun IRQ */
4287                         info->ie1_value &= ~IDLE;
4288                         info->ie1_value |= UDRN;
4289                         write_reg(info, IE1, info->ie1_value);
4290                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4291
4292                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4293                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4294
4295                         mod_timer(&info->tx_timer, jiffies +
4296                                         msecs_to_jiffies(5000));
4297                 }
4298                 else {
4299                         tx_load_fifo(info);
4300                         /* async, enable IRQ on txdata */
4301                         info->ie0_value |= TXRDYE;
4302                         write_reg(info, IE0, info->ie0_value);
4303                 }
4304
4305                 info->tx_active = true;
4306         }
4307 }
4308
4309 /* stop the transmitter and DMA
4310  */
4311 static void tx_stop( SLMP_INFO *info )
4312 {
4313         if (debug_level >= DEBUG_LEVEL_ISR)
4314                 printk("%s(%d):%s tx_stop()\n",
4315                          __FILE__,__LINE__, info->device_name );
4316
4317         del_timer(&info->tx_timer);
4318
4319         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4320         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4321
4322         write_reg(info, CMD, TXRESET);
4323
4324         info->ie1_value &= ~(UDRN + IDLE);
4325         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4326         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4327
4328         info->ie0_value &= ~TXRDYE;
4329         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4330
4331         info->tx_enabled = false;
4332         info->tx_active = false;
4333 }
4334
4335 /* Fill the transmit FIFO until the FIFO is full or
4336  * there is no more data to load.
4337  */
4338 static void tx_load_fifo(SLMP_INFO *info)
4339 {
4340         u8 TwoBytes[2];
4341
4342         /* do nothing is now tx data available and no XON/XOFF pending */
4343
4344         if ( !info->tx_count && !info->x_char )
4345                 return;
4346
4347         /* load the Transmit FIFO until FIFOs full or all data sent */
4348
4349         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4350
4351                 /* there is more space in the transmit FIFO and */
4352                 /* there is more data in transmit buffer */
4353
4354                 if ( (info->tx_count > 1) && !info->x_char ) {
4355                         /* write 16-bits */
4356                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4357                         if (info->tx_get >= info->max_frame_size)
4358                                 info->tx_get -= info->max_frame_size;
4359                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4360                         if (info->tx_get >= info->max_frame_size)
4361                                 info->tx_get -= info->max_frame_size;
4362
4363                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4364
4365                         info->tx_count -= 2;
4366                         info->icount.tx += 2;
4367                 } else {
4368                         /* only 1 byte left to transmit or 1 FIFO slot left */
4369
4370                         if (info->x_char) {
4371                                 /* transmit pending high priority char */
4372                                 write_reg(info, TRB, info->x_char);
4373                                 info->x_char = 0;
4374                         } else {
4375                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4376                                 if (info->tx_get >= info->max_frame_size)
4377                                         info->tx_get -= info->max_frame_size;
4378                                 info->tx_count--;
4379                         }
4380                         info->icount.tx++;
4381                 }
4382         }
4383 }
4384
4385 /* Reset a port to a known state
4386  */
4387 static void reset_port(SLMP_INFO *info)
4388 {
4389         if (info->sca_base) {
4390
4391                 tx_stop(info);
4392                 rx_stop(info);
4393
4394                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4395                 set_signals(info);
4396
4397                 /* disable all port interrupts */
4398                 info->ie0_value = 0;
4399                 info->ie1_value = 0;
4400                 info->ie2_value = 0;
4401                 write_reg(info, IE0, info->ie0_value);
4402                 write_reg(info, IE1, info->ie1_value);
4403                 write_reg(info, IE2, info->ie2_value);
4404
4405                 write_reg(info, CMD, CHRESET);
4406         }
4407 }
4408
4409 /* Reset all the ports to a known state.
4410  */
4411 static void reset_adapter(SLMP_INFO *info)
4412 {
4413         int i;
4414
4415         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4416                 if (info->port_array[i])
4417                         reset_port(info->port_array[i]);
4418         }
4419 }
4420
4421 /* Program port for asynchronous communications.
4422  */
4423 static void async_mode(SLMP_INFO *info)
4424 {
4425
4426         unsigned char RegValue;
4427
4428         tx_stop(info);
4429         rx_stop(info);
4430
4431         /* MD0, Mode Register 0
4432          *
4433          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4434          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4435          * 03      Reserved, must be 0
4436          * 02      CRCCC, CRC Calculation, 0=disabled
4437          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4438          *
4439          * 0000 0000
4440          */
4441         RegValue = 0x00;
4442         if (info->params.stop_bits != 1)
4443                 RegValue |= BIT1;
4444         write_reg(info, MD0, RegValue);
4445
4446         /* MD1, Mode Register 1
4447          *
4448          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4449          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4450          * 03..02  RXCHR<1..0>, rx char size
4451          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4452          *
4453          * 0100 0000
4454          */
4455         RegValue = 0x40;
4456         switch (info->params.data_bits) {
4457         case 7: RegValue |= BIT4 + BIT2; break;
4458         case 6: RegValue |= BIT5 + BIT3; break;
4459         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4460         }
4461         if (info->params.parity != ASYNC_PARITY_NONE) {
4462                 RegValue |= BIT1;
4463                 if (info->params.parity == ASYNC_PARITY_ODD)
4464                         RegValue |= BIT0;
4465         }
4466         write_reg(info, MD1, RegValue);
4467
4468         /* MD2, Mode Register 2
4469          *
4470          * 07..02  Reserved, must be 0
4471          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4472          *
4473          * 0000 0000
4474          */
4475         RegValue = 0x00;
4476         if (info->params.loopback)
4477                 RegValue |= (BIT1 + BIT0);
4478         write_reg(info, MD2, RegValue);
4479
4480         /* RXS, Receive clock source
4481          *
4482          * 07      Reserved, must be 0
4483          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4484          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4485          */
4486         RegValue=BIT6;
4487         write_reg(info, RXS, RegValue);
4488
4489         /* TXS, Transmit clock source
4490          *
4491          * 07      Reserved, must be 0
4492          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4493          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4494          */
4495         RegValue=BIT6;
4496         write_reg(info, TXS, RegValue);
4497
4498         /* Control Register
4499          *
4500          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4501          */
4502         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4503         write_control_reg(info);
4504
4505         tx_set_idle(info);
4506
4507         /* RRC Receive Ready Control 0
4508          *
4509          * 07..05  Reserved, must be 0
4510          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4511          */
4512         write_reg(info, RRC, 0x00);
4513
4514         /* TRC0 Transmit Ready Control 0
4515          *
4516          * 07..05  Reserved, must be 0
4517          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4518          */
4519         write_reg(info, TRC0, 0x10);
4520
4521         /* TRC1 Transmit Ready Control 1
4522          *
4523          * 07..05  Reserved, must be 0
4524          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4525          */
4526         write_reg(info, TRC1, 0x1e);
4527
4528         /* CTL, MSCI control register
4529          *
4530          * 07..06  Reserved, set to 0
4531          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4532          * 04      IDLC, idle control, 0=mark 1=idle register
4533          * 03      BRK, break, 0=off 1 =on (async)
4534          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4535          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4536          * 00      RTS, RTS output control, 0=active 1=inactive
4537          *
4538          * 0001 0001
4539          */
4540         RegValue = 0x10;
4541         if (!(info->serial_signals & SerialSignal_RTS))
4542                 RegValue |= 0x01;
4543         write_reg(info, CTL, RegValue);
4544
4545         /* enable status interrupts */
4546         info->ie0_value |= TXINTE + RXINTE;
4547         write_reg(info, IE0, info->ie0_value);
4548
4549         /* enable break detect interrupt */
4550         info->ie1_value = BRKD;
4551         write_reg(info, IE1, info->ie1_value);
4552
4553         /* enable rx overrun interrupt */
4554         info->ie2_value = OVRN;
4555         write_reg(info, IE2, info->ie2_value);
4556
4557         set_rate( info, info->params.data_rate * 16 );
4558 }
4559
4560 /* Program the SCA for HDLC communications.
4561  */
4562 static void hdlc_mode(SLMP_INFO *info)
4563 {
4564         unsigned char RegValue;
4565         u32 DpllDivisor;
4566
4567         // Can't use DPLL because SCA outputs recovered clock on RxC when
4568         // DPLL mode selected. This causes output contention with RxC receiver.
4569         // Use of DPLL would require external hardware to disable RxC receiver
4570         // when DPLL mode selected.
4571         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4572
4573         /* disable DMA interrupts */
4574         write_reg(info, TXDMA + DIR, 0);
4575         write_reg(info, RXDMA + DIR, 0);
4576
4577         /* MD0, Mode Register 0
4578          *
4579          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4580          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4581          * 03      Reserved, must be 0
4582          * 02      CRCCC, CRC Calculation, 1=enabled
4583          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4584          * 00      CRC0, CRC initial value, 1 = all 1s
4585          *
4586          * 1000 0001
4587          */
4588         RegValue = 0x81;
4589         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4590                 RegValue |= BIT4;
4591         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4592                 RegValue |= BIT4;
4593         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4594                 RegValue |= BIT2 + BIT1;
4595         write_reg(info, MD0, RegValue);
4596
4597         /* MD1, Mode Register 1
4598          *
4599          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4600          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4601          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4602          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4603          *
4604          * 0000 0000
4605          */
4606         RegValue = 0x00;
4607         write_reg(info, MD1, RegValue);
4608
4609         /* MD2, Mode Register 2
4610          *
4611          * 07      NRZFM, 0=NRZ, 1=FM
4612          * 06..05  CODE<1..0> Encoding, 00=NRZ
4613          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4614          * 02      Reserved, must be 0
4615          * 01..00  CNCT<1..0> Channel connection, 0=normal
4616          *
4617          * 0000 0000
4618          */
4619         RegValue = 0x00;
4620         switch(info->params.encoding) {
4621         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4622         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4623         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4624         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4625 #if 0
4626         case HDLC_ENCODING_NRZB:                                        /* not supported */
4627         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4628         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4629 #endif
4630         }
4631         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4632                 DpllDivisor = 16;
4633                 RegValue |= BIT3;
4634         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4635                 DpllDivisor = 8;
4636         } else {
4637                 DpllDivisor = 32;
4638                 RegValue |= BIT4;
4639         }
4640         write_reg(info, MD2, RegValue);
4641
4642
4643         /* RXS, Receive clock source
4644          *
4645          * 07      Reserved, must be 0
4646          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4647          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4648          */
4649         RegValue=0;
4650         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4651                 RegValue |= BIT6;
4652         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4653                 RegValue |= BIT6 + BIT5;
4654         write_reg(info, RXS, RegValue);
4655
4656         /* TXS, Transmit clock source
4657          *
4658          * 07      Reserved, must be 0
4659          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4660          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4661          */
4662         RegValue=0;
4663         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4664                 RegValue |= BIT6;
4665         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4666                 RegValue |= BIT6 + BIT5;
4667         write_reg(info, TXS, RegValue);
4668
4669         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4670                 set_rate(info, info->params.clock_speed * DpllDivisor);
4671         else
4672                 set_rate(info, info->params.clock_speed);
4673
4674         /* GPDATA (General Purpose I/O Data Register)
4675          *
4676          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4677          */
4678         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4679                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4680         else
4681                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4682         write_control_reg(info);
4683
4684         /* RRC Receive Ready Control 0
4685          *
4686          * 07..05  Reserved, must be 0
4687          * 04..00  RRC<4..0> Rx FIFO trigger active
4688          */
4689         write_reg(info, RRC, rx_active_fifo_level);
4690
4691         /* TRC0 Transmit Ready Control 0
4692          *
4693          * 07..05  Reserved, must be 0
4694          * 04..00  TRC<4..0> Tx FIFO trigger active
4695          */
4696         write_reg(info, TRC0, tx_active_fifo_level);
4697
4698         /* TRC1 Transmit Ready Control 1
4699          *
4700          * 07..05  Reserved, must be 0
4701          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4702          */
4703         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4704
4705         /* DMR, DMA Mode Register
4706          *
4707          * 07..05  Reserved, must be 0
4708          * 04      TMOD, Transfer Mode: 1=chained-block
4709          * 03      Reserved, must be 0
4710          * 02      NF, Number of Frames: 1=multi-frame
4711          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4712          * 00      Reserved, must be 0
4713          *
4714          * 0001 0100
4715          */
4716         write_reg(info, TXDMA + DMR, 0x14);
4717         write_reg(info, RXDMA + DMR, 0x14);
4718
4719         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4720         write_reg(info, RXDMA + CPB,
4721                 (unsigned char)(info->buffer_list_phys >> 16));
4722
4723         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4724         write_reg(info, TXDMA + CPB,
4725                 (unsigned char)(info->buffer_list_phys >> 16));
4726
4727         /* enable status interrupts. other code enables/disables
4728          * the individual sources for these two interrupt classes.
4729          */
4730         info->ie0_value |= TXINTE + RXINTE;
4731         write_reg(info, IE0, info->ie0_value);
4732
4733         /* CTL, MSCI control register
4734          *
4735          * 07..06  Reserved, set to 0
4736          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4737          * 04      IDLC, idle control, 0=mark 1=idle register
4738          * 03      BRK, break, 0=off 1 =on (async)
4739          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4740          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4741          * 00      RTS, RTS output control, 0=active 1=inactive
4742          *
4743          * 0001 0001
4744          */
4745         RegValue = 0x10;
4746         if (!(info->serial_signals & SerialSignal_RTS))
4747                 RegValue |= 0x01;
4748         write_reg(info, CTL, RegValue);
4749
4750         /* preamble not supported ! */
4751
4752         tx_set_idle(info);
4753         tx_stop(info);
4754         rx_stop(info);
4755
4756         set_rate(info, info->params.clock_speed);
4757
4758         if (info->params.loopback)
4759                 enable_loopback(info,1);
4760 }
4761
4762 /* Set the transmit HDLC idle mode
4763  */
4764 static void tx_set_idle(SLMP_INFO *info)
4765 {
4766         unsigned char RegValue = 0xff;
4767
4768         /* Map API idle mode to SCA register bits */
4769         switch(info->idle_mode) {
4770         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4771         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4772         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4773         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4774         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4775         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4776         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4777         }
4778
4779         write_reg(info, IDL, RegValue);
4780 }
4781
4782 /* Query the adapter for the state of the V24 status (input) signals.
4783  */
4784 static void get_signals(SLMP_INFO *info)
4785 {
4786         u16 status = read_reg(info, SR3);
4787         u16 gpstatus = read_status_reg(info);
4788         u16 testbit;
4789
4790         /* clear all serial signals except DTR and RTS */
4791         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4792
4793         /* set serial signal bits to reflect MISR */
4794
4795         if (!(status & BIT3))
4796                 info->serial_signals |= SerialSignal_CTS;
4797
4798         if ( !(status & BIT2))
4799                 info->serial_signals |= SerialSignal_DCD;
4800
4801         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4802         if (!(gpstatus & testbit))
4803                 info->serial_signals |= SerialSignal_RI;
4804
4805         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4806         if (!(gpstatus & testbit))
4807                 info->serial_signals |= SerialSignal_DSR;
4808 }
4809
4810 /* Set the state of DTR and RTS based on contents of
4811  * serial_signals member of device context.
4812  */
4813 static void set_signals(SLMP_INFO *info)
4814 {
4815         unsigned char RegValue;
4816         u16 EnableBit;
4817
4818         RegValue = read_reg(info, CTL);
4819         if (info->serial_signals & SerialSignal_RTS)
4820                 RegValue &= ~BIT0;
4821         else
4822                 RegValue |= BIT0;
4823         write_reg(info, CTL, RegValue);
4824
4825         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4826         EnableBit = BIT1 << (info->port_num*2);
4827         if (info->serial_signals & SerialSignal_DTR)
4828                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4829         else
4830                 info->port_array[0]->ctrlreg_value |= EnableBit;
4831         write_control_reg(info);
4832 }
4833
4834 /*******************/
4835 /* DMA Buffer Code */
4836 /*******************/
4837
4838 /* Set the count for all receive buffers to SCABUFSIZE
4839  * and set the current buffer to the first buffer. This effectively
4840  * makes all buffers free and discards any data in buffers.
4841  */
4842 static void rx_reset_buffers(SLMP_INFO *info)
4843 {
4844         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4845 }
4846
4847 /* Free the buffers used by a received frame
4848  *
4849  * info   pointer to device instance data
4850  * first  index of 1st receive buffer of frame
4851  * last   index of last receive buffer of frame
4852  */
4853 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4854 {
4855         bool done = false;
4856
4857         while(!done) {
4858                 /* reset current buffer for reuse */
4859                 info->rx_buf_list[first].status = 0xff;
4860
4861                 if (first == last) {
4862                         done = true;
4863                         /* set new last rx descriptor address */
4864                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4865                 }
4866
4867                 first++;
4868                 if (first == info->rx_buf_count)
4869                         first = 0;
4870         }
4871
4872         /* set current buffer to next buffer after last buffer of frame */
4873         info->current_rx_buf = first;
4874 }
4875
4876 /* Return a received frame from the receive DMA buffers.
4877  * Only frames received without errors are returned.
4878  *
4879  * Return Value:        true if frame returned, otherwise false
4880  */
4881 static bool rx_get_frame(SLMP_INFO *info)
4882 {
4883         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4884         unsigned short status;
4885         unsigned int framesize = 0;
4886         bool ReturnCode = false;
4887         unsigned long flags;
4888         struct tty_struct *tty = info->tty;
4889         unsigned char addr_field = 0xff;
4890         SCADESC *desc;
4891         SCADESC_EX *desc_ex;
4892
4893 CheckAgain:
4894         /* assume no frame returned, set zero length */
4895         framesize = 0;
4896         addr_field = 0xff;
4897
4898         /*
4899          * current_rx_buf points to the 1st buffer of the next available
4900          * receive frame. To find the last buffer of the frame look for
4901          * a non-zero status field in the buffer entries. (The status
4902          * field is set by the 16C32 after completing a receive frame.
4903          */
4904         StartIndex = EndIndex = info->current_rx_buf;
4905
4906         for ( ;; ) {
4907                 desc = &info->rx_buf_list[EndIndex];
4908                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4909
4910                 if (desc->status == 0xff)
4911                         goto Cleanup;   /* current desc still in use, no frames available */
4912
4913                 if (framesize == 0 && info->params.addr_filter != 0xff)
4914                         addr_field = desc_ex->virt_addr[0];
4915
4916                 framesize += desc->length;
4917
4918                 /* Status != 0 means last buffer of frame */
4919                 if (desc->status)
4920                         break;
4921
4922                 EndIndex++;
4923                 if (EndIndex == info->rx_buf_count)
4924                         EndIndex = 0;
4925
4926                 if (EndIndex == info->current_rx_buf) {
4927                         /* all buffers have been 'used' but none mark      */
4928                         /* the end of a frame. Reset buffers and receiver. */
4929                         if ( info->rx_enabled ){
4930                                 spin_lock_irqsave(&info->lock,flags);
4931                                 rx_start(info);
4932                                 spin_unlock_irqrestore(&info->lock,flags);
4933                         }
4934                         goto Cleanup;
4935                 }
4936
4937         }
4938
4939         /* check status of receive frame */
4940
4941         /* frame status is byte stored after frame data
4942          *
4943          * 7 EOM (end of msg), 1 = last buffer of frame
4944          * 6 Short Frame, 1 = short frame
4945          * 5 Abort, 1 = frame aborted
4946          * 4 Residue, 1 = last byte is partial
4947          * 3 Overrun, 1 = overrun occurred during frame reception
4948          * 2 CRC,     1 = CRC error detected
4949          *
4950          */
4951         status = desc->status;
4952
4953         /* ignore CRC bit if not using CRC (bit is undefined) */
4954         /* Note:CRC is not save to data buffer */
4955         if (info->params.crc_type == HDLC_CRC_NONE)
4956                 status &= ~BIT2;
4957
4958         if (framesize == 0 ||
4959                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4960                 /* discard 0 byte frames, this seems to occur sometime
4961                  * when remote is idling flags.
4962                  */
4963                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4964                 goto CheckAgain;
4965         }
4966
4967         if (framesize < 2)
4968                 status |= BIT6;
4969
4970         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4971                 /* received frame has errors,
4972                  * update counts and mark frame size as 0
4973                  */
4974                 if (status & BIT6)
4975                         info->icount.rxshort++;
4976                 else if (status & BIT5)
4977                         info->icount.rxabort++;
4978                 else if (status & BIT3)
4979                         info->icount.rxover++;
4980                 else
4981                         info->icount.rxcrc++;
4982
4983                 framesize = 0;
4984 #if SYNCLINK_GENERIC_HDLC
4985                 {
4986                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4987                         stats->rx_errors++;
4988                         stats->rx_frame_errors++;
4989                 }
4990 #endif
4991         }
4992
4993         if ( debug_level >= DEBUG_LEVEL_BH )
4994                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4995                         __FILE__,__LINE__,info->device_name,status,framesize);
4996
4997         if ( debug_level >= DEBUG_LEVEL_DATA )
4998                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4999                         min_t(int, framesize,SCABUFSIZE),0);
5000
5001         if (framesize) {
5002                 if (framesize > info->max_frame_size)
5003                         info->icount.rxlong++;
5004                 else {
5005                         /* copy dma buffer(s) to contiguous intermediate buffer */
5006                         int copy_count = framesize;
5007                         int index = StartIndex;
5008                         unsigned char *ptmp = info->tmp_rx_buf;
5009                         info->tmp_rx_buf_count = framesize;
5010
5011                         info->icount.rxok++;
5012
5013                         while(copy_count) {
5014                                 int partial_count = min(copy_count,SCABUFSIZE);
5015                                 memcpy( ptmp,
5016                                         info->rx_buf_list_ex[index].virt_addr,
5017                                         partial_count );
5018                                 ptmp += partial_count;
5019                                 copy_count -= partial_count;
5020
5021                                 if ( ++index == info->rx_buf_count )
5022                                         index = 0;
5023                         }
5024
5025 #if SYNCLINK_GENERIC_HDLC
5026                         if (info->netcount)
5027                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5028                         else
5029 #endif
5030                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5031                                                   info->flag_buf, framesize);
5032                 }
5033         }
5034         /* Free the buffers used by this frame. */
5035         rx_free_frame_buffers( info, StartIndex, EndIndex );
5036
5037         ReturnCode = true;
5038
5039 Cleanup:
5040         if ( info->rx_enabled && info->rx_overflow ) {
5041                 /* Receiver is enabled, but needs to restarted due to
5042                  * rx buffer overflow. If buffers are empty, restart receiver.
5043                  */
5044                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5045                         spin_lock_irqsave(&info->lock,flags);
5046                         rx_start(info);
5047                         spin_unlock_irqrestore(&info->lock,flags);
5048                 }
5049         }
5050
5051         return ReturnCode;
5052 }
5053
5054 /* load the transmit DMA buffer with data
5055  */
5056 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5057 {
5058         unsigned short copy_count;
5059         unsigned int i = 0;
5060         SCADESC *desc;
5061         SCADESC_EX *desc_ex;
5062
5063         if ( debug_level >= DEBUG_LEVEL_DATA )
5064                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5065
5066         /* Copy source buffer to one or more DMA buffers, starting with
5067          * the first transmit dma buffer.
5068          */
5069         for(i=0;;)
5070         {
5071                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5072
5073                 desc = &info->tx_buf_list[i];
5074                 desc_ex = &info->tx_buf_list_ex[i];
5075
5076                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5077
5078                 desc->length = copy_count;
5079                 desc->status = 0;
5080
5081                 buf += copy_count;
5082                 count -= copy_count;
5083
5084                 if (!count)
5085                         break;
5086
5087                 i++;
5088                 if (i >= info->tx_buf_count)
5089                         i = 0;
5090         }
5091
5092         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5093         info->last_tx_buf = ++i;
5094 }
5095
5096 static bool register_test(SLMP_INFO *info)
5097 {
5098         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5099         static unsigned int count = ARRAY_SIZE(testval);
5100         unsigned int i;
5101         bool rc = true;
5102         unsigned long flags;
5103
5104         spin_lock_irqsave(&info->lock,flags);
5105         reset_port(info);
5106
5107         /* assume failure */
5108         info->init_error = DiagStatus_AddressFailure;
5109
5110         /* Write bit patterns to various registers but do it out of */
5111         /* sync, then read back and verify values. */
5112
5113         for (i = 0 ; i < count ; i++) {
5114                 write_reg(info, TMC, testval[i]);
5115                 write_reg(info, IDL, testval[(i+1)%count]);
5116                 write_reg(info, SA0, testval[(i+2)%count]);
5117                 write_reg(info, SA1, testval[(i+3)%count]);
5118
5119                 if ( (read_reg(info, TMC) != testval[i]) ||
5120                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5121                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5122                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5123                 {
5124                         rc = false;
5125                         break;
5126                 }
5127         }
5128
5129         reset_port(info);
5130         spin_unlock_irqrestore(&info->lock,flags);
5131
5132         return rc;
5133 }
5134
5135 static bool irq_test(SLMP_INFO *info)
5136 {
5137         unsigned long timeout;
5138         unsigned long flags;
5139
5140         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5141
5142         spin_lock_irqsave(&info->lock,flags);
5143         reset_port(info);
5144
5145         /* assume failure */
5146         info->init_error = DiagStatus_IrqFailure;
5147         info->irq_occurred = false;
5148
5149         /* setup timer0 on SCA0 to interrupt */
5150
5151         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5152         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5153
5154         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5155         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5156
5157
5158         /* TMCS, Timer Control/Status Register
5159          *
5160          * 07      CMF, Compare match flag (read only) 1=match
5161          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5162          * 05      Reserved, must be 0
5163          * 04      TME, Timer Enable
5164          * 03..00  Reserved, must be 0
5165          *
5166          * 0101 0000
5167          */
5168         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5169
5170         spin_unlock_irqrestore(&info->lock,flags);
5171
5172         timeout=100;
5173         while( timeout-- && !info->irq_occurred ) {
5174                 msleep_interruptible(10);
5175         }
5176
5177         spin_lock_irqsave(&info->lock,flags);
5178         reset_port(info);
5179         spin_unlock_irqrestore(&info->lock,flags);
5180
5181         return info->irq_occurred;
5182 }
5183
5184 /* initialize individual SCA device (2 ports)
5185  */
5186 static bool sca_init(SLMP_INFO *info)
5187 {
5188         /* set wait controller to single mem partition (low), no wait states */
5189         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5190         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5191         write_reg(info, WCRL, 0);       /* wait controller low range */
5192         write_reg(info, WCRM, 0);       /* wait controller mid range */
5193         write_reg(info, WCRH, 0);       /* wait controller high range */
5194
5195         /* DPCR, DMA Priority Control
5196          *
5197          * 07..05  Not used, must be 0
5198          * 04      BRC, bus release condition: 0=all transfers complete
5199          * 03      CCC, channel change condition: 0=every cycle
5200          * 02..00  PR<2..0>, priority 100=round robin
5201          *
5202          * 00000100 = 0x04
5203          */
5204         write_reg(info, DPCR, dma_priority);
5205
5206         /* DMA Master Enable, BIT7: 1=enable all channels */
5207         write_reg(info, DMER, 0x80);
5208
5209         /* enable all interrupt classes */
5210         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5211         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5212         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5213
5214         /* ITCR, interrupt control register
5215          * 07      IPC, interrupt priority, 0=MSCI->DMA
5216          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5217          * 04      VOS, Vector Output, 0=unmodified vector
5218          * 03..00  Reserved, must be 0
5219          */
5220         write_reg(info, ITCR, 0);
5221
5222         return true;
5223 }
5224
5225 /* initialize adapter hardware
5226  */
5227 static bool init_adapter(SLMP_INFO *info)
5228 {
5229         int i;
5230
5231         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5232         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5233         u32 readval;
5234
5235         info->misc_ctrl_value |= BIT30;
5236         *MiscCtrl = info->misc_ctrl_value;
5237
5238         /*
5239          * Force at least 170ns delay before clearing
5240          * reset bit. Each read from LCR takes at least
5241          * 30ns so 10 times for 300ns to be safe.
5242          */
5243         for(i=0;i<10;i++)
5244                 readval = *MiscCtrl;
5245
5246         info->misc_ctrl_value &= ~BIT30;
5247         *MiscCtrl = info->misc_ctrl_value;
5248
5249         /* init control reg (all DTRs off, all clksel=input) */
5250         info->ctrlreg_value = 0xaa;
5251         write_control_reg(info);
5252
5253         {
5254                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5255                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5256
5257                 switch(read_ahead_count)
5258                 {
5259                 case 16:
5260                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5261                         break;
5262                 case 8:
5263                         lcr1_brdr_value |= BIT5 + BIT4;
5264                         break;
5265                 case 4:
5266                         lcr1_brdr_value |= BIT5 + BIT3;
5267                         break;
5268                 case 0:
5269                         lcr1_brdr_value |= BIT5;
5270                         break;
5271                 }
5272
5273                 *LCR1BRDR = lcr1_brdr_value;
5274                 *MiscCtrl = misc_ctrl_value;
5275         }
5276
5277         sca_init(info->port_array[0]);
5278         sca_init(info->port_array[2]);
5279
5280         return true;
5281 }
5282
5283 /* Loopback an HDLC frame to test the hardware
5284  * interrupt and DMA functions.
5285  */
5286 static bool loopback_test(SLMP_INFO *info)
5287 {
5288 #define TESTFRAMESIZE 20
5289
5290         unsigned long timeout;
5291         u16 count = TESTFRAMESIZE;
5292         unsigned char buf[TESTFRAMESIZE];
5293         bool rc = false;
5294         unsigned long flags;
5295
5296         struct tty_struct *oldtty = info->tty;
5297         u32 speed = info->params.clock_speed;
5298
5299         info->params.clock_speed = 3686400;
5300         info->tty = NULL;
5301
5302         /* assume failure */
5303         info->init_error = DiagStatus_DmaFailure;
5304
5305         /* build and send transmit frame */
5306         for (count = 0; count < TESTFRAMESIZE;++count)
5307                 buf[count] = (unsigned char)count;
5308
5309         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5310
5311         /* program hardware for HDLC and enabled receiver */
5312         spin_lock_irqsave(&info->lock,flags);
5313         hdlc_mode(info);
5314         enable_loopback(info,1);
5315         rx_start(info);
5316         info->tx_count = count;
5317         tx_load_dma_buffer(info,buf,count);
5318         tx_start(info);
5319         spin_unlock_irqrestore(&info->lock,flags);
5320
5321         /* wait for receive complete */
5322         /* Set a timeout for waiting for interrupt. */
5323         for ( timeout = 100; timeout; --timeout ) {
5324                 msleep_interruptible(10);
5325
5326                 if (rx_get_frame(info)) {
5327                         rc = true;
5328                         break;
5329                 }
5330         }
5331
5332         /* verify received frame length and contents */
5333         if (rc &&
5334             ( info->tmp_rx_buf_count != count ||
5335               memcmp(buf, info->tmp_rx_buf,count))) {
5336                 rc = false;
5337         }
5338
5339         spin_lock_irqsave(&info->lock,flags);
5340         reset_adapter(info);
5341         spin_unlock_irqrestore(&info->lock,flags);
5342
5343         info->params.clock_speed = speed;
5344         info->tty = oldtty;
5345
5346         return rc;
5347 }
5348
5349 /* Perform diagnostics on hardware
5350  */
5351 static int adapter_test( SLMP_INFO *info )
5352 {
5353         unsigned long flags;
5354         if ( debug_level >= DEBUG_LEVEL_INFO )
5355                 printk( "%s(%d):Testing device %s\n",
5356                         __FILE__,__LINE__,info->device_name );
5357
5358         spin_lock_irqsave(&info->lock,flags);
5359         init_adapter(info);
5360         spin_unlock_irqrestore(&info->lock,flags);
5361
5362         info->port_array[0]->port_count = 0;
5363
5364         if ( register_test(info->port_array[0]) &&
5365                 register_test(info->port_array[1])) {
5366
5367                 info->port_array[0]->port_count = 2;
5368
5369                 if ( register_test(info->port_array[2]) &&
5370                         register_test(info->port_array[3]) )
5371                         info->port_array[0]->port_count += 2;
5372         }
5373         else {
5374                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5375                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5376                 return -ENODEV;
5377         }
5378
5379         if ( !irq_test(info->port_array[0]) ||
5380                 !irq_test(info->port_array[1]) ||
5381                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5382                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5383                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5384                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5385                 return -ENODEV;
5386         }
5387
5388         if (!loopback_test(info->port_array[0]) ||
5389                 !loopback_test(info->port_array[1]) ||
5390                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5391                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5392                 printk( "%s(%d):DMA test failure for device %s\n",
5393                         __FILE__,__LINE__,info->device_name);
5394                 return -ENODEV;
5395         }
5396
5397         if ( debug_level >= DEBUG_LEVEL_INFO )
5398                 printk( "%s(%d):device %s passed diagnostics\n",
5399                         __FILE__,__LINE__,info->device_name );
5400
5401         info->port_array[0]->init_error = 0;
5402         info->port_array[1]->init_error = 0;
5403         if ( info->port_count > 2 ) {
5404                 info->port_array[2]->init_error = 0;
5405                 info->port_array[3]->init_error = 0;
5406         }
5407
5408         return 0;
5409 }
5410
5411 /* Test the shared memory on a PCI adapter.
5412  */
5413 static bool memory_test(SLMP_INFO *info)
5414 {
5415         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5416                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5417         unsigned long count = ARRAY_SIZE(testval);
5418         unsigned long i;
5419         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5420         unsigned long * addr = (unsigned long *)info->memory_base;
5421
5422         /* Test data lines with test pattern at one location. */
5423
5424         for ( i = 0 ; i < count ; i++ ) {
5425                 *addr = testval[i];
5426                 if ( *addr != testval[i] )
5427                         return false;
5428         }
5429
5430         /* Test address lines with incrementing pattern over */
5431         /* entire address range. */
5432
5433         for ( i = 0 ; i < limit ; i++ ) {
5434                 *addr = i * 4;
5435                 addr++;
5436         }
5437
5438         addr = (unsigned long *)info->memory_base;
5439
5440         for ( i = 0 ; i < limit ; i++ ) {
5441                 if ( *addr != i * 4 )
5442                         return false;
5443                 addr++;
5444         }
5445
5446         memset( info->memory_base, 0, SCA_MEM_SIZE );
5447         return true;
5448 }
5449
5450 /* Load data into PCI adapter shared memory.
5451  *
5452  * The PCI9050 releases control of the local bus
5453  * after completing the current read or write operation.
5454  *
5455  * While the PCI9050 write FIFO not empty, the
5456  * PCI9050 treats all of the writes as a single transaction
5457  * and does not release the bus. This causes DMA latency problems
5458  * at high speeds when copying large data blocks to the shared memory.
5459  *
5460  * This function breaks a write into multiple transations by
5461  * interleaving a read which flushes the write FIFO and 'completes'
5462  * the write transation. This allows any pending DMA request to gain control
5463  * of the local bus in a timely fasion.
5464  */
5465 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5466 {
5467         /* A load interval of 16 allows for 4 32-bit writes at */
5468         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5469
5470         unsigned short interval = count / sca_pci_load_interval;
5471         unsigned short i;
5472
5473         for ( i = 0 ; i < interval ; i++ )
5474         {
5475                 memcpy(dest, src, sca_pci_load_interval);
5476                 read_status_reg(info);
5477                 dest += sca_pci_load_interval;
5478                 src += sca_pci_load_interval;
5479         }
5480
5481         memcpy(dest, src, count % sca_pci_load_interval);
5482 }
5483
5484 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5485 {
5486         int i;
5487         int linecount;
5488         if (xmit)
5489                 printk("%s tx data:\n",info->device_name);
5490         else
5491                 printk("%s rx data:\n",info->device_name);
5492
5493         while(count) {
5494                 if (count > 16)
5495                         linecount = 16;
5496                 else
5497                         linecount = count;
5498
5499                 for(i=0;i<linecount;i++)
5500                         printk("%02X ",(unsigned char)data[i]);
5501                 for(;i<17;i++)
5502                         printk("   ");
5503                 for(i=0;i<linecount;i++) {
5504                         if (data[i]>=040 && data[i]<=0176)
5505                                 printk("%c",data[i]);
5506                         else
5507                                 printk(".");
5508                 }
5509                 printk("\n");
5510
5511                 data  += linecount;
5512                 count -= linecount;
5513         }
5514 }       /* end of trace_block() */
5515
5516 /* called when HDLC frame times out
5517  * update stats and do tx completion processing
5518  */
5519 static void tx_timeout(unsigned long context)
5520 {
5521         SLMP_INFO *info = (SLMP_INFO*)context;
5522         unsigned long flags;
5523
5524         if ( debug_level >= DEBUG_LEVEL_INFO )
5525                 printk( "%s(%d):%s tx_timeout()\n",
5526                         __FILE__,__LINE__,info->device_name);
5527         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5528                 info->icount.txtimeout++;
5529         }
5530         spin_lock_irqsave(&info->lock,flags);
5531         info->tx_active = false;
5532         info->tx_count = info->tx_put = info->tx_get = 0;
5533
5534         spin_unlock_irqrestore(&info->lock,flags);
5535
5536 #if SYNCLINK_GENERIC_HDLC
5537         if (info->netcount)
5538                 hdlcdev_tx_done(info);
5539         else
5540 #endif
5541                 bh_transmit(info);
5542 }
5543
5544 /* called to periodically check the DSR/RI modem signal input status
5545  */
5546 static void status_timeout(unsigned long context)
5547 {
5548         u16 status = 0;
5549         SLMP_INFO *info = (SLMP_INFO*)context;
5550         unsigned long flags;
5551         unsigned char delta;
5552
5553
5554         spin_lock_irqsave(&info->lock,flags);
5555         get_signals(info);
5556         spin_unlock_irqrestore(&info->lock,flags);
5557
5558         /* check for DSR/RI state change */
5559
5560         delta = info->old_signals ^ info->serial_signals;
5561         info->old_signals = info->serial_signals;
5562
5563         if (delta & SerialSignal_DSR)
5564                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5565
5566         if (delta & SerialSignal_RI)
5567                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5568
5569         if (delta & SerialSignal_DCD)
5570                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5571
5572         if (delta & SerialSignal_CTS)
5573                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5574
5575         if (status)
5576                 isr_io_pin(info,status);
5577
5578         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5579 }
5580
5581
5582 /* Register Access Routines -
5583  * All registers are memory mapped
5584  */
5585 #define CALC_REGADDR() \
5586         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5587         if (info->port_num > 1) \
5588                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5589         if ( info->port_num & 1) { \
5590                 if (Addr > 0x7f) \
5591                         RegAddr += 0x40;        /* DMA access */ \
5592                 else if (Addr > 0x1f && Addr < 0x60) \
5593                         RegAddr += 0x20;        /* MSCI access */ \
5594         }
5595
5596
5597 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5598 {
5599         CALC_REGADDR();
5600         return *RegAddr;
5601 }
5602 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5603 {
5604         CALC_REGADDR();
5605         *RegAddr = Value;
5606 }
5607
5608 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5609 {
5610         CALC_REGADDR();
5611         return *((u16 *)RegAddr);
5612 }
5613
5614 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5615 {
5616         CALC_REGADDR();
5617         *((u16 *)RegAddr) = Value;
5618 }
5619
5620 static unsigned char read_status_reg(SLMP_INFO * info)
5621 {
5622         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5623         return *RegAddr;
5624 }
5625
5626 static void write_control_reg(SLMP_INFO * info)
5627 {
5628         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5629         *RegAddr = info->port_array[0]->ctrlreg_value;
5630 }
5631
5632
5633 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5634                                           const struct pci_device_id *ent)
5635 {
5636         if (pci_enable_device(dev)) {
5637                 printk("error enabling pci device %p\n", dev);
5638                 return -EIO;
5639         }
5640         device_init( ++synclinkmp_adapter_count, dev );
5641         return 0;
5642 }
5643
5644 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5645 {
5646 }