drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/slab.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/vmalloc.h>
  56 #include <linux/init.h>
  57 #include <linux/delay.h>
  58 #include <linux/ioctl.h>
  59
  60 #include <asm/system.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/dma.h>
  64 #include <linux/bitops.h>
  65 #include <asm/types.h>
  66 #include <linux/termios.h>
  67 #include <linux/workqueue.h>
  68 #include <linux/hdlc.h>
  69 #include <linux/synclink.h>
  70
  71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72 #define SYNCLINK_GENERIC_HDLC 1
  73 #else
  74 #define SYNCLINK_GENERIC_HDLC 0
  75 #endif
  76
  77 #define GET_USER(error,value,addr) error = get_user(value,addr)
  78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82 #include <asm/uaccess.h>
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 struct  _input_signal_events {
 138         int     ri_up;
 139         int     ri_down;
 140         int     dsr_up;
 141         int     dsr_down;
 142         int     dcd_up;
 143         int     dcd_down;
 144         int     cts_up;
 145         int     cts_down;
 146 };
 147
 148 /*
 149  * Device instance data structure
 150  */
 151 typedef struct _synclinkmp_info {
 152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153         int                     magic;
 154         int                     flags;
 155         int                     count;          /* count of opens */
 156         int                     line;
 157         unsigned short          close_delay;
 158         unsigned short          closing_wait;   /* time to wait before closing */
 159
 160         struct mgsl_icount      icount;
 161
 162         struct tty_struct       *tty;
 163         int                     timeout;
 164         int                     x_char;         /* xon/xoff character */
 165         int                     blocked_open;   /* # of blocked opens */
 166         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 167         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 168         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 169         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           *tx_buf;
 171         int                     tx_put;
 172         int                     tx_get;
 173         int                     tx_count;
 174
 175         wait_queue_head_t       open_wait;
 176         wait_queue_head_t       close_wait;
 177
 178         wait_queue_head_t       status_event_wait_q;
 179         wait_queue_head_t       event_wait_q;
 180         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 181         struct _synclinkmp_info *next_device;   /* device list link */
 182         struct timer_list       status_timer;   /* input signal status check timer */
 183
 184         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 185         struct work_struct task;                        /* task structure for scheduling bh */
 186
 187         u32 max_frame_size;                     /* as set by device config */
 188
 189         u32 pending_bh;
 190
 191         bool bh_running;                                /* Protection from multiple */
 192         int isr_overflow;
 193         bool bh_requested;
 194
 195         int dcd_chkcount;                       /* check counts to prevent */
 196         int cts_chkcount;                       /* too many IRQs if a signal */
 197         int dsr_chkcount;                       /* is floating */
 198         int ri_chkcount;
 199
 200         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 201         unsigned long buffer_list_phys;
 202
 203         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 204         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 205         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 206         unsigned int current_rx_buf;
 207
 208         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 209         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 210         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 211         unsigned int last_tx_buf;
 212
 213         unsigned char *tmp_rx_buf;
 214         unsigned int tmp_rx_buf_count;
 215
 216         bool rx_enabled;
 217         bool rx_overflow;
 218
 219         bool tx_enabled;
 220         bool tx_active;
 221         u32 idle_mode;
 222
 223         unsigned char ie0_value;
 224         unsigned char ie1_value;
 225         unsigned char ie2_value;
 226         unsigned char ctrlreg_value;
 227         unsigned char old_signals;
 228
 229         char device_name[25];                   /* device instance name */
 230
 231         int port_count;
 232         int adapter_num;
 233         int port_num;
 234
 235         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 236
 237         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 238
 239         unsigned int irq_level;                 /* interrupt level */
 240         unsigned long irq_flags;
 241         bool irq_requested;                     /* true if IRQ requested */
 242
 243         MGSL_PARAMS params;                     /* communications parameters */
 244
 245         unsigned char serial_signals;           /* current serial signal states */
 246
 247         bool irq_occurred;                      /* for diagnostics use */
 248         unsigned int init_error;                /* Initialization startup error */
 249
 250         u32 last_mem_alloc;
 251         unsigned char* memory_base;             /* shared memory address (PCI only) */
 252         u32 phys_memory_base;
 253         int shared_mem_requested;
 254
 255         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 256         u32 phys_sca_base;
 257         u32 sca_offset;
 258         bool sca_base_requested;
 259
 260         unsigned char* lcr_base;                /* local config registers (PCI only) */
 261         u32 phys_lcr_base;
 262         u32 lcr_offset;
 263         int lcr_mem_requested;
 264
 265         unsigned char* statctrl_base;           /* status/control register memory */
 266         u32 phys_statctrl_base;
 267         u32 statctrl_offset;
 268         bool sca_statctrl_requested;
 269
 270         u32 misc_ctrl_value;
 271         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 272         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 273         bool drop_rts_on_tx_done;
 274
 275         struct  _input_signal_events    input_signal_events;
 276
 277         /* SPPP/Cisco HDLC device parts */
 278         int netcount;
 279         int dosyncppp;
 280         spinlock_t netlock;
 281
 282 #if SYNCLINK_GENERIC_HDLC
 283         struct net_device *netdev;
 284 #endif
 285
 286 } SLMP_INFO;
 287
 288 #define MGSL_MAGIC 0x5401
 289
 290 /*
 291  * define serial signal status change macros
 292  */
 293 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 294 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 295 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 296 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 297
 298 /* Common Register macros */
 299 #define LPR     0x00
 300 #define PABR0   0x02
 301 #define PABR1   0x03
 302 #define WCRL    0x04
 303 #define WCRM    0x05
 304 #define WCRH    0x06
 305 #define DPCR    0x08
 306 #define DMER    0x09
 307 #define ISR0    0x10
 308 #define ISR1    0x11
 309 #define ISR2    0x12
 310 #define IER0    0x14
 311 #define IER1    0x15
 312 #define IER2    0x16
 313 #define ITCR    0x18
 314 #define INTVR   0x1a
 315 #define IMVR    0x1c
 316
 317 /* MSCI Register macros */
 318 #define TRB     0x20
 319 #define TRBL    0x20
 320 #define TRBH    0x21
 321 #define SR0     0x22
 322 #define SR1     0x23
 323 #define SR2     0x24
 324 #define SR3     0x25
 325 #define FST     0x26
 326 #define IE0     0x28
 327 #define IE1     0x29
 328 #define IE2     0x2a
 329 #define FIE     0x2b
 330 #define CMD     0x2c
 331 #define MD0     0x2e
 332 #define MD1     0x2f
 333 #define MD2     0x30
 334 #define CTL     0x31
 335 #define SA0     0x32
 336 #define SA1     0x33
 337 #define IDL     0x34
 338 #define TMC     0x35
 339 #define RXS     0x36
 340 #define TXS     0x37
 341 #define TRC0    0x38
 342 #define TRC1    0x39
 343 #define RRC     0x3a
 344 #define CST0    0x3c
 345 #define CST1    0x3d
 346
 347 /* Timer Register Macros */
 348 #define TCNT    0x60
 349 #define TCNTL   0x60
 350 #define TCNTH   0x61
 351 #define TCONR   0x62
 352 #define TCONRL  0x62
 353 #define TCONRH  0x63
 354 #define TMCS    0x64
 355 #define TEPR    0x65
 356
 357 /* DMA Controller Register macros */
 358 #define DARL    0x80
 359 #define DARH    0x81
 360 #define DARB    0x82
 361 #define BAR     0x80
 362 #define BARL    0x80
 363 #define BARH    0x81
 364 #define BARB    0x82
 365 #define SAR     0x84
 366 #define SARL    0x84
 367 #define SARH    0x85
 368 #define SARB    0x86
 369 #define CPB     0x86
 370 #define CDA     0x88
 371 #define CDAL    0x88
 372 #define CDAH    0x89
 373 #define EDA     0x8a
 374 #define EDAL    0x8a
 375 #define EDAH    0x8b
 376 #define BFL     0x8c
 377 #define BFLL    0x8c
 378 #define BFLH    0x8d
 379 #define BCR     0x8e
 380 #define BCRL    0x8e
 381 #define BCRH    0x8f
 382 #define DSR     0x90
 383 #define DMR     0x91
 384 #define FCT     0x93
 385 #define DIR     0x94
 386 #define DCMD    0x95
 387
 388 /* combine with timer or DMA register address */
 389 #define TIMER0  0x00
 390 #define TIMER1  0x08
 391 #define TIMER2  0x10
 392 #define TIMER3  0x18
 393 #define RXDMA   0x00
 394 #define TXDMA   0x20
 395
 396 /* SCA Command Codes */
 397 #define NOOP            0x00
 398 #define TXRESET         0x01
 399 #define TXENABLE        0x02
 400 #define TXDISABLE       0x03
 401 #define TXCRCINIT       0x04
 402 #define TXCRCEXCL       0x05
 403 #define TXEOM           0x06
 404 #define TXABORT         0x07
 405 #define MPON            0x08
 406 #define TXBUFCLR        0x09
 407 #define RXRESET         0x11
 408 #define RXENABLE        0x12
 409 #define RXDISABLE       0x13
 410 #define RXCRCINIT       0x14
 411 #define RXREJECT        0x15
 412 #define SEARCHMP        0x16
 413 #define RXCRCEXCL       0x17
 414 #define RXCRCCALC       0x18
 415 #define CHRESET         0x21
 416 #define HUNT            0x31
 417
 418 /* DMA command codes */
 419 #define SWABORT         0x01
 420 #define FEICLEAR        0x02
 421
 422 /* IE0 */
 423 #define TXINTE          BIT7
 424 #define RXINTE          BIT6
 425 #define TXRDYE          BIT1
 426 #define RXRDYE          BIT0
 427
 428 /* IE1 & SR1 */
 429 #define UDRN    BIT7
 430 #define IDLE    BIT6
 431 #define SYNCD   BIT4
 432 #define FLGD    BIT4
 433 #define CCTS    BIT3
 434 #define CDCD    BIT2
 435 #define BRKD    BIT1
 436 #define ABTD    BIT1
 437 #define GAPD    BIT1
 438 #define BRKE    BIT0
 439 #define IDLD    BIT0
 440
 441 /* IE2 & SR2 */
 442 #define EOM     BIT7
 443 #define PMP     BIT6
 444 #define SHRT    BIT6
 445 #define PE      BIT5
 446 #define ABT     BIT5
 447 #define FRME    BIT4
 448 #define RBIT    BIT4
 449 #define OVRN    BIT3
 450 #define CRCE    BIT2
 451
 452
 453 /*
 454  * Global linked list of SyncLink devices
 455  */
 456 static SLMP_INFO *synclinkmp_device_list = NULL;
 457 static int synclinkmp_adapter_count = -1;
 458 static int synclinkmp_device_count = 0;
 459
 460 /*
 461  * Set this param to non-zero to load eax with the
 462  * .text section address and breakpoint on module load.
 463  * This is useful for use with gdb and add-symbol-file command.
 464  */
 465 static int break_on_load=0;
 466
 467 /*
 468  * Driver major number, defaults to zero to get auto
 469  * assigned major number. May be forced as module parameter.
 470  */
 471 static int ttymajor=0;
 472
 473 /*
 474  * Array of user specified options for ISA adapters.
 475  */
 476 static int debug_level = 0;
 477 static int maxframe[MAX_DEVICES] = {0,};
 478 static int dosyncppp[MAX_DEVICES] = {0,};
 479
 480 module_param(break_on_load, bool, 0);
 481 module_param(ttymajor, int, 0);
 482 module_param(debug_level, int, 0);
 483 module_param_array(maxframe, int, NULL, 0);
 484 module_param_array(dosyncppp, int, NULL, 0);
 485
 486 static char *driver_name = "SyncLink MultiPort driver";
 487 static char *driver_version = "$Revision: 4.38 $";
 488
 489 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 490 static void synclinkmp_remove_one(struct pci_dev *dev);
 491
 492 static struct pci_device_id synclinkmp_pci_tbl[] = {
 493         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 494         { 0, }, /* terminate list */
 495 };
 496 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 497
 498 MODULE_LICENSE("GPL");
 499
 500 static struct pci_driver synclinkmp_pci_driver = {
 501         .name           = "synclinkmp",
 502         .id_table       = synclinkmp_pci_tbl,
 503         .probe          = synclinkmp_init_one,
 504         .remove         = __devexit_p(synclinkmp_remove_one),
 505 };
 506
 507
 508 static struct tty_driver *serial_driver;
 509
 510 /* number of characters left in xmit buffer before we ask for more */
 511 #define WAKEUP_CHARS 256
 512
 513
 514 /* tty callbacks */
 515
 516 static int  open(struct tty_struct *tty, struct file * filp);
 517 static void close(struct tty_struct *tty, struct file * filp);
 518 static void hangup(struct tty_struct *tty);
 519 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 520
 521 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 522 static void put_char(struct tty_struct *tty, unsigned char ch);
 523 static void send_xchar(struct tty_struct *tty, char ch);
 524 static void wait_until_sent(struct tty_struct *tty, int timeout);
 525 static int  write_room(struct tty_struct *tty);
 526 static void flush_chars(struct tty_struct *tty);
 527 static void flush_buffer(struct tty_struct *tty);
 528 static void tx_hold(struct tty_struct *tty);
 529 static void tx_release(struct tty_struct *tty);
 530
 531 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 532 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 533 static int  chars_in_buffer(struct tty_struct *tty);
 534 static void throttle(struct tty_struct * tty);
 535 static void unthrottle(struct tty_struct * tty);
 536 static void set_break(struct tty_struct *tty, int break_state);
 537
 538 #if SYNCLINK_GENERIC_HDLC
 539 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 540 static void hdlcdev_tx_done(SLMP_INFO *info);
 541 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 542 static int  hdlcdev_init(SLMP_INFO *info);
 543 static void hdlcdev_exit(SLMP_INFO *info);
 544 #endif
 545
 546 /* ioctl handlers */
 547
 548 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 549 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 550 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 551 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 552 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 553 static int  tx_enable(SLMP_INFO *info, int enable);
 554 static int  tx_abort(SLMP_INFO *info);
 555 static int  rx_enable(SLMP_INFO *info, int enable);
 556 static int  modem_input_wait(SLMP_INFO *info,int arg);
 557 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 558 static int  tiocmget(struct tty_struct *tty, struct file *file);
 559 static int  tiocmset(struct tty_struct *tty, struct file *file,
 560                      unsigned int set, unsigned int clear);
 561 static void set_break(struct tty_struct *tty, int break_state);
 562
 563 static void add_device(SLMP_INFO *info);
 564 static void device_init(int adapter_num, struct pci_dev *pdev);
 565 static int  claim_resources(SLMP_INFO *info);
 566 static void release_resources(SLMP_INFO *info);
 567
 568 static int  startup(SLMP_INFO *info);
 569 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 570 static void shutdown(SLMP_INFO *info);
 571 static void program_hw(SLMP_INFO *info);
 572 static void change_params(SLMP_INFO *info);
 573
 574 static bool init_adapter(SLMP_INFO *info);
 575 static bool register_test(SLMP_INFO *info);
 576 static bool irq_test(SLMP_INFO *info);
 577 static bool loopback_test(SLMP_INFO *info);
 578 static int  adapter_test(SLMP_INFO *info);
 579 static bool memory_test(SLMP_INFO *info);
 580
 581 static void reset_adapter(SLMP_INFO *info);
 582 static void reset_port(SLMP_INFO *info);
 583 static void async_mode(SLMP_INFO *info);
 584 static void hdlc_mode(SLMP_INFO *info);
 585
 586 static void rx_stop(SLMP_INFO *info);
 587 static void rx_start(SLMP_INFO *info);
 588 static void rx_reset_buffers(SLMP_INFO *info);
 589 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 590 static bool rx_get_frame(SLMP_INFO *info);
 591
 592 static void tx_start(SLMP_INFO *info);
 593 static void tx_stop(SLMP_INFO *info);
 594 static void tx_load_fifo(SLMP_INFO *info);
 595 static void tx_set_idle(SLMP_INFO *info);
 596 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 597
 598 static void get_signals(SLMP_INFO *info);
 599 static void set_signals(SLMP_INFO *info);
 600 static void enable_loopback(SLMP_INFO *info, int enable);
 601 static void set_rate(SLMP_INFO *info, u32 data_rate);
 602
 603 static int  bh_action(SLMP_INFO *info);
 604 static void bh_handler(struct work_struct *work);
 605 static void bh_receive(SLMP_INFO *info);
 606 static void bh_transmit(SLMP_INFO *info);
 607 static void bh_status(SLMP_INFO *info);
 608 static void isr_timer(SLMP_INFO *info);
 609 static void isr_rxint(SLMP_INFO *info);
 610 static void isr_rxrdy(SLMP_INFO *info);
 611 static void isr_txint(SLMP_INFO *info);
 612 static void isr_txrdy(SLMP_INFO *info);
 613 static void isr_rxdmaok(SLMP_INFO *info);
 614 static void isr_rxdmaerror(SLMP_INFO *info);
 615 static void isr_txdmaok(SLMP_INFO *info);
 616 static void isr_txdmaerror(SLMP_INFO *info);
 617 static void isr_io_pin(SLMP_INFO *info, u16 status);
 618
 619 static int  alloc_dma_bufs(SLMP_INFO *info);
 620 static void free_dma_bufs(SLMP_INFO *info);
 621 static int  alloc_buf_list(SLMP_INFO *info);
 622 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 623 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 624 static void free_tmp_rx_buf(SLMP_INFO *info);
 625
 626 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 627 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 628 static void tx_timeout(unsigned long context);
 629 static void status_timeout(unsigned long context);
 630
 631 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 632 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 633 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 634 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 635 static unsigned char read_status_reg(SLMP_INFO * info);
 636 static void write_control_reg(SLMP_INFO * info);
 637
 638
 639 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 640 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 641 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 642
 643 static u32 misc_ctrl_value = 0x007e4040;
 644 static u32 lcr1_brdr_value = 0x00800028;
 645
 646 static u32 read_ahead_count = 8;
 647
 648 /* DPCR, DMA Priority Control
 649  *
 650  * 07..05  Not used, must be 0
 651  * 04      BRC, bus release condition: 0=all transfers complete
 652  *              1=release after 1 xfer on all channels
 653  * 03      CCC, channel change condition: 0=every cycle
 654  *              1=after each channel completes all xfers
 655  * 02..00  PR<2..0>, priority 100=round robin
 656  *
 657  * 00000100 = 0x00
 658  */
 659 static unsigned char dma_priority = 0x04;
 660
 661 // Number of bytes that can be written to shared RAM
 662 // in a single write operation
 663 static u32 sca_pci_load_interval = 64;
 664
 665 /*
 666  * 1st function defined in .text section. Calling this function in
 667  * init_module() followed by a breakpoint allows a remote debugger
 668  * (gdb) to get the .text address for the add-symbol-file command.
 669  * This allows remote debugging of dynamically loadable modules.
 670  */
 671 static void* synclinkmp_get_text_ptr(void);
 672 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 673
 674 static inline int sanity_check(SLMP_INFO *info,
 675                                char *name, const char *routine)
 676 {
 677 #ifdef SANITY_CHECK
 678         static const char *badmagic =
 679                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 680         static const char *badinfo =
 681                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 682
 683         if (!info) {
 684                 printk(badinfo, name, routine);
 685                 return 1;
 686         }
 687         if (info->magic != MGSL_MAGIC) {
 688                 printk(badmagic, name, routine);
 689                 return 1;
 690         }
 691 #else
 692         if (!info)
 693                 return 1;
 694 #endif
 695         return 0;
 696 }
 697
 698 /**
 699  * line discipline callback wrappers
 700  *
 701  * The wrappers maintain line discipline references
 702  * while calling into the line discipline.
 703  *
 704  * ldisc_receive_buf  - pass receive data to line discipline
 705  */
 706
 707 static void ldisc_receive_buf(struct tty_struct *tty,
 708                               const __u8 *data, char *flags, int count)
 709 {
 710         struct tty_ldisc *ld;
 711         if (!tty)
 712                 return;
 713         ld = tty_ldisc_ref(tty);
 714         if (ld) {
 715                 if (ld->receive_buf)
 716                         ld->receive_buf(tty, data, flags, count);
 717                 tty_ldisc_deref(ld);
 718         }
 719 }
 720
 721 /* tty callbacks */
 722
 723 /* Called when a port is opened.  Init and enable port.
 724  */
 725 static int open(struct tty_struct *tty, struct file *filp)
 726 {
 727         SLMP_INFO *info;
 728         int retval, line;
 729         unsigned long flags;
 730
 731         line = tty->index;
 732         if ((line < 0) || (line >= synclinkmp_device_count)) {
 733                 printk("%s(%d): open with invalid line #%d.\n",
 734                         __FILE__,__LINE__,line);
 735                 return -ENODEV;
 736         }
 737
 738         info = synclinkmp_device_list;
 739         while(info && info->line != line)
 740                 info = info->next_device;
 741         if (sanity_check(info, tty->name, "open"))
 742                 return -ENODEV;
 743         if ( info->init_error ) {
 744                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 745                         __FILE__,__LINE__,info->device_name,info->init_error);
 746                 return -ENODEV;
 747         }
 748
 749         tty->driver_data = info;
 750         info->tty = tty;
 751
 752         if (debug_level >= DEBUG_LEVEL_INFO)
 753                 printk("%s(%d):%s open(), old ref count = %d\n",
 754                          __FILE__,__LINE__,tty->driver->name, info->count);
 755
 756         /* If port is closing, signal caller to try again */
 757         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 758                 if (info->flags & ASYNC_CLOSING)
 759                         interruptible_sleep_on(&info->close_wait);
 760                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 761                         -EAGAIN : -ERESTARTSYS);
 762                 goto cleanup;
 763         }
 764
 765         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 766
 767         spin_lock_irqsave(&info->netlock, flags);
 768         if (info->netcount) {
 769                 retval = -EBUSY;
 770                 spin_unlock_irqrestore(&info->netlock, flags);
 771                 goto cleanup;
 772         }
 773         info->count++;
 774         spin_unlock_irqrestore(&info->netlock, flags);
 775
 776         if (info->count == 1) {
 777                 /* 1st open on this device, init hardware */
 778                 retval = startup(info);
 779                 if (retval < 0)
 780                         goto cleanup;
 781         }
 782
 783         retval = block_til_ready(tty, filp, info);
 784         if (retval) {
 785                 if (debug_level >= DEBUG_LEVEL_INFO)
 786                         printk("%s(%d):%s block_til_ready() returned %d\n",
 787                                  __FILE__,__LINE__, info->device_name, retval);
 788                 goto cleanup;
 789         }
 790
 791         if (debug_level >= DEBUG_LEVEL_INFO)
 792                 printk("%s(%d):%s open() success\n",
 793                          __FILE__,__LINE__, info->device_name);
 794         retval = 0;
 795
 796 cleanup:
 797         if (retval) {
 798                 if (tty->count == 1)
 799                         info->tty = NULL; /* tty layer will release tty struct */
 800                 if(info->count)
 801                         info->count--;
 802         }
 803
 804         return retval;
 805 }
 806
 807 /* Called when port is closed. Wait for remaining data to be
 808  * sent. Disable port and free resources.
 809  */
 810 static void close(struct tty_struct *tty, struct file *filp)
 811 {
 812         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 813
 814         if (sanity_check(info, tty->name, "close"))
 815                 return;
 816
 817         if (debug_level >= DEBUG_LEVEL_INFO)
 818                 printk("%s(%d):%s close() entry, count=%d\n",
 819                          __FILE__,__LINE__, info->device_name, info->count);
 820
 821         if (!info->count)
 822                 return;
 823
 824         if (tty_hung_up_p(filp))
 825                 goto cleanup;
 826
 827         if ((tty->count == 1) && (info->count != 1)) {
 828                 /*
 829                  * tty->count is 1 and the tty structure will be freed.
 830                  * info->count should be one in this case.
 831                  * if it's not, correct it so that the port is shutdown.
 832                  */
 833                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 834                        "info->count is %d\n",
 835                          __FILE__,__LINE__, info->device_name, info->count);
 836                 info->count = 1;
 837         }
 838
 839         info->count--;
 840
 841         /* if at least one open remaining, leave hardware active */
 842         if (info->count)
 843                 goto cleanup;
 844
 845         info->flags |= ASYNC_CLOSING;
 846
 847         /* set tty->closing to notify line discipline to
 848          * only process XON/XOFF characters. Only the N_TTY
 849          * discipline appears to use this (ppp does not).
 850          */
 851         tty->closing = 1;
 852
 853         /* wait for transmit data to clear all layers */
 854
 855         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 856                 if (debug_level >= DEBUG_LEVEL_INFO)
 857                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 858                                  __FILE__,__LINE__, info->device_name );
 859                 tty_wait_until_sent(tty, info->closing_wait);
 860         }
 861
 862         if (info->flags & ASYNC_INITIALIZED)
 863                 wait_until_sent(tty, info->timeout);
 864
 865         flush_buffer(tty);
 866
 867         tty_ldisc_flush(tty);
 868
 869         shutdown(info);
 870
 871         tty->closing = 0;
 872         info->tty = NULL;
 873
 874         if (info->blocked_open) {
 875                 if (info->close_delay) {
 876                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 877                 }
 878                 wake_up_interruptible(&info->open_wait);
 879         }
 880
 881         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 882
 883         wake_up_interruptible(&info->close_wait);
 884
 885 cleanup:
 886         if (debug_level >= DEBUG_LEVEL_INFO)
 887                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 888                         tty->driver->name, info->count);
 889 }
 890
 891 /* Called by tty_hangup() when a hangup is signaled.
 892  * This is the same as closing all open descriptors for the port.
 893  */
 894 static void hangup(struct tty_struct *tty)
 895 {
 896         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 897
 898         if (debug_level >= DEBUG_LEVEL_INFO)
 899                 printk("%s(%d):%s hangup()\n",
 900                          __FILE__,__LINE__, info->device_name );
 901
 902         if (sanity_check(info, tty->name, "hangup"))
 903                 return;
 904
 905         flush_buffer(tty);
 906         shutdown(info);
 907
 908         info->count = 0;
 909         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 910         info->tty = NULL;
 911
 912         wake_up_interruptible(&info->open_wait);
 913 }
 914
 915 /* Set new termios settings
 916  */
 917 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 918 {
 919         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 920         unsigned long flags;
 921
 922         if (debug_level >= DEBUG_LEVEL_INFO)
 923                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 924                         tty->driver->name );
 925
 926         change_params(info);
 927
 928         /* Handle transition to B0 status */
 929         if (old_termios->c_cflag & CBAUD &&
 930             !(tty->termios->c_cflag & CBAUD)) {
 931                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 932                 spin_lock_irqsave(&info->lock,flags);
 933                 set_signals(info);
 934                 spin_unlock_irqrestore(&info->lock,flags);
 935         }
 936
 937         /* Handle transition away from B0 status */
 938         if (!(old_termios->c_cflag & CBAUD) &&
 939             tty->termios->c_cflag & CBAUD) {
 940                 info->serial_signals |= SerialSignal_DTR;
 941                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 942                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 943                         info->serial_signals |= SerialSignal_RTS;
 944                 }
 945                 spin_lock_irqsave(&info->lock,flags);
 946                 set_signals(info);
 947                 spin_unlock_irqrestore(&info->lock,flags);
 948         }
 949
 950         /* Handle turning off CRTSCTS */
 951         if (old_termios->c_cflag & CRTSCTS &&
 952             !(tty->termios->c_cflag & CRTSCTS)) {
 953                 tty->hw_stopped = 0;
 954                 tx_release(tty);
 955         }
 956 }
 957
 958 /* Send a block of data
 959  *
 960  * Arguments:
 961  *
 962  *      tty             pointer to tty information structure
 963  *      buf             pointer to buffer containing send data
 964  *      count           size of send data in bytes
 965  *
 966  * Return Value:        number of characters written
 967  */
 968 static int write(struct tty_struct *tty,
 969                  const unsigned char *buf, int count)
 970 {
 971         int     c, ret = 0;
 972         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 973         unsigned long flags;
 974
 975         if (debug_level >= DEBUG_LEVEL_INFO)
 976                 printk("%s(%d):%s write() count=%d\n",
 977                        __FILE__,__LINE__,info->device_name,count);
 978
 979         if (sanity_check(info, tty->name, "write"))
 980                 goto cleanup;
 981
 982         if (!info->tx_buf)
 983                 goto cleanup;
 984
 985         if (info->params.mode == MGSL_MODE_HDLC) {
 986                 if (count > info->max_frame_size) {
 987                         ret = -EIO;
 988                         goto cleanup;
 989                 }
 990                 if (info->tx_active)
 991                         goto cleanup;
 992                 if (info->tx_count) {
 993                         /* send accumulated data from send_char() calls */
 994                         /* as frame and wait before accepting more data. */
 995                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 996                         goto start;
 997                 }
 998                 ret = info->tx_count = count;
 999                 tx_load_dma_buffer(info, buf, count);
1000                 goto start;
1001         }
1002
1003         for (;;) {
1004                 c = min_t(int, count,
1005                         min(info->max_frame_size - info->tx_count - 1,
1006                             info->max_frame_size - info->tx_put));
1007                 if (c <= 0)
1008                         break;
1009
1010                 memcpy(info->tx_buf + info->tx_put, buf, c);
1011
1012                 spin_lock_irqsave(&info->lock,flags);
1013                 info->tx_put += c;
1014                 if (info->tx_put >= info->max_frame_size)
1015                         info->tx_put -= info->max_frame_size;
1016                 info->tx_count += c;
1017                 spin_unlock_irqrestore(&info->lock,flags);
1018
1019                 buf += c;
1020                 count -= c;
1021                 ret += c;
1022         }
1023
1024         if (info->params.mode == MGSL_MODE_HDLC) {
1025                 if (count) {
1026                         ret = info->tx_count = 0;
1027                         goto cleanup;
1028                 }
1029                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1030         }
1031 start:
1032         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1033                 spin_lock_irqsave(&info->lock,flags);
1034                 if (!info->tx_active)
1035                         tx_start(info);
1036                 spin_unlock_irqrestore(&info->lock,flags);
1037         }
1038
1039 cleanup:
1040         if (debug_level >= DEBUG_LEVEL_INFO)
1041                 printk( "%s(%d):%s write() returning=%d\n",
1042                         __FILE__,__LINE__,info->device_name,ret);
1043         return ret;
1044 }
1045
1046 /* Add a character to the transmit buffer.
1047  */
1048 static void put_char(struct tty_struct *tty, unsigned char ch)
1049 {
1050         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1051         unsigned long flags;
1052
1053         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1054                 printk( "%s(%d):%s put_char(%d)\n",
1055                         __FILE__,__LINE__,info->device_name,ch);
1056         }
1057
1058         if (sanity_check(info, tty->name, "put_char"))
1059                 return;
1060
1061         if (!info->tx_buf)
1062                 return;
1063
1064         spin_lock_irqsave(&info->lock,flags);
1065
1066         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1067              !info->tx_active ) {
1068
1069                 if (info->tx_count < info->max_frame_size - 1) {
1070                         info->tx_buf[info->tx_put++] = ch;
1071                         if (info->tx_put >= info->max_frame_size)
1072                                 info->tx_put -= info->max_frame_size;
1073                         info->tx_count++;
1074                 }
1075         }
1076
1077         spin_unlock_irqrestore(&info->lock,flags);
1078 }
1079
1080 /* Send a high-priority XON/XOFF character
1081  */
1082 static void send_xchar(struct tty_struct *tty, char ch)
1083 {
1084         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1085         unsigned long flags;
1086
1087         if (debug_level >= DEBUG_LEVEL_INFO)
1088                 printk("%s(%d):%s send_xchar(%d)\n",
1089                          __FILE__,__LINE__, info->device_name, ch );
1090
1091         if (sanity_check(info, tty->name, "send_xchar"))
1092                 return;
1093
1094         info->x_char = ch;
1095         if (ch) {
1096                 /* Make sure transmit interrupts are on */
1097                 spin_lock_irqsave(&info->lock,flags);
1098                 if (!info->tx_enabled)
1099                         tx_start(info);
1100                 spin_unlock_irqrestore(&info->lock,flags);
1101         }
1102 }
1103
1104 /* Wait until the transmitter is empty.
1105  */
1106 static void wait_until_sent(struct tty_struct *tty, int timeout)
1107 {
1108         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1109         unsigned long orig_jiffies, char_time;
1110
1111         if (!info )
1112                 return;
1113
1114         if (debug_level >= DEBUG_LEVEL_INFO)
1115                 printk("%s(%d):%s wait_until_sent() entry\n",
1116                          __FILE__,__LINE__, info->device_name );
1117
1118         if (sanity_check(info, tty->name, "wait_until_sent"))
1119                 return;
1120
1121         lock_kernel();
1122
1123         if (!(info->flags & ASYNC_INITIALIZED))
1124                 goto exit;
1125
1126         orig_jiffies = jiffies;
1127
1128         /* Set check interval to 1/5 of estimated time to
1129          * send a character, and make it at least 1. The check
1130          * interval should also be less than the timeout.
1131          * Note: use tight timings here to satisfy the NIST-PCTS.
1132          */
1133
1134         if ( info->params.data_rate ) {
1135                 char_time = info->timeout/(32 * 5);
1136                 if (!char_time)
1137                         char_time++;
1138         } else
1139                 char_time = 1;
1140
1141         if (timeout)
1142                 char_time = min_t(unsigned long, char_time, timeout);
1143
1144         if ( info->params.mode == MGSL_MODE_HDLC ) {
1145                 while (info->tx_active) {
1146                         msleep_interruptible(jiffies_to_msecs(char_time));
1147                         if (signal_pending(current))
1148                                 break;
1149                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1150                                 break;
1151                 }
1152         } else {
1153                 //TODO: determine if there is something similar to USC16C32
1154                 //      TXSTATUS_ALL_SENT status
1155                 while ( info->tx_active && info->tx_enabled) {
1156                         msleep_interruptible(jiffies_to_msecs(char_time));
1157                         if (signal_pending(current))
1158                                 break;
1159                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1160                                 break;
1161                 }
1162         }
1163
1164 exit:
1165         unlock_kernel();
1166         if (debug_level >= DEBUG_LEVEL_INFO)
1167                 printk("%s(%d):%s wait_until_sent() exit\n",
1168                          __FILE__,__LINE__, info->device_name );
1169 }
1170
1171 /* Return the count of free bytes in transmit buffer
1172  */
1173 static int write_room(struct tty_struct *tty)
1174 {
1175         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1176         int ret;
1177
1178         if (sanity_check(info, tty->name, "write_room"))
1179                 return 0;
1180
1181         lock_kernel();
1182         if (info->params.mode == MGSL_MODE_HDLC) {
1183                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1184         } else {
1185                 ret = info->max_frame_size - info->tx_count - 1;
1186                 if (ret < 0)
1187                         ret = 0;
1188         }
1189         unlock_kernel();
1190
1191         if (debug_level >= DEBUG_LEVEL_INFO)
1192                 printk("%s(%d):%s write_room()=%d\n",
1193                        __FILE__, __LINE__, info->device_name, ret);
1194
1195         return ret;
1196 }
1197
1198 /* enable transmitter and send remaining buffered characters
1199  */
1200 static void flush_chars(struct tty_struct *tty)
1201 {
1202         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1203         unsigned long flags;
1204
1205         if ( debug_level >= DEBUG_LEVEL_INFO )
1206                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1207                         __FILE__,__LINE__,info->device_name,info->tx_count);
1208
1209         if (sanity_check(info, tty->name, "flush_chars"))
1210                 return;
1211
1212         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1213             !info->tx_buf)
1214                 return;
1215
1216         if ( debug_level >= DEBUG_LEVEL_INFO )
1217                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1218                         __FILE__,__LINE__,info->device_name );
1219
1220         spin_lock_irqsave(&info->lock,flags);
1221
1222         if (!info->tx_active) {
1223                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1224                         info->tx_count ) {
1225                         /* operating in synchronous (frame oriented) mode */
1226                         /* copy data from circular tx_buf to */
1227                         /* transmit DMA buffer. */
1228                         tx_load_dma_buffer(info,
1229                                  info->tx_buf,info->tx_count);
1230                 }
1231                 tx_start(info);
1232         }
1233
1234         spin_unlock_irqrestore(&info->lock,flags);
1235 }
1236
1237 /* Discard all data in the send buffer
1238  */
1239 static void flush_buffer(struct tty_struct *tty)
1240 {
1241         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1242         unsigned long flags;
1243
1244         if (debug_level >= DEBUG_LEVEL_INFO)
1245                 printk("%s(%d):%s flush_buffer() entry\n",
1246                          __FILE__,__LINE__, info->device_name );
1247
1248         if (sanity_check(info, tty->name, "flush_buffer"))
1249                 return;
1250
1251         spin_lock_irqsave(&info->lock,flags);
1252         info->tx_count = info->tx_put = info->tx_get = 0;
1253         del_timer(&info->tx_timer);
1254         spin_unlock_irqrestore(&info->lock,flags);
1255
1256         tty_wakeup(tty);
1257 }
1258
1259 /* throttle (stop) transmitter
1260  */
1261 static void tx_hold(struct tty_struct *tty)
1262 {
1263         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1264         unsigned long flags;
1265
1266         if (sanity_check(info, tty->name, "tx_hold"))
1267                 return;
1268
1269         if ( debug_level >= DEBUG_LEVEL_INFO )
1270                 printk("%s(%d):%s tx_hold()\n",
1271                         __FILE__,__LINE__,info->device_name);
1272
1273         spin_lock_irqsave(&info->lock,flags);
1274         if (info->tx_enabled)
1275                 tx_stop(info);
1276         spin_unlock_irqrestore(&info->lock,flags);
1277 }
1278
1279 /* release (start) transmitter
1280  */
1281 static void tx_release(struct tty_struct *tty)
1282 {
1283         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1284         unsigned long flags;
1285
1286         if (sanity_check(info, tty->name, "tx_release"))
1287                 return;
1288
1289         if ( debug_level >= DEBUG_LEVEL_INFO )
1290                 printk("%s(%d):%s tx_release()\n",
1291                         __FILE__,__LINE__,info->device_name);
1292
1293         spin_lock_irqsave(&info->lock,flags);
1294         if (!info->tx_enabled)
1295                 tx_start(info);
1296         spin_unlock_irqrestore(&info->lock,flags);
1297 }
1298
1299 /* Service an IOCTL request
1300  *
1301  * Arguments:
1302  *
1303  *      tty     pointer to tty instance data
1304  *      file    pointer to associated file object for device
1305  *      cmd     IOCTL command code
1306  *      arg     command argument/context
1307  *
1308  * Return Value:        0 if success, otherwise error code
1309  */
1310 static int do_ioctl(struct tty_struct *tty, struct file *file,
1311                  unsigned int cmd, unsigned long arg)
1312 {
1313         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1314         int error;
1315         struct mgsl_icount cnow;        /* kernel counter temps */
1316         struct serial_icounter_struct __user *p_cuser;  /* user space */
1317         unsigned long flags;
1318         void __user *argp = (void __user *)arg;
1319
1320         if (debug_level >= DEBUG_LEVEL_INFO)
1321                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1322                         info->device_name, cmd );
1323
1324         if (sanity_check(info, tty->name, "ioctl"))
1325                 return -ENODEV;
1326
1327         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1328             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1329                 if (tty->flags & (1 << TTY_IO_ERROR))
1330                     return -EIO;
1331         }
1332
1333         switch (cmd) {
1334         case MGSL_IOCGPARAMS:
1335                 return get_params(info, argp);
1336         case MGSL_IOCSPARAMS:
1337                 return set_params(info, argp);
1338         case MGSL_IOCGTXIDLE:
1339                 return get_txidle(info, argp);
1340         case MGSL_IOCSTXIDLE:
1341                 return set_txidle(info, (int)arg);
1342         case MGSL_IOCTXENABLE:
1343                 return tx_enable(info, (int)arg);
1344         case MGSL_IOCRXENABLE:
1345                 return rx_enable(info, (int)arg);
1346         case MGSL_IOCTXABORT:
1347                 return tx_abort(info);
1348         case MGSL_IOCGSTATS:
1349                 return get_stats(info, argp);
1350         case MGSL_IOCWAITEVENT:
1351                 return wait_mgsl_event(info, argp);
1352         case MGSL_IOCLOOPTXDONE:
1353                 return 0; // TODO: Not supported, need to document
1354                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1355                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1356                  */
1357         case TIOCMIWAIT:
1358                 return modem_input_wait(info,(int)arg);
1359
1360                 /*
1361                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1362                  * Return: write counters to the user passed counter struct
1363                  * NB: both 1->0 and 0->1 transitions are counted except for
1364                  *     RI where only 0->1 is counted.
1365                  */
1366         case TIOCGICOUNT:
1367                 spin_lock_irqsave(&info->lock,flags);
1368                 cnow = info->icount;
1369                 spin_unlock_irqrestore(&info->lock,flags);
1370                 p_cuser = argp;
1371                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1372                 if (error) return error;
1373                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1374                 if (error) return error;
1375                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1376                 if (error) return error;
1377                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1378                 if (error) return error;
1379                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1380                 if (error) return error;
1381                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1382                 if (error) return error;
1383                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1384                 if (error) return error;
1385                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1386                 if (error) return error;
1387                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1388                 if (error) return error;
1389                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1390                 if (error) return error;
1391                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1392                 if (error) return error;
1393                 return 0;
1394         default:
1395                 return -ENOIOCTLCMD;
1396         }
1397         return 0;
1398 }
1399
1400 static int ioctl(struct tty_struct *tty, struct file *file,
1401                  unsigned int cmd, unsigned long arg)
1402 {
1403         int ret;
1404         lock_kernel();
1405         ret = do_ioctl(tty, file, cmd, arg);
1406         unlock_kernel();
1407         return ret;
1408 }
1409
1410 /*
1411  * /proc fs routines....
1412  */
1413
1414 static inline int line_info(char *buf, SLMP_INFO *info)
1415 {
1416         char    stat_buf[30];
1417         int     ret;
1418         unsigned long flags;
1419
1420         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1421                        "\tIRQ=%d MaxFrameSize=%u\n",
1422                 info->device_name,
1423                 info->phys_sca_base,
1424                 info->phys_memory_base,
1425                 info->phys_statctrl_base,
1426                 info->phys_lcr_base,
1427                 info->irq_level,
1428                 info->max_frame_size );
1429
1430         /* output current serial signal states */
1431         spin_lock_irqsave(&info->lock,flags);
1432         get_signals(info);
1433         spin_unlock_irqrestore(&info->lock,flags);
1434
1435         stat_buf[0] = 0;
1436         stat_buf[1] = 0;
1437         if (info->serial_signals & SerialSignal_RTS)
1438                 strcat(stat_buf, "|RTS");
1439         if (info->serial_signals & SerialSignal_CTS)
1440                 strcat(stat_buf, "|CTS");
1441         if (info->serial_signals & SerialSignal_DTR)
1442                 strcat(stat_buf, "|DTR");
1443         if (info->serial_signals & SerialSignal_DSR)
1444                 strcat(stat_buf, "|DSR");
1445         if (info->serial_signals & SerialSignal_DCD)
1446                 strcat(stat_buf, "|CD");
1447         if (info->serial_signals & SerialSignal_RI)
1448                 strcat(stat_buf, "|RI");
1449
1450         if (info->params.mode == MGSL_MODE_HDLC) {
1451                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1452                               info->icount.txok, info->icount.rxok);
1453                 if (info->icount.txunder)
1454                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1455                 if (info->icount.txabort)
1456                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1457                 if (info->icount.rxshort)
1458                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1459                 if (info->icount.rxlong)
1460                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1461                 if (info->icount.rxover)
1462                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1463                 if (info->icount.rxcrc)
1464                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1465         } else {
1466                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1467                               info->icount.tx, info->icount.rx);
1468                 if (info->icount.frame)
1469                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1470                 if (info->icount.parity)
1471                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1472                 if (info->icount.brk)
1473                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1474                 if (info->icount.overrun)
1475                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1476         }
1477
1478         /* Append serial signal status to end */
1479         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1480
1481         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1482          info->tx_active,info->bh_requested,info->bh_running,
1483          info->pending_bh);
1484
1485         return ret;
1486 }
1487
1488 /* Called to print information about devices
1489  */
1490 static int read_proc(char *page, char **start, off_t off, int count,
1491               int *eof, void *data)
1492 {
1493         int len = 0, l;
1494         off_t   begin = 0;
1495         SLMP_INFO *info;
1496
1497         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1498
1499         info = synclinkmp_device_list;
1500         while( info ) {
1501                 l = line_info(page + len, info);
1502                 len += l;
1503                 if (len+begin > off+count)
1504                         goto done;
1505                 if (len+begin < off) {
1506                         begin += len;
1507                         len = 0;
1508                 }
1509                 info = info->next_device;
1510         }
1511
1512         *eof = 1;
1513 done:
1514         if (off >= len+begin)
1515                 return 0;
1516         *start = page + (off-begin);
1517         return ((count < begin+len-off) ? count : begin+len-off);
1518 }
1519
1520 /* Return the count of bytes in transmit buffer
1521  */
1522 static int chars_in_buffer(struct tty_struct *tty)
1523 {
1524         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1525
1526         if (sanity_check(info, tty->name, "chars_in_buffer"))
1527                 return 0;
1528
1529         if (debug_level >= DEBUG_LEVEL_INFO)
1530                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1531                        __FILE__, __LINE__, info->device_name, info->tx_count);
1532
1533         return info->tx_count;
1534 }
1535
1536 /* Signal remote device to throttle send data (our receive data)
1537  */
1538 static void throttle(struct tty_struct * tty)
1539 {
1540         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1541         unsigned long flags;
1542
1543         if (debug_level >= DEBUG_LEVEL_INFO)
1544                 printk("%s(%d):%s throttle() entry\n",
1545                          __FILE__,__LINE__, info->device_name );
1546
1547         if (sanity_check(info, tty->name, "throttle"))
1548                 return;
1549
1550         if (I_IXOFF(tty))
1551                 send_xchar(tty, STOP_CHAR(tty));
1552
1553         if (tty->termios->c_cflag & CRTSCTS) {
1554                 spin_lock_irqsave(&info->lock,flags);
1555                 info->serial_signals &= ~SerialSignal_RTS;
1556                 set_signals(info);
1557                 spin_unlock_irqrestore(&info->lock,flags);
1558         }
1559 }
1560
1561 /* Signal remote device to stop throttling send data (our receive data)
1562  */
1563 static void unthrottle(struct tty_struct * tty)
1564 {
1565         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1566         unsigned long flags;
1567
1568         if (debug_level >= DEBUG_LEVEL_INFO)
1569                 printk("%s(%d):%s unthrottle() entry\n",
1570                          __FILE__,__LINE__, info->device_name );
1571
1572         if (sanity_check(info, tty->name, "unthrottle"))
1573                 return;
1574
1575         if (I_IXOFF(tty)) {
1576                 if (info->x_char)
1577                         info->x_char = 0;
1578                 else
1579                         send_xchar(tty, START_CHAR(tty));
1580         }
1581
1582         if (tty->termios->c_cflag & CRTSCTS) {
1583                 spin_lock_irqsave(&info->lock,flags);
1584                 info->serial_signals |= SerialSignal_RTS;
1585                 set_signals(info);
1586                 spin_unlock_irqrestore(&info->lock,flags);
1587         }
1588 }
1589
1590 /* set or clear transmit break condition
1591  * break_state  -1=set break condition, 0=clear
1592  */
1593 static void set_break(struct tty_struct *tty, int break_state)
1594 {
1595         unsigned char RegValue;
1596         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1597         unsigned long flags;
1598
1599         if (debug_level >= DEBUG_LEVEL_INFO)
1600                 printk("%s(%d):%s set_break(%d)\n",
1601                          __FILE__,__LINE__, info->device_name, break_state);
1602
1603         if (sanity_check(info, tty->name, "set_break"))
1604                 return;
1605
1606         spin_lock_irqsave(&info->lock,flags);
1607         RegValue = read_reg(info, CTL);
1608         if (break_state == -1)
1609                 RegValue |= BIT3;
1610         else
1611                 RegValue &= ~BIT3;
1612         write_reg(info, CTL, RegValue);
1613         spin_unlock_irqrestore(&info->lock,flags);
1614 }
1615
1616 #if SYNCLINK_GENERIC_HDLC
1617
1618 /**
1619  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1620  * set encoding and frame check sequence (FCS) options
1621  *
1622  * dev       pointer to network device structure
1623  * encoding  serial encoding setting
1624  * parity    FCS setting
1625  *
1626  * returns 0 if success, otherwise error code
1627  */
1628 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1629                           unsigned short parity)
1630 {
1631         SLMP_INFO *info = dev_to_port(dev);
1632         unsigned char  new_encoding;
1633         unsigned short new_crctype;
1634
1635         /* return error if TTY interface open */
1636         if (info->count)
1637                 return -EBUSY;
1638
1639         switch (encoding)
1640         {
1641         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1642         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1643         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1644         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1645         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1646         default: return -EINVAL;
1647         }
1648
1649         switch (parity)
1650         {
1651         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1652         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1653         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1654         default: return -EINVAL;
1655         }
1656
1657         info->params.encoding = new_encoding;
1658         info->params.crc_type = new_crctype;
1659
1660         /* if network interface up, reprogram hardware */
1661         if (info->netcount)
1662                 program_hw(info);
1663
1664         return 0;
1665 }
1666
1667 /**
1668  * called by generic HDLC layer to send frame
1669  *
1670  * skb  socket buffer containing HDLC frame
1671  * dev  pointer to network device structure
1672  *
1673  * returns 0 if success, otherwise error code
1674  */
1675 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1676 {
1677         SLMP_INFO *info = dev_to_port(dev);
1678         struct net_device_stats *stats = hdlc_stats(dev);
1679         unsigned long flags;
1680
1681         if (debug_level >= DEBUG_LEVEL_INFO)
1682                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1683
1684         /* stop sending until this frame completes */
1685         netif_stop_queue(dev);
1686
1687         /* copy data to device buffers */
1688         info->tx_count = skb->len;
1689         tx_load_dma_buffer(info, skb->data, skb->len);
1690
1691         /* update network statistics */
1692         stats->tx_packets++;
1693         stats->tx_bytes += skb->len;
1694
1695         /* done with socket buffer, so free it */
1696         dev_kfree_skb(skb);
1697
1698         /* save start time for transmit timeout detection */
1699         dev->trans_start = jiffies;
1700
1701         /* start hardware transmitter if necessary */
1702         spin_lock_irqsave(&info->lock,flags);
1703         if (!info->tx_active)
1704                 tx_start(info);
1705         spin_unlock_irqrestore(&info->lock,flags);
1706
1707         return 0;
1708 }
1709
1710 /**
1711  * called by network layer when interface enabled
1712  * claim resources and initialize hardware
1713  *
1714  * dev  pointer to network device structure
1715  *
1716  * returns 0 if success, otherwise error code
1717  */
1718 static int hdlcdev_open(struct net_device *dev)
1719 {
1720         SLMP_INFO *info = dev_to_port(dev);
1721         int rc;
1722         unsigned long flags;
1723
1724         if (debug_level >= DEBUG_LEVEL_INFO)
1725                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1726
1727         /* generic HDLC layer open processing */
1728         if ((rc = hdlc_open(dev)))
1729                 return rc;
1730
1731         /* arbitrate between network and tty opens */
1732         spin_lock_irqsave(&info->netlock, flags);
1733         if (info->count != 0 || info->netcount != 0) {
1734                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1735                 spin_unlock_irqrestore(&info->netlock, flags);
1736                 return -EBUSY;
1737         }
1738         info->netcount=1;
1739         spin_unlock_irqrestore(&info->netlock, flags);
1740
1741         /* claim resources and init adapter */
1742         if ((rc = startup(info)) != 0) {
1743                 spin_lock_irqsave(&info->netlock, flags);
1744                 info->netcount=0;
1745                 spin_unlock_irqrestore(&info->netlock, flags);
1746                 return rc;
1747         }
1748
1749         /* assert DTR and RTS, apply hardware settings */
1750         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1751         program_hw(info);
1752
1753         /* enable network layer transmit */
1754         dev->trans_start = jiffies;
1755         netif_start_queue(dev);
1756
1757         /* inform generic HDLC layer of current DCD status */
1758         spin_lock_irqsave(&info->lock, flags);
1759         get_signals(info);
1760         spin_unlock_irqrestore(&info->lock, flags);
1761         if (info->serial_signals & SerialSignal_DCD)
1762                 netif_carrier_on(dev);
1763         else
1764                 netif_carrier_off(dev);
1765         return 0;
1766 }
1767
1768 /**
1769  * called by network layer when interface is disabled
1770  * shutdown hardware and release resources
1771  *
1772  * dev  pointer to network device structure
1773  *
1774  * returns 0 if success, otherwise error code
1775  */
1776 static int hdlcdev_close(struct net_device *dev)
1777 {
1778         SLMP_INFO *info = dev_to_port(dev);
1779         unsigned long flags;
1780
1781         if (debug_level >= DEBUG_LEVEL_INFO)
1782                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1783
1784         netif_stop_queue(dev);
1785
1786         /* shutdown adapter and release resources */
1787         shutdown(info);
1788
1789         hdlc_close(dev);
1790
1791         spin_lock_irqsave(&info->netlock, flags);
1792         info->netcount=0;
1793         spin_unlock_irqrestore(&info->netlock, flags);
1794
1795         return 0;
1796 }
1797
1798 /**
1799  * called by network layer to process IOCTL call to network device
1800  *
1801  * dev  pointer to network device structure
1802  * ifr  pointer to network interface request structure
1803  * cmd  IOCTL command code
1804  *
1805  * returns 0 if success, otherwise error code
1806  */
1807 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1808 {
1809         const size_t size = sizeof(sync_serial_settings);
1810         sync_serial_settings new_line;
1811         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1812         SLMP_INFO *info = dev_to_port(dev);
1813         unsigned int flags;
1814
1815         if (debug_level >= DEBUG_LEVEL_INFO)
1816                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1817
1818         /* return error if TTY interface open */
1819         if (info->count)
1820                 return -EBUSY;
1821
1822         if (cmd != SIOCWANDEV)
1823                 return hdlc_ioctl(dev, ifr, cmd);
1824
1825         switch(ifr->ifr_settings.type) {
1826         case IF_GET_IFACE: /* return current sync_serial_settings */
1827
1828                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1829                 if (ifr->ifr_settings.size < size) {
1830                         ifr->ifr_settings.size = size; /* data size wanted */
1831                         return -ENOBUFS;
1832                 }
1833
1834                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1835                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1836                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1837                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1838
1839                 switch (flags){
1840                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1841                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1842                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1843                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1844                 default: new_line.clock_type = CLOCK_DEFAULT;
1845                 }
1846
1847                 new_line.clock_rate = info->params.clock_speed;
1848                 new_line.loopback   = info->params.loopback ? 1:0;
1849
1850                 if (copy_to_user(line, &new_line, size))
1851                         return -EFAULT;
1852                 return 0;
1853
1854         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1855
1856                 if(!capable(CAP_NET_ADMIN))
1857                         return -EPERM;
1858                 if (copy_from_user(&new_line, line, size))
1859                         return -EFAULT;
1860
1861                 switch (new_line.clock_type)
1862                 {
1863                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1864                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1865                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1866                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1867                 case CLOCK_DEFAULT:  flags = info->params.flags &
1868                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1869                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1870                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1871                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1872                 default: return -EINVAL;
1873                 }
1874
1875                 if (new_line.loopback != 0 && new_line.loopback != 1)
1876                         return -EINVAL;
1877
1878                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1879                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1880                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1881                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1882                 info->params.flags |= flags;
1883
1884                 info->params.loopback = new_line.loopback;
1885
1886                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1887                         info->params.clock_speed = new_line.clock_rate;
1888                 else
1889                         info->params.clock_speed = 0;
1890
1891                 /* if network interface up, reprogram hardware */
1892                 if (info->netcount)
1893                         program_hw(info);
1894                 return 0;
1895
1896         default:
1897                 return hdlc_ioctl(dev, ifr, cmd);
1898         }
1899 }
1900
1901 /**
1902  * called by network layer when transmit timeout is detected
1903  *
1904  * dev  pointer to network device structure
1905  */
1906 static void hdlcdev_tx_timeout(struct net_device *dev)
1907 {
1908         SLMP_INFO *info = dev_to_port(dev);
1909         struct net_device_stats *stats = hdlc_stats(dev);
1910         unsigned long flags;
1911
1912         if (debug_level >= DEBUG_LEVEL_INFO)
1913                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1914
1915         stats->tx_errors++;
1916         stats->tx_aborted_errors++;
1917
1918         spin_lock_irqsave(&info->lock,flags);
1919         tx_stop(info);
1920         spin_unlock_irqrestore(&info->lock,flags);
1921
1922         netif_wake_queue(dev);
1923 }
1924
1925 /**
1926  * called by device driver when transmit completes
1927  * reenable network layer transmit if stopped
1928  *
1929  * info  pointer to device instance information
1930  */
1931 static void hdlcdev_tx_done(SLMP_INFO *info)
1932 {
1933         if (netif_queue_stopped(info->netdev))
1934                 netif_wake_queue(info->netdev);
1935 }
1936
1937 /**
1938  * called by device driver when frame received
1939  * pass frame to network layer
1940  *
1941  * info  pointer to device instance information
1942  * buf   pointer to buffer contianing frame data
1943  * size  count of data bytes in buf
1944  */
1945 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1946 {
1947         struct sk_buff *skb = dev_alloc_skb(size);
1948         struct net_device *dev = info->netdev;
1949         struct net_device_stats *stats = hdlc_stats(dev);
1950
1951         if (debug_level >= DEBUG_LEVEL_INFO)
1952                 printk("hdlcdev_rx(%s)\n",dev->name);
1953
1954         if (skb == NULL) {
1955                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1956                 stats->rx_dropped++;
1957                 return;
1958         }
1959
1960         memcpy(skb_put(skb, size),buf,size);
1961
1962         skb->protocol = hdlc_type_trans(skb, info->netdev);
1963
1964         stats->rx_packets++;
1965         stats->rx_bytes += size;
1966
1967         netif_rx(skb);
1968
1969         info->netdev->last_rx = jiffies;
1970 }
1971
1972 /**
1973  * called by device driver when adding device instance
1974  * do generic HDLC initialization
1975  *
1976  * info  pointer to device instance information
1977  *
1978  * returns 0 if success, otherwise error code
1979  */
1980 static int hdlcdev_init(SLMP_INFO *info)
1981 {
1982         int rc;
1983         struct net_device *dev;
1984         hdlc_device *hdlc;
1985
1986         /* allocate and initialize network and HDLC layer objects */
1987
1988         if (!(dev = alloc_hdlcdev(info))) {
1989                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1990                 return -ENOMEM;
1991         }
1992
1993         /* for network layer reporting purposes only */
1994         dev->mem_start = info->phys_sca_base;
1995         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1996         dev->irq       = info->irq_level;
1997
1998         /* network layer callbacks and settings */
1999         dev->do_ioctl       = hdlcdev_ioctl;
2000         dev->open           = hdlcdev_open;
2001         dev->stop           = hdlcdev_close;
2002         dev->tx_timeout     = hdlcdev_tx_timeout;
2003         dev->watchdog_timeo = 10*HZ;
2004         dev->tx_queue_len   = 50;
2005
2006         /* generic HDLC layer callbacks and settings */
2007         hdlc         = dev_to_hdlc(dev);
2008         hdlc->attach = hdlcdev_attach;
2009         hdlc->xmit   = hdlcdev_xmit;
2010
2011         /* register objects with HDLC layer */
2012         if ((rc = register_hdlc_device(dev))) {
2013                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2014                 free_netdev(dev);
2015                 return rc;
2016         }
2017
2018         info->netdev = dev;
2019         return 0;
2020 }
2021
2022 /**
2023  * called by device driver when removing device instance
2024  * do generic HDLC cleanup
2025  *
2026  * info  pointer to device instance information
2027  */
2028 static void hdlcdev_exit(SLMP_INFO *info)
2029 {
2030         unregister_hdlc_device(info->netdev);
2031         free_netdev(info->netdev);
2032         info->netdev = NULL;
2033 }
2034
2035 #endif /* CONFIG_HDLC */
2036
2037
2038 /* Return next bottom half action to perform.
2039  * Return Value:        BH action code or 0 if nothing to do.
2040  */
2041 static int bh_action(SLMP_INFO *info)
2042 {
2043         unsigned long flags;
2044         int rc = 0;
2045
2046         spin_lock_irqsave(&info->lock,flags);
2047
2048         if (info->pending_bh & BH_RECEIVE) {
2049                 info->pending_bh &= ~BH_RECEIVE;
2050                 rc = BH_RECEIVE;
2051         } else if (info->pending_bh & BH_TRANSMIT) {
2052                 info->pending_bh &= ~BH_TRANSMIT;
2053                 rc = BH_TRANSMIT;
2054         } else if (info->pending_bh & BH_STATUS) {
2055                 info->pending_bh &= ~BH_STATUS;
2056                 rc = BH_STATUS;
2057         }
2058
2059         if (!rc) {
2060                 /* Mark BH routine as complete */
2061                 info->bh_running = false;
2062                 info->bh_requested = false;
2063         }
2064
2065         spin_unlock_irqrestore(&info->lock,flags);
2066
2067         return rc;
2068 }
2069
2070 /* Perform bottom half processing of work items queued by ISR.
2071  */
2072 static void bh_handler(struct work_struct *work)
2073 {
2074         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2075         int action;
2076
2077         if (!info)
2078                 return;
2079
2080         if ( debug_level >= DEBUG_LEVEL_BH )
2081                 printk( "%s(%d):%s bh_handler() entry\n",
2082                         __FILE__,__LINE__,info->device_name);
2083
2084         info->bh_running = true;
2085
2086         while((action = bh_action(info)) != 0) {
2087
2088                 /* Process work item */
2089                 if ( debug_level >= DEBUG_LEVEL_BH )
2090                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2091                                 __FILE__,__LINE__,info->device_name, action);
2092
2093                 switch (action) {
2094
2095                 case BH_RECEIVE:
2096                         bh_receive(info);
2097                         break;
2098                 case BH_TRANSMIT:
2099                         bh_transmit(info);
2100                         break;
2101                 case BH_STATUS:
2102                         bh_status(info);
2103                         break;
2104                 default:
2105                         /* unknown work item ID */
2106                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2107                                 __FILE__,__LINE__,info->device_name,action);
2108                         break;
2109                 }
2110         }
2111
2112         if ( debug_level >= DEBUG_LEVEL_BH )
2113                 printk( "%s(%d):%s bh_handler() exit\n",
2114                         __FILE__,__LINE__,info->device_name);
2115 }
2116
2117 static void bh_receive(SLMP_INFO *info)
2118 {
2119         if ( debug_level >= DEBUG_LEVEL_BH )
2120                 printk( "%s(%d):%s bh_receive()\n",
2121                         __FILE__,__LINE__,info->device_name);
2122
2123         while( rx_get_frame(info) );
2124 }
2125
2126 static void bh_transmit(SLMP_INFO *info)
2127 {
2128         struct tty_struct *tty = info->tty;
2129
2130         if ( debug_level >= DEBUG_LEVEL_BH )
2131                 printk( "%s(%d):%s bh_transmit() entry\n",
2132                         __FILE__,__LINE__,info->device_name);
2133
2134         if (tty)
2135                 tty_wakeup(tty);
2136 }
2137
2138 static void bh_status(SLMP_INFO *info)
2139 {
2140         if ( debug_level >= DEBUG_LEVEL_BH )
2141                 printk( "%s(%d):%s bh_status() entry\n",
2142                         __FILE__,__LINE__,info->device_name);
2143
2144         info->ri_chkcount = 0;
2145         info->dsr_chkcount = 0;
2146         info->dcd_chkcount = 0;
2147         info->cts_chkcount = 0;
2148 }
2149
2150 static void isr_timer(SLMP_INFO * info)
2151 {
2152         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2153
2154         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2155         write_reg(info, IER2, 0);
2156
2157         /* TMCS, Timer Control/Status Register
2158          *
2159          * 07      CMF, Compare match flag (read only) 1=match
2160          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2161          * 05      Reserved, must be 0
2162          * 04      TME, Timer Enable
2163          * 03..00  Reserved, must be 0
2164          *
2165          * 0000 0000
2166          */
2167         write_reg(info, (unsigned char)(timer + TMCS), 0);
2168
2169         info->irq_occurred = true;
2170
2171         if ( debug_level >= DEBUG_LEVEL_ISR )
2172                 printk("%s(%d):%s isr_timer()\n",
2173                         __FILE__,__LINE__,info->device_name);
2174 }
2175
2176 static void isr_rxint(SLMP_INFO * info)
2177 {
2178         struct tty_struct *tty = info->tty;
2179         struct  mgsl_icount *icount = &info->icount;
2180         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2181         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2182
2183         /* clear status bits */
2184         if (status)
2185                 write_reg(info, SR1, status);
2186
2187         if (status2)
2188                 write_reg(info, SR2, status2);
2189
2190         if ( debug_level >= DEBUG_LEVEL_ISR )
2191                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2192                         __FILE__,__LINE__,info->device_name,status,status2);
2193
2194         if (info->params.mode == MGSL_MODE_ASYNC) {
2195                 if (status & BRKD) {
2196                         icount->brk++;
2197
2198                         /* process break detection if tty control
2199                          * is not set to ignore it
2200                          */
2201                         if ( tty ) {
2202                                 if (!(status & info->ignore_status_mask1)) {
2203                                         if (info->read_status_mask1 & BRKD) {
2204                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2205                                                 if (info->flags & ASYNC_SAK)
2206                                                         do_SAK(tty);
2207                                         }
2208                                 }
2209                         }
2210                 }
2211         }
2212         else {
2213                 if (status & (FLGD|IDLD)) {
2214                         if (status & FLGD)
2215                                 info->icount.exithunt++;
2216                         else if (status & IDLD)
2217                                 info->icount.rxidle++;
2218                         wake_up_interruptible(&info->event_wait_q);
2219                 }
2220         }
2221
2222         if (status & CDCD) {
2223                 /* simulate a common modem status change interrupt
2224                  * for our handler
2225                  */
2226                 get_signals( info );
2227                 isr_io_pin(info,
2228                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2229         }
2230 }
2231
2232 /*
2233  * handle async rx data interrupts
2234  */
2235 static void isr_rxrdy(SLMP_INFO * info)
2236 {
2237         u16 status;
2238         unsigned char DataByte;
2239         struct tty_struct *tty = info->tty;
2240         struct  mgsl_icount *icount = &info->icount;
2241
2242         if ( debug_level >= DEBUG_LEVEL_ISR )
2243                 printk("%s(%d):%s isr_rxrdy\n",
2244                         __FILE__,__LINE__,info->device_name);
2245
2246         while((status = read_reg(info,CST0)) & BIT0)
2247         {
2248                 int flag = 0;
2249                 bool over = false;
2250                 DataByte = read_reg(info,TRB);
2251
2252                 icount->rx++;
2253
2254                 if ( status & (PE + FRME + OVRN) ) {
2255                         printk("%s(%d):%s rxerr=%04X\n",
2256                                 __FILE__,__LINE__,info->device_name,status);
2257
2258                         /* update error statistics */
2259                         if (status & PE)
2260                                 icount->parity++;
2261                         else if (status & FRME)
2262                                 icount->frame++;
2263                         else if (status & OVRN)
2264                                 icount->overrun++;
2265
2266                         /* discard char if tty control flags say so */
2267                         if (status & info->ignore_status_mask2)
2268                                 continue;
2269
2270                         status &= info->read_status_mask2;
2271
2272                         if ( tty ) {
2273                                 if (status & PE)
2274                                         flag = TTY_PARITY;
2275                                 else if (status & FRME)
2276                                         flag = TTY_FRAME;
2277                                 if (status & OVRN) {
2278                                         /* Overrun is special, since it's
2279                                          * reported immediately, and doesn't
2280                                          * affect the current character
2281                                          */
2282                                         over = true;
2283                                 }
2284                         }
2285                 }       /* end of if (error) */
2286
2287                 if ( tty ) {
2288                         tty_insert_flip_char(tty, DataByte, flag);
2289                         if (over)
2290                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2291                 }
2292         }
2293
2294         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2295                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2296                         __FILE__,__LINE__,info->device_name,
2297                         icount->rx,icount->brk,icount->parity,
2298                         icount->frame,icount->overrun);
2299         }
2300
2301         if ( tty )
2302                 tty_flip_buffer_push(tty);
2303 }
2304
2305 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2306 {
2307         if ( debug_level >= DEBUG_LEVEL_ISR )
2308                 printk("%s(%d):%s isr_txeom status=%02x\n",
2309                         __FILE__,__LINE__,info->device_name,status);
2310
2311         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2312         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2313         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2314
2315         if (status & UDRN) {
2316                 write_reg(info, CMD, TXRESET);
2317                 write_reg(info, CMD, TXENABLE);
2318         } else
2319                 write_reg(info, CMD, TXBUFCLR);
2320
2321         /* disable and clear tx interrupts */
2322         info->ie0_value &= ~TXRDYE;
2323         info->ie1_value &= ~(IDLE + UDRN);
2324         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2325         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2326
2327         if ( info->tx_active ) {
2328                 if (info->params.mode != MGSL_MODE_ASYNC) {
2329                         if (status & UDRN)
2330                                 info->icount.txunder++;
2331                         else if (status & IDLE)
2332                                 info->icount.txok++;
2333                 }
2334
2335                 info->tx_active = false;
2336                 info->tx_count = info->tx_put = info->tx_get = 0;
2337
2338                 del_timer(&info->tx_timer);
2339
2340                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2341                         info->serial_signals &= ~SerialSignal_RTS;
2342                         info->drop_rts_on_tx_done = false;
2343                         set_signals(info);
2344                 }
2345
2346 #if SYNCLINK_GENERIC_HDLC
2347                 if (info->netcount)
2348                         hdlcdev_tx_done(info);
2349                 else
2350 #endif
2351                 {
2352                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2353                                 tx_stop(info);
2354                                 return;
2355                         }
2356                         info->pending_bh |= BH_TRANSMIT;
2357                 }
2358         }
2359 }
2360
2361
2362 /*
2363  * handle tx status interrupts
2364  */
2365 static void isr_txint(SLMP_INFO * info)
2366 {
2367         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2368
2369         /* clear status bits */
2370         write_reg(info, SR1, status);
2371
2372         if ( debug_level >= DEBUG_LEVEL_ISR )
2373                 printk("%s(%d):%s isr_txint status=%02x\n",
2374                         __FILE__,__LINE__,info->device_name,status);
2375
2376         if (status & (UDRN + IDLE))
2377                 isr_txeom(info, status);
2378
2379         if (status & CCTS) {
2380                 /* simulate a common modem status change interrupt
2381                  * for our handler
2382                  */
2383                 get_signals( info );
2384                 isr_io_pin(info,
2385                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2386
2387         }
2388 }
2389
2390 /*
2391  * handle async tx data interrupts
2392  */
2393 static void isr_txrdy(SLMP_INFO * info)
2394 {
2395         if ( debug_level >= DEBUG_LEVEL_ISR )
2396                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2397                         __FILE__,__LINE__,info->device_name,info->tx_count);
2398
2399         if (info->params.mode != MGSL_MODE_ASYNC) {
2400                 /* disable TXRDY IRQ, enable IDLE IRQ */
2401                 info->ie0_value &= ~TXRDYE;
2402                 info->ie1_value |= IDLE;
2403                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2404                 return;
2405         }
2406
2407         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2408                 tx_stop(info);
2409                 return;
2410         }
2411
2412         if ( info->tx_count )
2413                 tx_load_fifo( info );
2414         else {
2415                 info->tx_active = false;
2416                 info->ie0_value &= ~TXRDYE;
2417                 write_reg(info, IE0, info->ie0_value);
2418         }
2419
2420         if (info->tx_count < WAKEUP_CHARS)
2421                 info->pending_bh |= BH_TRANSMIT;
2422 }
2423
2424 static void isr_rxdmaok(SLMP_INFO * info)
2425 {
2426         /* BIT7 = EOT (end of transfer)
2427          * BIT6 = EOM (end of message/frame)
2428          */
2429         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2430
2431         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2432         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2433
2434         if ( debug_level >= DEBUG_LEVEL_ISR )
2435                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2436                         __FILE__,__LINE__,info->device_name,status);
2437
2438         info->pending_bh |= BH_RECEIVE;
2439 }
2440
2441 static void isr_rxdmaerror(SLMP_INFO * info)
2442 {
2443         /* BIT5 = BOF (buffer overflow)
2444          * BIT4 = COF (counter overflow)
2445          */
2446         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2447
2448         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2449         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2450
2451         if ( debug_level >= DEBUG_LEVEL_ISR )
2452                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2453                         __FILE__,__LINE__,info->device_name,status);
2454
2455         info->rx_overflow = true;
2456         info->pending_bh |= BH_RECEIVE;
2457 }
2458
2459 static void isr_txdmaok(SLMP_INFO * info)
2460 {
2461         unsigned char status_reg1 = read_reg(info, SR1);
2462
2463         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2464         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2465         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2466
2467         if ( debug_level >= DEBUG_LEVEL_ISR )
2468                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2469                         __FILE__,__LINE__,info->device_name,status_reg1);
2470
2471         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2472         write_reg16(info, TRC0, 0);
2473         info->ie0_value |= TXRDYE;
2474         write_reg(info, IE0, info->ie0_value);
2475 }
2476
2477 static void isr_txdmaerror(SLMP_INFO * info)
2478 {
2479         /* BIT5 = BOF (buffer overflow)
2480          * BIT4 = COF (counter overflow)
2481          */
2482         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2483
2484         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2485         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2486
2487         if ( debug_level >= DEBUG_LEVEL_ISR )
2488                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2489                         __FILE__,__LINE__,info->device_name,status);
2490 }
2491
2492 /* handle input serial signal changes
2493  */
2494 static void isr_io_pin( SLMP_INFO *info, u16 status )
2495 {
2496         struct  mgsl_icount *icount;
2497
2498         if ( debug_level >= DEBUG_LEVEL_ISR )
2499                 printk("%s(%d):isr_io_pin status=%04X\n",
2500                         __FILE__,__LINE__,status);
2501
2502         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2503                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2504                 icount = &info->icount;
2505                 /* update input line counters */
2506                 if (status & MISCSTATUS_RI_LATCHED) {
2507                         icount->rng++;
2508                         if ( status & SerialSignal_RI )
2509                                 info->input_signal_events.ri_up++;
2510                         else
2511                                 info->input_signal_events.ri_down++;
2512                 }
2513                 if (status & MISCSTATUS_DSR_LATCHED) {
2514                         icount->dsr++;
2515                         if ( status & SerialSignal_DSR )
2516                                 info->input_signal_events.dsr_up++;
2517                         else
2518                                 info->input_signal_events.dsr_down++;
2519                 }
2520                 if (status & MISCSTATUS_DCD_LATCHED) {
2521                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2522                                 info->ie1_value &= ~CDCD;
2523                                 write_reg(info, IE1, info->ie1_value);
2524                         }
2525                         icount->dcd++;
2526                         if (status & SerialSignal_DCD) {
2527                                 info->input_signal_events.dcd_up++;
2528                         } else
2529                                 info->input_signal_events.dcd_down++;
2530 #if SYNCLINK_GENERIC_HDLC
2531                         if (info->netcount) {
2532                                 if (status & SerialSignal_DCD)
2533                                         netif_carrier_on(info->netdev);
2534                                 else
2535                                         netif_carrier_off(info->netdev);
2536                         }
2537 #endif
2538                 }
2539                 if (status & MISCSTATUS_CTS_LATCHED)
2540                 {
2541                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2542                                 info->ie1_value &= ~CCTS;
2543                                 write_reg(info, IE1, info->ie1_value);
2544                         }
2545                         icount->cts++;
2546                         if ( status & SerialSignal_CTS )
2547                                 info->input_signal_events.cts_up++;
2548                         else
2549                                 info->input_signal_events.cts_down++;
2550                 }
2551                 wake_up_interruptible(&info->status_event_wait_q);
2552                 wake_up_interruptible(&info->event_wait_q);
2553
2554                 if ( (info->flags & ASYNC_CHECK_CD) &&
2555                      (status & MISCSTATUS_DCD_LATCHED) ) {
2556                         if ( debug_level >= DEBUG_LEVEL_ISR )
2557                                 printk("%s CD now %s...", info->device_name,
2558                                        (status & SerialSignal_DCD) ? "on" : "off");
2559                         if (status & SerialSignal_DCD)
2560                                 wake_up_interruptible(&info->open_wait);
2561                         else {
2562                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2563                                         printk("doing serial hangup...");
2564                                 if (info->tty)
2565                                         tty_hangup(info->tty);
2566                         }
2567                 }
2568
2569                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2570                      (status & MISCSTATUS_CTS_LATCHED) ) {
2571                         if ( info->tty ) {
2572                                 if (info->tty->hw_stopped) {
2573                                         if (status & SerialSignal_CTS) {
2574                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2575                                                         printk("CTS tx start...");
2576                                                 info->tty->hw_stopped = 0;
2577                                                 tx_start(info);
2578                                                 info->pending_bh |= BH_TRANSMIT;
2579                                                 return;
2580                                         }
2581                                 } else {
2582                                         if (!(status & SerialSignal_CTS)) {
2583                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2584                                                         printk("CTS tx stop...");
2585                                                 info->tty->hw_stopped = 1;
2586                                                 tx_stop(info);
2587                                         }
2588                                 }
2589                         }
2590                 }
2591         }
2592
2593         info->pending_bh |= BH_STATUS;
2594 }
2595
2596 /* Interrupt service routine entry point.
2597  *
2598  * Arguments:
2599  *      irq             interrupt number that caused interrupt
2600  *      dev_id          device ID supplied during interrupt registration
2601  *      regs            interrupted processor context
2602  */
2603 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2604 {
2605         SLMP_INFO *info = dev_id;
2606         unsigned char status, status0, status1=0;
2607         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2608         unsigned char timerstatus0, timerstatus1=0;
2609         unsigned char shift;
2610         unsigned int i;
2611         unsigned short tmp;
2612
2613         if ( debug_level >= DEBUG_LEVEL_ISR )
2614                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2615                         __FILE__, __LINE__, info->irq_level);
2616
2617         spin_lock(&info->lock);
2618
2619         for(;;) {
2620
2621                 /* get status for SCA0 (ports 0-1) */
2622                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2623                 status0 = (unsigned char)tmp;
2624                 dmastatus0 = (unsigned char)(tmp>>8);
2625                 timerstatus0 = read_reg(info, ISR2);
2626
2627                 if ( debug_level >= DEBUG_LEVEL_ISR )
2628                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2629                                 __FILE__, __LINE__, info->device_name,
2630                                 status0, dmastatus0, timerstatus0);
2631
2632                 if (info->port_count == 4) {
2633                         /* get status for SCA1 (ports 2-3) */
2634                         tmp = read_reg16(info->port_array[2], ISR0);
2635                         status1 = (unsigned char)tmp;
2636                         dmastatus1 = (unsigned char)(tmp>>8);
2637                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2638
2639                         if ( debug_level >= DEBUG_LEVEL_ISR )
2640                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2641                                         __FILE__,__LINE__,info->device_name,
2642                                         status1,dmastatus1,timerstatus1);
2643                 }
2644
2645                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2646                          !status1 && !dmastatus1 && !timerstatus1)
2647                         break;
2648
2649                 for(i=0; i < info->port_count ; i++) {
2650                         if (info->port_array[i] == NULL)
2651                                 continue;
2652                         if (i < 2) {
2653                                 status = status0;
2654                                 dmastatus = dmastatus0;
2655                         } else {
2656                                 status = status1;
2657                                 dmastatus = dmastatus1;
2658                         }
2659
2660                         shift = i & 1 ? 4 :0;
2661
2662                         if (status & BIT0 << shift)
2663                                 isr_rxrdy(info->port_array[i]);
2664                         if (status & BIT1 << shift)
2665                                 isr_txrdy(info->port_array[i]);
2666                         if (status & BIT2 << shift)
2667                                 isr_rxint(info->port_array[i]);
2668                         if (status & BIT3 << shift)
2669                                 isr_txint(info->port_array[i]);
2670
2671                         if (dmastatus & BIT0 << shift)
2672                                 isr_rxdmaerror(info->port_array[i]);
2673                         if (dmastatus & BIT1 << shift)
2674                                 isr_rxdmaok(info->port_array[i]);
2675                         if (dmastatus & BIT2 << shift)
2676                                 isr_txdmaerror(info->port_array[i]);
2677                         if (dmastatus & BIT3 << shift)
2678                                 isr_txdmaok(info->port_array[i]);
2679                 }
2680
2681                 if (timerstatus0 & (BIT5 | BIT4))
2682                         isr_timer(info->port_array[0]);
2683                 if (timerstatus0 & (BIT7 | BIT6))
2684                         isr_timer(info->port_array[1]);
2685                 if (timerstatus1 & (BIT5 | BIT4))
2686                         isr_timer(info->port_array[2]);
2687                 if (timerstatus1 & (BIT7 | BIT6))
2688                         isr_timer(info->port_array[3]);
2689         }
2690
2691         for(i=0; i < info->port_count ; i++) {
2692                 SLMP_INFO * port = info->port_array[i];
2693
2694                 /* Request bottom half processing if there's something
2695                  * for it to do and the bh is not already running.
2696                  *
2697                  * Note: startup adapter diags require interrupts.
2698                  * do not request bottom half processing if the
2699                  * device is not open in a normal mode.
2700                  */
2701                 if ( port && (port->count || port->netcount) &&
2702                      port->pending_bh && !port->bh_running &&
2703                      !port->bh_requested ) {
2704                         if ( debug_level >= DEBUG_LEVEL_ISR )
2705                                 printk("%s(%d):%s queueing bh task.\n",
2706                                         __FILE__,__LINE__,port->device_name);
2707                         schedule_work(&port->task);
2708                         port->bh_requested = true;
2709                 }
2710         }
2711
2712         spin_unlock(&info->lock);
2713
2714         if ( debug_level >= DEBUG_LEVEL_ISR )
2715                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2716                         __FILE__, __LINE__, info->irq_level);
2717         return IRQ_HANDLED;
2718 }
2719
2720 /* Initialize and start device.
2721  */
2722 static int startup(SLMP_INFO * info)
2723 {
2724         if ( debug_level >= DEBUG_LEVEL_INFO )
2725                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2726
2727         if (info->flags & ASYNC_INITIALIZED)
2728                 return 0;
2729
2730         if (!info->tx_buf) {
2731                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2732                 if (!info->tx_buf) {
2733                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2734                                 __FILE__,__LINE__,info->device_name);
2735                         return -ENOMEM;
2736                 }
2737         }
2738
2739         info->pending_bh = 0;
2740
2741         memset(&info->icount, 0, sizeof(info->icount));
2742
2743         /* program hardware for current parameters */
2744         reset_port(info);
2745
2746         change_params(info);
2747
2748         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2749
2750         if (info->tty)
2751                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2752
2753         info->flags |= ASYNC_INITIALIZED;
2754
2755         return 0;
2756 }
2757
2758 /* Called by close() and hangup() to shutdown hardware
2759  */
2760 static void shutdown(SLMP_INFO * info)
2761 {
2762         unsigned long flags;
2763
2764         if (!(info->flags & ASYNC_INITIALIZED))
2765                 return;
2766
2767         if (debug_level >= DEBUG_LEVEL_INFO)
2768                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2769                          __FILE__,__LINE__, info->device_name );
2770
2771         /* clear status wait queue because status changes */
2772         /* can't happen after shutting down the hardware */
2773         wake_up_interruptible(&info->status_event_wait_q);
2774         wake_up_interruptible(&info->event_wait_q);
2775
2776         del_timer(&info->tx_timer);
2777         del_timer(&info->status_timer);
2778
2779         kfree(info->tx_buf);
2780         info->tx_buf = NULL;
2781
2782         spin_lock_irqsave(&info->lock,flags);
2783
2784         reset_port(info);
2785
2786         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2787                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2788                 set_signals(info);
2789         }
2790
2791         spin_unlock_irqrestore(&info->lock,flags);
2792
2793         if (info->tty)
2794                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2795
2796         info->flags &= ~ASYNC_INITIALIZED;
2797 }
2798
2799 static void program_hw(SLMP_INFO *info)
2800 {
2801         unsigned long flags;
2802
2803         spin_lock_irqsave(&info->lock,flags);
2804
2805         rx_stop(info);
2806         tx_stop(info);
2807
2808         info->tx_count = info->tx_put = info->tx_get = 0;
2809
2810         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2811                 hdlc_mode(info);
2812         else
2813                 async_mode(info);
2814
2815         set_signals(info);
2816
2817         info->dcd_chkcount = 0;
2818         info->cts_chkcount = 0;
2819         info->ri_chkcount = 0;
2820         info->dsr_chkcount = 0;
2821
2822         info->ie1_value |= (CDCD|CCTS);
2823         write_reg(info, IE1, info->ie1_value);
2824
2825         get_signals(info);
2826
2827         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2828                 rx_start(info);
2829
2830         spin_unlock_irqrestore(&info->lock,flags);
2831 }
2832
2833 /* Reconfigure adapter based on new parameters
2834  */
2835 static void change_params(SLMP_INFO *info)
2836 {
2837         unsigned cflag;
2838         int bits_per_char;
2839
2840         if (!info->tty || !info->tty->termios)
2841                 return;
2842
2843         if (debug_level >= DEBUG_LEVEL_INFO)
2844                 printk("%s(%d):%s change_params()\n",
2845                          __FILE__,__LINE__, info->device_name );
2846
2847         cflag = info->tty->termios->c_cflag;
2848
2849         /* if B0 rate (hangup) specified then negate DTR and RTS */
2850         /* otherwise assert DTR and RTS */
2851         if (cflag & CBAUD)
2852                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2853         else
2854                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2855
2856         /* byte size and parity */
2857
2858         switch (cflag & CSIZE) {
2859               case CS5: info->params.data_bits = 5; break;
2860               case CS6: info->params.data_bits = 6; break;
2861               case CS7: info->params.data_bits = 7; break;
2862               case CS8: info->params.data_bits = 8; break;
2863               /* Never happens, but GCC is too dumb to figure it out */
2864               default:  info->params.data_bits = 7; break;
2865               }
2866
2867         if (cflag & CSTOPB)
2868                 info->params.stop_bits = 2;
2869         else
2870                 info->params.stop_bits = 1;
2871
2872         info->params.parity = ASYNC_PARITY_NONE;
2873         if (cflag & PARENB) {
2874                 if (cflag & PARODD)
2875                         info->params.parity = ASYNC_PARITY_ODD;
2876                 else
2877                         info->params.parity = ASYNC_PARITY_EVEN;
2878 #ifdef CMSPAR
2879                 if (cflag & CMSPAR)
2880                         info->params.parity = ASYNC_PARITY_SPACE;
2881 #endif
2882         }
2883
2884         /* calculate number of jiffies to transmit a full
2885          * FIFO (32 bytes) at specified data rate
2886          */
2887         bits_per_char = info->params.data_bits +
2888                         info->params.stop_bits + 1;
2889
2890         /* if port data rate is set to 460800 or less then
2891          * allow tty settings to override, otherwise keep the
2892          * current data rate.
2893          */
2894         if (info->params.data_rate <= 460800) {
2895                 info->params.data_rate = tty_get_baud_rate(info->tty);
2896         }
2897
2898         if ( info->params.data_rate ) {
2899                 info->timeout = (32*HZ*bits_per_char) /
2900                                 info->params.data_rate;
2901         }
2902         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2903
2904         if (cflag & CRTSCTS)
2905                 info->flags |= ASYNC_CTS_FLOW;
2906         else
2907                 info->flags &= ~ASYNC_CTS_FLOW;
2908
2909         if (cflag & CLOCAL)
2910                 info->flags &= ~ASYNC_CHECK_CD;
2911         else
2912                 info->flags |= ASYNC_CHECK_CD;
2913
2914         /* process tty input control flags */
2915
2916         info->read_status_mask2 = OVRN;
2917         if (I_INPCK(info->tty))
2918                 info->read_status_mask2 |= PE | FRME;
2919         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2920                 info->read_status_mask1 |= BRKD;
2921         if (I_IGNPAR(info->tty))
2922                 info->ignore_status_mask2 |= PE | FRME;
2923         if (I_IGNBRK(info->tty)) {
2924                 info->ignore_status_mask1 |= BRKD;
2925                 /* If ignoring parity and break indicators, ignore
2926                  * overruns too.  (For real raw support).
2927                  */
2928                 if (I_IGNPAR(info->tty))
2929                         info->ignore_status_mask2 |= OVRN;
2930         }
2931
2932         program_hw(info);
2933 }
2934
2935 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2936 {
2937         int err;
2938
2939         if (debug_level >= DEBUG_LEVEL_INFO)
2940                 printk("%s(%d):%s get_params()\n",
2941                          __FILE__,__LINE__, info->device_name);
2942
2943         if (!user_icount) {
2944                 memset(&info->icount, 0, sizeof(info->icount));
2945         } else {
2946                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2947                 if (err)
2948                         return -EFAULT;
2949         }
2950
2951         return 0;
2952 }
2953
2954 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2955 {
2956         int err;
2957         if (debug_level >= DEBUG_LEVEL_INFO)
2958                 printk("%s(%d):%s get_params()\n",
2959                          __FILE__,__LINE__, info->device_name);
2960
2961         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2962         if (err) {
2963                 if ( debug_level >= DEBUG_LEVEL_INFO )
2964                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2965                                 __FILE__,__LINE__,info->device_name);
2966                 return -EFAULT;
2967         }
2968
2969         return 0;
2970 }
2971
2972 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2973 {
2974         unsigned long flags;
2975         MGSL_PARAMS tmp_params;
2976         int err;
2977
2978         if (debug_level >= DEBUG_LEVEL_INFO)
2979                 printk("%s(%d):%s set_params\n",
2980                         __FILE__,__LINE__,info->device_name );
2981         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2982         if (err) {
2983                 if ( debug_level >= DEBUG_LEVEL_INFO )
2984                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2985                                 __FILE__,__LINE__,info->device_name);
2986                 return -EFAULT;
2987         }
2988
2989         spin_lock_irqsave(&info->lock,flags);
2990         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2991         spin_unlock_irqrestore(&info->lock,flags);
2992
2993         change_params(info);
2994
2995         return 0;
2996 }
2997
2998 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2999 {
3000         int err;
3001
3002         if (debug_level >= DEBUG_LEVEL_INFO)
3003                 printk("%s(%d):%s get_txidle()=%d\n",
3004                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3005
3006         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3007         if (err) {
3008                 if ( debug_level >= DEBUG_LEVEL_INFO )
3009                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3010                                 __FILE__,__LINE__,info->device_name);
3011                 return -EFAULT;
3012         }
3013
3014         return 0;
3015 }
3016
3017 static int set_txidle(SLMP_INFO * info, int idle_mode)
3018 {
3019         unsigned long flags;
3020
3021         if (debug_level >= DEBUG_LEVEL_INFO)
3022                 printk("%s(%d):%s set_txidle(%d)\n",
3023                         __FILE__,__LINE__,info->device_name, idle_mode );
3024
3025         spin_lock_irqsave(&info->lock,flags);
3026         info->idle_mode = idle_mode;
3027         tx_set_idle( info );
3028         spin_unlock_irqrestore(&info->lock,flags);
3029         return 0;
3030 }
3031
3032 static int tx_enable(SLMP_INFO * info, int enable)
3033 {
3034         unsigned long flags;
3035
3036         if (debug_level >= DEBUG_LEVEL_INFO)
3037                 printk("%s(%d):%s tx_enable(%d)\n",
3038                         __FILE__,__LINE__,info->device_name, enable);
3039
3040         spin_lock_irqsave(&info->lock,flags);
3041         if ( enable ) {
3042                 if ( !info->tx_enabled ) {
3043                         tx_start(info);
3044                 }
3045         } else {
3046                 if ( info->tx_enabled )
3047                         tx_stop(info);
3048         }
3049         spin_unlock_irqrestore(&info->lock,flags);
3050         return 0;
3051 }
3052
3053 /* abort send HDLC frame
3054  */
3055 static int tx_abort(SLMP_INFO * info)
3056 {
3057         unsigned long flags;
3058
3059         if (debug_level >= DEBUG_LEVEL_INFO)
3060                 printk("%s(%d):%s tx_abort()\n",
3061                         __FILE__,__LINE__,info->device_name);
3062
3063         spin_lock_irqsave(&info->lock,flags);
3064         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3065                 info->ie1_value &= ~UDRN;
3066                 info->ie1_value |= IDLE;
3067                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3068                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3069
3070                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3071                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3072
3073                 write_reg(info, CMD, TXABORT);
3074         }
3075         spin_unlock_irqrestore(&info->lock,flags);
3076         return 0;
3077 }
3078
3079 static int rx_enable(SLMP_INFO * info, int enable)
3080 {
3081         unsigned long flags;
3082
3083         if (debug_level >= DEBUG_LEVEL_INFO)
3084                 printk("%s(%d):%s rx_enable(%d)\n",
3085                         __FILE__,__LINE__,info->device_name,enable);
3086
3087         spin_lock_irqsave(&info->lock,flags);
3088         if ( enable ) {
3089                 if ( !info->rx_enabled )
3090                         rx_start(info);
3091         } else {
3092                 if ( info->rx_enabled )
3093                         rx_stop(info);
3094         }
3095         spin_unlock_irqrestore(&info->lock,flags);
3096         return 0;
3097 }
3098
3099 /* wait for specified event to occur
3100  */
3101 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3102 {
3103         unsigned long flags;
3104         int s;
3105         int rc=0;
3106         struct mgsl_icount cprev, cnow;
3107         int events;
3108         int mask;
3109         struct  _input_signal_events oldsigs, newsigs;
3110         DECLARE_WAITQUEUE(wait, current);
3111
3112         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3113         if (rc) {
3114                 return  -EFAULT;
3115         }
3116
3117         if (debug_level >= DEBUG_LEVEL_INFO)
3118                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3119                         __FILE__,__LINE__,info->device_name,mask);
3120
3121         spin_lock_irqsave(&info->lock,flags);
3122
3123         /* return immediately if state matches requested events */
3124         get_signals(info);
3125         s = info->serial_signals;
3126
3127         events = mask &
3128                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3129                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3130                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3131                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3132         if (events) {
3133                 spin_unlock_irqrestore(&info->lock,flags);
3134                 goto exit;
3135         }
3136
3137         /* save current irq counts */
3138         cprev = info->icount;
3139         oldsigs = info->input_signal_events;
3140
3141         /* enable hunt and idle irqs if needed */
3142         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3143                 unsigned char oldval = info->ie1_value;
3144                 unsigned char newval = oldval +
3145                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3146                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3147                 if ( oldval != newval ) {
3148                         info->ie1_value = newval;
3149                         write_reg(info, IE1, info->ie1_value);
3150                 }
3151         }
3152
3153         set_current_state(TASK_INTERRUPTIBLE);
3154         add_wait_queue(&info->event_wait_q, &wait);
3155
3156         spin_unlock_irqrestore(&info->lock,flags);
3157
3158         for(;;) {
3159                 schedule();
3160                 if (signal_pending(current)) {
3161                         rc = -ERESTARTSYS;
3162                         break;
3163                 }
3164
3165                 /* get current irq counts */
3166                 spin_lock_irqsave(&info->lock,flags);
3167                 cnow = info->icount;
3168                 newsigs = info->input_signal_events;
3169                 set_current_state(TASK_INTERRUPTIBLE);
3170                 spin_unlock_irqrestore(&info->lock,flags);
3171
3172                 /* if no change, wait aborted for some reason */
3173                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3174                     newsigs.dsr_down == oldsigs.dsr_down &&
3175                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3176                     newsigs.dcd_down == oldsigs.dcd_down &&
3177                     newsigs.cts_up   == oldsigs.cts_up   &&
3178                     newsigs.cts_down == oldsigs.cts_down &&
3179                     newsigs.ri_up    == oldsigs.ri_up    &&
3180                     newsigs.ri_down  == oldsigs.ri_down  &&
3181                     cnow.exithunt    == cprev.exithunt   &&
3182                     cnow.rxidle      == cprev.rxidle) {
3183                         rc = -EIO;
3184                         break;
3185                 }
3186
3187                 events = mask &
3188                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3189                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3190                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3191                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3192                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3193                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3194                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3195                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3196                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3197                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3198                 if (events)
3199                         break;
3200
3201                 cprev = cnow;
3202                 oldsigs = newsigs;
3203         }
3204
3205         remove_wait_queue(&info->event_wait_q, &wait);
3206         set_current_state(TASK_RUNNING);
3207
3208
3209         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3210                 spin_lock_irqsave(&info->lock,flags);
3211                 if (!waitqueue_active(&info->event_wait_q)) {
3212                         /* disable enable exit hunt mode/idle rcvd IRQs */
3213                         info->ie1_value &= ~(FLGD|IDLD);
3214                         write_reg(info, IE1, info->ie1_value);
3215                 }
3216                 spin_unlock_irqrestore(&info->lock,flags);
3217         }
3218 exit:
3219         if ( rc == 0 )
3220                 PUT_USER(rc, events, mask_ptr);
3221
3222         return rc;
3223 }
3224
3225 static int modem_input_wait(SLMP_INFO *info,int arg)
3226 {
3227         unsigned long flags;
3228         int rc;
3229         struct mgsl_icount cprev, cnow;
3230         DECLARE_WAITQUEUE(wait, current);
3231
3232         /* save current irq counts */
3233         spin_lock_irqsave(&info->lock,flags);
3234         cprev = info->icount;
3235         add_wait_queue(&info->status_event_wait_q, &wait);
3236         set_current_state(TASK_INTERRUPTIBLE);
3237         spin_unlock_irqrestore(&info->lock,flags);
3238
3239         for(;;) {
3240                 schedule();
3241                 if (signal_pending(current)) {
3242                         rc = -ERESTARTSYS;
3243                         break;
3244                 }
3245
3246                 /* get new irq counts */
3247                 spin_lock_irqsave(&info->lock,flags);
3248                 cnow = info->icount;
3249                 set_current_state(TASK_INTERRUPTIBLE);
3250                 spin_unlock_irqrestore(&info->lock,flags);
3251
3252                 /* if no change, wait aborted for some reason */
3253                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3254                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3255                         rc = -EIO;
3256                         break;
3257                 }
3258
3259                 /* check for change in caller specified modem input */
3260                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3261                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3262                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3263                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3264                         rc = 0;
3265                         break;
3266                 }
3267
3268                 cprev = cnow;
3269         }
3270         remove_wait_queue(&info->status_event_wait_q, &wait);
3271         set_current_state(TASK_RUNNING);
3272         return rc;
3273 }
3274
3275 /* return the state of the serial control and status signals
3276  */
3277 static int tiocmget(struct tty_struct *tty, struct file *file)
3278 {
3279         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3280         unsigned int result;
3281         unsigned long flags;
3282
3283         spin_lock_irqsave(&info->lock,flags);
3284         get_signals(info);
3285         spin_unlock_irqrestore(&info->lock,flags);
3286
3287         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3288                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3289                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3290                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3291                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3292                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3293
3294         if (debug_level >= DEBUG_LEVEL_INFO)
3295                 printk("%s(%d):%s tiocmget() value=%08X\n",
3296                          __FILE__,__LINE__, info->device_name, result );
3297         return result;
3298 }
3299
3300 /* set modem control signals (DTR/RTS)
3301  */
3302 static int tiocmset(struct tty_struct *tty, struct file *file,
3303                     unsigned int set, unsigned int clear)
3304 {
3305         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3306         unsigned long flags;
3307
3308         if (debug_level >= DEBUG_LEVEL_INFO)
3309                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3310                         __FILE__,__LINE__,info->device_name, set, clear);
3311
3312         if (set & TIOCM_RTS)
3313                 info->serial_signals |= SerialSignal_RTS;
3314         if (set & TIOCM_DTR)
3315                 info->serial_signals |= SerialSignal_DTR;
3316         if (clear & TIOCM_RTS)
3317                 info->serial_signals &= ~SerialSignal_RTS;
3318         if (clear & TIOCM_DTR)
3319                 info->serial_signals &= ~SerialSignal_DTR;
3320
3321         spin_lock_irqsave(&info->lock,flags);
3322         set_signals(info);
3323         spin_unlock_irqrestore(&info->lock,flags);
3324
3325         return 0;
3326 }
3327
3328
3329
3330 /* Block the current process until the specified port is ready to open.
3331  */
3332 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3333                            SLMP_INFO *info)
3334 {
3335         DECLARE_WAITQUEUE(wait, current);
3336         int             retval;
3337         bool            do_clocal = false;
3338         bool            extra_count = false;
3339         unsigned long   flags;
3340
3341         if (debug_level >= DEBUG_LEVEL_INFO)
3342                 printk("%s(%d):%s block_til_ready()\n",
3343                          __FILE__,__LINE__, tty->driver->name );
3344
3345         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3346                 /* nonblock mode is set or port is not enabled */
3347                 /* just verify that callout device is not active */
3348                 info->flags |= ASYNC_NORMAL_ACTIVE;
3349                 return 0;
3350         }
3351
3352         if (tty->termios->c_cflag & CLOCAL)
3353                 do_clocal = true;
3354
3355         /* Wait for carrier detect and the line to become
3356          * free (i.e., not in use by the callout).  While we are in
3357          * this loop, info->count is dropped by one, so that
3358          * close() knows when to free things.  We restore it upon
3359          * exit, either normal or abnormal.
3360          */
3361
3362         retval = 0;
3363         add_wait_queue(&info->open_wait, &wait);
3364
3365         if (debug_level >= DEBUG_LEVEL_INFO)
3366                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3367                          __FILE__,__LINE__, tty->driver->name, info->count );
3368
3369         spin_lock_irqsave(&info->lock, flags);
3370         if (!tty_hung_up_p(filp)) {
3371                 extra_count = true;
3372                 info->count--;
3373         }
3374         spin_unlock_irqrestore(&info->lock, flags);
3375         info->blocked_open++;
3376
3377         while (1) {
3378                 if ((tty->termios->c_cflag & CBAUD)) {
3379                         spin_lock_irqsave(&info->lock,flags);
3380                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3381                         set_signals(info);
3382                         spin_unlock_irqrestore(&info->lock,flags);
3383                 }
3384
3385                 set_current_state(TASK_INTERRUPTIBLE);
3386
3387                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3388                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3389                                         -EAGAIN : -ERESTARTSYS;
3390                         break;
3391                 }
3392
3393                 spin_lock_irqsave(&info->lock,flags);
3394                 get_signals(info);
3395                 spin_unlock_irqrestore(&info->lock,flags);
3396
3397                 if (!(info->flags & ASYNC_CLOSING) &&
3398                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3399                         break;
3400                 }
3401
3402                 if (signal_pending(current)) {
3403                         retval = -ERESTARTSYS;
3404                         break;
3405                 }
3406
3407                 if (debug_level >= DEBUG_LEVEL_INFO)
3408                         printk("%s(%d):%s block_til_ready() count=%d\n",
3409                                  __FILE__,__LINE__, tty->driver->name, info->count );
3410
3411                 schedule();
3412         }
3413
3414         set_current_state(TASK_RUNNING);
3415         remove_wait_queue(&info->open_wait, &wait);
3416
3417         if (extra_count)
3418                 info->count++;
3419         info->blocked_open--;
3420
3421         if (debug_level >= DEBUG_LEVEL_INFO)
3422                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3423                          __FILE__,__LINE__, tty->driver->name, info->count );
3424
3425         if (!retval)
3426                 info->flags |= ASYNC_NORMAL_ACTIVE;
3427
3428         return retval;
3429 }
3430
3431 static int alloc_dma_bufs(SLMP_INFO *info)
3432 {
3433         unsigned short BuffersPerFrame;
3434         unsigned short BufferCount;
3435
3436         // Force allocation to start at 64K boundary for each port.
3437         // This is necessary because *all* buffer descriptors for a port
3438         // *must* be in the same 64K block. All descriptors on a port
3439         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3440         // into the CBP register.
3441         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3442
3443         /* Calculate the number of DMA buffers necessary to hold the */
3444         /* largest allowable frame size. Note: If the max frame size is */
3445         /* not an even multiple of the DMA buffer size then we need to */
3446         /* round the buffer count per frame up one. */
3447
3448         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3449         if ( info->max_frame_size % SCABUFSIZE )
3450                 BuffersPerFrame++;
3451
3452         /* calculate total number of data buffers (SCABUFSIZE) possible
3453          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3454          * for the descriptor list (BUFFERLISTSIZE).
3455          */
3456         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3457
3458         /* limit number of buffers to maximum amount of descriptors */
3459         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3460                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3461
3462         /* use enough buffers to transmit one max size frame */
3463         info->tx_buf_count = BuffersPerFrame + 1;
3464
3465         /* never use more than half the available buffers for transmit */
3466         if (info->tx_buf_count > (BufferCount/2))
3467                 info->tx_buf_count = BufferCount/2;
3468
3469         if (info->tx_buf_count > SCAMAXDESC)
3470                 info->tx_buf_count = SCAMAXDESC;
3471
3472         /* use remaining buffers for receive */
3473         info->rx_buf_count = BufferCount - info->tx_buf_count;
3474
3475         if (info->rx_buf_count > SCAMAXDESC)
3476                 info->rx_buf_count = SCAMAXDESC;
3477
3478         if ( debug_level >= DEBUG_LEVEL_INFO )
3479                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3480                         __FILE__,__LINE__, info->device_name,
3481                         info->tx_buf_count,info->rx_buf_count);
3482
3483         if ( alloc_buf_list( info ) < 0 ||
3484                 alloc_frame_bufs(info,
3485                                         info->rx_buf_list,
3486                                         info->rx_buf_list_ex,
3487                                         info->rx_buf_count) < 0 ||
3488                 alloc_frame_bufs(info,
3489                                         info->tx_buf_list,
3490                                         info->tx_buf_list_ex,
3491                                         info->tx_buf_count) < 0 ||
3492                 alloc_tmp_rx_buf(info) < 0 ) {
3493                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3494                         __FILE__,__LINE__, info->device_name);
3495                 return -ENOMEM;
3496         }
3497
3498         rx_reset_buffers( info );
3499
3500         return 0;
3501 }
3502
3503 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3504  */
3505 static int alloc_buf_list(SLMP_INFO *info)
3506 {
3507         unsigned int i;
3508
3509         /* build list in adapter shared memory */
3510         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3511         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3512         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3513
3514         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3515
3516         /* Save virtual address pointers to the receive and */
3517         /* transmit buffer lists. (Receive 1st). These pointers will */
3518         /* be used by the processor to access the lists. */
3519         info->rx_buf_list = (SCADESC *)info->buffer_list;
3520
3521         info->tx_buf_list = (SCADESC *)info->buffer_list;
3522         info->tx_buf_list += info->rx_buf_count;
3523
3524         /* Build links for circular buffer entry lists (tx and rx)
3525          *
3526          * Note: links are physical addresses read by the SCA device
3527          * to determine the next buffer entry to use.
3528          */
3529
3530         for ( i = 0; i < info->rx_buf_count; i++ ) {
3531                 /* calculate and store physical address of this buffer entry */
3532                 info->rx_buf_list_ex[i].phys_entry =
3533                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3534
3535                 /* calculate and store physical address of */
3536                 /* next entry in cirular list of entries */
3537                 info->rx_buf_list[i].next = info->buffer_list_phys;
3538                 if ( i < info->rx_buf_count - 1 )
3539                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3540
3541                 info->rx_buf_list[i].length = SCABUFSIZE;
3542         }
3543
3544         for ( i = 0; i < info->tx_buf_count; i++ ) {
3545                 /* calculate and store physical address of this buffer entry */
3546                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3547                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3548
3549                 /* calculate and store physical address of */
3550                 /* next entry in cirular list of entries */
3551
3552                 info->tx_buf_list[i].next = info->buffer_list_phys +
3553                         info->rx_buf_count * sizeof(SCADESC);
3554
3555                 if ( i < info->tx_buf_count - 1 )
3556                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3557         }
3558
3559         return 0;
3560 }
3561
3562 /* Allocate the frame DMA buffers used by the specified buffer list.
3563  */
3564 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3565 {
3566         int i;
3567         unsigned long phys_addr;
3568
3569         for ( i = 0; i < count; i++ ) {
3570                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3571                 phys_addr = info->port_array[0]->last_mem_alloc;
3572                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3573
3574                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3575                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3576         }
3577
3578         return 0;
3579 }
3580
3581 static void free_dma_bufs(SLMP_INFO *info)
3582 {
3583         info->buffer_list = NULL;
3584         info->rx_buf_list = NULL;
3585         info->tx_buf_list = NULL;
3586 }
3587
3588 /* allocate buffer large enough to hold max_frame_size.
3589  * This buffer is used to pass an assembled frame to the line discipline.
3590  */
3591 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3592 {
3593         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3594         if (info->tmp_rx_buf == NULL)
3595                 return -ENOMEM;
3596         return 0;
3597 }
3598
3599 static void free_tmp_rx_buf(SLMP_INFO *info)
3600 {
3601         kfree(info->tmp_rx_buf);
3602         info->tmp_rx_buf = NULL;
3603 }
3604
3605 static int claim_resources(SLMP_INFO *info)
3606 {
3607         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3608                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3609                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3610                 info->init_error = DiagStatus_AddressConflict;
3611                 goto errout;
3612         }
3613         else
3614                 info->shared_mem_requested = true;
3615
3616         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3617                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3618                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3619                 info->init_error = DiagStatus_AddressConflict;
3620                 goto errout;
3621         }
3622         else
3623                 info->lcr_mem_requested = true;
3624
3625         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3626                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3627                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3628                 info->init_error = DiagStatus_AddressConflict;
3629                 goto errout;
3630         }
3631         else
3632                 info->sca_base_requested = true;
3633
3634         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3635                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3636                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3637                 info->init_error = DiagStatus_AddressConflict;
3638                 goto errout;
3639         }
3640         else
3641                 info->sca_statctrl_requested = true;
3642
3643         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3644         if (!info->memory_base) {
3645                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3646                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3647                 info->init_error = DiagStatus_CantAssignPciResources;
3648                 goto errout;
3649         }
3650
3651         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3652         if (!info->lcr_base) {
3653                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3654                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3655                 info->init_error = DiagStatus_CantAssignPciResources;
3656                 goto errout;
3657         }
3658         info->lcr_base += info->lcr_offset;
3659
3660         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3661         if (!info->sca_base) {
3662                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3663                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3664                 info->init_error = DiagStatus_CantAssignPciResources;
3665                 goto errout;
3666         }
3667         info->sca_base += info->sca_offset;
3668
3669         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3670         if (!info->statctrl_base) {
3671                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3672                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3673                 info->init_error = DiagStatus_CantAssignPciResources;
3674                 goto errout;
3675         }
3676         info->statctrl_base += info->statctrl_offset;
3677
3678         if ( !memory_test(info) ) {
3679                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3680                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3681                 info->init_error = DiagStatus_MemoryError;
3682                 goto errout;
3683         }
3684
3685         return 0;
3686
3687 errout:
3688         release_resources( info );
3689         return -ENODEV;
3690 }
3691
3692 static void release_resources(SLMP_INFO *info)
3693 {
3694         if ( debug_level >= DEBUG_LEVEL_INFO )
3695                 printk( "%s(%d):%s release_resources() entry\n",
3696                         __FILE__,__LINE__,info->device_name );
3697
3698         if ( info->irq_requested ) {
3699                 free_irq(info->irq_level, info);
3700                 info->irq_requested = false;
3701         }
3702
3703         if ( info->shared_mem_requested ) {
3704                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3705                 info->shared_mem_requested = false;
3706         }
3707         if ( info->lcr_mem_requested ) {
3708                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3709                 info->lcr_mem_requested = false;
3710         }
3711         if ( info->sca_base_requested ) {
3712                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3713                 info->sca_base_requested = false;
3714         }
3715         if ( info->sca_statctrl_requested ) {
3716                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3717                 info->sca_statctrl_requested = false;
3718         }
3719
3720         if (info->memory_base){
3721                 iounmap(info->memory_base);
3722                 info->memory_base = NULL;
3723         }
3724
3725         if (info->sca_base) {
3726                 iounmap(info->sca_base - info->sca_offset);
3727                 info->sca_base=NULL;
3728         }
3729
3730         if (info->statctrl_base) {
3731                 iounmap(info->statctrl_base - info->statctrl_offset);
3732                 info->statctrl_base=NULL;
3733         }
3734
3735         if (info->lcr_base){
3736                 iounmap(info->lcr_base - info->lcr_offset);
3737                 info->lcr_base = NULL;
3738         }
3739
3740         if ( debug_level >= DEBUG_LEVEL_INFO )
3741                 printk( "%s(%d):%s release_resources() exit\n",
3742                         __FILE__,__LINE__,info->device_name );
3743 }
3744
3745 /* Add the specified device instance data structure to the
3746  * global linked list of devices and increment the device count.
3747  */
3748 static void add_device(SLMP_INFO *info)
3749 {
3750         info->next_device = NULL;
3751         info->line = synclinkmp_device_count;
3752         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3753
3754         if (info->line < MAX_DEVICES) {
3755                 if (maxframe[info->line])
3756                         info->max_frame_size = maxframe[info->line];
3757                 info->dosyncppp = dosyncppp[info->line];
3758         }
3759
3760         synclinkmp_device_count++;
3761
3762         if ( !synclinkmp_device_list )
3763                 synclinkmp_device_list = info;
3764         else {
3765                 SLMP_INFO *current_dev = synclinkmp_device_list;
3766                 while( current_dev->next_device )
3767                         current_dev = current_dev->next_device;
3768                 current_dev->next_device = info;
3769         }
3770
3771         if ( info->max_frame_size < 4096 )
3772                 info->max_frame_size = 4096;
3773         else if ( info->max_frame_size > 65535 )
3774                 info->max_frame_size = 65535;
3775
3776         printk( "SyncLink MultiPort %s: "
3777                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3778                 info->device_name,
3779                 info->phys_sca_base,
3780                 info->phys_memory_base,
3781                 info->phys_statctrl_base,
3782                 info->phys_lcr_base,
3783                 info->irq_level,
3784                 info->max_frame_size );
3785
3786 #if SYNCLINK_GENERIC_HDLC
3787         hdlcdev_init(info);
3788 #endif
3789 }
3790
3791 /* Allocate and initialize a device instance structure
3792  *
3793  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3794  */
3795 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3796 {
3797         SLMP_INFO *info;
3798
3799         info = kzalloc(sizeof(SLMP_INFO),
3800                  GFP_KERNEL);
3801
3802         if (!info) {
3803                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3804                         __FILE__,__LINE__, adapter_num, port_num);
3805         } else {
3806                 info->magic = MGSL_MAGIC;
3807                 INIT_WORK(&info->task, bh_handler);
3808                 info->max_frame_size = 4096;
3809                 info->close_delay = 5*HZ/10;
3810                 info->closing_wait = 30*HZ;
3811                 init_waitqueue_head(&info->open_wait);
3812                 init_waitqueue_head(&info->close_wait);
3813                 init_waitqueue_head(&info->status_event_wait_q);
3814                 init_waitqueue_head(&info->event_wait_q);
3815                 spin_lock_init(&info->netlock);
3816                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3817                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3818                 info->adapter_num = adapter_num;
3819                 info->port_num = port_num;
3820
3821                 /* Copy configuration info to device instance data */
3822                 info->irq_level = pdev->irq;
3823                 info->phys_lcr_base = pci_resource_start(pdev,0);
3824                 info->phys_sca_base = pci_resource_start(pdev,2);
3825                 info->phys_memory_base = pci_resource_start(pdev,3);
3826                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3827
3828                 /* Because veremap only works on page boundaries we must map
3829                  * a larger area than is actually implemented for the LCR
3830                  * memory range. We map a full page starting at the page boundary.
3831                  */
3832                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3833                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3834
3835                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3836                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3837
3838                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3839                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3840
3841                 info->bus_type = MGSL_BUS_TYPE_PCI;
3842                 info->irq_flags = IRQF_SHARED;
3843
3844                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3845                 setup_timer(&info->status_timer, status_timeout,
3846                                 (unsigned long)info);
3847
3848                 /* Store the PCI9050 misc control register value because a flaw
3849                  * in the PCI9050 prevents LCR registers from being read if
3850                  * BIOS assigns an LCR base address with bit 7 set.
3851                  *
3852                  * Only the misc control register is accessed for which only
3853                  * write access is needed, so set an initial value and change
3854                  * bits to the device instance data as we write the value
3855                  * to the actual misc control register.
3856                  */
3857                 info->misc_ctrl_value = 0x087e4546;
3858
3859                 /* initial port state is unknown - if startup errors
3860                  * occur, init_error will be set to indicate the
3861                  * problem. Once the port is fully initialized,
3862                  * this value will be set to 0 to indicate the
3863                  * port is available.
3864                  */
3865                 info->init_error = -1;
3866         }
3867
3868         return info;
3869 }
3870
3871 static void device_init(int adapter_num, struct pci_dev *pdev)
3872 {
3873         SLMP_INFO *port_array[SCA_MAX_PORTS];
3874         int port;
3875
3876         /* allocate device instances for up to SCA_MAX_PORTS devices */
3877         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3878                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3879                 if( port_array[port] == NULL ) {
3880                         for ( --port; port >= 0; --port )
3881                                 kfree(port_array[port]);
3882                         return;
3883                 }
3884         }
3885
3886         /* give copy of port_array to all ports and add to device list  */
3887         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3888                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3889                 add_device( port_array[port] );
3890                 spin_lock_init(&port_array[port]->lock);
3891         }
3892
3893         /* Allocate and claim adapter resources */
3894         if ( !claim_resources(port_array[0]) ) {
3895
3896                 alloc_dma_bufs(port_array[0]);
3897
3898                 /* copy resource information from first port to others */
3899                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3900                         port_array[port]->lock  = port_array[0]->lock;
3901                         port_array[port]->irq_level     = port_array[0]->irq_level;
3902                         port_array[port]->memory_base   = port_array[0]->memory_base;
3903                         port_array[port]->sca_base      = port_array[0]->sca_base;
3904                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3905                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3906                         alloc_dma_bufs(port_array[port]);
3907                 }
3908
3909                 if ( request_irq(port_array[0]->irq_level,
3910                                         synclinkmp_interrupt,
3911                                         port_array[0]->irq_flags,
3912                                         port_array[0]->device_name,
3913                                         port_array[0]) < 0 ) {
3914                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3915                                 __FILE__,__LINE__,
3916                                 port_array[0]->device_name,
3917                                 port_array[0]->irq_level );
3918                 }
3919                 else {
3920                         port_array[0]->irq_requested = true;
3921                         adapter_test(port_array[0]);
3922                 }
3923         }
3924 }
3925
3926 static const struct tty_operations ops = {
3927         .open = open,
3928         .close = close,
3929         .write = write,
3930         .put_char = put_char,
3931         .flush_chars = flush_chars,
3932         .write_room = write_room,
3933         .chars_in_buffer = chars_in_buffer,
3934         .flush_buffer = flush_buffer,
3935         .ioctl = ioctl,
3936         .throttle = throttle,
3937         .unthrottle = unthrottle,
3938         .send_xchar = send_xchar,
3939         .break_ctl = set_break,
3940         .wait_until_sent = wait_until_sent,
3941         .read_proc = read_proc,
3942         .set_termios = set_termios,
3943         .stop = tx_hold,
3944         .start = tx_release,
3945         .hangup = hangup,
3946         .tiocmget = tiocmget,
3947         .tiocmset = tiocmset,
3948 };
3949
3950 static void synclinkmp_cleanup(void)
3951 {
3952         int rc;
3953         SLMP_INFO *info;
3954         SLMP_INFO *tmp;
3955
3956         printk("Unloading %s %s\n", driver_name, driver_version);
3957
3958         if (serial_driver) {
3959                 if ((rc = tty_unregister_driver(serial_driver)))
3960                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3961                                __FILE__,__LINE__,rc);
3962                 put_tty_driver(serial_driver);
3963         }
3964
3965         /* reset devices */
3966         info = synclinkmp_device_list;
3967         while(info) {
3968                 reset_port(info);
3969                 info = info->next_device;
3970         }
3971
3972         /* release devices */
3973         info = synclinkmp_device_list;
3974         while(info) {
3975 #if SYNCLINK_GENERIC_HDLC
3976                 hdlcdev_exit(info);
3977 #endif
3978                 free_dma_bufs(info);
3979                 free_tmp_rx_buf(info);
3980                 if ( info->port_num == 0 ) {
3981                         if (info->sca_base)
3982                                 write_reg(info, LPR, 1); /* set low power mode */
3983                         release_resources(info);
3984                 }
3985                 tmp = info;
3986                 info = info->next_device;
3987                 kfree(tmp);
3988         }
3989
3990         pci_unregister_driver(&synclinkmp_pci_driver);
3991 }
3992
3993 /* Driver initialization entry point.
3994  */
3995
3996 static int __init synclinkmp_init(void)
3997 {
3998         int rc;
3999
4000         if (break_on_load) {
4001                 synclinkmp_get_text_ptr();
4002                 BREAKPOINT();
4003         }
4004
4005         printk("%s %s\n", driver_name, driver_version);
4006
4007         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4008                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4009                 return rc;
4010         }
4011
4012         serial_driver = alloc_tty_driver(128);
4013         if (!serial_driver) {
4014                 rc = -ENOMEM;
4015                 goto error;
4016         }
4017
4018         /* Initialize the tty_driver structure */
4019
4020         serial_driver->owner = THIS_MODULE;
4021         serial_driver->driver_name = "synclinkmp";
4022         serial_driver->name = "ttySLM";
4023         serial_driver->major = ttymajor;
4024         serial_driver->minor_start = 64;
4025         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4026         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4027         serial_driver->init_termios = tty_std_termios;
4028         serial_driver->init_termios.c_cflag =
4029                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4030         serial_driver->init_termios.c_ispeed = 9600;
4031         serial_driver->init_termios.c_ospeed = 9600;
4032         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4033         tty_set_operations(serial_driver, &ops);
4034         if ((rc = tty_register_driver(serial_driver)) < 0) {
4035                 printk("%s(%d):Couldn't register serial driver\n",
4036                         __FILE__,__LINE__);
4037                 put_tty_driver(serial_driver);
4038                 serial_driver = NULL;
4039                 goto error;
4040         }
4041
4042         printk("%s %s, tty major#%d\n",
4043                 driver_name, driver_version,
4044                 serial_driver->major);
4045
4046         return 0;
4047
4048 error:
4049         synclinkmp_cleanup();
4050         return rc;
4051 }
4052
4053 static void __exit synclinkmp_exit(void)
4054 {
4055         synclinkmp_cleanup();
4056 }
4057
4058 module_init(synclinkmp_init);
4059 module_exit(synclinkmp_exit);
4060
4061 /* Set the port for internal loopback mode.
4062  * The TxCLK and RxCLK signals are generated from the BRG and
4063  * the TxD is looped back to the RxD internally.
4064  */
4065 static void enable_loopback(SLMP_INFO *info, int enable)
4066 {
4067         if (enable) {
4068                 /* MD2 (Mode Register 2)
4069                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4070                  */
4071                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4072
4073                 /* degate external TxC clock source */
4074                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4075                 write_control_reg(info);
4076
4077                 /* RXS/TXS (Rx/Tx clock source)
4078                  * 07      Reserved, must be 0
4079                  * 06..04  Clock Source, 100=BRG
4080                  * 03..00  Clock Divisor, 0000=1
4081                  */
4082                 write_reg(info, RXS, 0x40);
4083                 write_reg(info, TXS, 0x40);
4084
4085         } else {
4086                 /* MD2 (Mode Register 2)
4087                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4088                  */
4089                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4090
4091                 /* RXS/TXS (Rx/Tx clock source)
4092                  * 07      Reserved, must be 0
4093                  * 06..04  Clock Source, 000=RxC/TxC Pin
4094                  * 03..00  Clock Divisor, 0000=1
4095                  */
4096                 write_reg(info, RXS, 0x00);
4097                 write_reg(info, TXS, 0x00);
4098         }
4099
4100         /* set LinkSpeed if available, otherwise default to 2Mbps */
4101         if (info->params.clock_speed)
4102                 set_rate(info, info->params.clock_speed);
4103         else
4104                 set_rate(info, 3686400);
4105 }
4106
4107 /* Set the baud rate register to the desired speed
4108  *
4109  *      data_rate       data rate of clock in bits per second
4110  *                      A data rate of 0 disables the AUX clock.
4111  */
4112 static void set_rate( SLMP_INFO *info, u32 data_rate )
4113 {
4114         u32 TMCValue;
4115         unsigned char BRValue;
4116         u32 Divisor=0;
4117
4118         /* fBRG = fCLK/(TMC * 2^BR)
4119          */
4120         if (data_rate != 0) {
4121                 Divisor = 14745600/data_rate;
4122                 if (!Divisor)
4123                         Divisor = 1;
4124
4125                 TMCValue = Divisor;
4126
4127                 BRValue = 0;
4128                 if (TMCValue != 1 && TMCValue != 2) {
4129                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4130                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4131                          * 50/50 duty cycle.
4132                          */
4133                         BRValue = 1;
4134                         TMCValue >>= 1;
4135                 }
4136
4137                 /* while TMCValue is too big for TMC register, divide
4138                  * by 2 and increment BR exponent.
4139                  */
4140                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4141                         TMCValue >>= 1;
4142
4143                 write_reg(info, TXS,
4144                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4145                 write_reg(info, RXS,
4146                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4147                 write_reg(info, TMC, (unsigned char)TMCValue);
4148         }
4149         else {
4150                 write_reg(info, TXS,0);
4151                 write_reg(info, RXS,0);
4152                 write_reg(info, TMC, 0);
4153         }
4154 }
4155
4156 /* Disable receiver
4157  */
4158 static void rx_stop(SLMP_INFO *info)
4159 {
4160         if (debug_level >= DEBUG_LEVEL_ISR)
4161                 printk("%s(%d):%s rx_stop()\n",
4162                          __FILE__,__LINE__, info->device_name );
4163
4164         write_reg(info, CMD, RXRESET);
4165
4166         info->ie0_value &= ~RXRDYE;
4167         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4168
4169         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4170         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4171         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4172
4173         info->rx_enabled = false;
4174         info->rx_overflow = false;
4175 }
4176
4177 /* enable the receiver
4178  */
4179 static void rx_start(SLMP_INFO *info)
4180 {
4181         int i;
4182
4183         if (debug_level >= DEBUG_LEVEL_ISR)
4184                 printk("%s(%d):%s rx_start()\n",
4185                          __FILE__,__LINE__, info->device_name );
4186
4187         write_reg(info, CMD, RXRESET);
4188
4189         if ( info->params.mode == MGSL_MODE_HDLC ) {
4190                 /* HDLC, disabe IRQ on rxdata */
4191                 info->ie0_value &= ~RXRDYE;
4192                 write_reg(info, IE0, info->ie0_value);
4193
4194                 /* Reset all Rx DMA buffers and program rx dma */
4195                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4196                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4197
4198                 for (i = 0; i < info->rx_buf_count; i++) {
4199                         info->rx_buf_list[i].status = 0xff;
4200
4201                         // throttle to 4 shared memory writes at a time to prevent
4202                         // hogging local bus (keep latency time for DMA requests low).
4203                         if (!(i % 4))
4204                                 read_status_reg(info);
4205                 }
4206                 info->current_rx_buf = 0;
4207
4208                 /* set current/1st descriptor address */
4209                 write_reg16(info, RXDMA + CDA,
4210                         info->rx_buf_list_ex[0].phys_entry);
4211
4212                 /* set new last rx descriptor address */
4213                 write_reg16(info, RXDMA + EDA,
4214                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4215
4216                 /* set buffer length (shared by all rx dma data buffers) */
4217                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4218
4219                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4220                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4221         } else {
4222                 /* async, enable IRQ on rxdata */
4223                 info->ie0_value |= RXRDYE;
4224                 write_reg(info, IE0, info->ie0_value);
4225         }
4226
4227         write_reg(info, CMD, RXENABLE);
4228
4229         info->rx_overflow = false;
4230         info->rx_enabled = true;
4231 }
4232
4233 /* Enable the transmitter and send a transmit frame if
4234  * one is loaded in the DMA buffers.
4235  */
4236 static void tx_start(SLMP_INFO *info)
4237 {
4238         if (debug_level >= DEBUG_LEVEL_ISR)
4239                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4240                          __FILE__,__LINE__, info->device_name,info->tx_count );
4241
4242         if (!info->tx_enabled ) {
4243                 write_reg(info, CMD, TXRESET);
4244                 write_reg(info, CMD, TXENABLE);
4245                 info->tx_enabled = true;
4246         }
4247
4248         if ( info->tx_count ) {
4249
4250                 /* If auto RTS enabled and RTS is inactive, then assert */
4251                 /* RTS and set a flag indicating that the driver should */
4252                 /* negate RTS when the transmission completes. */
4253
4254                 info->drop_rts_on_tx_done = false;
4255
4256                 if (info->params.mode != MGSL_MODE_ASYNC) {
4257
4258                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4259                                 get_signals( info );
4260                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4261                                         info->serial_signals |= SerialSignal_RTS;
4262                                         set_signals( info );
4263                                         info->drop_rts_on_tx_done = true;
4264                                 }
4265                         }
4266
4267                         write_reg16(info, TRC0,
4268                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4269
4270                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4271                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4272
4273                         /* set TX CDA (current descriptor address) */
4274                         write_reg16(info, TXDMA + CDA,
4275                                 info->tx_buf_list_ex[0].phys_entry);
4276
4277                         /* set TX EDA (last descriptor address) */
4278                         write_reg16(info, TXDMA + EDA,
4279                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4280
4281                         /* enable underrun IRQ */
4282                         info->ie1_value &= ~IDLE;
4283                         info->ie1_value |= UDRN;
4284                         write_reg(info, IE1, info->ie1_value);
4285                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4286
4287                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4288                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4289
4290                         mod_timer(&info->tx_timer, jiffies +
4291                                         msecs_to_jiffies(5000));
4292                 }
4293                 else {
4294                         tx_load_fifo(info);
4295                         /* async, enable IRQ on txdata */
4296                         info->ie0_value |= TXRDYE;
4297                         write_reg(info, IE0, info->ie0_value);
4298                 }
4299
4300                 info->tx_active = true;
4301         }
4302 }
4303
4304 /* stop the transmitter and DMA
4305  */
4306 static void tx_stop( SLMP_INFO *info )
4307 {
4308         if (debug_level >= DEBUG_LEVEL_ISR)
4309                 printk("%s(%d):%s tx_stop()\n",
4310                          __FILE__,__LINE__, info->device_name );
4311
4312         del_timer(&info->tx_timer);
4313
4314         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4315         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4316
4317         write_reg(info, CMD, TXRESET);
4318
4319         info->ie1_value &= ~(UDRN + IDLE);
4320         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4321         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4322
4323         info->ie0_value &= ~TXRDYE;
4324         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4325
4326         info->tx_enabled = false;
4327         info->tx_active = false;
4328 }
4329
4330 /* Fill the transmit FIFO until the FIFO is full or
4331  * there is no more data to load.
4332  */
4333 static void tx_load_fifo(SLMP_INFO *info)
4334 {
4335         u8 TwoBytes[2];
4336
4337         /* do nothing is now tx data available and no XON/XOFF pending */
4338
4339         if ( !info->tx_count && !info->x_char )
4340                 return;
4341
4342         /* load the Transmit FIFO until FIFOs full or all data sent */
4343
4344         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4345
4346                 /* there is more space in the transmit FIFO and */
4347                 /* there is more data in transmit buffer */
4348
4349                 if ( (info->tx_count > 1) && !info->x_char ) {
4350                         /* write 16-bits */
4351                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4352                         if (info->tx_get >= info->max_frame_size)
4353                                 info->tx_get -= info->max_frame_size;
4354                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4355                         if (info->tx_get >= info->max_frame_size)
4356                                 info->tx_get -= info->max_frame_size;
4357
4358                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4359
4360                         info->tx_count -= 2;
4361                         info->icount.tx += 2;
4362                 } else {
4363                         /* only 1 byte left to transmit or 1 FIFO slot left */
4364
4365                         if (info->x_char) {
4366                                 /* transmit pending high priority char */
4367                                 write_reg(info, TRB, info->x_char);
4368                                 info->x_char = 0;
4369                         } else {
4370                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4371                                 if (info->tx_get >= info->max_frame_size)
4372                                         info->tx_get -= info->max_frame_size;
4373                                 info->tx_count--;
4374                         }
4375                         info->icount.tx++;
4376                 }
4377         }
4378 }
4379
4380 /* Reset a port to a known state
4381  */
4382 static void reset_port(SLMP_INFO *info)
4383 {
4384         if (info->sca_base) {
4385
4386                 tx_stop(info);
4387                 rx_stop(info);
4388
4389                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4390                 set_signals(info);
4391
4392                 /* disable all port interrupts */
4393                 info->ie0_value = 0;
4394                 info->ie1_value = 0;
4395                 info->ie2_value = 0;
4396                 write_reg(info, IE0, info->ie0_value);
4397                 write_reg(info, IE1, info->ie1_value);
4398                 write_reg(info, IE2, info->ie2_value);
4399
4400                 write_reg(info, CMD, CHRESET);
4401         }
4402 }
4403
4404 /* Reset all the ports to a known state.
4405  */
4406 static void reset_adapter(SLMP_INFO *info)
4407 {
4408         int i;
4409
4410         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4411                 if (info->port_array[i])
4412                         reset_port(info->port_array[i]);
4413         }
4414 }
4415
4416 /* Program port for asynchronous communications.
4417  */
4418 static void async_mode(SLMP_INFO *info)
4419 {
4420
4421         unsigned char RegValue;
4422
4423         tx_stop(info);
4424         rx_stop(info);
4425
4426         /* MD0, Mode Register 0
4427          *
4428          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4429          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4430          * 03      Reserved, must be 0
4431          * 02      CRCCC, CRC Calculation, 0=disabled
4432          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4433          *
4434          * 0000 0000
4435          */
4436         RegValue = 0x00;
4437         if (info->params.stop_bits != 1)
4438                 RegValue |= BIT1;
4439         write_reg(info, MD0, RegValue);
4440
4441         /* MD1, Mode Register 1
4442          *
4443          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4444          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4445          * 03..02  RXCHR<1..0>, rx char size
4446          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4447          *
4448          * 0100 0000
4449          */
4450         RegValue = 0x40;
4451         switch (info->params.data_bits) {
4452         case 7: RegValue |= BIT4 + BIT2; break;
4453         case 6: RegValue |= BIT5 + BIT3; break;
4454         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4455         }
4456         if (info->params.parity != ASYNC_PARITY_NONE) {
4457                 RegValue |= BIT1;
4458                 if (info->params.parity == ASYNC_PARITY_ODD)
4459                         RegValue |= BIT0;
4460         }
4461         write_reg(info, MD1, RegValue);
4462
4463         /* MD2, Mode Register 2
4464          *
4465          * 07..02  Reserved, must be 0
4466          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4467          *
4468          * 0000 0000
4469          */
4470         RegValue = 0x00;
4471         if (info->params.loopback)
4472                 RegValue |= (BIT1 + BIT0);
4473         write_reg(info, MD2, RegValue);
4474
4475         /* RXS, Receive clock source
4476          *
4477          * 07      Reserved, must be 0
4478          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4479          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4480          */
4481         RegValue=BIT6;
4482         write_reg(info, RXS, RegValue);
4483
4484         /* TXS, Transmit clock source
4485          *
4486          * 07      Reserved, must be 0
4487          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4488          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4489          */
4490         RegValue=BIT6;
4491         write_reg(info, TXS, RegValue);
4492
4493         /* Control Register
4494          *
4495          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4496          */
4497         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4498         write_control_reg(info);
4499
4500         tx_set_idle(info);
4501
4502         /* RRC Receive Ready Control 0
4503          *
4504          * 07..05  Reserved, must be 0
4505          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4506          */
4507         write_reg(info, RRC, 0x00);
4508
4509         /* TRC0 Transmit Ready Control 0
4510          *
4511          * 07..05  Reserved, must be 0
4512          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4513          */
4514         write_reg(info, TRC0, 0x10);
4515
4516         /* TRC1 Transmit Ready Control 1
4517          *
4518          * 07..05  Reserved, must be 0
4519          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4520          */
4521         write_reg(info, TRC1, 0x1e);
4522
4523         /* CTL, MSCI control register
4524          *
4525          * 07..06  Reserved, set to 0
4526          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4527          * 04      IDLC, idle control, 0=mark 1=idle register
4528          * 03      BRK, break, 0=off 1 =on (async)
4529          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4530          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4531          * 00      RTS, RTS output control, 0=active 1=inactive
4532          *
4533          * 0001 0001
4534          */
4535         RegValue = 0x10;
4536         if (!(info->serial_signals & SerialSignal_RTS))
4537                 RegValue |= 0x01;
4538         write_reg(info, CTL, RegValue);
4539
4540         /* enable status interrupts */
4541         info->ie0_value |= TXINTE + RXINTE;
4542         write_reg(info, IE0, info->ie0_value);
4543
4544         /* enable break detect interrupt */
4545         info->ie1_value = BRKD;
4546         write_reg(info, IE1, info->ie1_value);
4547
4548         /* enable rx overrun interrupt */
4549         info->ie2_value = OVRN;
4550         write_reg(info, IE2, info->ie2_value);
4551
4552         set_rate( info, info->params.data_rate * 16 );
4553 }
4554
4555 /* Program the SCA for HDLC communications.
4556  */
4557 static void hdlc_mode(SLMP_INFO *info)
4558 {
4559         unsigned char RegValue;
4560         u32 DpllDivisor;
4561
4562         // Can't use DPLL because SCA outputs recovered clock on RxC when
4563         // DPLL mode selected. This causes output contention with RxC receiver.
4564         // Use of DPLL would require external hardware to disable RxC receiver
4565         // when DPLL mode selected.
4566         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4567
4568         /* disable DMA interrupts */
4569         write_reg(info, TXDMA + DIR, 0);
4570         write_reg(info, RXDMA + DIR, 0);
4571
4572         /* MD0, Mode Register 0
4573          *
4574          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4575          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4576          * 03      Reserved, must be 0
4577          * 02      CRCCC, CRC Calculation, 1=enabled
4578          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4579          * 00      CRC0, CRC initial value, 1 = all 1s
4580          *
4581          * 1000 0001
4582          */
4583         RegValue = 0x81;
4584         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4585                 RegValue |= BIT4;
4586         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4587                 RegValue |= BIT4;
4588         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4589                 RegValue |= BIT2 + BIT1;
4590         write_reg(info, MD0, RegValue);
4591
4592         /* MD1, Mode Register 1
4593          *
4594          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4595          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4596          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4597          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4598          *
4599          * 0000 0000
4600          */
4601         RegValue = 0x00;
4602         write_reg(info, MD1, RegValue);
4603
4604         /* MD2, Mode Register 2
4605          *
4606          * 07      NRZFM, 0=NRZ, 1=FM
4607          * 06..05  CODE<1..0> Encoding, 00=NRZ
4608          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4609          * 02      Reserved, must be 0
4610          * 01..00  CNCT<1..0> Channel connection, 0=normal
4611          *
4612          * 0000 0000
4613          */
4614         RegValue = 0x00;
4615         switch(info->params.encoding) {
4616         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4617         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4618         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4619         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4620 #if 0
4621         case HDLC_ENCODING_NRZB:                                        /* not supported */
4622         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4623         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4624 #endif
4625         }
4626         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4627                 DpllDivisor = 16;
4628                 RegValue |= BIT3;
4629         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4630                 DpllDivisor = 8;
4631         } else {
4632                 DpllDivisor = 32;
4633                 RegValue |= BIT4;
4634         }
4635         write_reg(info, MD2, RegValue);
4636
4637
4638         /* RXS, Receive clock source
4639          *
4640          * 07      Reserved, must be 0
4641          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4642          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4643          */
4644         RegValue=0;
4645         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4646                 RegValue |= BIT6;
4647         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4648                 RegValue |= BIT6 + BIT5;
4649         write_reg(info, RXS, RegValue);
4650
4651         /* TXS, Transmit clock source
4652          *
4653          * 07      Reserved, must be 0
4654          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4655          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4656          */
4657         RegValue=0;
4658         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4659                 RegValue |= BIT6;
4660         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4661                 RegValue |= BIT6 + BIT5;
4662         write_reg(info, TXS, RegValue);
4663
4664         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4665                 set_rate(info, info->params.clock_speed * DpllDivisor);
4666         else
4667                 set_rate(info, info->params.clock_speed);
4668
4669         /* GPDATA (General Purpose I/O Data Register)
4670          *
4671          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4672          */
4673         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4674                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4675         else
4676                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4677         write_control_reg(info);
4678
4679         /* RRC Receive Ready Control 0
4680          *
4681          * 07..05  Reserved, must be 0
4682          * 04..00  RRC<4..0> Rx FIFO trigger active
4683          */
4684         write_reg(info, RRC, rx_active_fifo_level);
4685
4686         /* TRC0 Transmit Ready Control 0
4687          *
4688          * 07..05  Reserved, must be 0
4689          * 04..00  TRC<4..0> Tx FIFO trigger active
4690          */
4691         write_reg(info, TRC0, tx_active_fifo_level);
4692
4693         /* TRC1 Transmit Ready Control 1
4694          *
4695          * 07..05  Reserved, must be 0
4696          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4697          */
4698         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4699
4700         /* DMR, DMA Mode Register
4701          *
4702          * 07..05  Reserved, must be 0
4703          * 04      TMOD, Transfer Mode: 1=chained-block
4704          * 03      Reserved, must be 0
4705          * 02      NF, Number of Frames: 1=multi-frame
4706          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4707          * 00      Reserved, must be 0
4708          *
4709          * 0001 0100
4710          */
4711         write_reg(info, TXDMA + DMR, 0x14);
4712         write_reg(info, RXDMA + DMR, 0x14);
4713
4714         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4715         write_reg(info, RXDMA + CPB,
4716                 (unsigned char)(info->buffer_list_phys >> 16));
4717
4718         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4719         write_reg(info, TXDMA + CPB,
4720                 (unsigned char)(info->buffer_list_phys >> 16));
4721
4722         /* enable status interrupts. other code enables/disables
4723          * the individual sources for these two interrupt classes.
4724          */
4725         info->ie0_value |= TXINTE + RXINTE;
4726         write_reg(info, IE0, info->ie0_value);
4727
4728         /* CTL, MSCI control register
4729          *
4730          * 07..06  Reserved, set to 0
4731          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4732          * 04      IDLC, idle control, 0=mark 1=idle register
4733          * 03      BRK, break, 0=off 1 =on (async)
4734          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4735          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4736          * 00      RTS, RTS output control, 0=active 1=inactive
4737          *
4738          * 0001 0001
4739          */
4740         RegValue = 0x10;
4741         if (!(info->serial_signals & SerialSignal_RTS))
4742                 RegValue |= 0x01;
4743         write_reg(info, CTL, RegValue);
4744
4745         /* preamble not supported ! */
4746
4747         tx_set_idle(info);
4748         tx_stop(info);
4749         rx_stop(info);
4750
4751         set_rate(info, info->params.clock_speed);
4752
4753         if (info->params.loopback)
4754                 enable_loopback(info,1);
4755 }
4756
4757 /* Set the transmit HDLC idle mode
4758  */
4759 static void tx_set_idle(SLMP_INFO *info)
4760 {
4761         unsigned char RegValue = 0xff;
4762
4763         /* Map API idle mode to SCA register bits */
4764         switch(info->idle_mode) {
4765         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4766         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4767         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4768         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4769         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4770         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4771         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4772         }
4773
4774         write_reg(info, IDL, RegValue);
4775 }
4776
4777 /* Query the adapter for the state of the V24 status (input) signals.
4778  */
4779 static void get_signals(SLMP_INFO *info)
4780 {
4781         u16 status = read_reg(info, SR3);
4782         u16 gpstatus = read_status_reg(info);
4783         u16 testbit;
4784
4785         /* clear all serial signals except DTR and RTS */
4786         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4787
4788         /* set serial signal bits to reflect MISR */
4789
4790         if (!(status & BIT3))
4791                 info->serial_signals |= SerialSignal_CTS;
4792
4793         if ( !(status & BIT2))
4794                 info->serial_signals |= SerialSignal_DCD;
4795
4796         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4797         if (!(gpstatus & testbit))
4798                 info->serial_signals |= SerialSignal_RI;
4799
4800         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4801         if (!(gpstatus & testbit))
4802                 info->serial_signals |= SerialSignal_DSR;
4803 }
4804
4805 /* Set the state of DTR and RTS based on contents of
4806  * serial_signals member of device context.
4807  */
4808 static void set_signals(SLMP_INFO *info)
4809 {
4810         unsigned char RegValue;
4811         u16 EnableBit;
4812
4813         RegValue = read_reg(info, CTL);
4814         if (info->serial_signals & SerialSignal_RTS)
4815                 RegValue &= ~BIT0;
4816         else
4817                 RegValue |= BIT0;
4818         write_reg(info, CTL, RegValue);
4819
4820         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4821         EnableBit = BIT1 << (info->port_num*2);
4822         if (info->serial_signals & SerialSignal_DTR)
4823                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4824         else
4825                 info->port_array[0]->ctrlreg_value |= EnableBit;
4826         write_control_reg(info);
4827 }
4828
4829 /*******************/
4830 /* DMA Buffer Code */
4831 /*******************/
4832
4833 /* Set the count for all receive buffers to SCABUFSIZE
4834  * and set the current buffer to the first buffer. This effectively
4835  * makes all buffers free and discards any data in buffers.
4836  */
4837 static void rx_reset_buffers(SLMP_INFO *info)
4838 {
4839         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4840 }
4841
4842 /* Free the buffers used by a received frame
4843  *
4844  * info   pointer to device instance data
4845  * first  index of 1st receive buffer of frame
4846  * last   index of last receive buffer of frame
4847  */
4848 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4849 {
4850         bool done = false;
4851
4852         while(!done) {
4853                 /* reset current buffer for reuse */
4854                 info->rx_buf_list[first].status = 0xff;
4855
4856                 if (first == last) {
4857                         done = true;
4858                         /* set new last rx descriptor address */
4859                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4860                 }
4861
4862                 first++;
4863                 if (first == info->rx_buf_count)
4864                         first = 0;
4865         }
4866
4867         /* set current buffer to next buffer after last buffer of frame */
4868         info->current_rx_buf = first;
4869 }
4870
4871 /* Return a received frame from the receive DMA buffers.
4872  * Only frames received without errors are returned.
4873  *
4874  * Return Value:        true if frame returned, otherwise false
4875  */
4876 static bool rx_get_frame(SLMP_INFO *info)
4877 {
4878         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4879         unsigned short status;
4880         unsigned int framesize = 0;
4881         bool ReturnCode = false;
4882         unsigned long flags;
4883         struct tty_struct *tty = info->tty;
4884         unsigned char addr_field = 0xff;
4885         SCADESC *desc;
4886         SCADESC_EX *desc_ex;
4887
4888 CheckAgain:
4889         /* assume no frame returned, set zero length */
4890         framesize = 0;
4891         addr_field = 0xff;
4892
4893         /*
4894          * current_rx_buf points to the 1st buffer of the next available
4895          * receive frame. To find the last buffer of the frame look for
4896          * a non-zero status field in the buffer entries. (The status
4897          * field is set by the 16C32 after completing a receive frame.
4898          */
4899         StartIndex = EndIndex = info->current_rx_buf;
4900
4901         for ( ;; ) {
4902                 desc = &info->rx_buf_list[EndIndex];
4903                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4904
4905                 if (desc->status == 0xff)
4906                         goto Cleanup;   /* current desc still in use, no frames available */
4907
4908                 if (framesize == 0 && info->params.addr_filter != 0xff)
4909                         addr_field = desc_ex->virt_addr[0];
4910
4911                 framesize += desc->length;
4912
4913                 /* Status != 0 means last buffer of frame */
4914                 if (desc->status)
4915                         break;
4916
4917                 EndIndex++;
4918                 if (EndIndex == info->rx_buf_count)
4919                         EndIndex = 0;
4920
4921                 if (EndIndex == info->current_rx_buf) {
4922                         /* all buffers have been 'used' but none mark      */
4923                         /* the end of a frame. Reset buffers and receiver. */
4924                         if ( info->rx_enabled ){
4925                                 spin_lock_irqsave(&info->lock,flags);
4926                                 rx_start(info);
4927                                 spin_unlock_irqrestore(&info->lock,flags);
4928                         }
4929                         goto Cleanup;
4930                 }
4931
4932         }
4933
4934         /* check status of receive frame */
4935
4936         /* frame status is byte stored after frame data
4937          *
4938          * 7 EOM (end of msg), 1 = last buffer of frame
4939          * 6 Short Frame, 1 = short frame
4940          * 5 Abort, 1 = frame aborted
4941          * 4 Residue, 1 = last byte is partial
4942          * 3 Overrun, 1 = overrun occurred during frame reception
4943          * 2 CRC,     1 = CRC error detected
4944          *
4945          */
4946         status = desc->status;
4947
4948         /* ignore CRC bit if not using CRC (bit is undefined) */
4949         /* Note:CRC is not save to data buffer */
4950         if (info->params.crc_type == HDLC_CRC_NONE)
4951                 status &= ~BIT2;
4952
4953         if (framesize == 0 ||
4954                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4955                 /* discard 0 byte frames, this seems to occur sometime
4956                  * when remote is idling flags.
4957                  */
4958                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4959                 goto CheckAgain;
4960         }
4961
4962         if (framesize < 2)
4963                 status |= BIT6;
4964
4965         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4966                 /* received frame has errors,
4967                  * update counts and mark frame size as 0
4968                  */
4969                 if (status & BIT6)
4970                         info->icount.rxshort++;
4971                 else if (status & BIT5)
4972                         info->icount.rxabort++;
4973                 else if (status & BIT3)
4974                         info->icount.rxover++;
4975                 else
4976                         info->icount.rxcrc++;
4977
4978                 framesize = 0;
4979 #if SYNCLINK_GENERIC_HDLC
4980                 {
4981                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4982                         stats->rx_errors++;
4983                         stats->rx_frame_errors++;
4984                 }
4985 #endif
4986         }
4987
4988         if ( debug_level >= DEBUG_LEVEL_BH )
4989                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4990                         __FILE__,__LINE__,info->device_name,status,framesize);
4991
4992         if ( debug_level >= DEBUG_LEVEL_DATA )
4993                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4994                         min_t(int, framesize,SCABUFSIZE),0);
4995
4996         if (framesize) {
4997                 if (framesize > info->max_frame_size)
4998                         info->icount.rxlong++;
4999                 else {
5000                         /* copy dma buffer(s) to contiguous intermediate buffer */
5001                         int copy_count = framesize;
5002                         int index = StartIndex;
5003                         unsigned char *ptmp = info->tmp_rx_buf;
5004                         info->tmp_rx_buf_count = framesize;
5005
5006                         info->icount.rxok++;
5007
5008                         while(copy_count) {
5009                                 int partial_count = min(copy_count,SCABUFSIZE);
5010                                 memcpy( ptmp,
5011                                         info->rx_buf_list_ex[index].virt_addr,
5012                                         partial_count );
5013                                 ptmp += partial_count;
5014                                 copy_count -= partial_count;
5015
5016                                 if ( ++index == info->rx_buf_count )
5017                                         index = 0;
5018                         }
5019
5020 #if SYNCLINK_GENERIC_HDLC
5021                         if (info->netcount)
5022                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5023                         else
5024 #endif
5025                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5026                                                   info->flag_buf, framesize);
5027                 }
5028         }
5029         /* Free the buffers used by this frame. */
5030         rx_free_frame_buffers( info, StartIndex, EndIndex );
5031
5032         ReturnCode = true;
5033
5034 Cleanup:
5035         if ( info->rx_enabled && info->rx_overflow ) {
5036                 /* Receiver is enabled, but needs to restarted due to
5037                  * rx buffer overflow. If buffers are empty, restart receiver.
5038                  */
5039                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5040                         spin_lock_irqsave(&info->lock,flags);
5041                         rx_start(info);
5042                         spin_unlock_irqrestore(&info->lock,flags);
5043                 }
5044         }
5045
5046         return ReturnCode;
5047 }
5048
5049 /* load the transmit DMA buffer with data
5050  */
5051 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5052 {
5053         unsigned short copy_count;
5054         unsigned int i = 0;
5055         SCADESC *desc;
5056         SCADESC_EX *desc_ex;
5057
5058         if ( debug_level >= DEBUG_LEVEL_DATA )
5059                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5060
5061         /* Copy source buffer to one or more DMA buffers, starting with
5062          * the first transmit dma buffer.
5063          */
5064         for(i=0;;)
5065         {
5066                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5067
5068                 desc = &info->tx_buf_list[i];
5069                 desc_ex = &info->tx_buf_list_ex[i];
5070
5071                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5072
5073                 desc->length = copy_count;
5074                 desc->status = 0;
5075
5076                 buf += copy_count;
5077                 count -= copy_count;
5078
5079                 if (!count)
5080                         break;
5081
5082                 i++;
5083                 if (i >= info->tx_buf_count)
5084                         i = 0;
5085         }
5086
5087         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5088         info->last_tx_buf = ++i;
5089 }
5090
5091 static bool register_test(SLMP_INFO *info)
5092 {
5093         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5094         static unsigned int count = ARRAY_SIZE(testval);
5095         unsigned int i;
5096         bool rc = true;
5097         unsigned long flags;
5098
5099         spin_lock_irqsave(&info->lock,flags);
5100         reset_port(info);
5101
5102         /* assume failure */
5103         info->init_error = DiagStatus_AddressFailure;
5104
5105         /* Write bit patterns to various registers but do it out of */
5106         /* sync, then read back and verify values. */
5107
5108         for (i = 0 ; i < count ; i++) {
5109                 write_reg(info, TMC, testval[i]);
5110                 write_reg(info, IDL, testval[(i+1)%count]);
5111                 write_reg(info, SA0, testval[(i+2)%count]);
5112                 write_reg(info, SA1, testval[(i+3)%count]);
5113
5114                 if ( (read_reg(info, TMC) != testval[i]) ||
5115                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5116                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5117                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5118                 {
5119                         rc = false;
5120                         break;
5121                 }
5122         }
5123
5124         reset_port(info);
5125         spin_unlock_irqrestore(&info->lock,flags);
5126
5127         return rc;
5128 }
5129
5130 static bool irq_test(SLMP_INFO *info)
5131 {
5132         unsigned long timeout;
5133         unsigned long flags;
5134
5135         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5136
5137         spin_lock_irqsave(&info->lock,flags);
5138         reset_port(info);
5139
5140         /* assume failure */
5141         info->init_error = DiagStatus_IrqFailure;
5142         info->irq_occurred = false;
5143
5144         /* setup timer0 on SCA0 to interrupt */
5145
5146         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5147         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5148
5149         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5150         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5151
5152
5153         /* TMCS, Timer Control/Status Register
5154          *
5155          * 07      CMF, Compare match flag (read only) 1=match
5156          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5157          * 05      Reserved, must be 0
5158          * 04      TME, Timer Enable
5159          * 03..00  Reserved, must be 0
5160          *
5161          * 0101 0000
5162          */
5163         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5164
5165         spin_unlock_irqrestore(&info->lock,flags);
5166
5167         timeout=100;
5168         while( timeout-- && !info->irq_occurred ) {
5169                 msleep_interruptible(10);
5170         }
5171
5172         spin_lock_irqsave(&info->lock,flags);
5173         reset_port(info);
5174         spin_unlock_irqrestore(&info->lock,flags);
5175
5176         return info->irq_occurred;
5177 }
5178
5179 /* initialize individual SCA device (2 ports)
5180  */
5181 static bool sca_init(SLMP_INFO *info)
5182 {
5183         /* set wait controller to single mem partition (low), no wait states */
5184         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5185         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5186         write_reg(info, WCRL, 0);       /* wait controller low range */
5187         write_reg(info, WCRM, 0);       /* wait controller mid range */
5188         write_reg(info, WCRH, 0);       /* wait controller high range */
5189
5190         /* DPCR, DMA Priority Control
5191          *
5192          * 07..05  Not used, must be 0
5193          * 04      BRC, bus release condition: 0=all transfers complete
5194          * 03      CCC, channel change condition: 0=every cycle
5195          * 02..00  PR<2..0>, priority 100=round robin
5196          *
5197          * 00000100 = 0x04
5198          */
5199         write_reg(info, DPCR, dma_priority);
5200
5201         /* DMA Master Enable, BIT7: 1=enable all channels */
5202         write_reg(info, DMER, 0x80);
5203
5204         /* enable all interrupt classes */
5205         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5206         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5207         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5208
5209         /* ITCR, interrupt control register
5210          * 07      IPC, interrupt priority, 0=MSCI->DMA
5211          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5212          * 04      VOS, Vector Output, 0=unmodified vector
5213          * 03..00  Reserved, must be 0
5214          */
5215         write_reg(info, ITCR, 0);
5216
5217         return true;
5218 }
5219
5220 /* initialize adapter hardware
5221  */
5222 static bool init_adapter(SLMP_INFO *info)
5223 {
5224         int i;
5225
5226         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5227         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5228         u32 readval;
5229
5230         info->misc_ctrl_value |= BIT30;
5231         *MiscCtrl = info->misc_ctrl_value;
5232
5233         /*
5234          * Force at least 170ns delay before clearing
5235          * reset bit. Each read from LCR takes at least
5236          * 30ns so 10 times for 300ns to be safe.
5237          */
5238         for(i=0;i<10;i++)
5239                 readval = *MiscCtrl;
5240
5241         info->misc_ctrl_value &= ~BIT30;
5242         *MiscCtrl = info->misc_ctrl_value;
5243
5244         /* init control reg (all DTRs off, all clksel=input) */
5245         info->ctrlreg_value = 0xaa;
5246         write_control_reg(info);
5247
5248         {
5249                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5250                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5251
5252                 switch(read_ahead_count)
5253                 {
5254                 case 16:
5255                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5256                         break;
5257                 case 8:
5258                         lcr1_brdr_value |= BIT5 + BIT4;
5259                         break;
5260                 case 4:
5261                         lcr1_brdr_value |= BIT5 + BIT3;
5262                         break;
5263                 case 0:
5264                         lcr1_brdr_value |= BIT5;
5265                         break;
5266                 }
5267
5268                 *LCR1BRDR = lcr1_brdr_value;
5269                 *MiscCtrl = misc_ctrl_value;
5270         }
5271
5272         sca_init(info->port_array[0]);
5273         sca_init(info->port_array[2]);
5274
5275         return true;
5276 }
5277
5278 /* Loopback an HDLC frame to test the hardware
5279  * interrupt and DMA functions.
5280  */
5281 static bool loopback_test(SLMP_INFO *info)
5282 {
5283 #define TESTFRAMESIZE 20
5284
5285         unsigned long timeout;
5286         u16 count = TESTFRAMESIZE;
5287         unsigned char buf[TESTFRAMESIZE];
5288         bool rc = false;
5289         unsigned long flags;
5290
5291         struct tty_struct *oldtty = info->tty;
5292         u32 speed = info->params.clock_speed;
5293
5294         info->params.clock_speed = 3686400;
5295         info->tty = NULL;
5296
5297         /* assume failure */
5298         info->init_error = DiagStatus_DmaFailure;
5299
5300         /* build and send transmit frame */
5301         for (count = 0; count < TESTFRAMESIZE;++count)
5302                 buf[count] = (unsigned char)count;
5303
5304         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5305
5306         /* program hardware for HDLC and enabled receiver */
5307         spin_lock_irqsave(&info->lock,flags);
5308         hdlc_mode(info);
5309         enable_loopback(info,1);
5310         rx_start(info);
5311         info->tx_count = count;
5312         tx_load_dma_buffer(info,buf,count);
5313         tx_start(info);
5314         spin_unlock_irqrestore(&info->lock,flags);
5315
5316         /* wait for receive complete */
5317         /* Set a timeout for waiting for interrupt. */
5318         for ( timeout = 100; timeout; --timeout ) {
5319                 msleep_interruptible(10);
5320
5321                 if (rx_get_frame(info)) {
5322                         rc = true;
5323                         break;
5324                 }
5325         }
5326
5327         /* verify received frame length and contents */
5328         if (rc &&
5329             ( info->tmp_rx_buf_count != count ||
5330               memcmp(buf, info->tmp_rx_buf,count))) {
5331                 rc = false;
5332         }
5333
5334         spin_lock_irqsave(&info->lock,flags);
5335         reset_adapter(info);
5336         spin_unlock_irqrestore(&info->lock,flags);
5337
5338         info->params.clock_speed = speed;
5339         info->tty = oldtty;
5340
5341         return rc;
5342 }
5343
5344 /* Perform diagnostics on hardware
5345  */
5346 static int adapter_test( SLMP_INFO *info )
5347 {
5348         unsigned long flags;
5349         if ( debug_level >= DEBUG_LEVEL_INFO )
5350                 printk( "%s(%d):Testing device %s\n",
5351                         __FILE__,__LINE__,info->device_name );
5352
5353         spin_lock_irqsave(&info->lock,flags);
5354         init_adapter(info);
5355         spin_unlock_irqrestore(&info->lock,flags);
5356
5357         info->port_array[0]->port_count = 0;
5358
5359         if ( register_test(info->port_array[0]) &&
5360                 register_test(info->port_array[1])) {
5361
5362                 info->port_array[0]->port_count = 2;
5363
5364                 if ( register_test(info->port_array[2]) &&
5365                         register_test(info->port_array[3]) )
5366                         info->port_array[0]->port_count += 2;
5367         }
5368         else {
5369                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5370                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5371                 return -ENODEV;
5372         }
5373
5374         if ( !irq_test(info->port_array[0]) ||
5375                 !irq_test(info->port_array[1]) ||
5376                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5377                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5378                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5379                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5380                 return -ENODEV;
5381         }
5382
5383         if (!loopback_test(info->port_array[0]) ||
5384                 !loopback_test(info->port_array[1]) ||
5385                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5386                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5387                 printk( "%s(%d):DMA test failure for device %s\n",
5388                         __FILE__,__LINE__,info->device_name);
5389                 return -ENODEV;
5390         }
5391
5392         if ( debug_level >= DEBUG_LEVEL_INFO )
5393                 printk( "%s(%d):device %s passed diagnostics\n",
5394                         __FILE__,__LINE__,info->device_name );
5395
5396         info->port_array[0]->init_error = 0;
5397         info->port_array[1]->init_error = 0;
5398         if ( info->port_count > 2 ) {
5399                 info->port_array[2]->init_error = 0;
5400                 info->port_array[3]->init_error = 0;
5401         }
5402
5403         return 0;
5404 }
5405
5406 /* Test the shared memory on a PCI adapter.
5407  */
5408 static bool memory_test(SLMP_INFO *info)
5409 {
5410         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5411                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5412         unsigned long count = ARRAY_SIZE(testval);
5413         unsigned long i;
5414         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5415         unsigned long * addr = (unsigned long *)info->memory_base;
5416
5417         /* Test data lines with test pattern at one location. */
5418
5419         for ( i = 0 ; i < count ; i++ ) {
5420                 *addr = testval[i];
5421                 if ( *addr != testval[i] )
5422                         return false;
5423         }
5424
5425         /* Test address lines with incrementing pattern over */
5426         /* entire address range. */
5427
5428         for ( i = 0 ; i < limit ; i++ ) {
5429                 *addr = i * 4;
5430                 addr++;
5431         }
5432
5433         addr = (unsigned long *)info->memory_base;
5434
5435         for ( i = 0 ; i < limit ; i++ ) {
5436                 if ( *addr != i * 4 )
5437                         return false;
5438                 addr++;
5439         }
5440
5441         memset( info->memory_base, 0, SCA_MEM_SIZE );
5442         return true;
5443 }
5444
5445 /* Load data into PCI adapter shared memory.
5446  *
5447  * The PCI9050 releases control of the local bus
5448  * after completing the current read or write operation.
5449  *
5450  * While the PCI9050 write FIFO not empty, the
5451  * PCI9050 treats all of the writes as a single transaction
5452  * and does not release the bus. This causes DMA latency problems
5453  * at high speeds when copying large data blocks to the shared memory.
5454  *
5455  * This function breaks a write into multiple transations by
5456  * interleaving a read which flushes the write FIFO and 'completes'
5457  * the write transation. This allows any pending DMA request to gain control
5458  * of the local bus in a timely fasion.
5459  */
5460 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5461 {
5462         /* A load interval of 16 allows for 4 32-bit writes at */
5463         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5464
5465         unsigned short interval = count / sca_pci_load_interval;
5466         unsigned short i;
5467
5468         for ( i = 0 ; i < interval ; i++ )
5469         {
5470                 memcpy(dest, src, sca_pci_load_interval);
5471                 read_status_reg(info);
5472                 dest += sca_pci_load_interval;
5473                 src += sca_pci_load_interval;
5474         }
5475
5476         memcpy(dest, src, count % sca_pci_load_interval);
5477 }
5478
5479 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5480 {
5481         int i;
5482         int linecount;
5483         if (xmit)
5484                 printk("%s tx data:\n",info->device_name);
5485         else
5486                 printk("%s rx data:\n",info->device_name);
5487
5488         while(count) {
5489                 if (count > 16)
5490                         linecount = 16;
5491                 else
5492                         linecount = count;
5493
5494                 for(i=0;i<linecount;i++)
5495                         printk("%02X ",(unsigned char)data[i]);
5496                 for(;i<17;i++)
5497                         printk("   ");
5498                 for(i=0;i<linecount;i++) {
5499                         if (data[i]>=040 && data[i]<=0176)
5500                                 printk("%c",data[i]);
5501                         else
5502                                 printk(".");
5503                 }
5504                 printk("\n");
5505
5506                 data  += linecount;
5507                 count -= linecount;
5508         }
5509 }       /* end of trace_block() */
5510
5511 /* called when HDLC frame times out
5512  * update stats and do tx completion processing
5513  */
5514 static void tx_timeout(unsigned long context)
5515 {
5516         SLMP_INFO *info = (SLMP_INFO*)context;
5517         unsigned long flags;
5518
5519         if ( debug_level >= DEBUG_LEVEL_INFO )
5520                 printk( "%s(%d):%s tx_timeout()\n",
5521                         __FILE__,__LINE__,info->device_name);
5522         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5523                 info->icount.txtimeout++;
5524         }
5525         spin_lock_irqsave(&info->lock,flags);
5526         info->tx_active = false;
5527         info->tx_count = info->tx_put = info->tx_get = 0;
5528
5529         spin_unlock_irqrestore(&info->lock,flags);
5530
5531 #if SYNCLINK_GENERIC_HDLC
5532         if (info->netcount)
5533                 hdlcdev_tx_done(info);
5534         else
5535 #endif
5536                 bh_transmit(info);
5537 }
5538
5539 /* called to periodically check the DSR/RI modem signal input status
5540  */
5541 static void status_timeout(unsigned long context)
5542 {
5543         u16 status = 0;
5544         SLMP_INFO *info = (SLMP_INFO*)context;
5545         unsigned long flags;
5546         unsigned char delta;
5547
5548
5549         spin_lock_irqsave(&info->lock,flags);
5550         get_signals(info);
5551         spin_unlock_irqrestore(&info->lock,flags);
5552
5553         /* check for DSR/RI state change */
5554
5555         delta = info->old_signals ^ info->serial_signals;
5556         info->old_signals = info->serial_signals;
5557
5558         if (delta & SerialSignal_DSR)
5559                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5560
5561         if (delta & SerialSignal_RI)
5562                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5563
5564         if (delta & SerialSignal_DCD)
5565                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5566
5567         if (delta & SerialSignal_CTS)
5568                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5569
5570         if (status)
5571                 isr_io_pin(info,status);
5572
5573         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5574 }
5575
5576
5577 /* Register Access Routines -
5578  * All registers are memory mapped
5579  */
5580 #define CALC_REGADDR() \
5581         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5582         if (info->port_num > 1) \
5583                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5584         if ( info->port_num & 1) { \
5585                 if (Addr > 0x7f) \
5586                         RegAddr += 0x40;        /* DMA access */ \
5587                 else if (Addr > 0x1f && Addr < 0x60) \
5588                         RegAddr += 0x20;        /* MSCI access */ \
5589         }
5590
5591
5592 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5593 {
5594         CALC_REGADDR();
5595         return *RegAddr;
5596 }
5597 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5598 {
5599         CALC_REGADDR();
5600         *RegAddr = Value;
5601 }
5602
5603 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5604 {
5605         CALC_REGADDR();
5606         return *((u16 *)RegAddr);
5607 }
5608
5609 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5610 {
5611         CALC_REGADDR();
5612         *((u16 *)RegAddr) = Value;
5613 }
5614
5615 static unsigned char read_status_reg(SLMP_INFO * info)
5616 {
5617         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5618         return *RegAddr;
5619 }
5620
5621 static void write_control_reg(SLMP_INFO * info)
5622 {
5623         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5624         *RegAddr = info->port_array[0]->ctrlreg_value;
5625 }
5626
5627
5628 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5629                                           const struct pci_device_id *ent)
5630 {
5631         if (pci_enable_device(dev)) {
5632                 printk("error enabling pci device %p\n", dev);
5633                 return -EIO;
5634         }
5635         device_init( ++synclinkmp_adapter_count, dev );
5636         return 0;
5637 }
5638
5639 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5640 {
5641 }