drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/seq_file.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70 #include <linux/synclink.h>
  71
  72 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  73 #define SYNCLINK_GENERIC_HDLC 1
  74 #else
  75 #define SYNCLINK_GENERIC_HDLC 0
  76 #endif
  77
  78 #define GET_USER(error,value,addr) error = get_user(value,addr)
  79 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  80 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  81 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  82
  83 #include <asm/uaccess.h>
  84
  85 static MGSL_PARAMS default_params = {
  86         MGSL_MODE_HDLC,                 /* unsigned long mode */
  87         0,                              /* unsigned char loopback; */
  88         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  89         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  90         0,                              /* unsigned long clock_speed; */
  91         0xff,                           /* unsigned char addr_filter; */
  92         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  93         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  94         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  95         9600,                           /* unsigned long data_rate; */
  96         8,                              /* unsigned char data_bits; */
  97         1,                              /* unsigned char stop_bits; */
  98         ASYNC_PARITY_NONE               /* unsigned char parity; */
  99 };
 100
 101 /* size in bytes of DMA data buffers */
 102 #define SCABUFSIZE      1024
 103 #define SCA_MEM_SIZE    0x40000
 104 #define SCA_BASE_SIZE   512
 105 #define SCA_REG_SIZE    16
 106 #define SCA_MAX_PORTS   4
 107 #define SCAMAXDESC      128
 108
 109 #define BUFFERLISTSIZE  4096
 110
 111 /* SCA-I style DMA buffer descriptor */
 112 typedef struct _SCADESC
 113 {
 114         u16     next;           /* lower l6 bits of next descriptor addr */
 115         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 116         u8      buf_base;       /* upper 8 bits of buffer addr */
 117         u8      pad1;
 118         u16     length;         /* length of buffer */
 119         u8      status;         /* status of buffer */
 120         u8      pad2;
 121 } SCADESC, *PSCADESC;
 122
 123 typedef struct _SCADESC_EX
 124 {
 125         /* device driver bookkeeping section */
 126         char    *virt_addr;     /* virtual address of data buffer */
 127         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 128 } SCADESC_EX, *PSCADESC_EX;
 129
 130 /* The queue of BH actions to be performed */
 131
 132 #define BH_RECEIVE  1
 133 #define BH_TRANSMIT 2
 134 #define BH_STATUS   4
 135
 136 #define IO_PIN_SHUTDOWN_LIMIT 100
 137
 138 struct  _input_signal_events {
 139         int     ri_up;
 140         int     ri_down;
 141         int     dsr_up;
 142         int     dsr_down;
 143         int     dcd_up;
 144         int     dcd_down;
 145         int     cts_up;
 146         int     cts_down;
 147 };
 148
 149 /*
 150  * Device instance data structure
 151  */
 152 typedef struct _synclinkmp_info {
 153         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 154         int                     magic;
 155         struct tty_port         port;
 156         int                     line;
 157         unsigned short          close_delay;
 158         unsigned short          closing_wait;   /* time to wait before closing */
 159
 160         struct mgsl_icount      icount;
 161
 162         int                     timeout;
 163         int                     x_char;         /* xon/xoff character */
 164         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 165         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 166         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 167         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 168         unsigned char           *tx_buf;
 169         int                     tx_put;
 170         int                     tx_get;
 171         int                     tx_count;
 172
 173         wait_queue_head_t       status_event_wait_q;
 174         wait_queue_head_t       event_wait_q;
 175         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 176         struct _synclinkmp_info *next_device;   /* device list link */
 177         struct timer_list       status_timer;   /* input signal status check timer */
 178
 179         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 180         struct work_struct task;                        /* task structure for scheduling bh */
 181
 182         u32 max_frame_size;                     /* as set by device config */
 183
 184         u32 pending_bh;
 185
 186         bool bh_running;                                /* Protection from multiple */
 187         int isr_overflow;
 188         bool bh_requested;
 189
 190         int dcd_chkcount;                       /* check counts to prevent */
 191         int cts_chkcount;                       /* too many IRQs if a signal */
 192         int dsr_chkcount;                       /* is floating */
 193         int ri_chkcount;
 194
 195         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 196         unsigned long buffer_list_phys;
 197
 198         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 199         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 200         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 201         unsigned int current_rx_buf;
 202
 203         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 204         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 205         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 206         unsigned int last_tx_buf;
 207
 208         unsigned char *tmp_rx_buf;
 209         unsigned int tmp_rx_buf_count;
 210
 211         bool rx_enabled;
 212         bool rx_overflow;
 213
 214         bool tx_enabled;
 215         bool tx_active;
 216         u32 idle_mode;
 217
 218         unsigned char ie0_value;
 219         unsigned char ie1_value;
 220         unsigned char ie2_value;
 221         unsigned char ctrlreg_value;
 222         unsigned char old_signals;
 223
 224         char device_name[25];                   /* device instance name */
 225
 226         int port_count;
 227         int adapter_num;
 228         int port_num;
 229
 230         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 231
 232         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 233
 234         unsigned int irq_level;                 /* interrupt level */
 235         unsigned long irq_flags;
 236         bool irq_requested;                     /* true if IRQ requested */
 237
 238         MGSL_PARAMS params;                     /* communications parameters */
 239
 240         unsigned char serial_signals;           /* current serial signal states */
 241
 242         bool irq_occurred;                      /* for diagnostics use */
 243         unsigned int init_error;                /* Initialization startup error */
 244
 245         u32 last_mem_alloc;
 246         unsigned char* memory_base;             /* shared memory address (PCI only) */
 247         u32 phys_memory_base;
 248         int shared_mem_requested;
 249
 250         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 251         u32 phys_sca_base;
 252         u32 sca_offset;
 253         bool sca_base_requested;
 254
 255         unsigned char* lcr_base;                /* local config registers (PCI only) */
 256         u32 phys_lcr_base;
 257         u32 lcr_offset;
 258         int lcr_mem_requested;
 259
 260         unsigned char* statctrl_base;           /* status/control register memory */
 261         u32 phys_statctrl_base;
 262         u32 statctrl_offset;
 263         bool sca_statctrl_requested;
 264
 265         u32 misc_ctrl_value;
 266         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 267         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 268         bool drop_rts_on_tx_done;
 269
 270         struct  _input_signal_events    input_signal_events;
 271
 272         /* SPPP/Cisco HDLC device parts */
 273         int netcount;
 274         spinlock_t netlock;
 275
 276 #if SYNCLINK_GENERIC_HDLC
 277         struct net_device *netdev;
 278 #endif
 279
 280 } SLMP_INFO;
 281
 282 #define MGSL_MAGIC 0x5401
 283
 284 /*
 285  * define serial signal status change macros
 286  */
 287 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 288 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 289 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 290 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 291
 292 /* Common Register macros */
 293 #define LPR     0x00
 294 #define PABR0   0x02
 295 #define PABR1   0x03
 296 #define WCRL    0x04
 297 #define WCRM    0x05
 298 #define WCRH    0x06
 299 #define DPCR    0x08
 300 #define DMER    0x09
 301 #define ISR0    0x10
 302 #define ISR1    0x11
 303 #define ISR2    0x12
 304 #define IER0    0x14
 305 #define IER1    0x15
 306 #define IER2    0x16
 307 #define ITCR    0x18
 308 #define INTVR   0x1a
 309 #define IMVR    0x1c
 310
 311 /* MSCI Register macros */
 312 #define TRB     0x20
 313 #define TRBL    0x20
 314 #define TRBH    0x21
 315 #define SR0     0x22
 316 #define SR1     0x23
 317 #define SR2     0x24
 318 #define SR3     0x25
 319 #define FST     0x26
 320 #define IE0     0x28
 321 #define IE1     0x29
 322 #define IE2     0x2a
 323 #define FIE     0x2b
 324 #define CMD     0x2c
 325 #define MD0     0x2e
 326 #define MD1     0x2f
 327 #define MD2     0x30
 328 #define CTL     0x31
 329 #define SA0     0x32
 330 #define SA1     0x33
 331 #define IDL     0x34
 332 #define TMC     0x35
 333 #define RXS     0x36
 334 #define TXS     0x37
 335 #define TRC0    0x38
 336 #define TRC1    0x39
 337 #define RRC     0x3a
 338 #define CST0    0x3c
 339 #define CST1    0x3d
 340
 341 /* Timer Register Macros */
 342 #define TCNT    0x60
 343 #define TCNTL   0x60
 344 #define TCNTH   0x61
 345 #define TCONR   0x62
 346 #define TCONRL  0x62
 347 #define TCONRH  0x63
 348 #define TMCS    0x64
 349 #define TEPR    0x65
 350
 351 /* DMA Controller Register macros */
 352 #define DARL    0x80
 353 #define DARH    0x81
 354 #define DARB    0x82
 355 #define BAR     0x80
 356 #define BARL    0x80
 357 #define BARH    0x81
 358 #define BARB    0x82
 359 #define SAR     0x84
 360 #define SARL    0x84
 361 #define SARH    0x85
 362 #define SARB    0x86
 363 #define CPB     0x86
 364 #define CDA     0x88
 365 #define CDAL    0x88
 366 #define CDAH    0x89
 367 #define EDA     0x8a
 368 #define EDAL    0x8a
 369 #define EDAH    0x8b
 370 #define BFL     0x8c
 371 #define BFLL    0x8c
 372 #define BFLH    0x8d
 373 #define BCR     0x8e
 374 #define BCRL    0x8e
 375 #define BCRH    0x8f
 376 #define DSR     0x90
 377 #define DMR     0x91
 378 #define FCT     0x93
 379 #define DIR     0x94
 380 #define DCMD    0x95
 381
 382 /* combine with timer or DMA register address */
 383 #define TIMER0  0x00
 384 #define TIMER1  0x08
 385 #define TIMER2  0x10
 386 #define TIMER3  0x18
 387 #define RXDMA   0x00
 388 #define TXDMA   0x20
 389
 390 /* SCA Command Codes */
 391 #define NOOP            0x00
 392 #define TXRESET         0x01
 393 #define TXENABLE        0x02
 394 #define TXDISABLE       0x03
 395 #define TXCRCINIT       0x04
 396 #define TXCRCEXCL       0x05
 397 #define TXEOM           0x06
 398 #define TXABORT         0x07
 399 #define MPON            0x08
 400 #define TXBUFCLR        0x09
 401 #define RXRESET         0x11
 402 #define RXENABLE        0x12
 403 #define RXDISABLE       0x13
 404 #define RXCRCINIT       0x14
 405 #define RXREJECT        0x15
 406 #define SEARCHMP        0x16
 407 #define RXCRCEXCL       0x17
 408 #define RXCRCCALC       0x18
 409 #define CHRESET         0x21
 410 #define HUNT            0x31
 411
 412 /* DMA command codes */
 413 #define SWABORT         0x01
 414 #define FEICLEAR        0x02
 415
 416 /* IE0 */
 417 #define TXINTE          BIT7
 418 #define RXINTE          BIT6
 419 #define TXRDYE          BIT1
 420 #define RXRDYE          BIT0
 421
 422 /* IE1 & SR1 */
 423 #define UDRN    BIT7
 424 #define IDLE    BIT6
 425 #define SYNCD   BIT4
 426 #define FLGD    BIT4
 427 #define CCTS    BIT3
 428 #define CDCD    BIT2
 429 #define BRKD    BIT1
 430 #define ABTD    BIT1
 431 #define GAPD    BIT1
 432 #define BRKE    BIT0
 433 #define IDLD    BIT0
 434
 435 /* IE2 & SR2 */
 436 #define EOM     BIT7
 437 #define PMP     BIT6
 438 #define SHRT    BIT6
 439 #define PE      BIT5
 440 #define ABT     BIT5
 441 #define FRME    BIT4
 442 #define RBIT    BIT4
 443 #define OVRN    BIT3
 444 #define CRCE    BIT2
 445
 446
 447 /*
 448  * Global linked list of SyncLink devices
 449  */
 450 static SLMP_INFO *synclinkmp_device_list = NULL;
 451 static int synclinkmp_adapter_count = -1;
 452 static int synclinkmp_device_count = 0;
 453
 454 /*
 455  * Set this param to non-zero to load eax with the
 456  * .text section address and breakpoint on module load.
 457  * This is useful for use with gdb and add-symbol-file command.
 458  */
 459 static int break_on_load = 0;
 460
 461 /*
 462  * Driver major number, defaults to zero to get auto
 463  * assigned major number. May be forced as module parameter.
 464  */
 465 static int ttymajor = 0;
 466
 467 /*
 468  * Array of user specified options for ISA adapters.
 469  */
 470 static int debug_level = 0;
 471 static int maxframe[MAX_DEVICES] = {0,};
 472
 473 module_param(break_on_load, bool, 0);
 474 module_param(ttymajor, int, 0);
 475 module_param(debug_level, int, 0);
 476 module_param_array(maxframe, int, NULL, 0);
 477
 478 static char *driver_name = "SyncLink MultiPort driver";
 479 static char *driver_version = "$Revision: 4.38 $";
 480
 481 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 482 static void synclinkmp_remove_one(struct pci_dev *dev);
 483
 484 static struct pci_device_id synclinkmp_pci_tbl[] = {
 485         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 486         { 0, }, /* terminate list */
 487 };
 488 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 489
 490 MODULE_LICENSE("GPL");
 491
 492 static struct pci_driver synclinkmp_pci_driver = {
 493         .name           = "synclinkmp",
 494         .id_table       = synclinkmp_pci_tbl,
 495         .probe          = synclinkmp_init_one,
 496         .remove         = __devexit_p(synclinkmp_remove_one),
 497 };
 498
 499
 500 static struct tty_driver *serial_driver;
 501
 502 /* number of characters left in xmit buffer before we ask for more */
 503 #define WAKEUP_CHARS 256
 504
 505
 506 /* tty callbacks */
 507
 508 static int  open(struct tty_struct *tty, struct file * filp);
 509 static void close(struct tty_struct *tty, struct file * filp);
 510 static void hangup(struct tty_struct *tty);
 511 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 512
 513 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 514 static int put_char(struct tty_struct *tty, unsigned char ch);
 515 static void send_xchar(struct tty_struct *tty, char ch);
 516 static void wait_until_sent(struct tty_struct *tty, int timeout);
 517 static int  write_room(struct tty_struct *tty);
 518 static void flush_chars(struct tty_struct *tty);
 519 static void flush_buffer(struct tty_struct *tty);
 520 static void tx_hold(struct tty_struct *tty);
 521 static void tx_release(struct tty_struct *tty);
 522
 523 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 524 static int  chars_in_buffer(struct tty_struct *tty);
 525 static void throttle(struct tty_struct * tty);
 526 static void unthrottle(struct tty_struct * tty);
 527 static int set_break(struct tty_struct *tty, int break_state);
 528
 529 #if SYNCLINK_GENERIC_HDLC
 530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 531 static void hdlcdev_tx_done(SLMP_INFO *info);
 532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 533 static int  hdlcdev_init(SLMP_INFO *info);
 534 static void hdlcdev_exit(SLMP_INFO *info);
 535 #endif
 536
 537 /* ioctl handlers */
 538
 539 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 540 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 541 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 542 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 543 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 544 static int  tx_enable(SLMP_INFO *info, int enable);
 545 static int  tx_abort(SLMP_INFO *info);
 546 static int  rx_enable(SLMP_INFO *info, int enable);
 547 static int  modem_input_wait(SLMP_INFO *info,int arg);
 548 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 549 static int  tiocmget(struct tty_struct *tty, struct file *file);
 550 static int  tiocmset(struct tty_struct *tty, struct file *file,
 551                      unsigned int set, unsigned int clear);
 552 static int  set_break(struct tty_struct *tty, int break_state);
 553
 554 static void add_device(SLMP_INFO *info);
 555 static void device_init(int adapter_num, struct pci_dev *pdev);
 556 static int  claim_resources(SLMP_INFO *info);
 557 static void release_resources(SLMP_INFO *info);
 558
 559 static int  startup(SLMP_INFO *info);
 560 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 561 static int carrier_raised(struct tty_port *port);
 562 static void shutdown(SLMP_INFO *info);
 563 static void program_hw(SLMP_INFO *info);
 564 static void change_params(SLMP_INFO *info);
 565
 566 static bool init_adapter(SLMP_INFO *info);
 567 static bool register_test(SLMP_INFO *info);
 568 static bool irq_test(SLMP_INFO *info);
 569 static bool loopback_test(SLMP_INFO *info);
 570 static int  adapter_test(SLMP_INFO *info);
 571 static bool memory_test(SLMP_INFO *info);
 572
 573 static void reset_adapter(SLMP_INFO *info);
 574 static void reset_port(SLMP_INFO *info);
 575 static void async_mode(SLMP_INFO *info);
 576 static void hdlc_mode(SLMP_INFO *info);
 577
 578 static void rx_stop(SLMP_INFO *info);
 579 static void rx_start(SLMP_INFO *info);
 580 static void rx_reset_buffers(SLMP_INFO *info);
 581 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 582 static bool rx_get_frame(SLMP_INFO *info);
 583
 584 static void tx_start(SLMP_INFO *info);
 585 static void tx_stop(SLMP_INFO *info);
 586 static void tx_load_fifo(SLMP_INFO *info);
 587 static void tx_set_idle(SLMP_INFO *info);
 588 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 589
 590 static void get_signals(SLMP_INFO *info);
 591 static void set_signals(SLMP_INFO *info);
 592 static void enable_loopback(SLMP_INFO *info, int enable);
 593 static void set_rate(SLMP_INFO *info, u32 data_rate);
 594
 595 static int  bh_action(SLMP_INFO *info);
 596 static void bh_handler(struct work_struct *work);
 597 static void bh_receive(SLMP_INFO *info);
 598 static void bh_transmit(SLMP_INFO *info);
 599 static void bh_status(SLMP_INFO *info);
 600 static void isr_timer(SLMP_INFO *info);
 601 static void isr_rxint(SLMP_INFO *info);
 602 static void isr_rxrdy(SLMP_INFO *info);
 603 static void isr_txint(SLMP_INFO *info);
 604 static void isr_txrdy(SLMP_INFO *info);
 605 static void isr_rxdmaok(SLMP_INFO *info);
 606 static void isr_rxdmaerror(SLMP_INFO *info);
 607 static void isr_txdmaok(SLMP_INFO *info);
 608 static void isr_txdmaerror(SLMP_INFO *info);
 609 static void isr_io_pin(SLMP_INFO *info, u16 status);
 610
 611 static int  alloc_dma_bufs(SLMP_INFO *info);
 612 static void free_dma_bufs(SLMP_INFO *info);
 613 static int  alloc_buf_list(SLMP_INFO *info);
 614 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 615 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 616 static void free_tmp_rx_buf(SLMP_INFO *info);
 617
 618 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 619 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 620 static void tx_timeout(unsigned long context);
 621 static void status_timeout(unsigned long context);
 622
 623 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 624 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 625 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 626 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 627 static unsigned char read_status_reg(SLMP_INFO * info);
 628 static void write_control_reg(SLMP_INFO * info);
 629
 630
 631 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 632 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 633 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 634
 635 static u32 misc_ctrl_value = 0x007e4040;
 636 static u32 lcr1_brdr_value = 0x00800028;
 637
 638 static u32 read_ahead_count = 8;
 639
 640 /* DPCR, DMA Priority Control
 641  *
 642  * 07..05  Not used, must be 0
 643  * 04      BRC, bus release condition: 0=all transfers complete
 644  *              1=release after 1 xfer on all channels
 645  * 03      CCC, channel change condition: 0=every cycle
 646  *              1=after each channel completes all xfers
 647  * 02..00  PR<2..0>, priority 100=round robin
 648  *
 649  * 00000100 = 0x00
 650  */
 651 static unsigned char dma_priority = 0x04;
 652
 653 // Number of bytes that can be written to shared RAM
 654 // in a single write operation
 655 static u32 sca_pci_load_interval = 64;
 656
 657 /*
 658  * 1st function defined in .text section. Calling this function in
 659  * init_module() followed by a breakpoint allows a remote debugger
 660  * (gdb) to get the .text address for the add-symbol-file command.
 661  * This allows remote debugging of dynamically loadable modules.
 662  */
 663 static void* synclinkmp_get_text_ptr(void);
 664 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 665
 666 static inline int sanity_check(SLMP_INFO *info,
 667                                char *name, const char *routine)
 668 {
 669 #ifdef SANITY_CHECK
 670         static const char *badmagic =
 671                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 672         static const char *badinfo =
 673                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 674
 675         if (!info) {
 676                 printk(badinfo, name, routine);
 677                 return 1;
 678         }
 679         if (info->magic != MGSL_MAGIC) {
 680                 printk(badmagic, name, routine);
 681                 return 1;
 682         }
 683 #else
 684         if (!info)
 685                 return 1;
 686 #endif
 687         return 0;
 688 }
 689
 690 /**
 691  * line discipline callback wrappers
 692  *
 693  * The wrappers maintain line discipline references
 694  * while calling into the line discipline.
 695  *
 696  * ldisc_receive_buf  - pass receive data to line discipline
 697  */
 698
 699 static void ldisc_receive_buf(struct tty_struct *tty,
 700                               const __u8 *data, char *flags, int count)
 701 {
 702         struct tty_ldisc *ld;
 703         if (!tty)
 704                 return;
 705         ld = tty_ldisc_ref(tty);
 706         if (ld) {
 707                 if (ld->ops->receive_buf)
 708                         ld->ops->receive_buf(tty, data, flags, count);
 709                 tty_ldisc_deref(ld);
 710         }
 711 }
 712
 713 /* tty callbacks */
 714
 715 /* Called when a port is opened.  Init and enable port.
 716  */
 717 static int open(struct tty_struct *tty, struct file *filp)
 718 {
 719         SLMP_INFO *info;
 720         int retval, line;
 721         unsigned long flags;
 722
 723         line = tty->index;
 724         if ((line < 0) || (line >= synclinkmp_device_count)) {
 725                 printk("%s(%d): open with invalid line #%d.\n",
 726                         __FILE__,__LINE__,line);
 727                 return -ENODEV;
 728         }
 729
 730         info = synclinkmp_device_list;
 731         while(info && info->line != line)
 732                 info = info->next_device;
 733         if (sanity_check(info, tty->name, "open"))
 734                 return -ENODEV;
 735         if ( info->init_error ) {
 736                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 737                         __FILE__,__LINE__,info->device_name,info->init_error);
 738                 return -ENODEV;
 739         }
 740
 741         tty->driver_data = info;
 742         info->port.tty = tty;
 743
 744         if (debug_level >= DEBUG_LEVEL_INFO)
 745                 printk("%s(%d):%s open(), old ref count = %d\n",
 746                          __FILE__,__LINE__,tty->driver->name, info->port.count);
 747
 748         /* If port is closing, signal caller to try again */
 749         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 750                 if (info->port.flags & ASYNC_CLOSING)
 751                         interruptible_sleep_on(&info->port.close_wait);
 752                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 753                         -EAGAIN : -ERESTARTSYS);
 754                 goto cleanup;
 755         }
 756
 757         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 758
 759         spin_lock_irqsave(&info->netlock, flags);
 760         if (info->netcount) {
 761                 retval = -EBUSY;
 762                 spin_unlock_irqrestore(&info->netlock, flags);
 763                 goto cleanup;
 764         }
 765         info->port.count++;
 766         spin_unlock_irqrestore(&info->netlock, flags);
 767
 768         if (info->port.count == 1) {
 769                 /* 1st open on this device, init hardware */
 770                 retval = startup(info);
 771                 if (retval < 0)
 772                         goto cleanup;
 773         }
 774
 775         retval = block_til_ready(tty, filp, info);
 776         if (retval) {
 777                 if (debug_level >= DEBUG_LEVEL_INFO)
 778                         printk("%s(%d):%s block_til_ready() returned %d\n",
 779                                  __FILE__,__LINE__, info->device_name, retval);
 780                 goto cleanup;
 781         }
 782
 783         if (debug_level >= DEBUG_LEVEL_INFO)
 784                 printk("%s(%d):%s open() success\n",
 785                          __FILE__,__LINE__, info->device_name);
 786         retval = 0;
 787
 788 cleanup:
 789         if (retval) {
 790                 if (tty->count == 1)
 791                         info->port.tty = NULL; /* tty layer will release tty struct */
 792                 if(info->port.count)
 793                         info->port.count--;
 794         }
 795
 796         return retval;
 797 }
 798
 799 /* Called when port is closed. Wait for remaining data to be
 800  * sent. Disable port and free resources.
 801  */
 802 static void close(struct tty_struct *tty, struct file *filp)
 803 {
 804         SLMP_INFO * info = tty->driver_data;
 805
 806         if (sanity_check(info, tty->name, "close"))
 807                 return;
 808
 809         if (debug_level >= DEBUG_LEVEL_INFO)
 810                 printk("%s(%d):%s close() entry, count=%d\n",
 811                          __FILE__,__LINE__, info->device_name, info->port.count);
 812
 813         if (tty_port_close_start(&info->port, tty, filp) == 0)
 814                 goto cleanup;
 815
 816         mutex_lock(&info->port.mutex);
 817         if (info->port.flags & ASYNC_INITIALIZED)
 818                 wait_until_sent(tty, info->timeout);
 819
 820         flush_buffer(tty);
 821         tty_ldisc_flush(tty);
 822         shutdown(info);
 823         mutex_unlock(&info->port.mutex);
 824
 825         tty_port_close_end(&info->port, tty);
 826         info->port.tty = NULL;
 827 cleanup:
 828         if (debug_level >= DEBUG_LEVEL_INFO)
 829                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 830                         tty->driver->name, info->port.count);
 831 }
 832
 833 /* Called by tty_hangup() when a hangup is signaled.
 834  * This is the same as closing all open descriptors for the port.
 835  */
 836 static void hangup(struct tty_struct *tty)
 837 {
 838         SLMP_INFO *info = tty->driver_data;
 839         unsigned long flags;
 840
 841         if (debug_level >= DEBUG_LEVEL_INFO)
 842                 printk("%s(%d):%s hangup()\n",
 843                          __FILE__,__LINE__, info->device_name );
 844
 845         if (sanity_check(info, tty->name, "hangup"))
 846                 return;
 847
 848         mutex_lock(&info->port.mutex);
 849         flush_buffer(tty);
 850         shutdown(info);
 851
 852         spin_lock_irqsave(&info->port.lock, flags);
 853         info->port.count = 0;
 854         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 855         info->port.tty = NULL;
 856         spin_unlock_irqrestore(&info->port.lock, flags);
 857         mutex_unlock(&info->port.mutex);
 858
 859         wake_up_interruptible(&info->port.open_wait);
 860 }
 861
 862 /* Set new termios settings
 863  */
 864 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 865 {
 866         SLMP_INFO *info = tty->driver_data;
 867         unsigned long flags;
 868
 869         if (debug_level >= DEBUG_LEVEL_INFO)
 870                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 871                         tty->driver->name );
 872
 873         change_params(info);
 874
 875         /* Handle transition to B0 status */
 876         if (old_termios->c_cflag & CBAUD &&
 877             !(tty->termios->c_cflag & CBAUD)) {
 878                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 879                 spin_lock_irqsave(&info->lock,flags);
 880                 set_signals(info);
 881                 spin_unlock_irqrestore(&info->lock,flags);
 882         }
 883
 884         /* Handle transition away from B0 status */
 885         if (!(old_termios->c_cflag & CBAUD) &&
 886             tty->termios->c_cflag & CBAUD) {
 887                 info->serial_signals |= SerialSignal_DTR;
 888                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 889                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 890                         info->serial_signals |= SerialSignal_RTS;
 891                 }
 892                 spin_lock_irqsave(&info->lock,flags);
 893                 set_signals(info);
 894                 spin_unlock_irqrestore(&info->lock,flags);
 895         }
 896
 897         /* Handle turning off CRTSCTS */
 898         if (old_termios->c_cflag & CRTSCTS &&
 899             !(tty->termios->c_cflag & CRTSCTS)) {
 900                 tty->hw_stopped = 0;
 901                 tx_release(tty);
 902         }
 903 }
 904
 905 /* Send a block of data
 906  *
 907  * Arguments:
 908  *
 909  *      tty             pointer to tty information structure
 910  *      buf             pointer to buffer containing send data
 911  *      count           size of send data in bytes
 912  *
 913  * Return Value:        number of characters written
 914  */
 915 static int write(struct tty_struct *tty,
 916                  const unsigned char *buf, int count)
 917 {
 918         int     c, ret = 0;
 919         SLMP_INFO *info = tty->driver_data;
 920         unsigned long flags;
 921
 922         if (debug_level >= DEBUG_LEVEL_INFO)
 923                 printk("%s(%d):%s write() count=%d\n",
 924                        __FILE__,__LINE__,info->device_name,count);
 925
 926         if (sanity_check(info, tty->name, "write"))
 927                 goto cleanup;
 928
 929         if (!info->tx_buf)
 930                 goto cleanup;
 931
 932         if (info->params.mode == MGSL_MODE_HDLC) {
 933                 if (count > info->max_frame_size) {
 934                         ret = -EIO;
 935                         goto cleanup;
 936                 }
 937                 if (info->tx_active)
 938                         goto cleanup;
 939                 if (info->tx_count) {
 940                         /* send accumulated data from send_char() calls */
 941                         /* as frame and wait before accepting more data. */
 942                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 943                         goto start;
 944                 }
 945                 ret = info->tx_count = count;
 946                 tx_load_dma_buffer(info, buf, count);
 947                 goto start;
 948         }
 949
 950         for (;;) {
 951                 c = min_t(int, count,
 952                         min(info->max_frame_size - info->tx_count - 1,
 953                             info->max_frame_size - info->tx_put));
 954                 if (c <= 0)
 955                         break;
 956
 957                 memcpy(info->tx_buf + info->tx_put, buf, c);
 958
 959                 spin_lock_irqsave(&info->lock,flags);
 960                 info->tx_put += c;
 961                 if (info->tx_put >= info->max_frame_size)
 962                         info->tx_put -= info->max_frame_size;
 963                 info->tx_count += c;
 964                 spin_unlock_irqrestore(&info->lock,flags);
 965
 966                 buf += c;
 967                 count -= c;
 968                 ret += c;
 969         }
 970
 971         if (info->params.mode == MGSL_MODE_HDLC) {
 972                 if (count) {
 973                         ret = info->tx_count = 0;
 974                         goto cleanup;
 975                 }
 976                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 977         }
 978 start:
 979         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 980                 spin_lock_irqsave(&info->lock,flags);
 981                 if (!info->tx_active)
 982                         tx_start(info);
 983                 spin_unlock_irqrestore(&info->lock,flags);
 984         }
 985
 986 cleanup:
 987         if (debug_level >= DEBUG_LEVEL_INFO)
 988                 printk( "%s(%d):%s write() returning=%d\n",
 989                         __FILE__,__LINE__,info->device_name,ret);
 990         return ret;
 991 }
 992
 993 /* Add a character to the transmit buffer.
 994  */
 995 static int put_char(struct tty_struct *tty, unsigned char ch)
 996 {
 997         SLMP_INFO *info = tty->driver_data;
 998         unsigned long flags;
 999         int ret = 0;
1000
1001         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1002                 printk( "%s(%d):%s put_char(%d)\n",
1003                         __FILE__,__LINE__,info->device_name,ch);
1004         }
1005
1006         if (sanity_check(info, tty->name, "put_char"))
1007                 return 0;
1008
1009         if (!info->tx_buf)
1010                 return 0;
1011
1012         spin_lock_irqsave(&info->lock,flags);
1013
1014         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1015              !info->tx_active ) {
1016
1017                 if (info->tx_count < info->max_frame_size - 1) {
1018                         info->tx_buf[info->tx_put++] = ch;
1019                         if (info->tx_put >= info->max_frame_size)
1020                                 info->tx_put -= info->max_frame_size;
1021                         info->tx_count++;
1022                         ret = 1;
1023                 }
1024         }
1025
1026         spin_unlock_irqrestore(&info->lock,flags);
1027         return ret;
1028 }
1029
1030 /* Send a high-priority XON/XOFF character
1031  */
1032 static void send_xchar(struct tty_struct *tty, char ch)
1033 {
1034         SLMP_INFO *info = tty->driver_data;
1035         unsigned long flags;
1036
1037         if (debug_level >= DEBUG_LEVEL_INFO)
1038                 printk("%s(%d):%s send_xchar(%d)\n",
1039                          __FILE__,__LINE__, info->device_name, ch );
1040
1041         if (sanity_check(info, tty->name, "send_xchar"))
1042                 return;
1043
1044         info->x_char = ch;
1045         if (ch) {
1046                 /* Make sure transmit interrupts are on */
1047                 spin_lock_irqsave(&info->lock,flags);
1048                 if (!info->tx_enabled)
1049                         tx_start(info);
1050                 spin_unlock_irqrestore(&info->lock,flags);
1051         }
1052 }
1053
1054 /* Wait until the transmitter is empty.
1055  */
1056 static void wait_until_sent(struct tty_struct *tty, int timeout)
1057 {
1058         SLMP_INFO * info = tty->driver_data;
1059         unsigned long orig_jiffies, char_time;
1060
1061         if (!info )
1062                 return;
1063
1064         if (debug_level >= DEBUG_LEVEL_INFO)
1065                 printk("%s(%d):%s wait_until_sent() entry\n",
1066                          __FILE__,__LINE__, info->device_name );
1067
1068         if (sanity_check(info, tty->name, "wait_until_sent"))
1069                 return;
1070
1071         if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1072                 goto exit;
1073
1074         orig_jiffies = jiffies;
1075
1076         /* Set check interval to 1/5 of estimated time to
1077          * send a character, and make it at least 1. The check
1078          * interval should also be less than the timeout.
1079          * Note: use tight timings here to satisfy the NIST-PCTS.
1080          */
1081
1082         if ( info->params.data_rate ) {
1083                 char_time = info->timeout/(32 * 5);
1084                 if (!char_time)
1085                         char_time++;
1086         } else
1087                 char_time = 1;
1088
1089         if (timeout)
1090                 char_time = min_t(unsigned long, char_time, timeout);
1091
1092         if ( info->params.mode == MGSL_MODE_HDLC ) {
1093                 while (info->tx_active) {
1094                         msleep_interruptible(jiffies_to_msecs(char_time));
1095                         if (signal_pending(current))
1096                                 break;
1097                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1098                                 break;
1099                 }
1100         } else {
1101                 /*
1102                  * TODO: determine if there is something similar to USC16C32
1103                  *       TXSTATUS_ALL_SENT status
1104                  */
1105                 while ( info->tx_active && info->tx_enabled) {
1106                         msleep_interruptible(jiffies_to_msecs(char_time));
1107                         if (signal_pending(current))
1108                                 break;
1109                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1110                                 break;
1111                 }
1112         }
1113
1114 exit:
1115         if (debug_level >= DEBUG_LEVEL_INFO)
1116                 printk("%s(%d):%s wait_until_sent() exit\n",
1117                          __FILE__,__LINE__, info->device_name );
1118 }
1119
1120 /* Return the count of free bytes in transmit buffer
1121  */
1122 static int write_room(struct tty_struct *tty)
1123 {
1124         SLMP_INFO *info = tty->driver_data;
1125         int ret;
1126
1127         if (sanity_check(info, tty->name, "write_room"))
1128                 return 0;
1129
1130         if (info->params.mode == MGSL_MODE_HDLC) {
1131                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1132         } else {
1133                 ret = info->max_frame_size - info->tx_count - 1;
1134                 if (ret < 0)
1135                         ret = 0;
1136         }
1137
1138         if (debug_level >= DEBUG_LEVEL_INFO)
1139                 printk("%s(%d):%s write_room()=%d\n",
1140                        __FILE__, __LINE__, info->device_name, ret);
1141
1142         return ret;
1143 }
1144
1145 /* enable transmitter and send remaining buffered characters
1146  */
1147 static void flush_chars(struct tty_struct *tty)
1148 {
1149         SLMP_INFO *info = tty->driver_data;
1150         unsigned long flags;
1151
1152         if ( debug_level >= DEBUG_LEVEL_INFO )
1153                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1154                         __FILE__,__LINE__,info->device_name,info->tx_count);
1155
1156         if (sanity_check(info, tty->name, "flush_chars"))
1157                 return;
1158
1159         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1160             !info->tx_buf)
1161                 return;
1162
1163         if ( debug_level >= DEBUG_LEVEL_INFO )
1164                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1165                         __FILE__,__LINE__,info->device_name );
1166
1167         spin_lock_irqsave(&info->lock,flags);
1168
1169         if (!info->tx_active) {
1170                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1171                         info->tx_count ) {
1172                         /* operating in synchronous (frame oriented) mode */
1173                         /* copy data from circular tx_buf to */
1174                         /* transmit DMA buffer. */
1175                         tx_load_dma_buffer(info,
1176                                  info->tx_buf,info->tx_count);
1177                 }
1178                 tx_start(info);
1179         }
1180
1181         spin_unlock_irqrestore(&info->lock,flags);
1182 }
1183
1184 /* Discard all data in the send buffer
1185  */
1186 static void flush_buffer(struct tty_struct *tty)
1187 {
1188         SLMP_INFO *info = tty->driver_data;
1189         unsigned long flags;
1190
1191         if (debug_level >= DEBUG_LEVEL_INFO)
1192                 printk("%s(%d):%s flush_buffer() entry\n",
1193                          __FILE__,__LINE__, info->device_name );
1194
1195         if (sanity_check(info, tty->name, "flush_buffer"))
1196                 return;
1197
1198         spin_lock_irqsave(&info->lock,flags);
1199         info->tx_count = info->tx_put = info->tx_get = 0;
1200         del_timer(&info->tx_timer);
1201         spin_unlock_irqrestore(&info->lock,flags);
1202
1203         tty_wakeup(tty);
1204 }
1205
1206 /* throttle (stop) transmitter
1207  */
1208 static void tx_hold(struct tty_struct *tty)
1209 {
1210         SLMP_INFO *info = tty->driver_data;
1211         unsigned long flags;
1212
1213         if (sanity_check(info, tty->name, "tx_hold"))
1214                 return;
1215
1216         if ( debug_level >= DEBUG_LEVEL_INFO )
1217                 printk("%s(%d):%s tx_hold()\n",
1218                         __FILE__,__LINE__,info->device_name);
1219
1220         spin_lock_irqsave(&info->lock,flags);
1221         if (info->tx_enabled)
1222                 tx_stop(info);
1223         spin_unlock_irqrestore(&info->lock,flags);
1224 }
1225
1226 /* release (start) transmitter
1227  */
1228 static void tx_release(struct tty_struct *tty)
1229 {
1230         SLMP_INFO *info = tty->driver_data;
1231         unsigned long flags;
1232
1233         if (sanity_check(info, tty->name, "tx_release"))
1234                 return;
1235
1236         if ( debug_level >= DEBUG_LEVEL_INFO )
1237                 printk("%s(%d):%s tx_release()\n",
1238                         __FILE__,__LINE__,info->device_name);
1239
1240         spin_lock_irqsave(&info->lock,flags);
1241         if (!info->tx_enabled)
1242                 tx_start(info);
1243         spin_unlock_irqrestore(&info->lock,flags);
1244 }
1245
1246 /* Service an IOCTL request
1247  *
1248  * Arguments:
1249  *
1250  *      tty     pointer to tty instance data
1251  *      file    pointer to associated file object for device
1252  *      cmd     IOCTL command code
1253  *      arg     command argument/context
1254  *
1255  * Return Value:        0 if success, otherwise error code
1256  */
1257 static int ioctl(struct tty_struct *tty, struct file *file,
1258                  unsigned int cmd, unsigned long arg)
1259 {
1260         SLMP_INFO *info = tty->driver_data;
1261         int error;
1262         struct mgsl_icount cnow;        /* kernel counter temps */
1263         struct serial_icounter_struct __user *p_cuser;  /* user space */
1264         unsigned long flags;
1265         void __user *argp = (void __user *)arg;
1266
1267         if (debug_level >= DEBUG_LEVEL_INFO)
1268                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1269                         info->device_name, cmd );
1270
1271         if (sanity_check(info, tty->name, "ioctl"))
1272                 return -ENODEV;
1273
1274         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1275             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1276                 if (tty->flags & (1 << TTY_IO_ERROR))
1277                     return -EIO;
1278         }
1279
1280         switch (cmd) {
1281         case MGSL_IOCGPARAMS:
1282                 return get_params(info, argp);
1283         case MGSL_IOCSPARAMS:
1284                 return set_params(info, argp);
1285         case MGSL_IOCGTXIDLE:
1286                 return get_txidle(info, argp);
1287         case MGSL_IOCSTXIDLE:
1288                 return set_txidle(info, (int)arg);
1289         case MGSL_IOCTXENABLE:
1290                 return tx_enable(info, (int)arg);
1291         case MGSL_IOCRXENABLE:
1292                 return rx_enable(info, (int)arg);
1293         case MGSL_IOCTXABORT:
1294                 return tx_abort(info);
1295         case MGSL_IOCGSTATS:
1296                 return get_stats(info, argp);
1297         case MGSL_IOCWAITEVENT:
1298                 return wait_mgsl_event(info, argp);
1299         case MGSL_IOCLOOPTXDONE:
1300                 return 0; // TODO: Not supported, need to document
1301                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1302                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1303                  */
1304         case TIOCMIWAIT:
1305                 return modem_input_wait(info,(int)arg);
1306
1307                 /*
1308                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1309                  * Return: write counters to the user passed counter struct
1310                  * NB: both 1->0 and 0->1 transitions are counted except for
1311                  *     RI where only 0->1 is counted.
1312                  */
1313         case TIOCGICOUNT:
1314                 spin_lock_irqsave(&info->lock,flags);
1315                 cnow = info->icount;
1316                 spin_unlock_irqrestore(&info->lock,flags);
1317                 p_cuser = argp;
1318                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1319                 if (error) return error;
1320                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1321                 if (error) return error;
1322                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1323                 if (error) return error;
1324                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1325                 if (error) return error;
1326                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1327                 if (error) return error;
1328                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1329                 if (error) return error;
1330                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1331                 if (error) return error;
1332                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1333                 if (error) return error;
1334                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1335                 if (error) return error;
1336                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1337                 if (error) return error;
1338                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1339                 if (error) return error;
1340                 return 0;
1341         default:
1342                 return -ENOIOCTLCMD;
1343         }
1344         return 0;
1345 }
1346
1347 /*
1348  * /proc fs routines....
1349  */
1350
1351 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1352 {
1353         char    stat_buf[30];
1354         unsigned long flags;
1355
1356         seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1357                        "\tIRQ=%d MaxFrameSize=%u\n",
1358                 info->device_name,
1359                 info->phys_sca_base,
1360                 info->phys_memory_base,
1361                 info->phys_statctrl_base,
1362                 info->phys_lcr_base,
1363                 info->irq_level,
1364                 info->max_frame_size );
1365
1366         /* output current serial signal states */
1367         spin_lock_irqsave(&info->lock,flags);
1368         get_signals(info);
1369         spin_unlock_irqrestore(&info->lock,flags);
1370
1371         stat_buf[0] = 0;
1372         stat_buf[1] = 0;
1373         if (info->serial_signals & SerialSignal_RTS)
1374                 strcat(stat_buf, "|RTS");
1375         if (info->serial_signals & SerialSignal_CTS)
1376                 strcat(stat_buf, "|CTS");
1377         if (info->serial_signals & SerialSignal_DTR)
1378                 strcat(stat_buf, "|DTR");
1379         if (info->serial_signals & SerialSignal_DSR)
1380                 strcat(stat_buf, "|DSR");
1381         if (info->serial_signals & SerialSignal_DCD)
1382                 strcat(stat_buf, "|CD");
1383         if (info->serial_signals & SerialSignal_RI)
1384                 strcat(stat_buf, "|RI");
1385
1386         if (info->params.mode == MGSL_MODE_HDLC) {
1387                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1388                               info->icount.txok, info->icount.rxok);
1389                 if (info->icount.txunder)
1390                         seq_printf(m, " txunder:%d", info->icount.txunder);
1391                 if (info->icount.txabort)
1392                         seq_printf(m, " txabort:%d", info->icount.txabort);
1393                 if (info->icount.rxshort)
1394                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1395                 if (info->icount.rxlong)
1396                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1397                 if (info->icount.rxover)
1398                         seq_printf(m, " rxover:%d", info->icount.rxover);
1399                 if (info->icount.rxcrc)
1400                         seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1401         } else {
1402                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1403                               info->icount.tx, info->icount.rx);
1404                 if (info->icount.frame)
1405                         seq_printf(m, " fe:%d", info->icount.frame);
1406                 if (info->icount.parity)
1407                         seq_printf(m, " pe:%d", info->icount.parity);
1408                 if (info->icount.brk)
1409                         seq_printf(m, " brk:%d", info->icount.brk);
1410                 if (info->icount.overrun)
1411                         seq_printf(m, " oe:%d", info->icount.overrun);
1412         }
1413
1414         /* Append serial signal status to end */
1415         seq_printf(m, " %s\n", stat_buf+1);
1416
1417         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1418          info->tx_active,info->bh_requested,info->bh_running,
1419          info->pending_bh);
1420 }
1421
1422 /* Called to print information about devices
1423  */
1424 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1425 {
1426         SLMP_INFO *info;
1427
1428         seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1429
1430         info = synclinkmp_device_list;
1431         while( info ) {
1432                 line_info(m, info);
1433                 info = info->next_device;
1434         }
1435         return 0;
1436 }
1437
1438 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1439 {
1440         return single_open(file, synclinkmp_proc_show, NULL);
1441 }
1442
1443 static const struct file_operations synclinkmp_proc_fops = {
1444         .owner          = THIS_MODULE,
1445         .open           = synclinkmp_proc_open,
1446         .read           = seq_read,
1447         .llseek         = seq_lseek,
1448         .release        = single_release,
1449 };
1450
1451 /* Return the count of bytes in transmit buffer
1452  */
1453 static int chars_in_buffer(struct tty_struct *tty)
1454 {
1455         SLMP_INFO *info = tty->driver_data;
1456
1457         if (sanity_check(info, tty->name, "chars_in_buffer"))
1458                 return 0;
1459
1460         if (debug_level >= DEBUG_LEVEL_INFO)
1461                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1462                        __FILE__, __LINE__, info->device_name, info->tx_count);
1463
1464         return info->tx_count;
1465 }
1466
1467 /* Signal remote device to throttle send data (our receive data)
1468  */
1469 static void throttle(struct tty_struct * tty)
1470 {
1471         SLMP_INFO *info = tty->driver_data;
1472         unsigned long flags;
1473
1474         if (debug_level >= DEBUG_LEVEL_INFO)
1475                 printk("%s(%d):%s throttle() entry\n",
1476                          __FILE__,__LINE__, info->device_name );
1477
1478         if (sanity_check(info, tty->name, "throttle"))
1479                 return;
1480
1481         if (I_IXOFF(tty))
1482                 send_xchar(tty, STOP_CHAR(tty));
1483
1484         if (tty->termios->c_cflag & CRTSCTS) {
1485                 spin_lock_irqsave(&info->lock,flags);
1486                 info->serial_signals &= ~SerialSignal_RTS;
1487                 set_signals(info);
1488                 spin_unlock_irqrestore(&info->lock,flags);
1489         }
1490 }
1491
1492 /* Signal remote device to stop throttling send data (our receive data)
1493  */
1494 static void unthrottle(struct tty_struct * tty)
1495 {
1496         SLMP_INFO *info = tty->driver_data;
1497         unsigned long flags;
1498
1499         if (debug_level >= DEBUG_LEVEL_INFO)
1500                 printk("%s(%d):%s unthrottle() entry\n",
1501                          __FILE__,__LINE__, info->device_name );
1502
1503         if (sanity_check(info, tty->name, "unthrottle"))
1504                 return;
1505
1506         if (I_IXOFF(tty)) {
1507                 if (info->x_char)
1508                         info->x_char = 0;
1509                 else
1510                         send_xchar(tty, START_CHAR(tty));
1511         }
1512
1513         if (tty->termios->c_cflag & CRTSCTS) {
1514                 spin_lock_irqsave(&info->lock,flags);
1515                 info->serial_signals |= SerialSignal_RTS;
1516                 set_signals(info);
1517                 spin_unlock_irqrestore(&info->lock,flags);
1518         }
1519 }
1520
1521 /* set or clear transmit break condition
1522  * break_state  -1=set break condition, 0=clear
1523  */
1524 static int set_break(struct tty_struct *tty, int break_state)
1525 {
1526         unsigned char RegValue;
1527         SLMP_INFO * info = tty->driver_data;
1528         unsigned long flags;
1529
1530         if (debug_level >= DEBUG_LEVEL_INFO)
1531                 printk("%s(%d):%s set_break(%d)\n",
1532                          __FILE__,__LINE__, info->device_name, break_state);
1533
1534         if (sanity_check(info, tty->name, "set_break"))
1535                 return -EINVAL;
1536
1537         spin_lock_irqsave(&info->lock,flags);
1538         RegValue = read_reg(info, CTL);
1539         if (break_state == -1)
1540                 RegValue |= BIT3;
1541         else
1542                 RegValue &= ~BIT3;
1543         write_reg(info, CTL, RegValue);
1544         spin_unlock_irqrestore(&info->lock,flags);
1545         return 0;
1546 }
1547
1548 #if SYNCLINK_GENERIC_HDLC
1549
1550 /**
1551  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1552  * set encoding and frame check sequence (FCS) options
1553  *
1554  * dev       pointer to network device structure
1555  * encoding  serial encoding setting
1556  * parity    FCS setting
1557  *
1558  * returns 0 if success, otherwise error code
1559  */
1560 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1561                           unsigned short parity)
1562 {
1563         SLMP_INFO *info = dev_to_port(dev);
1564         unsigned char  new_encoding;
1565         unsigned short new_crctype;
1566
1567         /* return error if TTY interface open */
1568         if (info->port.count)
1569                 return -EBUSY;
1570
1571         switch (encoding)
1572         {
1573         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1574         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1575         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1576         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1577         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1578         default: return -EINVAL;
1579         }
1580
1581         switch (parity)
1582         {
1583         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1584         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1585         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1586         default: return -EINVAL;
1587         }
1588
1589         info->params.encoding = new_encoding;
1590         info->params.crc_type = new_crctype;
1591
1592         /* if network interface up, reprogram hardware */
1593         if (info->netcount)
1594                 program_hw(info);
1595
1596         return 0;
1597 }
1598
1599 /**
1600  * called by generic HDLC layer to send frame
1601  *
1602  * skb  socket buffer containing HDLC frame
1603  * dev  pointer to network device structure
1604  */
1605 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1606                                       struct net_device *dev)
1607 {
1608         SLMP_INFO *info = dev_to_port(dev);
1609         unsigned long flags;
1610
1611         if (debug_level >= DEBUG_LEVEL_INFO)
1612                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1613
1614         /* stop sending until this frame completes */
1615         netif_stop_queue(dev);
1616
1617         /* copy data to device buffers */
1618         info->tx_count = skb->len;
1619         tx_load_dma_buffer(info, skb->data, skb->len);
1620
1621         /* update network statistics */
1622         dev->stats.tx_packets++;
1623         dev->stats.tx_bytes += skb->len;
1624
1625         /* done with socket buffer, so free it */
1626         dev_kfree_skb(skb);
1627
1628         /* save start time for transmit timeout detection */
1629         dev->trans_start = jiffies;
1630
1631         /* start hardware transmitter if necessary */
1632         spin_lock_irqsave(&info->lock,flags);
1633         if (!info->tx_active)
1634                 tx_start(info);
1635         spin_unlock_irqrestore(&info->lock,flags);
1636
1637         return NETDEV_TX_OK;
1638 }
1639
1640 /**
1641  * called by network layer when interface enabled
1642  * claim resources and initialize hardware
1643  *
1644  * dev  pointer to network device structure
1645  *
1646  * returns 0 if success, otherwise error code
1647  */
1648 static int hdlcdev_open(struct net_device *dev)
1649 {
1650         SLMP_INFO *info = dev_to_port(dev);
1651         int rc;
1652         unsigned long flags;
1653
1654         if (debug_level >= DEBUG_LEVEL_INFO)
1655                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1656
1657         /* generic HDLC layer open processing */
1658         if ((rc = hdlc_open(dev)))
1659                 return rc;
1660
1661         /* arbitrate between network and tty opens */
1662         spin_lock_irqsave(&info->netlock, flags);
1663         if (info->port.count != 0 || info->netcount != 0) {
1664                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1665                 spin_unlock_irqrestore(&info->netlock, flags);
1666                 return -EBUSY;
1667         }
1668         info->netcount=1;
1669         spin_unlock_irqrestore(&info->netlock, flags);
1670
1671         /* claim resources and init adapter */
1672         if ((rc = startup(info)) != 0) {
1673                 spin_lock_irqsave(&info->netlock, flags);
1674                 info->netcount=0;
1675                 spin_unlock_irqrestore(&info->netlock, flags);
1676                 return rc;
1677         }
1678
1679         /* assert DTR and RTS, apply hardware settings */
1680         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1681         program_hw(info);
1682
1683         /* enable network layer transmit */
1684         dev->trans_start = jiffies;
1685         netif_start_queue(dev);
1686
1687         /* inform generic HDLC layer of current DCD status */
1688         spin_lock_irqsave(&info->lock, flags);
1689         get_signals(info);
1690         spin_unlock_irqrestore(&info->lock, flags);
1691         if (info->serial_signals & SerialSignal_DCD)
1692                 netif_carrier_on(dev);
1693         else
1694                 netif_carrier_off(dev);
1695         return 0;
1696 }
1697
1698 /**
1699  * called by network layer when interface is disabled
1700  * shutdown hardware and release resources
1701  *
1702  * dev  pointer to network device structure
1703  *
1704  * returns 0 if success, otherwise error code
1705  */
1706 static int hdlcdev_close(struct net_device *dev)
1707 {
1708         SLMP_INFO *info = dev_to_port(dev);
1709         unsigned long flags;
1710
1711         if (debug_level >= DEBUG_LEVEL_INFO)
1712                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1713
1714         netif_stop_queue(dev);
1715
1716         /* shutdown adapter and release resources */
1717         shutdown(info);
1718
1719         hdlc_close(dev);
1720
1721         spin_lock_irqsave(&info->netlock, flags);
1722         info->netcount=0;
1723         spin_unlock_irqrestore(&info->netlock, flags);
1724
1725         return 0;
1726 }
1727
1728 /**
1729  * called by network layer to process IOCTL call to network device
1730  *
1731  * dev  pointer to network device structure
1732  * ifr  pointer to network interface request structure
1733  * cmd  IOCTL command code
1734  *
1735  * returns 0 if success, otherwise error code
1736  */
1737 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1738 {
1739         const size_t size = sizeof(sync_serial_settings);
1740         sync_serial_settings new_line;
1741         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1742         SLMP_INFO *info = dev_to_port(dev);
1743         unsigned int flags;
1744
1745         if (debug_level >= DEBUG_LEVEL_INFO)
1746                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1747
1748         /* return error if TTY interface open */
1749         if (info->port.count)
1750                 return -EBUSY;
1751
1752         if (cmd != SIOCWANDEV)
1753                 return hdlc_ioctl(dev, ifr, cmd);
1754
1755         switch(ifr->ifr_settings.type) {
1756         case IF_GET_IFACE: /* return current sync_serial_settings */
1757
1758                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1759                 if (ifr->ifr_settings.size < size) {
1760                         ifr->ifr_settings.size = size; /* data size wanted */
1761                         return -ENOBUFS;
1762                 }
1763
1764                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1765                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1766                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1767                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1768
1769                 switch (flags){
1770                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1771                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1772                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1773                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1774                 default: new_line.clock_type = CLOCK_DEFAULT;
1775                 }
1776
1777                 new_line.clock_rate = info->params.clock_speed;
1778                 new_line.loopback   = info->params.loopback ? 1:0;
1779
1780                 if (copy_to_user(line, &new_line, size))
1781                         return -EFAULT;
1782                 return 0;
1783
1784         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1785
1786                 if(!capable(CAP_NET_ADMIN))
1787                         return -EPERM;
1788                 if (copy_from_user(&new_line, line, size))
1789                         return -EFAULT;
1790
1791                 switch (new_line.clock_type)
1792                 {
1793                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1794                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1795                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1796                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1797                 case CLOCK_DEFAULT:  flags = info->params.flags &
1798                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1799                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1800                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1801                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1802                 default: return -EINVAL;
1803                 }
1804
1805                 if (new_line.loopback != 0 && new_line.loopback != 1)
1806                         return -EINVAL;
1807
1808                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1809                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1810                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1811                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1812                 info->params.flags |= flags;
1813
1814                 info->params.loopback = new_line.loopback;
1815
1816                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1817                         info->params.clock_speed = new_line.clock_rate;
1818                 else
1819                         info->params.clock_speed = 0;
1820
1821                 /* if network interface up, reprogram hardware */
1822                 if (info->netcount)
1823                         program_hw(info);
1824                 return 0;
1825
1826         default:
1827                 return hdlc_ioctl(dev, ifr, cmd);
1828         }
1829 }
1830
1831 /**
1832  * called by network layer when transmit timeout is detected
1833  *
1834  * dev  pointer to network device structure
1835  */
1836 static void hdlcdev_tx_timeout(struct net_device *dev)
1837 {
1838         SLMP_INFO *info = dev_to_port(dev);
1839         unsigned long flags;
1840
1841         if (debug_level >= DEBUG_LEVEL_INFO)
1842                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1843
1844         dev->stats.tx_errors++;
1845         dev->stats.tx_aborted_errors++;
1846
1847         spin_lock_irqsave(&info->lock,flags);
1848         tx_stop(info);
1849         spin_unlock_irqrestore(&info->lock,flags);
1850
1851         netif_wake_queue(dev);
1852 }
1853
1854 /**
1855  * called by device driver when transmit completes
1856  * reenable network layer transmit if stopped
1857  *
1858  * info  pointer to device instance information
1859  */
1860 static void hdlcdev_tx_done(SLMP_INFO *info)
1861 {
1862         if (netif_queue_stopped(info->netdev))
1863                 netif_wake_queue(info->netdev);
1864 }
1865
1866 /**
1867  * called by device driver when frame received
1868  * pass frame to network layer
1869  *
1870  * info  pointer to device instance information
1871  * buf   pointer to buffer contianing frame data
1872  * size  count of data bytes in buf
1873  */
1874 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1875 {
1876         struct sk_buff *skb = dev_alloc_skb(size);
1877         struct net_device *dev = info->netdev;
1878
1879         if (debug_level >= DEBUG_LEVEL_INFO)
1880                 printk("hdlcdev_rx(%s)\n",dev->name);
1881
1882         if (skb == NULL) {
1883                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1884                        dev->name);
1885                 dev->stats.rx_dropped++;
1886                 return;
1887         }
1888
1889         memcpy(skb_put(skb, size), buf, size);
1890
1891         skb->protocol = hdlc_type_trans(skb, dev);
1892
1893         dev->stats.rx_packets++;
1894         dev->stats.rx_bytes += size;
1895
1896         netif_rx(skb);
1897 }
1898
1899 static const struct net_device_ops hdlcdev_ops = {
1900         .ndo_open       = hdlcdev_open,
1901         .ndo_stop       = hdlcdev_close,
1902         .ndo_change_mtu = hdlc_change_mtu,
1903         .ndo_start_xmit = hdlc_start_xmit,
1904         .ndo_do_ioctl   = hdlcdev_ioctl,
1905         .ndo_tx_timeout = hdlcdev_tx_timeout,
1906 };
1907
1908 /**
1909  * called by device driver when adding device instance
1910  * do generic HDLC initialization
1911  *
1912  * info  pointer to device instance information
1913  *
1914  * returns 0 if success, otherwise error code
1915  */
1916 static int hdlcdev_init(SLMP_INFO *info)
1917 {
1918         int rc;
1919         struct net_device *dev;
1920         hdlc_device *hdlc;
1921
1922         /* allocate and initialize network and HDLC layer objects */
1923
1924         if (!(dev = alloc_hdlcdev(info))) {
1925                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1926                 return -ENOMEM;
1927         }
1928
1929         /* for network layer reporting purposes only */
1930         dev->mem_start = info->phys_sca_base;
1931         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1932         dev->irq       = info->irq_level;
1933
1934         /* network layer callbacks and settings */
1935         dev->netdev_ops     = &hdlcdev_ops;
1936         dev->watchdog_timeo = 10 * HZ;
1937         dev->tx_queue_len   = 50;
1938
1939         /* generic HDLC layer callbacks and settings */
1940         hdlc         = dev_to_hdlc(dev);
1941         hdlc->attach = hdlcdev_attach;
1942         hdlc->xmit   = hdlcdev_xmit;
1943
1944         /* register objects with HDLC layer */
1945         if ((rc = register_hdlc_device(dev))) {
1946                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1947                 free_netdev(dev);
1948                 return rc;
1949         }
1950
1951         info->netdev = dev;
1952         return 0;
1953 }
1954
1955 /**
1956  * called by device driver when removing device instance
1957  * do generic HDLC cleanup
1958  *
1959  * info  pointer to device instance information
1960  */
1961 static void hdlcdev_exit(SLMP_INFO *info)
1962 {
1963         unregister_hdlc_device(info->netdev);
1964         free_netdev(info->netdev);
1965         info->netdev = NULL;
1966 }
1967
1968 #endif /* CONFIG_HDLC */
1969
1970
1971 /* Return next bottom half action to perform.
1972  * Return Value:        BH action code or 0 if nothing to do.
1973  */
1974 static int bh_action(SLMP_INFO *info)
1975 {
1976         unsigned long flags;
1977         int rc = 0;
1978
1979         spin_lock_irqsave(&info->lock,flags);
1980
1981         if (info->pending_bh & BH_RECEIVE) {
1982                 info->pending_bh &= ~BH_RECEIVE;
1983                 rc = BH_RECEIVE;
1984         } else if (info->pending_bh & BH_TRANSMIT) {
1985                 info->pending_bh &= ~BH_TRANSMIT;
1986                 rc = BH_TRANSMIT;
1987         } else if (info->pending_bh & BH_STATUS) {
1988                 info->pending_bh &= ~BH_STATUS;
1989                 rc = BH_STATUS;
1990         }
1991
1992         if (!rc) {
1993                 /* Mark BH routine as complete */
1994                 info->bh_running = false;
1995                 info->bh_requested = false;
1996         }
1997
1998         spin_unlock_irqrestore(&info->lock,flags);
1999
2000         return rc;
2001 }
2002
2003 /* Perform bottom half processing of work items queued by ISR.
2004  */
2005 static void bh_handler(struct work_struct *work)
2006 {
2007         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2008         int action;
2009
2010         if (!info)
2011                 return;
2012
2013         if ( debug_level >= DEBUG_LEVEL_BH )
2014                 printk( "%s(%d):%s bh_handler() entry\n",
2015                         __FILE__,__LINE__,info->device_name);
2016
2017         info->bh_running = true;
2018
2019         while((action = bh_action(info)) != 0) {
2020
2021                 /* Process work item */
2022                 if ( debug_level >= DEBUG_LEVEL_BH )
2023                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2024                                 __FILE__,__LINE__,info->device_name, action);
2025
2026                 switch (action) {
2027
2028                 case BH_RECEIVE:
2029                         bh_receive(info);
2030                         break;
2031                 case BH_TRANSMIT:
2032                         bh_transmit(info);
2033                         break;
2034                 case BH_STATUS:
2035                         bh_status(info);
2036                         break;
2037                 default:
2038                         /* unknown work item ID */
2039                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2040                                 __FILE__,__LINE__,info->device_name,action);
2041                         break;
2042                 }
2043         }
2044
2045         if ( debug_level >= DEBUG_LEVEL_BH )
2046                 printk( "%s(%d):%s bh_handler() exit\n",
2047                         __FILE__,__LINE__,info->device_name);
2048 }
2049
2050 static void bh_receive(SLMP_INFO *info)
2051 {
2052         if ( debug_level >= DEBUG_LEVEL_BH )
2053                 printk( "%s(%d):%s bh_receive()\n",
2054                         __FILE__,__LINE__,info->device_name);
2055
2056         while( rx_get_frame(info) );
2057 }
2058
2059 static void bh_transmit(SLMP_INFO *info)
2060 {
2061         struct tty_struct *tty = info->port.tty;
2062
2063         if ( debug_level >= DEBUG_LEVEL_BH )
2064                 printk( "%s(%d):%s bh_transmit() entry\n",
2065                         __FILE__,__LINE__,info->device_name);
2066
2067         if (tty)
2068                 tty_wakeup(tty);
2069 }
2070
2071 static void bh_status(SLMP_INFO *info)
2072 {
2073         if ( debug_level >= DEBUG_LEVEL_BH )
2074                 printk( "%s(%d):%s bh_status() entry\n",
2075                         __FILE__,__LINE__,info->device_name);
2076
2077         info->ri_chkcount = 0;
2078         info->dsr_chkcount = 0;
2079         info->dcd_chkcount = 0;
2080         info->cts_chkcount = 0;
2081 }
2082
2083 static void isr_timer(SLMP_INFO * info)
2084 {
2085         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2086
2087         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2088         write_reg(info, IER2, 0);
2089
2090         /* TMCS, Timer Control/Status Register
2091          *
2092          * 07      CMF, Compare match flag (read only) 1=match
2093          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2094          * 05      Reserved, must be 0
2095          * 04      TME, Timer Enable
2096          * 03..00  Reserved, must be 0
2097          *
2098          * 0000 0000
2099          */
2100         write_reg(info, (unsigned char)(timer + TMCS), 0);
2101
2102         info->irq_occurred = true;
2103
2104         if ( debug_level >= DEBUG_LEVEL_ISR )
2105                 printk("%s(%d):%s isr_timer()\n",
2106                         __FILE__,__LINE__,info->device_name);
2107 }
2108
2109 static void isr_rxint(SLMP_INFO * info)
2110 {
2111         struct tty_struct *tty = info->port.tty;
2112         struct  mgsl_icount *icount = &info->icount;
2113         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2114         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2115
2116         /* clear status bits */
2117         if (status)
2118                 write_reg(info, SR1, status);
2119
2120         if (status2)
2121                 write_reg(info, SR2, status2);
2122
2123         if ( debug_level >= DEBUG_LEVEL_ISR )
2124                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2125                         __FILE__,__LINE__,info->device_name,status,status2);
2126
2127         if (info->params.mode == MGSL_MODE_ASYNC) {
2128                 if (status & BRKD) {
2129                         icount->brk++;
2130
2131                         /* process break detection if tty control
2132                          * is not set to ignore it
2133                          */
2134                         if ( tty ) {
2135                                 if (!(status & info->ignore_status_mask1)) {
2136                                         if (info->read_status_mask1 & BRKD) {
2137                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2138                                                 if (info->port.flags & ASYNC_SAK)
2139                                                         do_SAK(tty);
2140                                         }
2141                                 }
2142                         }
2143                 }
2144         }
2145         else {
2146                 if (status & (FLGD|IDLD)) {
2147                         if (status & FLGD)
2148                                 info->icount.exithunt++;
2149                         else if (status & IDLD)
2150                                 info->icount.rxidle++;
2151                         wake_up_interruptible(&info->event_wait_q);
2152                 }
2153         }
2154
2155         if (status & CDCD) {
2156                 /* simulate a common modem status change interrupt
2157                  * for our handler
2158                  */
2159                 get_signals( info );
2160                 isr_io_pin(info,
2161                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2162         }
2163 }
2164
2165 /*
2166  * handle async rx data interrupts
2167  */
2168 static void isr_rxrdy(SLMP_INFO * info)
2169 {
2170         u16 status;
2171         unsigned char DataByte;
2172         struct tty_struct *tty = info->port.tty;
2173         struct  mgsl_icount *icount = &info->icount;
2174
2175         if ( debug_level >= DEBUG_LEVEL_ISR )
2176                 printk("%s(%d):%s isr_rxrdy\n",
2177                         __FILE__,__LINE__,info->device_name);
2178
2179         while((status = read_reg(info,CST0)) & BIT0)
2180         {
2181                 int flag = 0;
2182                 bool over = false;
2183                 DataByte = read_reg(info,TRB);
2184
2185                 icount->rx++;
2186
2187                 if ( status & (PE + FRME + OVRN) ) {
2188                         printk("%s(%d):%s rxerr=%04X\n",
2189                                 __FILE__,__LINE__,info->device_name,status);
2190
2191                         /* update error statistics */
2192                         if (status & PE)
2193                                 icount->parity++;
2194                         else if (status & FRME)
2195                                 icount->frame++;
2196                         else if (status & OVRN)
2197                                 icount->overrun++;
2198
2199                         /* discard char if tty control flags say so */
2200                         if (status & info->ignore_status_mask2)
2201                                 continue;
2202
2203                         status &= info->read_status_mask2;
2204
2205                         if ( tty ) {
2206                                 if (status & PE)
2207                                         flag = TTY_PARITY;
2208                                 else if (status & FRME)
2209                                         flag = TTY_FRAME;
2210                                 if (status & OVRN) {
2211                                         /* Overrun is special, since it's
2212                                          * reported immediately, and doesn't
2213                                          * affect the current character
2214                                          */
2215                                         over = true;
2216                                 }
2217                         }
2218                 }       /* end of if (error) */
2219
2220                 if ( tty ) {
2221                         tty_insert_flip_char(tty, DataByte, flag);
2222                         if (over)
2223                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2224                 }
2225         }
2226
2227         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2228                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2229                         __FILE__,__LINE__,info->device_name,
2230                         icount->rx,icount->brk,icount->parity,
2231                         icount->frame,icount->overrun);
2232         }
2233
2234         if ( tty )
2235                 tty_flip_buffer_push(tty);
2236 }
2237
2238 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2239 {
2240         if ( debug_level >= DEBUG_LEVEL_ISR )
2241                 printk("%s(%d):%s isr_txeom status=%02x\n",
2242                         __FILE__,__LINE__,info->device_name,status);
2243
2244         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2245         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2246         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2247
2248         if (status & UDRN) {
2249                 write_reg(info, CMD, TXRESET);
2250                 write_reg(info, CMD, TXENABLE);
2251         } else
2252                 write_reg(info, CMD, TXBUFCLR);
2253
2254         /* disable and clear tx interrupts */
2255         info->ie0_value &= ~TXRDYE;
2256         info->ie1_value &= ~(IDLE + UDRN);
2257         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2258         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2259
2260         if ( info->tx_active ) {
2261                 if (info->params.mode != MGSL_MODE_ASYNC) {
2262                         if (status & UDRN)
2263                                 info->icount.txunder++;
2264                         else if (status & IDLE)
2265                                 info->icount.txok++;
2266                 }
2267
2268                 info->tx_active = false;
2269                 info->tx_count = info->tx_put = info->tx_get = 0;
2270
2271                 del_timer(&info->tx_timer);
2272
2273                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2274                         info->serial_signals &= ~SerialSignal_RTS;
2275                         info->drop_rts_on_tx_done = false;
2276                         set_signals(info);
2277                 }
2278
2279 #if SYNCLINK_GENERIC_HDLC
2280                 if (info->netcount)
2281                         hdlcdev_tx_done(info);
2282                 else
2283 #endif
2284                 {
2285                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2286                                 tx_stop(info);
2287                                 return;
2288                         }
2289                         info->pending_bh |= BH_TRANSMIT;
2290                 }
2291         }
2292 }
2293
2294
2295 /*
2296  * handle tx status interrupts
2297  */
2298 static void isr_txint(SLMP_INFO * info)
2299 {
2300         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2301
2302         /* clear status bits */
2303         write_reg(info, SR1, status);
2304
2305         if ( debug_level >= DEBUG_LEVEL_ISR )
2306                 printk("%s(%d):%s isr_txint status=%02x\n",
2307                         __FILE__,__LINE__,info->device_name,status);
2308
2309         if (status & (UDRN + IDLE))
2310                 isr_txeom(info, status);
2311
2312         if (status & CCTS) {
2313                 /* simulate a common modem status change interrupt
2314                  * for our handler
2315                  */
2316                 get_signals( info );
2317                 isr_io_pin(info,
2318                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2319
2320         }
2321 }
2322
2323 /*
2324  * handle async tx data interrupts
2325  */
2326 static void isr_txrdy(SLMP_INFO * info)
2327 {
2328         if ( debug_level >= DEBUG_LEVEL_ISR )
2329                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2330                         __FILE__,__LINE__,info->device_name,info->tx_count);
2331
2332         if (info->params.mode != MGSL_MODE_ASYNC) {
2333                 /* disable TXRDY IRQ, enable IDLE IRQ */
2334                 info->ie0_value &= ~TXRDYE;
2335                 info->ie1_value |= IDLE;
2336                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2337                 return;
2338         }
2339
2340         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2341                 tx_stop(info);
2342                 return;
2343         }
2344
2345         if ( info->tx_count )
2346                 tx_load_fifo( info );
2347         else {
2348                 info->tx_active = false;
2349                 info->ie0_value &= ~TXRDYE;
2350                 write_reg(info, IE0, info->ie0_value);
2351         }
2352
2353         if (info->tx_count < WAKEUP_CHARS)
2354                 info->pending_bh |= BH_TRANSMIT;
2355 }
2356
2357 static void isr_rxdmaok(SLMP_INFO * info)
2358 {
2359         /* BIT7 = EOT (end of transfer)
2360          * BIT6 = EOM (end of message/frame)
2361          */
2362         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2363
2364         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2365         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2366
2367         if ( debug_level >= DEBUG_LEVEL_ISR )
2368                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2369                         __FILE__,__LINE__,info->device_name,status);
2370
2371         info->pending_bh |= BH_RECEIVE;
2372 }
2373
2374 static void isr_rxdmaerror(SLMP_INFO * info)
2375 {
2376         /* BIT5 = BOF (buffer overflow)
2377          * BIT4 = COF (counter overflow)
2378          */
2379         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2380
2381         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2382         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2383
2384         if ( debug_level >= DEBUG_LEVEL_ISR )
2385                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2386                         __FILE__,__LINE__,info->device_name,status);
2387
2388         info->rx_overflow = true;
2389         info->pending_bh |= BH_RECEIVE;
2390 }
2391
2392 static void isr_txdmaok(SLMP_INFO * info)
2393 {
2394         unsigned char status_reg1 = read_reg(info, SR1);
2395
2396         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2397         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2398         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2399
2400         if ( debug_level >= DEBUG_LEVEL_ISR )
2401                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2402                         __FILE__,__LINE__,info->device_name,status_reg1);
2403
2404         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2405         write_reg16(info, TRC0, 0);
2406         info->ie0_value |= TXRDYE;
2407         write_reg(info, IE0, info->ie0_value);
2408 }
2409
2410 static void isr_txdmaerror(SLMP_INFO * info)
2411 {
2412         /* BIT5 = BOF (buffer overflow)
2413          * BIT4 = COF (counter overflow)
2414          */
2415         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2416
2417         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2418         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2419
2420         if ( debug_level >= DEBUG_LEVEL_ISR )
2421                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2422                         __FILE__,__LINE__,info->device_name,status);
2423 }
2424
2425 /* handle input serial signal changes
2426  */
2427 static void isr_io_pin( SLMP_INFO *info, u16 status )
2428 {
2429         struct  mgsl_icount *icount;
2430
2431         if ( debug_level >= DEBUG_LEVEL_ISR )
2432                 printk("%s(%d):isr_io_pin status=%04X\n",
2433                         __FILE__,__LINE__,status);
2434
2435         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2436                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2437                 icount = &info->icount;
2438                 /* update input line counters */
2439                 if (status & MISCSTATUS_RI_LATCHED) {
2440                         icount->rng++;
2441                         if ( status & SerialSignal_RI )
2442                                 info->input_signal_events.ri_up++;
2443                         else
2444                                 info->input_signal_events.ri_down++;
2445                 }
2446                 if (status & MISCSTATUS_DSR_LATCHED) {
2447                         icount->dsr++;
2448                         if ( status & SerialSignal_DSR )
2449                                 info->input_signal_events.dsr_up++;
2450                         else
2451                                 info->input_signal_events.dsr_down++;
2452                 }
2453                 if (status & MISCSTATUS_DCD_LATCHED) {
2454                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2455                                 info->ie1_value &= ~CDCD;
2456                                 write_reg(info, IE1, info->ie1_value);
2457                         }
2458                         icount->dcd++;
2459                         if (status & SerialSignal_DCD) {
2460                                 info->input_signal_events.dcd_up++;
2461                         } else
2462                                 info->input_signal_events.dcd_down++;
2463 #if SYNCLINK_GENERIC_HDLC
2464                         if (info->netcount) {
2465                                 if (status & SerialSignal_DCD)
2466                                         netif_carrier_on(info->netdev);
2467                                 else
2468                                         netif_carrier_off(info->netdev);
2469                         }
2470 #endif
2471                 }
2472                 if (status & MISCSTATUS_CTS_LATCHED)
2473                 {
2474                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2475                                 info->ie1_value &= ~CCTS;
2476                                 write_reg(info, IE1, info->ie1_value);
2477                         }
2478                         icount->cts++;
2479                         if ( status & SerialSignal_CTS )
2480                                 info->input_signal_events.cts_up++;
2481                         else
2482                                 info->input_signal_events.cts_down++;
2483                 }
2484                 wake_up_interruptible(&info->status_event_wait_q);
2485                 wake_up_interruptible(&info->event_wait_q);
2486
2487                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2488                      (status & MISCSTATUS_DCD_LATCHED) ) {
2489                         if ( debug_level >= DEBUG_LEVEL_ISR )
2490                                 printk("%s CD now %s...", info->device_name,
2491                                        (status & SerialSignal_DCD) ? "on" : "off");
2492                         if (status & SerialSignal_DCD)
2493                                 wake_up_interruptible(&info->port.open_wait);
2494                         else {
2495                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2496                                         printk("doing serial hangup...");
2497                                 if (info->port.tty)
2498                                         tty_hangup(info->port.tty);
2499                         }
2500                 }
2501
2502                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2503                      (status & MISCSTATUS_CTS_LATCHED) ) {
2504                         if ( info->port.tty ) {
2505                                 if (info->port.tty->hw_stopped) {
2506                                         if (status & SerialSignal_CTS) {
2507                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2508                                                         printk("CTS tx start...");
2509                                                 info->port.tty->hw_stopped = 0;
2510                                                 tx_start(info);
2511                                                 info->pending_bh |= BH_TRANSMIT;
2512                                                 return;
2513                                         }
2514                                 } else {
2515                                         if (!(status & SerialSignal_CTS)) {
2516                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2517                                                         printk("CTS tx stop...");
2518                                                 info->port.tty->hw_stopped = 1;
2519                                                 tx_stop(info);
2520                                         }
2521                                 }
2522                         }
2523                 }
2524         }
2525
2526         info->pending_bh |= BH_STATUS;
2527 }
2528
2529 /* Interrupt service routine entry point.
2530  *
2531  * Arguments:
2532  *      irq             interrupt number that caused interrupt
2533  *      dev_id          device ID supplied during interrupt registration
2534  *      regs            interrupted processor context
2535  */
2536 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2537 {
2538         SLMP_INFO *info = dev_id;
2539         unsigned char status, status0, status1=0;
2540         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2541         unsigned char timerstatus0, timerstatus1=0;
2542         unsigned char shift;
2543         unsigned int i;
2544         unsigned short tmp;
2545
2546         if ( debug_level >= DEBUG_LEVEL_ISR )
2547                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2548                         __FILE__, __LINE__, info->irq_level);
2549
2550         spin_lock(&info->lock);
2551
2552         for(;;) {
2553
2554                 /* get status for SCA0 (ports 0-1) */
2555                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2556                 status0 = (unsigned char)tmp;
2557                 dmastatus0 = (unsigned char)(tmp>>8);
2558                 timerstatus0 = read_reg(info, ISR2);
2559
2560                 if ( debug_level >= DEBUG_LEVEL_ISR )
2561                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2562                                 __FILE__, __LINE__, info->device_name,
2563                                 status0, dmastatus0, timerstatus0);
2564
2565                 if (info->port_count == 4) {
2566                         /* get status for SCA1 (ports 2-3) */
2567                         tmp = read_reg16(info->port_array[2], ISR0);
2568                         status1 = (unsigned char)tmp;
2569                         dmastatus1 = (unsigned char)(tmp>>8);
2570                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2571
2572                         if ( debug_level >= DEBUG_LEVEL_ISR )
2573                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2574                                         __FILE__,__LINE__,info->device_name,
2575                                         status1,dmastatus1,timerstatus1);
2576                 }
2577
2578                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2579                          !status1 && !dmastatus1 && !timerstatus1)
2580                         break;
2581
2582                 for(i=0; i < info->port_count ; i++) {
2583                         if (info->port_array[i] == NULL)
2584                                 continue;
2585                         if (i < 2) {
2586                                 status = status0;
2587                                 dmastatus = dmastatus0;
2588                         } else {
2589                                 status = status1;
2590                                 dmastatus = dmastatus1;
2591                         }
2592
2593                         shift = i & 1 ? 4 :0;
2594
2595                         if (status & BIT0 << shift)
2596                                 isr_rxrdy(info->port_array[i]);
2597                         if (status & BIT1 << shift)
2598                                 isr_txrdy(info->port_array[i]);
2599                         if (status & BIT2 << shift)
2600                                 isr_rxint(info->port_array[i]);
2601                         if (status & BIT3 << shift)
2602                                 isr_txint(info->port_array[i]);
2603
2604                         if (dmastatus & BIT0 << shift)
2605                                 isr_rxdmaerror(info->port_array[i]);
2606                         if (dmastatus & BIT1 << shift)
2607                                 isr_rxdmaok(info->port_array[i]);
2608                         if (dmastatus & BIT2 << shift)
2609                                 isr_txdmaerror(info->port_array[i]);
2610                         if (dmastatus & BIT3 << shift)
2611                                 isr_txdmaok(info->port_array[i]);
2612                 }
2613
2614                 if (timerstatus0 & (BIT5 | BIT4))
2615                         isr_timer(info->port_array[0]);
2616                 if (timerstatus0 & (BIT7 | BIT6))
2617                         isr_timer(info->port_array[1]);
2618                 if (timerstatus1 & (BIT5 | BIT4))
2619                         isr_timer(info->port_array[2]);
2620                 if (timerstatus1 & (BIT7 | BIT6))
2621                         isr_timer(info->port_array[3]);
2622         }
2623
2624         for(i=0; i < info->port_count ; i++) {
2625                 SLMP_INFO * port = info->port_array[i];
2626
2627                 /* Request bottom half processing if there's something
2628                  * for it to do and the bh is not already running.
2629                  *
2630                  * Note: startup adapter diags require interrupts.
2631                  * do not request bottom half processing if the
2632                  * device is not open in a normal mode.
2633                  */
2634                 if ( port && (port->port.count || port->netcount) &&
2635                      port->pending_bh && !port->bh_running &&
2636                      !port->bh_requested ) {
2637                         if ( debug_level >= DEBUG_LEVEL_ISR )
2638                                 printk("%s(%d):%s queueing bh task.\n",
2639                                         __FILE__,__LINE__,port->device_name);
2640                         schedule_work(&port->task);
2641                         port->bh_requested = true;
2642                 }
2643         }
2644
2645         spin_unlock(&info->lock);
2646
2647         if ( debug_level >= DEBUG_LEVEL_ISR )
2648                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2649                         __FILE__, __LINE__, info->irq_level);
2650         return IRQ_HANDLED;
2651 }
2652
2653 /* Initialize and start device.
2654  */
2655 static int startup(SLMP_INFO * info)
2656 {
2657         if ( debug_level >= DEBUG_LEVEL_INFO )
2658                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2659
2660         if (info->port.flags & ASYNC_INITIALIZED)
2661                 return 0;
2662
2663         if (!info->tx_buf) {
2664                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2665                 if (!info->tx_buf) {
2666                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2667                                 __FILE__,__LINE__,info->device_name);
2668                         return -ENOMEM;
2669                 }
2670         }
2671
2672         info->pending_bh = 0;
2673
2674         memset(&info->icount, 0, sizeof(info->icount));
2675
2676         /* program hardware for current parameters */
2677         reset_port(info);
2678
2679         change_params(info);
2680
2681         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2682
2683         if (info->port.tty)
2684                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2685
2686         info->port.flags |= ASYNC_INITIALIZED;
2687
2688         return 0;
2689 }
2690
2691 /* Called by close() and hangup() to shutdown hardware
2692  */
2693 static void shutdown(SLMP_INFO * info)
2694 {
2695         unsigned long flags;
2696
2697         if (!(info->port.flags & ASYNC_INITIALIZED))
2698                 return;
2699
2700         if (debug_level >= DEBUG_LEVEL_INFO)
2701                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2702                          __FILE__,__LINE__, info->device_name );
2703
2704         /* clear status wait queue because status changes */
2705         /* can't happen after shutting down the hardware */
2706         wake_up_interruptible(&info->status_event_wait_q);
2707         wake_up_interruptible(&info->event_wait_q);
2708
2709         del_timer(&info->tx_timer);
2710         del_timer(&info->status_timer);
2711
2712         kfree(info->tx_buf);
2713         info->tx_buf = NULL;
2714
2715         spin_lock_irqsave(&info->lock,flags);
2716
2717         reset_port(info);
2718
2719         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2720                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2721                 set_signals(info);
2722         }
2723
2724         spin_unlock_irqrestore(&info->lock,flags);
2725
2726         if (info->port.tty)
2727                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2728
2729         info->port.flags &= ~ASYNC_INITIALIZED;
2730 }
2731
2732 static void program_hw(SLMP_INFO *info)
2733 {
2734         unsigned long flags;
2735
2736         spin_lock_irqsave(&info->lock,flags);
2737
2738         rx_stop(info);
2739         tx_stop(info);
2740
2741         info->tx_count = info->tx_put = info->tx_get = 0;
2742
2743         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2744                 hdlc_mode(info);
2745         else
2746                 async_mode(info);
2747
2748         set_signals(info);
2749
2750         info->dcd_chkcount = 0;
2751         info->cts_chkcount = 0;
2752         info->ri_chkcount = 0;
2753         info->dsr_chkcount = 0;
2754
2755         info->ie1_value |= (CDCD|CCTS);
2756         write_reg(info, IE1, info->ie1_value);
2757
2758         get_signals(info);
2759
2760         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2761                 rx_start(info);
2762
2763         spin_unlock_irqrestore(&info->lock,flags);
2764 }
2765
2766 /* Reconfigure adapter based on new parameters
2767  */
2768 static void change_params(SLMP_INFO *info)
2769 {
2770         unsigned cflag;
2771         int bits_per_char;
2772
2773         if (!info->port.tty || !info->port.tty->termios)
2774                 return;
2775
2776         if (debug_level >= DEBUG_LEVEL_INFO)
2777                 printk("%s(%d):%s change_params()\n",
2778                          __FILE__,__LINE__, info->device_name );
2779
2780         cflag = info->port.tty->termios->c_cflag;
2781
2782         /* if B0 rate (hangup) specified then negate DTR and RTS */
2783         /* otherwise assert DTR and RTS */
2784         if (cflag & CBAUD)
2785                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2786         else
2787                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2788
2789         /* byte size and parity */
2790
2791         switch (cflag & CSIZE) {
2792               case CS5: info->params.data_bits = 5; break;
2793               case CS6: info->params.data_bits = 6; break;
2794               case CS7: info->params.data_bits = 7; break;
2795               case CS8: info->params.data_bits = 8; break;
2796               /* Never happens, but GCC is too dumb to figure it out */
2797               default:  info->params.data_bits = 7; break;
2798               }
2799
2800         if (cflag & CSTOPB)
2801                 info->params.stop_bits = 2;
2802         else
2803                 info->params.stop_bits = 1;
2804
2805         info->params.parity = ASYNC_PARITY_NONE;
2806         if (cflag & PARENB) {
2807                 if (cflag & PARODD)
2808                         info->params.parity = ASYNC_PARITY_ODD;
2809                 else
2810                         info->params.parity = ASYNC_PARITY_EVEN;
2811 #ifdef CMSPAR
2812                 if (cflag & CMSPAR)
2813                         info->params.parity = ASYNC_PARITY_SPACE;
2814 #endif
2815         }
2816
2817         /* calculate number of jiffies to transmit a full
2818          * FIFO (32 bytes) at specified data rate
2819          */
2820         bits_per_char = info->params.data_bits +
2821                         info->params.stop_bits + 1;
2822
2823         /* if port data rate is set to 460800 or less then
2824          * allow tty settings to override, otherwise keep the
2825          * current data rate.
2826          */
2827         if (info->params.data_rate <= 460800) {
2828                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2829         }
2830
2831         if ( info->params.data_rate ) {
2832                 info->timeout = (32*HZ*bits_per_char) /
2833                                 info->params.data_rate;
2834         }
2835         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2836
2837         if (cflag & CRTSCTS)
2838                 info->port.flags |= ASYNC_CTS_FLOW;
2839         else
2840                 info->port.flags &= ~ASYNC_CTS_FLOW;
2841
2842         if (cflag & CLOCAL)
2843                 info->port.flags &= ~ASYNC_CHECK_CD;
2844         else
2845                 info->port.flags |= ASYNC_CHECK_CD;
2846
2847         /* process tty input control flags */
2848
2849         info->read_status_mask2 = OVRN;
2850         if (I_INPCK(info->port.tty))
2851                 info->read_status_mask2 |= PE | FRME;
2852         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2853                 info->read_status_mask1 |= BRKD;
2854         if (I_IGNPAR(info->port.tty))
2855                 info->ignore_status_mask2 |= PE | FRME;
2856         if (I_IGNBRK(info->port.tty)) {
2857                 info->ignore_status_mask1 |= BRKD;
2858                 /* If ignoring parity and break indicators, ignore
2859                  * overruns too.  (For real raw support).
2860                  */
2861                 if (I_IGNPAR(info->port.tty))
2862                         info->ignore_status_mask2 |= OVRN;
2863         }
2864
2865         program_hw(info);
2866 }
2867
2868 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2869 {
2870         int err;
2871
2872         if (debug_level >= DEBUG_LEVEL_INFO)
2873                 printk("%s(%d):%s get_params()\n",
2874                          __FILE__,__LINE__, info->device_name);
2875
2876         if (!user_icount) {
2877                 memset(&info->icount, 0, sizeof(info->icount));
2878         } else {
2879                 mutex_lock(&info->port.mutex);
2880                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2881                 mutex_unlock(&info->port.mutex);
2882                 if (err)
2883                         return -EFAULT;
2884         }
2885
2886         return 0;
2887 }
2888
2889 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2890 {
2891         int err;
2892         if (debug_level >= DEBUG_LEVEL_INFO)
2893                 printk("%s(%d):%s get_params()\n",
2894                          __FILE__,__LINE__, info->device_name);
2895
2896         mutex_lock(&info->port.mutex);
2897         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2898         mutex_unlock(&info->port.mutex);
2899         if (err) {
2900                 if ( debug_level >= DEBUG_LEVEL_INFO )
2901                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2902                                 __FILE__,__LINE__,info->device_name);
2903                 return -EFAULT;
2904         }
2905
2906         return 0;
2907 }
2908
2909 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2910 {
2911         unsigned long flags;
2912         MGSL_PARAMS tmp_params;
2913         int err;
2914
2915         if (debug_level >= DEBUG_LEVEL_INFO)
2916                 printk("%s(%d):%s set_params\n",
2917                         __FILE__,__LINE__,info->device_name );
2918         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2919         if (err) {
2920                 if ( debug_level >= DEBUG_LEVEL_INFO )
2921                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2922                                 __FILE__,__LINE__,info->device_name);
2923                 return -EFAULT;
2924         }
2925
2926         mutex_lock(&info->port.mutex);
2927         spin_lock_irqsave(&info->lock,flags);
2928         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2929         spin_unlock_irqrestore(&info->lock,flags);
2930
2931         change_params(info);
2932         mutex_unlock(&info->port.mutex);
2933
2934         return 0;
2935 }
2936
2937 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2938 {
2939         int err;
2940
2941         if (debug_level >= DEBUG_LEVEL_INFO)
2942                 printk("%s(%d):%s get_txidle()=%d\n",
2943                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2944
2945         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2946         if (err) {
2947                 if ( debug_level >= DEBUG_LEVEL_INFO )
2948                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2949                                 __FILE__,__LINE__,info->device_name);
2950                 return -EFAULT;
2951         }
2952
2953         return 0;
2954 }
2955
2956 static int set_txidle(SLMP_INFO * info, int idle_mode)
2957 {
2958         unsigned long flags;
2959
2960         if (debug_level >= DEBUG_LEVEL_INFO)
2961                 printk("%s(%d):%s set_txidle(%d)\n",
2962                         __FILE__,__LINE__,info->device_name, idle_mode );
2963
2964         spin_lock_irqsave(&info->lock,flags);
2965         info->idle_mode = idle_mode;
2966         tx_set_idle( info );
2967         spin_unlock_irqrestore(&info->lock,flags);
2968         return 0;
2969 }
2970
2971 static int tx_enable(SLMP_INFO * info, int enable)
2972 {
2973         unsigned long flags;
2974
2975         if (debug_level >= DEBUG_LEVEL_INFO)
2976                 printk("%s(%d):%s tx_enable(%d)\n",
2977                         __FILE__,__LINE__,info->device_name, enable);
2978
2979         spin_lock_irqsave(&info->lock,flags);
2980         if ( enable ) {
2981                 if ( !info->tx_enabled ) {
2982                         tx_start(info);
2983                 }
2984         } else {
2985                 if ( info->tx_enabled )
2986                         tx_stop(info);
2987         }
2988         spin_unlock_irqrestore(&info->lock,flags);
2989         return 0;
2990 }
2991
2992 /* abort send HDLC frame
2993  */
2994 static int tx_abort(SLMP_INFO * info)
2995 {
2996         unsigned long flags;
2997
2998         if (debug_level >= DEBUG_LEVEL_INFO)
2999                 printk("%s(%d):%s tx_abort()\n",
3000                         __FILE__,__LINE__,info->device_name);
3001
3002         spin_lock_irqsave(&info->lock,flags);
3003         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3004                 info->ie1_value &= ~UDRN;
3005                 info->ie1_value |= IDLE;
3006                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3007                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3008
3009                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3010                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3011
3012                 write_reg(info, CMD, TXABORT);
3013         }
3014         spin_unlock_irqrestore(&info->lock,flags);
3015         return 0;
3016 }
3017
3018 static int rx_enable(SLMP_INFO * info, int enable)
3019 {
3020         unsigned long flags;
3021
3022         if (debug_level >= DEBUG_LEVEL_INFO)
3023                 printk("%s(%d):%s rx_enable(%d)\n",
3024                         __FILE__,__LINE__,info->device_name,enable);
3025
3026         spin_lock_irqsave(&info->lock,flags);
3027         if ( enable ) {
3028                 if ( !info->rx_enabled )
3029                         rx_start(info);
3030         } else {
3031                 if ( info->rx_enabled )
3032                         rx_stop(info);
3033         }
3034         spin_unlock_irqrestore(&info->lock,flags);
3035         return 0;
3036 }
3037
3038 /* wait for specified event to occur
3039  */
3040 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3041 {
3042         unsigned long flags;
3043         int s;
3044         int rc=0;
3045         struct mgsl_icount cprev, cnow;
3046         int events;
3047         int mask;
3048         struct  _input_signal_events oldsigs, newsigs;
3049         DECLARE_WAITQUEUE(wait, current);
3050
3051         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3052         if (rc) {
3053                 return  -EFAULT;
3054         }
3055
3056         if (debug_level >= DEBUG_LEVEL_INFO)
3057                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3058                         __FILE__,__LINE__,info->device_name,mask);
3059
3060         spin_lock_irqsave(&info->lock,flags);
3061
3062         /* return immediately if state matches requested events */
3063         get_signals(info);
3064         s = info->serial_signals;
3065
3066         events = mask &
3067                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3068                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3069                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3070                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3071         if (events) {
3072                 spin_unlock_irqrestore(&info->lock,flags);
3073                 goto exit;
3074         }
3075
3076         /* save current irq counts */
3077         cprev = info->icount;
3078         oldsigs = info->input_signal_events;
3079
3080         /* enable hunt and idle irqs if needed */
3081         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3082                 unsigned char oldval = info->ie1_value;
3083                 unsigned char newval = oldval +
3084                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3085                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3086                 if ( oldval != newval ) {
3087                         info->ie1_value = newval;
3088                         write_reg(info, IE1, info->ie1_value);
3089                 }
3090         }
3091
3092         set_current_state(TASK_INTERRUPTIBLE);
3093         add_wait_queue(&info->event_wait_q, &wait);
3094
3095         spin_unlock_irqrestore(&info->lock,flags);
3096
3097         for(;;) {
3098                 schedule();
3099                 if (signal_pending(current)) {
3100                         rc = -ERESTARTSYS;
3101                         break;
3102                 }
3103
3104                 /* get current irq counts */
3105                 spin_lock_irqsave(&info->lock,flags);
3106                 cnow = info->icount;
3107                 newsigs = info->input_signal_events;
3108                 set_current_state(TASK_INTERRUPTIBLE);
3109                 spin_unlock_irqrestore(&info->lock,flags);
3110
3111                 /* if no change, wait aborted for some reason */
3112                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3113                     newsigs.dsr_down == oldsigs.dsr_down &&
3114                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3115                     newsigs.dcd_down == oldsigs.dcd_down &&
3116                     newsigs.cts_up   == oldsigs.cts_up   &&
3117                     newsigs.cts_down == oldsigs.cts_down &&
3118                     newsigs.ri_up    == oldsigs.ri_up    &&
3119                     newsigs.ri_down  == oldsigs.ri_down  &&
3120                     cnow.exithunt    == cprev.exithunt   &&
3121                     cnow.rxidle      == cprev.rxidle) {
3122                         rc = -EIO;
3123                         break;
3124                 }
3125
3126                 events = mask &
3127                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3128                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3129                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3130                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3131                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3132                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3133                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3134                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3135                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3136                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3137                 if (events)
3138                         break;
3139
3140                 cprev = cnow;
3141                 oldsigs = newsigs;
3142         }
3143
3144         remove_wait_queue(&info->event_wait_q, &wait);
3145         set_current_state(TASK_RUNNING);
3146
3147
3148         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3149                 spin_lock_irqsave(&info->lock,flags);
3150                 if (!waitqueue_active(&info->event_wait_q)) {
3151                         /* disable enable exit hunt mode/idle rcvd IRQs */
3152                         info->ie1_value &= ~(FLGD|IDLD);
3153                         write_reg(info, IE1, info->ie1_value);
3154                 }
3155                 spin_unlock_irqrestore(&info->lock,flags);
3156         }
3157 exit:
3158         if ( rc == 0 )
3159                 PUT_USER(rc, events, mask_ptr);
3160
3161         return rc;
3162 }
3163
3164 static int modem_input_wait(SLMP_INFO *info,int arg)
3165 {
3166         unsigned long flags;
3167         int rc;
3168         struct mgsl_icount cprev, cnow;
3169         DECLARE_WAITQUEUE(wait, current);
3170
3171         /* save current irq counts */
3172         spin_lock_irqsave(&info->lock,flags);
3173         cprev = info->icount;
3174         add_wait_queue(&info->status_event_wait_q, &wait);
3175         set_current_state(TASK_INTERRUPTIBLE);
3176         spin_unlock_irqrestore(&info->lock,flags);
3177
3178         for(;;) {
3179                 schedule();
3180                 if (signal_pending(current)) {
3181                         rc = -ERESTARTSYS;
3182                         break;
3183                 }
3184
3185                 /* get new irq counts */
3186                 spin_lock_irqsave(&info->lock,flags);
3187                 cnow = info->icount;
3188                 set_current_state(TASK_INTERRUPTIBLE);
3189                 spin_unlock_irqrestore(&info->lock,flags);
3190
3191                 /* if no change, wait aborted for some reason */
3192                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3193                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3194                         rc = -EIO;
3195                         break;
3196                 }
3197
3198                 /* check for change in caller specified modem input */
3199                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3200                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3201                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3202                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3203                         rc = 0;
3204                         break;
3205                 }
3206
3207                 cprev = cnow;
3208         }
3209         remove_wait_queue(&info->status_event_wait_q, &wait);
3210         set_current_state(TASK_RUNNING);
3211         return rc;
3212 }
3213
3214 /* return the state of the serial control and status signals
3215  */
3216 static int tiocmget(struct tty_struct *tty, struct file *file)
3217 {
3218         SLMP_INFO *info = tty->driver_data;
3219         unsigned int result;
3220         unsigned long flags;
3221
3222         spin_lock_irqsave(&info->lock,flags);
3223         get_signals(info);
3224         spin_unlock_irqrestore(&info->lock,flags);
3225
3226         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3227                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3228                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3229                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3230                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3231                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3232
3233         if (debug_level >= DEBUG_LEVEL_INFO)
3234                 printk("%s(%d):%s tiocmget() value=%08X\n",
3235                          __FILE__,__LINE__, info->device_name, result );
3236         return result;
3237 }
3238
3239 /* set modem control signals (DTR/RTS)
3240  */
3241 static int tiocmset(struct tty_struct *tty, struct file *file,
3242                     unsigned int set, unsigned int clear)
3243 {
3244         SLMP_INFO *info = tty->driver_data;
3245         unsigned long flags;
3246
3247         if (debug_level >= DEBUG_LEVEL_INFO)
3248                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3249                         __FILE__,__LINE__,info->device_name, set, clear);
3250
3251         if (set & TIOCM_RTS)
3252                 info->serial_signals |= SerialSignal_RTS;
3253         if (set & TIOCM_DTR)
3254                 info->serial_signals |= SerialSignal_DTR;
3255         if (clear & TIOCM_RTS)
3256                 info->serial_signals &= ~SerialSignal_RTS;
3257         if (clear & TIOCM_DTR)
3258                 info->serial_signals &= ~SerialSignal_DTR;
3259
3260         spin_lock_irqsave(&info->lock,flags);
3261         set_signals(info);
3262         spin_unlock_irqrestore(&info->lock,flags);
3263
3264         return 0;
3265 }
3266
3267 static int carrier_raised(struct tty_port *port)
3268 {
3269         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3270         unsigned long flags;
3271
3272         spin_lock_irqsave(&info->lock,flags);
3273         get_signals(info);
3274         spin_unlock_irqrestore(&info->lock,flags);
3275
3276         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3277 }
3278
3279 static void dtr_rts(struct tty_port *port, int on)
3280 {
3281         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3282         unsigned long flags;
3283
3284         spin_lock_irqsave(&info->lock,flags);
3285         if (on)
3286                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3287         else
3288                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3289         set_signals(info);
3290         spin_unlock_irqrestore(&info->lock,flags);
3291 }
3292
3293 /* Block the current process until the specified port is ready to open.
3294  */
3295 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3296                            SLMP_INFO *info)
3297 {
3298         DECLARE_WAITQUEUE(wait, current);
3299         int             retval;
3300         bool            do_clocal = false;
3301         bool            extra_count = false;
3302         unsigned long   flags;
3303         int             cd;
3304         struct tty_port *port = &info->port;
3305
3306         if (debug_level >= DEBUG_LEVEL_INFO)
3307                 printk("%s(%d):%s block_til_ready()\n",
3308                          __FILE__,__LINE__, tty->driver->name );
3309
3310         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3311                 /* nonblock mode is set or port is not enabled */
3312                 /* just verify that callout device is not active */
3313                 port->flags |= ASYNC_NORMAL_ACTIVE;
3314                 return 0;
3315         }
3316
3317         if (tty->termios->c_cflag & CLOCAL)
3318                 do_clocal = true;
3319
3320         /* Wait for carrier detect and the line to become
3321          * free (i.e., not in use by the callout).  While we are in
3322          * this loop, port->count is dropped by one, so that
3323          * close() knows when to free things.  We restore it upon
3324          * exit, either normal or abnormal.
3325          */
3326
3327         retval = 0;
3328         add_wait_queue(&port->open_wait, &wait);
3329
3330         if (debug_level >= DEBUG_LEVEL_INFO)
3331                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3332                          __FILE__,__LINE__, tty->driver->name, port->count );
3333
3334         spin_lock_irqsave(&info->lock, flags);
3335         if (!tty_hung_up_p(filp)) {
3336                 extra_count = true;
3337                 port->count--;
3338         }
3339         spin_unlock_irqrestore(&info->lock, flags);
3340         port->blocked_open++;
3341
3342         while (1) {
3343                 if (tty->termios->c_cflag & CBAUD)
3344                         tty_port_raise_dtr_rts(port);
3345
3346                 set_current_state(TASK_INTERRUPTIBLE);
3347
3348                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3349                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3350                                         -EAGAIN : -ERESTARTSYS;
3351                         break;
3352                 }
3353
3354                 cd = tty_port_carrier_raised(port);
3355
3356                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3357                         break;
3358
3359                 if (signal_pending(current)) {
3360                         retval = -ERESTARTSYS;
3361                         break;
3362                 }
3363
3364                 if (debug_level >= DEBUG_LEVEL_INFO)
3365                         printk("%s(%d):%s block_til_ready() count=%d\n",
3366                                  __FILE__,__LINE__, tty->driver->name, port->count );
3367
3368                 tty_unlock();
3369                 schedule();
3370                 tty_lock();
3371         }
3372
3373         set_current_state(TASK_RUNNING);
3374         remove_wait_queue(&port->open_wait, &wait);
3375
3376         if (extra_count)
3377                 port->count++;
3378         port->blocked_open--;
3379
3380         if (debug_level >= DEBUG_LEVEL_INFO)
3381                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3382                          __FILE__,__LINE__, tty->driver->name, port->count );
3383
3384         if (!retval)
3385                 port->flags |= ASYNC_NORMAL_ACTIVE;
3386
3387         return retval;
3388 }
3389
3390 static int alloc_dma_bufs(SLMP_INFO *info)
3391 {
3392         unsigned short BuffersPerFrame;
3393         unsigned short BufferCount;
3394
3395         // Force allocation to start at 64K boundary for each port.
3396         // This is necessary because *all* buffer descriptors for a port
3397         // *must* be in the same 64K block. All descriptors on a port
3398         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3399         // into the CBP register.
3400         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3401
3402         /* Calculate the number of DMA buffers necessary to hold the */
3403         /* largest allowable frame size. Note: If the max frame size is */
3404         /* not an even multiple of the DMA buffer size then we need to */
3405         /* round the buffer count per frame up one. */
3406
3407         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3408         if ( info->max_frame_size % SCABUFSIZE )
3409                 BuffersPerFrame++;
3410
3411         /* calculate total number of data buffers (SCABUFSIZE) possible
3412          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3413          * for the descriptor list (BUFFERLISTSIZE).
3414          */
3415         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3416
3417         /* limit number of buffers to maximum amount of descriptors */
3418         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3419                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3420
3421         /* use enough buffers to transmit one max size frame */
3422         info->tx_buf_count = BuffersPerFrame + 1;
3423
3424         /* never use more than half the available buffers for transmit */
3425         if (info->tx_buf_count > (BufferCount/2))
3426                 info->tx_buf_count = BufferCount/2;
3427
3428         if (info->tx_buf_count > SCAMAXDESC)
3429                 info->tx_buf_count = SCAMAXDESC;
3430
3431         /* use remaining buffers for receive */
3432         info->rx_buf_count = BufferCount - info->tx_buf_count;
3433
3434         if (info->rx_buf_count > SCAMAXDESC)
3435                 info->rx_buf_count = SCAMAXDESC;
3436
3437         if ( debug_level >= DEBUG_LEVEL_INFO )
3438                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3439                         __FILE__,__LINE__, info->device_name,
3440                         info->tx_buf_count,info->rx_buf_count);
3441
3442         if ( alloc_buf_list( info ) < 0 ||
3443                 alloc_frame_bufs(info,
3444                                         info->rx_buf_list,
3445                                         info->rx_buf_list_ex,
3446                                         info->rx_buf_count) < 0 ||
3447                 alloc_frame_bufs(info,
3448                                         info->tx_buf_list,
3449                                         info->tx_buf_list_ex,
3450                                         info->tx_buf_count) < 0 ||
3451                 alloc_tmp_rx_buf(info) < 0 ) {
3452                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3453                         __FILE__,__LINE__, info->device_name);
3454                 return -ENOMEM;
3455         }
3456
3457         rx_reset_buffers( info );
3458
3459         return 0;
3460 }
3461
3462 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3463  */
3464 static int alloc_buf_list(SLMP_INFO *info)
3465 {
3466         unsigned int i;
3467
3468         /* build list in adapter shared memory */
3469         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3470         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3471         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3472
3473         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3474
3475         /* Save virtual address pointers to the receive and */
3476         /* transmit buffer lists. (Receive 1st). These pointers will */
3477         /* be used by the processor to access the lists. */
3478         info->rx_buf_list = (SCADESC *)info->buffer_list;
3479
3480         info->tx_buf_list = (SCADESC *)info->buffer_list;
3481         info->tx_buf_list += info->rx_buf_count;
3482
3483         /* Build links for circular buffer entry lists (tx and rx)
3484          *
3485          * Note: links are physical addresses read by the SCA device
3486          * to determine the next buffer entry to use.
3487          */
3488
3489         for ( i = 0; i < info->rx_buf_count; i++ ) {
3490                 /* calculate and store physical address of this buffer entry */
3491                 info->rx_buf_list_ex[i].phys_entry =
3492                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3493
3494                 /* calculate and store physical address of */
3495                 /* next entry in cirular list of entries */
3496                 info->rx_buf_list[i].next = info->buffer_list_phys;
3497                 if ( i < info->rx_buf_count - 1 )
3498                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3499
3500                 info->rx_buf_list[i].length = SCABUFSIZE;
3501         }
3502
3503         for ( i = 0; i < info->tx_buf_count; i++ ) {
3504                 /* calculate and store physical address of this buffer entry */
3505                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3506                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3507
3508                 /* calculate and store physical address of */
3509                 /* next entry in cirular list of entries */
3510
3511                 info->tx_buf_list[i].next = info->buffer_list_phys +
3512                         info->rx_buf_count * sizeof(SCADESC);
3513
3514                 if ( i < info->tx_buf_count - 1 )
3515                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3516         }
3517
3518         return 0;
3519 }
3520
3521 /* Allocate the frame DMA buffers used by the specified buffer list.
3522  */
3523 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3524 {
3525         int i;
3526         unsigned long phys_addr;
3527
3528         for ( i = 0; i < count; i++ ) {
3529                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3530                 phys_addr = info->port_array[0]->last_mem_alloc;
3531                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3532
3533                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3534                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3535         }
3536
3537         return 0;
3538 }
3539
3540 static void free_dma_bufs(SLMP_INFO *info)
3541 {
3542         info->buffer_list = NULL;
3543         info->rx_buf_list = NULL;
3544         info->tx_buf_list = NULL;
3545 }
3546
3547 /* allocate buffer large enough to hold max_frame_size.
3548  * This buffer is used to pass an assembled frame to the line discipline.
3549  */
3550 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3551 {
3552         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3553         if (info->tmp_rx_buf == NULL)
3554                 return -ENOMEM;
3555         return 0;
3556 }
3557
3558 static void free_tmp_rx_buf(SLMP_INFO *info)
3559 {
3560         kfree(info->tmp_rx_buf);
3561         info->tmp_rx_buf = NULL;
3562 }
3563
3564 static int claim_resources(SLMP_INFO *info)
3565 {
3566         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3567                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3568                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3569                 info->init_error = DiagStatus_AddressConflict;
3570                 goto errout;
3571         }
3572         else
3573                 info->shared_mem_requested = true;
3574
3575         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3576                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3577                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3578                 info->init_error = DiagStatus_AddressConflict;
3579                 goto errout;
3580         }
3581         else
3582                 info->lcr_mem_requested = true;
3583
3584         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3585                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3586                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3587                 info->init_error = DiagStatus_AddressConflict;
3588                 goto errout;
3589         }
3590         else
3591                 info->sca_base_requested = true;
3592
3593         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3594                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3595                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3596                 info->init_error = DiagStatus_AddressConflict;
3597                 goto errout;
3598         }
3599         else
3600                 info->sca_statctrl_requested = true;
3601
3602         info->memory_base = ioremap_nocache(info->phys_memory_base,
3603                                                                 SCA_MEM_SIZE);
3604         if (!info->memory_base) {
3605                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3606                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3607                 info->init_error = DiagStatus_CantAssignPciResources;
3608                 goto errout;
3609         }
3610
3611         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3612         if (!info->lcr_base) {
3613                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3614                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3615                 info->init_error = DiagStatus_CantAssignPciResources;
3616                 goto errout;
3617         }
3618         info->lcr_base += info->lcr_offset;
3619
3620         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3621         if (!info->sca_base) {
3622                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3623                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3624                 info->init_error = DiagStatus_CantAssignPciResources;
3625                 goto errout;
3626         }
3627         info->sca_base += info->sca_offset;
3628
3629         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3630                                                                 PAGE_SIZE);
3631         if (!info->statctrl_base) {
3632                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3633                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3634                 info->init_error = DiagStatus_CantAssignPciResources;
3635                 goto errout;
3636         }
3637         info->statctrl_base += info->statctrl_offset;
3638
3639         if ( !memory_test(info) ) {
3640                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3641                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3642                 info->init_error = DiagStatus_MemoryError;
3643                 goto errout;
3644         }
3645
3646         return 0;
3647
3648 errout:
3649         release_resources( info );
3650         return -ENODEV;
3651 }
3652
3653 static void release_resources(SLMP_INFO *info)
3654 {
3655         if ( debug_level >= DEBUG_LEVEL_INFO )
3656                 printk( "%s(%d):%s release_resources() entry\n",
3657                         __FILE__,__LINE__,info->device_name );
3658
3659         if ( info->irq_requested ) {
3660                 free_irq(info->irq_level, info);
3661                 info->irq_requested = false;
3662         }
3663
3664         if ( info->shared_mem_requested ) {
3665                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3666                 info->shared_mem_requested = false;
3667         }
3668         if ( info->lcr_mem_requested ) {
3669                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3670                 info->lcr_mem_requested = false;
3671         }
3672         if ( info->sca_base_requested ) {
3673                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3674                 info->sca_base_requested = false;
3675         }
3676         if ( info->sca_statctrl_requested ) {
3677                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3678                 info->sca_statctrl_requested = false;
3679         }
3680
3681         if (info->memory_base){
3682                 iounmap(info->memory_base);
3683                 info->memory_base = NULL;
3684         }
3685
3686         if (info->sca_base) {
3687                 iounmap(info->sca_base - info->sca_offset);
3688                 info->sca_base=NULL;
3689         }
3690
3691         if (info->statctrl_base) {
3692                 iounmap(info->statctrl_base - info->statctrl_offset);
3693                 info->statctrl_base=NULL;
3694         }
3695
3696         if (info->lcr_base){
3697                 iounmap(info->lcr_base - info->lcr_offset);
3698                 info->lcr_base = NULL;
3699         }
3700
3701         if ( debug_level >= DEBUG_LEVEL_INFO )
3702                 printk( "%s(%d):%s release_resources() exit\n",
3703                         __FILE__,__LINE__,info->device_name );
3704 }
3705
3706 /* Add the specified device instance data structure to the
3707  * global linked list of devices and increment the device count.
3708  */
3709 static void add_device(SLMP_INFO *info)
3710 {
3711         info->next_device = NULL;
3712         info->line = synclinkmp_device_count;
3713         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3714
3715         if (info->line < MAX_DEVICES) {
3716                 if (maxframe[info->line])
3717                         info->max_frame_size = maxframe[info->line];
3718         }
3719
3720         synclinkmp_device_count++;
3721
3722         if ( !synclinkmp_device_list )
3723                 synclinkmp_device_list = info;
3724         else {
3725                 SLMP_INFO *current_dev = synclinkmp_device_list;
3726                 while( current_dev->next_device )
3727                         current_dev = current_dev->next_device;
3728                 current_dev->next_device = info;
3729         }
3730
3731         if ( info->max_frame_size < 4096 )
3732                 info->max_frame_size = 4096;
3733         else if ( info->max_frame_size > 65535 )
3734                 info->max_frame_size = 65535;
3735
3736         printk( "SyncLink MultiPort %s: "
3737                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3738                 info->device_name,
3739                 info->phys_sca_base,
3740                 info->phys_memory_base,
3741                 info->phys_statctrl_base,
3742                 info->phys_lcr_base,
3743                 info->irq_level,
3744                 info->max_frame_size );
3745
3746 #if SYNCLINK_GENERIC_HDLC
3747         hdlcdev_init(info);
3748 #endif
3749 }
3750
3751 static const struct tty_port_operations port_ops = {
3752         .carrier_raised = carrier_raised,
3753         .dtr_rts = dtr_rts,
3754 };
3755
3756 /* Allocate and initialize a device instance structure
3757  *
3758  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3759  */
3760 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3761 {
3762         SLMP_INFO *info;
3763
3764         info = kzalloc(sizeof(SLMP_INFO),
3765                  GFP_KERNEL);
3766
3767         if (!info) {
3768                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3769                         __FILE__,__LINE__, adapter_num, port_num);
3770         } else {
3771                 tty_port_init(&info->port);
3772                 info->port.ops = &port_ops;
3773                 info->magic = MGSL_MAGIC;
3774                 INIT_WORK(&info->task, bh_handler);
3775                 info->max_frame_size = 4096;
3776                 info->port.close_delay = 5*HZ/10;
3777                 info->port.closing_wait = 30*HZ;
3778                 init_waitqueue_head(&info->status_event_wait_q);
3779                 init_waitqueue_head(&info->event_wait_q);
3780                 spin_lock_init(&info->netlock);
3781                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3782                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3783                 info->adapter_num = adapter_num;
3784                 info->port_num = port_num;
3785
3786                 /* Copy configuration info to device instance data */
3787                 info->irq_level = pdev->irq;
3788                 info->phys_lcr_base = pci_resource_start(pdev,0);
3789                 info->phys_sca_base = pci_resource_start(pdev,2);
3790                 info->phys_memory_base = pci_resource_start(pdev,3);
3791                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3792
3793                 /* Because veremap only works on page boundaries we must map
3794                  * a larger area than is actually implemented for the LCR
3795                  * memory range. We map a full page starting at the page boundary.
3796                  */
3797                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3798                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3799
3800                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3801                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3802
3803                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3804                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3805
3806                 info->bus_type = MGSL_BUS_TYPE_PCI;
3807                 info->irq_flags = IRQF_SHARED;
3808
3809                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3810                 setup_timer(&info->status_timer, status_timeout,
3811                                 (unsigned long)info);
3812
3813                 /* Store the PCI9050 misc control register value because a flaw
3814                  * in the PCI9050 prevents LCR registers from being read if
3815                  * BIOS assigns an LCR base address with bit 7 set.
3816                  *
3817                  * Only the misc control register is accessed for which only
3818                  * write access is needed, so set an initial value and change
3819                  * bits to the device instance data as we write the value
3820                  * to the actual misc control register.
3821                  */
3822                 info->misc_ctrl_value = 0x087e4546;
3823
3824                 /* initial port state is unknown - if startup errors
3825                  * occur, init_error will be set to indicate the
3826                  * problem. Once the port is fully initialized,
3827                  * this value will be set to 0 to indicate the
3828                  * port is available.
3829                  */
3830                 info->init_error = -1;
3831         }
3832
3833         return info;
3834 }
3835
3836 static void device_init(int adapter_num, struct pci_dev *pdev)
3837 {
3838         SLMP_INFO *port_array[SCA_MAX_PORTS];
3839         int port;
3840
3841         /* allocate device instances for up to SCA_MAX_PORTS devices */
3842         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3843                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3844                 if( port_array[port] == NULL ) {
3845                         for ( --port; port >= 0; --port )
3846                                 kfree(port_array[port]);
3847                         return;
3848                 }
3849         }
3850
3851         /* give copy of port_array to all ports and add to device list  */
3852         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3853                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3854                 add_device( port_array[port] );
3855                 spin_lock_init(&port_array[port]->lock);
3856         }
3857
3858         /* Allocate and claim adapter resources */
3859         if ( !claim_resources(port_array[0]) ) {
3860
3861                 alloc_dma_bufs(port_array[0]);
3862
3863                 /* copy resource information from first port to others */
3864                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3865                         port_array[port]->lock  = port_array[0]->lock;
3866                         port_array[port]->irq_level     = port_array[0]->irq_level;
3867                         port_array[port]->memory_base   = port_array[0]->memory_base;
3868                         port_array[port]->sca_base      = port_array[0]->sca_base;
3869                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3870                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3871                         alloc_dma_bufs(port_array[port]);
3872                 }
3873
3874                 if ( request_irq(port_array[0]->irq_level,
3875                                         synclinkmp_interrupt,
3876                                         port_array[0]->irq_flags,
3877                                         port_array[0]->device_name,
3878                                         port_array[0]) < 0 ) {
3879                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3880                                 __FILE__,__LINE__,
3881                                 port_array[0]->device_name,
3882                                 port_array[0]->irq_level );
3883                 }
3884                 else {
3885                         port_array[0]->irq_requested = true;
3886                         adapter_test(port_array[0]);
3887                 }
3888         }
3889 }
3890
3891 static const struct tty_operations ops = {
3892         .open = open,
3893         .close = close,
3894         .write = write,
3895         .put_char = put_char,
3896         .flush_chars = flush_chars,
3897         .write_room = write_room,
3898         .chars_in_buffer = chars_in_buffer,
3899         .flush_buffer = flush_buffer,
3900         .ioctl = ioctl,
3901         .throttle = throttle,
3902         .unthrottle = unthrottle,
3903         .send_xchar = send_xchar,
3904         .break_ctl = set_break,
3905         .wait_until_sent = wait_until_sent,
3906         .set_termios = set_termios,
3907         .stop = tx_hold,
3908         .start = tx_release,
3909         .hangup = hangup,
3910         .tiocmget = tiocmget,
3911         .tiocmset = tiocmset,
3912         .proc_fops = &synclinkmp_proc_fops,
3913 };
3914
3915
3916 static void synclinkmp_cleanup(void)
3917 {
3918         int rc;
3919         SLMP_INFO *info;
3920         SLMP_INFO *tmp;
3921
3922         printk("Unloading %s %s\n", driver_name, driver_version);
3923
3924         if (serial_driver) {
3925                 if ((rc = tty_unregister_driver(serial_driver)))
3926                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3927                                __FILE__,__LINE__,rc);
3928                 put_tty_driver(serial_driver);
3929         }
3930
3931         /* reset devices */
3932         info = synclinkmp_device_list;
3933         while(info) {
3934                 reset_port(info);
3935                 info = info->next_device;
3936         }
3937
3938         /* release devices */
3939         info = synclinkmp_device_list;
3940         while(info) {
3941 #if SYNCLINK_GENERIC_HDLC
3942                 hdlcdev_exit(info);
3943 #endif
3944                 free_dma_bufs(info);
3945                 free_tmp_rx_buf(info);
3946                 if ( info->port_num == 0 ) {
3947                         if (info->sca_base)
3948                                 write_reg(info, LPR, 1); /* set low power mode */
3949                         release_resources(info);
3950                 }
3951                 tmp = info;
3952                 info = info->next_device;
3953                 kfree(tmp);
3954         }
3955
3956         pci_unregister_driver(&synclinkmp_pci_driver);
3957 }
3958
3959 /* Driver initialization entry point.
3960  */
3961
3962 static int __init synclinkmp_init(void)
3963 {
3964         int rc;
3965
3966         if (break_on_load) {
3967                 synclinkmp_get_text_ptr();
3968                 BREAKPOINT();
3969         }
3970
3971         printk("%s %s\n", driver_name, driver_version);
3972
3973         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3974                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3975                 return rc;
3976         }
3977
3978         serial_driver = alloc_tty_driver(128);
3979         if (!serial_driver) {
3980                 rc = -ENOMEM;
3981                 goto error;
3982         }
3983
3984         /* Initialize the tty_driver structure */
3985
3986         serial_driver->owner = THIS_MODULE;
3987         serial_driver->driver_name = "synclinkmp";
3988         serial_driver->name = "ttySLM";
3989         serial_driver->major = ttymajor;
3990         serial_driver->minor_start = 64;
3991         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3992         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3993         serial_driver->init_termios = tty_std_termios;
3994         serial_driver->init_termios.c_cflag =
3995                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3996         serial_driver->init_termios.c_ispeed = 9600;
3997         serial_driver->init_termios.c_ospeed = 9600;
3998         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3999         tty_set_operations(serial_driver, &ops);
4000         if ((rc = tty_register_driver(serial_driver)) < 0) {
4001                 printk("%s(%d):Couldn't register serial driver\n",
4002                         __FILE__,__LINE__);
4003                 put_tty_driver(serial_driver);
4004                 serial_driver = NULL;
4005                 goto error;
4006         }
4007
4008         printk("%s %s, tty major#%d\n",
4009                 driver_name, driver_version,
4010                 serial_driver->major);
4011
4012         return 0;
4013
4014 error:
4015         synclinkmp_cleanup();
4016         return rc;
4017 }
4018
4019 static void __exit synclinkmp_exit(void)
4020 {
4021         synclinkmp_cleanup();
4022 }
4023
4024 module_init(synclinkmp_init);
4025 module_exit(synclinkmp_exit);
4026
4027 /* Set the port for internal loopback mode.
4028  * The TxCLK and RxCLK signals are generated from the BRG and
4029  * the TxD is looped back to the RxD internally.
4030  */
4031 static void enable_loopback(SLMP_INFO *info, int enable)
4032 {
4033         if (enable) {
4034                 /* MD2 (Mode Register 2)
4035                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4036                  */
4037                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4038
4039                 /* degate external TxC clock source */
4040                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4041                 write_control_reg(info);
4042
4043                 /* RXS/TXS (Rx/Tx clock source)
4044                  * 07      Reserved, must be 0
4045                  * 06..04  Clock Source, 100=BRG
4046                  * 03..00  Clock Divisor, 0000=1
4047                  */
4048                 write_reg(info, RXS, 0x40);
4049                 write_reg(info, TXS, 0x40);
4050
4051         } else {
4052                 /* MD2 (Mode Register 2)
4053                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4054                  */
4055                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4056
4057                 /* RXS/TXS (Rx/Tx clock source)
4058                  * 07      Reserved, must be 0
4059                  * 06..04  Clock Source, 000=RxC/TxC Pin
4060                  * 03..00  Clock Divisor, 0000=1
4061                  */
4062                 write_reg(info, RXS, 0x00);
4063                 write_reg(info, TXS, 0x00);
4064         }
4065
4066         /* set LinkSpeed if available, otherwise default to 2Mbps */
4067         if (info->params.clock_speed)
4068                 set_rate(info, info->params.clock_speed);
4069         else
4070                 set_rate(info, 3686400);
4071 }
4072
4073 /* Set the baud rate register to the desired speed
4074  *
4075  *      data_rate       data rate of clock in bits per second
4076  *                      A data rate of 0 disables the AUX clock.
4077  */
4078 static void set_rate( SLMP_INFO *info, u32 data_rate )
4079 {
4080         u32 TMCValue;
4081         unsigned char BRValue;
4082         u32 Divisor=0;
4083
4084         /* fBRG = fCLK/(TMC * 2^BR)
4085          */
4086         if (data_rate != 0) {
4087                 Divisor = 14745600/data_rate;
4088                 if (!Divisor)
4089                         Divisor = 1;
4090
4091                 TMCValue = Divisor;
4092
4093                 BRValue = 0;
4094                 if (TMCValue != 1 && TMCValue != 2) {
4095                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4096                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4097                          * 50/50 duty cycle.
4098                          */
4099                         BRValue = 1;
4100                         TMCValue >>= 1;
4101                 }
4102
4103                 /* while TMCValue is too big for TMC register, divide
4104                  * by 2 and increment BR exponent.
4105                  */
4106                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4107                         TMCValue >>= 1;
4108
4109                 write_reg(info, TXS,
4110                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4111                 write_reg(info, RXS,
4112                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4113                 write_reg(info, TMC, (unsigned char)TMCValue);
4114         }
4115         else {
4116                 write_reg(info, TXS,0);
4117                 write_reg(info, RXS,0);
4118                 write_reg(info, TMC, 0);
4119         }
4120 }
4121
4122 /* Disable receiver
4123  */
4124 static void rx_stop(SLMP_INFO *info)
4125 {
4126         if (debug_level >= DEBUG_LEVEL_ISR)
4127                 printk("%s(%d):%s rx_stop()\n",
4128                          __FILE__,__LINE__, info->device_name );
4129
4130         write_reg(info, CMD, RXRESET);
4131
4132         info->ie0_value &= ~RXRDYE;
4133         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4134
4135         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4136         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4137         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4138
4139         info->rx_enabled = false;
4140         info->rx_overflow = false;
4141 }
4142
4143 /* enable the receiver
4144  */
4145 static void rx_start(SLMP_INFO *info)
4146 {
4147         int i;
4148
4149         if (debug_level >= DEBUG_LEVEL_ISR)
4150                 printk("%s(%d):%s rx_start()\n",
4151                          __FILE__,__LINE__, info->device_name );
4152
4153         write_reg(info, CMD, RXRESET);
4154
4155         if ( info->params.mode == MGSL_MODE_HDLC ) {
4156                 /* HDLC, disabe IRQ on rxdata */
4157                 info->ie0_value &= ~RXRDYE;
4158                 write_reg(info, IE0, info->ie0_value);
4159
4160                 /* Reset all Rx DMA buffers and program rx dma */
4161                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4162                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4163
4164                 for (i = 0; i < info->rx_buf_count; i++) {
4165                         info->rx_buf_list[i].status = 0xff;
4166
4167                         // throttle to 4 shared memory writes at a time to prevent
4168                         // hogging local bus (keep latency time for DMA requests low).
4169                         if (!(i % 4))
4170                                 read_status_reg(info);
4171                 }
4172                 info->current_rx_buf = 0;
4173
4174                 /* set current/1st descriptor address */
4175                 write_reg16(info, RXDMA + CDA,
4176                         info->rx_buf_list_ex[0].phys_entry);
4177
4178                 /* set new last rx descriptor address */
4179                 write_reg16(info, RXDMA + EDA,
4180                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4181
4182                 /* set buffer length (shared by all rx dma data buffers) */
4183                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4184
4185                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4186                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4187         } else {
4188                 /* async, enable IRQ on rxdata */
4189                 info->ie0_value |= RXRDYE;
4190                 write_reg(info, IE0, info->ie0_value);
4191         }
4192
4193         write_reg(info, CMD, RXENABLE);
4194
4195         info->rx_overflow = false;
4196         info->rx_enabled = true;
4197 }
4198
4199 /* Enable the transmitter and send a transmit frame if
4200  * one is loaded in the DMA buffers.
4201  */
4202 static void tx_start(SLMP_INFO *info)
4203 {
4204         if (debug_level >= DEBUG_LEVEL_ISR)
4205                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4206                          __FILE__,__LINE__, info->device_name,info->tx_count );
4207
4208         if (!info->tx_enabled ) {
4209                 write_reg(info, CMD, TXRESET);
4210                 write_reg(info, CMD, TXENABLE);
4211                 info->tx_enabled = true;
4212         }
4213
4214         if ( info->tx_count ) {
4215
4216                 /* If auto RTS enabled and RTS is inactive, then assert */
4217                 /* RTS and set a flag indicating that the driver should */
4218                 /* negate RTS when the transmission completes. */
4219
4220                 info->drop_rts_on_tx_done = false;
4221
4222                 if (info->params.mode != MGSL_MODE_ASYNC) {
4223
4224                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4225                                 get_signals( info );
4226                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4227                                         info->serial_signals |= SerialSignal_RTS;
4228                                         set_signals( info );
4229                                         info->drop_rts_on_tx_done = true;
4230                                 }
4231                         }
4232
4233                         write_reg16(info, TRC0,
4234                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4235
4236                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4237                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4238
4239                         /* set TX CDA (current descriptor address) */
4240                         write_reg16(info, TXDMA + CDA,
4241                                 info->tx_buf_list_ex[0].phys_entry);
4242
4243                         /* set TX EDA (last descriptor address) */
4244                         write_reg16(info, TXDMA + EDA,
4245                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4246
4247                         /* enable underrun IRQ */
4248                         info->ie1_value &= ~IDLE;
4249                         info->ie1_value |= UDRN;
4250                         write_reg(info, IE1, info->ie1_value);
4251                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4252
4253                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4254                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4255
4256                         mod_timer(&info->tx_timer, jiffies +
4257                                         msecs_to_jiffies(5000));
4258                 }
4259                 else {
4260                         tx_load_fifo(info);
4261                         /* async, enable IRQ on txdata */
4262                         info->ie0_value |= TXRDYE;
4263                         write_reg(info, IE0, info->ie0_value);
4264                 }
4265
4266                 info->tx_active = true;
4267         }
4268 }
4269
4270 /* stop the transmitter and DMA
4271  */
4272 static void tx_stop( SLMP_INFO *info )
4273 {
4274         if (debug_level >= DEBUG_LEVEL_ISR)
4275                 printk("%s(%d):%s tx_stop()\n",
4276                          __FILE__,__LINE__, info->device_name );
4277
4278         del_timer(&info->tx_timer);
4279
4280         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4281         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4282
4283         write_reg(info, CMD, TXRESET);
4284
4285         info->ie1_value &= ~(UDRN + IDLE);
4286         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4287         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4288
4289         info->ie0_value &= ~TXRDYE;
4290         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4291
4292         info->tx_enabled = false;
4293         info->tx_active = false;
4294 }
4295
4296 /* Fill the transmit FIFO until the FIFO is full or
4297  * there is no more data to load.
4298  */
4299 static void tx_load_fifo(SLMP_INFO *info)
4300 {
4301         u8 TwoBytes[2];
4302
4303         /* do nothing is now tx data available and no XON/XOFF pending */
4304
4305         if ( !info->tx_count && !info->x_char )
4306                 return;
4307
4308         /* load the Transmit FIFO until FIFOs full or all data sent */
4309
4310         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4311
4312                 /* there is more space in the transmit FIFO and */
4313                 /* there is more data in transmit buffer */
4314
4315                 if ( (info->tx_count > 1) && !info->x_char ) {
4316                         /* write 16-bits */
4317                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4318                         if (info->tx_get >= info->max_frame_size)
4319                                 info->tx_get -= info->max_frame_size;
4320                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4321                         if (info->tx_get >= info->max_frame_size)
4322                                 info->tx_get -= info->max_frame_size;
4323
4324                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4325
4326                         info->tx_count -= 2;
4327                         info->icount.tx += 2;
4328                 } else {
4329                         /* only 1 byte left to transmit or 1 FIFO slot left */
4330
4331                         if (info->x_char) {
4332                                 /* transmit pending high priority char */
4333                                 write_reg(info, TRB, info->x_char);
4334                                 info->x_char = 0;
4335                         } else {
4336                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4337                                 if (info->tx_get >= info->max_frame_size)
4338                                         info->tx_get -= info->max_frame_size;
4339                                 info->tx_count--;
4340                         }
4341                         info->icount.tx++;
4342                 }
4343         }
4344 }
4345
4346 /* Reset a port to a known state
4347  */
4348 static void reset_port(SLMP_INFO *info)
4349 {
4350         if (info->sca_base) {
4351
4352                 tx_stop(info);
4353                 rx_stop(info);
4354
4355                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4356                 set_signals(info);
4357
4358                 /* disable all port interrupts */
4359                 info->ie0_value = 0;
4360                 info->ie1_value = 0;
4361                 info->ie2_value = 0;
4362                 write_reg(info, IE0, info->ie0_value);
4363                 write_reg(info, IE1, info->ie1_value);
4364                 write_reg(info, IE2, info->ie2_value);
4365
4366                 write_reg(info, CMD, CHRESET);
4367         }
4368 }
4369
4370 /* Reset all the ports to a known state.
4371  */
4372 static void reset_adapter(SLMP_INFO *info)
4373 {
4374         int i;
4375
4376         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4377                 if (info->port_array[i])
4378                         reset_port(info->port_array[i]);
4379         }
4380 }
4381
4382 /* Program port for asynchronous communications.
4383  */
4384 static void async_mode(SLMP_INFO *info)
4385 {
4386
4387         unsigned char RegValue;
4388
4389         tx_stop(info);
4390         rx_stop(info);
4391
4392         /* MD0, Mode Register 0
4393          *
4394          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4395          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4396          * 03      Reserved, must be 0
4397          * 02      CRCCC, CRC Calculation, 0=disabled
4398          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4399          *
4400          * 0000 0000
4401          */
4402         RegValue = 0x00;
4403         if (info->params.stop_bits != 1)
4404                 RegValue |= BIT1;
4405         write_reg(info, MD0, RegValue);
4406
4407         /* MD1, Mode Register 1
4408          *
4409          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4410          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4411          * 03..02  RXCHR<1..0>, rx char size
4412          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4413          *
4414          * 0100 0000
4415          */
4416         RegValue = 0x40;
4417         switch (info->params.data_bits) {
4418         case 7: RegValue |= BIT4 + BIT2; break;
4419         case 6: RegValue |= BIT5 + BIT3; break;
4420         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4421         }
4422         if (info->params.parity != ASYNC_PARITY_NONE) {
4423                 RegValue |= BIT1;
4424                 if (info->params.parity == ASYNC_PARITY_ODD)
4425                         RegValue |= BIT0;
4426         }
4427         write_reg(info, MD1, RegValue);
4428
4429         /* MD2, Mode Register 2
4430          *
4431          * 07..02  Reserved, must be 0
4432          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4433          *
4434          * 0000 0000
4435          */
4436         RegValue = 0x00;
4437         if (info->params.loopback)
4438                 RegValue |= (BIT1 + BIT0);
4439         write_reg(info, MD2, RegValue);
4440
4441         /* RXS, Receive clock source
4442          *
4443          * 07      Reserved, must be 0
4444          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4445          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4446          */
4447         RegValue=BIT6;
4448         write_reg(info, RXS, RegValue);
4449
4450         /* TXS, Transmit clock source
4451          *
4452          * 07      Reserved, must be 0
4453          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4454          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4455          */
4456         RegValue=BIT6;
4457         write_reg(info, TXS, RegValue);
4458
4459         /* Control Register
4460          *
4461          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4462          */
4463         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4464         write_control_reg(info);
4465
4466         tx_set_idle(info);
4467
4468         /* RRC Receive Ready Control 0
4469          *
4470          * 07..05  Reserved, must be 0
4471          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4472          */
4473         write_reg(info, RRC, 0x00);
4474
4475         /* TRC0 Transmit Ready Control 0
4476          *
4477          * 07..05  Reserved, must be 0
4478          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4479          */
4480         write_reg(info, TRC0, 0x10);
4481
4482         /* TRC1 Transmit Ready Control 1
4483          *
4484          * 07..05  Reserved, must be 0
4485          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4486          */
4487         write_reg(info, TRC1, 0x1e);
4488
4489         /* CTL, MSCI control register
4490          *
4491          * 07..06  Reserved, set to 0
4492          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4493          * 04      IDLC, idle control, 0=mark 1=idle register
4494          * 03      BRK, break, 0=off 1 =on (async)
4495          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4496          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4497          * 00      RTS, RTS output control, 0=active 1=inactive
4498          *
4499          * 0001 0001
4500          */
4501         RegValue = 0x10;
4502         if (!(info->serial_signals & SerialSignal_RTS))
4503                 RegValue |= 0x01;
4504         write_reg(info, CTL, RegValue);
4505
4506         /* enable status interrupts */
4507         info->ie0_value |= TXINTE + RXINTE;
4508         write_reg(info, IE0, info->ie0_value);
4509
4510         /* enable break detect interrupt */
4511         info->ie1_value = BRKD;
4512         write_reg(info, IE1, info->ie1_value);
4513
4514         /* enable rx overrun interrupt */
4515         info->ie2_value = OVRN;
4516         write_reg(info, IE2, info->ie2_value);
4517
4518         set_rate( info, info->params.data_rate * 16 );
4519 }
4520
4521 /* Program the SCA for HDLC communications.
4522  */
4523 static void hdlc_mode(SLMP_INFO *info)
4524 {
4525         unsigned char RegValue;
4526         u32 DpllDivisor;
4527
4528         // Can't use DPLL because SCA outputs recovered clock on RxC when
4529         // DPLL mode selected. This causes output contention with RxC receiver.
4530         // Use of DPLL would require external hardware to disable RxC receiver
4531         // when DPLL mode selected.
4532         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4533
4534         /* disable DMA interrupts */
4535         write_reg(info, TXDMA + DIR, 0);
4536         write_reg(info, RXDMA + DIR, 0);
4537
4538         /* MD0, Mode Register 0
4539          *
4540          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4541          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4542          * 03      Reserved, must be 0
4543          * 02      CRCCC, CRC Calculation, 1=enabled
4544          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4545          * 00      CRC0, CRC initial value, 1 = all 1s
4546          *
4547          * 1000 0001
4548          */
4549         RegValue = 0x81;
4550         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4551                 RegValue |= BIT4;
4552         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4553                 RegValue |= BIT4;
4554         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4555                 RegValue |= BIT2 + BIT1;
4556         write_reg(info, MD0, RegValue);
4557
4558         /* MD1, Mode Register 1
4559          *
4560          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4561          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4562          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4563          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4564          *
4565          * 0000 0000
4566          */
4567         RegValue = 0x00;
4568         write_reg(info, MD1, RegValue);
4569
4570         /* MD2, Mode Register 2
4571          *
4572          * 07      NRZFM, 0=NRZ, 1=FM
4573          * 06..05  CODE<1..0> Encoding, 00=NRZ
4574          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4575          * 02      Reserved, must be 0
4576          * 01..00  CNCT<1..0> Channel connection, 0=normal
4577          *
4578          * 0000 0000
4579          */
4580         RegValue = 0x00;
4581         switch(info->params.encoding) {
4582         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4583         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4584         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4585         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4586 #if 0
4587         case HDLC_ENCODING_NRZB:                                        /* not supported */
4588         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4589         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4590 #endif
4591         }
4592         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4593                 DpllDivisor = 16;
4594                 RegValue |= BIT3;
4595         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4596                 DpllDivisor = 8;
4597         } else {
4598                 DpllDivisor = 32;
4599                 RegValue |= BIT4;
4600         }
4601         write_reg(info, MD2, RegValue);
4602
4603
4604         /* RXS, Receive clock source
4605          *
4606          * 07      Reserved, must be 0
4607          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4608          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4609          */
4610         RegValue=0;
4611         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4612                 RegValue |= BIT6;
4613         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4614                 RegValue |= BIT6 + BIT5;
4615         write_reg(info, RXS, RegValue);
4616
4617         /* TXS, Transmit clock source
4618          *
4619          * 07      Reserved, must be 0
4620          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4621          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4622          */
4623         RegValue=0;
4624         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4625                 RegValue |= BIT6;
4626         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4627                 RegValue |= BIT6 + BIT5;
4628         write_reg(info, TXS, RegValue);
4629
4630         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4631                 set_rate(info, info->params.clock_speed * DpllDivisor);
4632         else
4633                 set_rate(info, info->params.clock_speed);
4634
4635         /* GPDATA (General Purpose I/O Data Register)
4636          *
4637          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4638          */
4639         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4640                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4641         else
4642                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4643         write_control_reg(info);
4644
4645         /* RRC Receive Ready Control 0
4646          *
4647          * 07..05  Reserved, must be 0
4648          * 04..00  RRC<4..0> Rx FIFO trigger active
4649          */
4650         write_reg(info, RRC, rx_active_fifo_level);
4651
4652         /* TRC0 Transmit Ready Control 0
4653          *
4654          * 07..05  Reserved, must be 0
4655          * 04..00  TRC<4..0> Tx FIFO trigger active
4656          */
4657         write_reg(info, TRC0, tx_active_fifo_level);
4658
4659         /* TRC1 Transmit Ready Control 1
4660          *
4661          * 07..05  Reserved, must be 0
4662          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4663          */
4664         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4665
4666         /* DMR, DMA Mode Register
4667          *
4668          * 07..05  Reserved, must be 0
4669          * 04      TMOD, Transfer Mode: 1=chained-block
4670          * 03      Reserved, must be 0
4671          * 02      NF, Number of Frames: 1=multi-frame
4672          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4673          * 00      Reserved, must be 0
4674          *
4675          * 0001 0100
4676          */
4677         write_reg(info, TXDMA + DMR, 0x14);
4678         write_reg(info, RXDMA + DMR, 0x14);
4679
4680         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4681         write_reg(info, RXDMA + CPB,
4682                 (unsigned char)(info->buffer_list_phys >> 16));
4683
4684         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4685         write_reg(info, TXDMA + CPB,
4686                 (unsigned char)(info->buffer_list_phys >> 16));
4687
4688         /* enable status interrupts. other code enables/disables
4689          * the individual sources for these two interrupt classes.
4690          */
4691         info->ie0_value |= TXINTE + RXINTE;
4692         write_reg(info, IE0, info->ie0_value);
4693
4694         /* CTL, MSCI control register
4695          *
4696          * 07..06  Reserved, set to 0
4697          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4698          * 04      IDLC, idle control, 0=mark 1=idle register
4699          * 03      BRK, break, 0=off 1 =on (async)
4700          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4701          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4702          * 00      RTS, RTS output control, 0=active 1=inactive
4703          *
4704          * 0001 0001
4705          */
4706         RegValue = 0x10;
4707         if (!(info->serial_signals & SerialSignal_RTS))
4708                 RegValue |= 0x01;
4709         write_reg(info, CTL, RegValue);
4710
4711         /* preamble not supported ! */
4712
4713         tx_set_idle(info);
4714         tx_stop(info);
4715         rx_stop(info);
4716
4717         set_rate(info, info->params.clock_speed);
4718
4719         if (info->params.loopback)
4720                 enable_loopback(info,1);
4721 }
4722
4723 /* Set the transmit HDLC idle mode
4724  */
4725 static void tx_set_idle(SLMP_INFO *info)
4726 {
4727         unsigned char RegValue = 0xff;
4728
4729         /* Map API idle mode to SCA register bits */
4730         switch(info->idle_mode) {
4731         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4732         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4733         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4734         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4735         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4736         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4737         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4738         }
4739
4740         write_reg(info, IDL, RegValue);
4741 }
4742
4743 /* Query the adapter for the state of the V24 status (input) signals.
4744  */
4745 static void get_signals(SLMP_INFO *info)
4746 {
4747         u16 status = read_reg(info, SR3);
4748         u16 gpstatus = read_status_reg(info);
4749         u16 testbit;
4750
4751         /* clear all serial signals except DTR and RTS */
4752         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4753
4754         /* set serial signal bits to reflect MISR */
4755
4756         if (!(status & BIT3))
4757                 info->serial_signals |= SerialSignal_CTS;
4758
4759         if ( !(status & BIT2))
4760                 info->serial_signals |= SerialSignal_DCD;
4761
4762         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4763         if (!(gpstatus & testbit))
4764                 info->serial_signals |= SerialSignal_RI;
4765
4766         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4767         if (!(gpstatus & testbit))
4768                 info->serial_signals |= SerialSignal_DSR;
4769 }
4770
4771 /* Set the state of DTR and RTS based on contents of
4772  * serial_signals member of device context.
4773  */
4774 static void set_signals(SLMP_INFO *info)
4775 {
4776         unsigned char RegValue;
4777         u16 EnableBit;
4778
4779         RegValue = read_reg(info, CTL);
4780         if (info->serial_signals & SerialSignal_RTS)
4781                 RegValue &= ~BIT0;
4782         else
4783                 RegValue |= BIT0;
4784         write_reg(info, CTL, RegValue);
4785
4786         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4787         EnableBit = BIT1 << (info->port_num*2);
4788         if (info->serial_signals & SerialSignal_DTR)
4789                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4790         else
4791                 info->port_array[0]->ctrlreg_value |= EnableBit;
4792         write_control_reg(info);
4793 }
4794
4795 /*******************/
4796 /* DMA Buffer Code */
4797 /*******************/
4798
4799 /* Set the count for all receive buffers to SCABUFSIZE
4800  * and set the current buffer to the first buffer. This effectively
4801  * makes all buffers free and discards any data in buffers.
4802  */
4803 static void rx_reset_buffers(SLMP_INFO *info)
4804 {
4805         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4806 }
4807
4808 /* Free the buffers used by a received frame
4809  *
4810  * info   pointer to device instance data
4811  * first  index of 1st receive buffer of frame
4812  * last   index of last receive buffer of frame
4813  */
4814 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4815 {
4816         bool done = false;
4817
4818         while(!done) {
4819                 /* reset current buffer for reuse */
4820                 info->rx_buf_list[first].status = 0xff;
4821
4822                 if (first == last) {
4823                         done = true;
4824                         /* set new last rx descriptor address */
4825                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4826                 }
4827
4828                 first++;
4829                 if (first == info->rx_buf_count)
4830                         first = 0;
4831         }
4832
4833         /* set current buffer to next buffer after last buffer of frame */
4834         info->current_rx_buf = first;
4835 }
4836
4837 /* Return a received frame from the receive DMA buffers.
4838  * Only frames received without errors are returned.
4839  *
4840  * Return Value:        true if frame returned, otherwise false
4841  */
4842 static bool rx_get_frame(SLMP_INFO *info)
4843 {
4844         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4845         unsigned short status;
4846         unsigned int framesize = 0;
4847         bool ReturnCode = false;
4848         unsigned long flags;
4849         struct tty_struct *tty = info->port.tty;
4850         unsigned char addr_field = 0xff;
4851         SCADESC *desc;
4852         SCADESC_EX *desc_ex;
4853
4854 CheckAgain:
4855         /* assume no frame returned, set zero length */
4856         framesize = 0;
4857         addr_field = 0xff;
4858
4859         /*
4860          * current_rx_buf points to the 1st buffer of the next available
4861          * receive frame. To find the last buffer of the frame look for
4862          * a non-zero status field in the buffer entries. (The status
4863          * field is set by the 16C32 after completing a receive frame.
4864          */
4865         StartIndex = EndIndex = info->current_rx_buf;
4866
4867         for ( ;; ) {
4868                 desc = &info->rx_buf_list[EndIndex];
4869                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4870
4871                 if (desc->status == 0xff)
4872                         goto Cleanup;   /* current desc still in use, no frames available */
4873
4874                 if (framesize == 0 && info->params.addr_filter != 0xff)
4875                         addr_field = desc_ex->virt_addr[0];
4876
4877                 framesize += desc->length;
4878
4879                 /* Status != 0 means last buffer of frame */
4880                 if (desc->status)
4881                         break;
4882
4883                 EndIndex++;
4884                 if (EndIndex == info->rx_buf_count)
4885                         EndIndex = 0;
4886
4887                 if (EndIndex == info->current_rx_buf) {
4888                         /* all buffers have been 'used' but none mark      */
4889                         /* the end of a frame. Reset buffers and receiver. */
4890                         if ( info->rx_enabled ){
4891                                 spin_lock_irqsave(&info->lock,flags);
4892                                 rx_start(info);
4893                                 spin_unlock_irqrestore(&info->lock,flags);
4894                         }
4895                         goto Cleanup;
4896                 }
4897
4898         }
4899
4900         /* check status of receive frame */
4901
4902         /* frame status is byte stored after frame data
4903          *
4904          * 7 EOM (end of msg), 1 = last buffer of frame
4905          * 6 Short Frame, 1 = short frame
4906          * 5 Abort, 1 = frame aborted
4907          * 4 Residue, 1 = last byte is partial
4908          * 3 Overrun, 1 = overrun occurred during frame reception
4909          * 2 CRC,     1 = CRC error detected
4910          *
4911          */
4912         status = desc->status;
4913
4914         /* ignore CRC bit if not using CRC (bit is undefined) */
4915         /* Note:CRC is not save to data buffer */
4916         if (info->params.crc_type == HDLC_CRC_NONE)
4917                 status &= ~BIT2;
4918
4919         if (framesize == 0 ||
4920                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4921                 /* discard 0 byte frames, this seems to occur sometime
4922                  * when remote is idling flags.
4923                  */
4924                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4925                 goto CheckAgain;
4926         }
4927
4928         if (framesize < 2)
4929                 status |= BIT6;
4930
4931         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4932                 /* received frame has errors,
4933                  * update counts and mark frame size as 0
4934                  */
4935                 if (status & BIT6)
4936                         info->icount.rxshort++;
4937                 else if (status & BIT5)
4938                         info->icount.rxabort++;
4939                 else if (status & BIT3)
4940                         info->icount.rxover++;
4941                 else
4942                         info->icount.rxcrc++;
4943
4944                 framesize = 0;
4945 #if SYNCLINK_GENERIC_HDLC
4946                 {
4947                         info->netdev->stats.rx_errors++;
4948                         info->netdev->stats.rx_frame_errors++;
4949                 }
4950 #endif
4951         }
4952
4953         if ( debug_level >= DEBUG_LEVEL_BH )
4954                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4955                         __FILE__,__LINE__,info->device_name,status,framesize);
4956
4957         if ( debug_level >= DEBUG_LEVEL_DATA )
4958                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4959                         min_t(int, framesize,SCABUFSIZE),0);
4960
4961         if (framesize) {
4962                 if (framesize > info->max_frame_size)
4963                         info->icount.rxlong++;
4964                 else {
4965                         /* copy dma buffer(s) to contiguous intermediate buffer */
4966                         int copy_count = framesize;
4967                         int index = StartIndex;
4968                         unsigned char *ptmp = info->tmp_rx_buf;
4969                         info->tmp_rx_buf_count = framesize;
4970
4971                         info->icount.rxok++;
4972
4973                         while(copy_count) {
4974                                 int partial_count = min(copy_count,SCABUFSIZE);
4975                                 memcpy( ptmp,
4976                                         info->rx_buf_list_ex[index].virt_addr,
4977                                         partial_count );
4978                                 ptmp += partial_count;
4979                                 copy_count -= partial_count;
4980
4981                                 if ( ++index == info->rx_buf_count )
4982                                         index = 0;
4983                         }
4984
4985 #if SYNCLINK_GENERIC_HDLC
4986                         if (info->netcount)
4987                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4988                         else
4989 #endif
4990                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4991                                                   info->flag_buf, framesize);
4992                 }
4993         }
4994         /* Free the buffers used by this frame. */
4995         rx_free_frame_buffers( info, StartIndex, EndIndex );
4996
4997         ReturnCode = true;
4998
4999 Cleanup:
5000         if ( info->rx_enabled && info->rx_overflow ) {
5001                 /* Receiver is enabled, but needs to restarted due to
5002                  * rx buffer overflow. If buffers are empty, restart receiver.
5003                  */
5004                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5005                         spin_lock_irqsave(&info->lock,flags);
5006                         rx_start(info);
5007                         spin_unlock_irqrestore(&info->lock,flags);
5008                 }
5009         }
5010
5011         return ReturnCode;
5012 }
5013
5014 /* load the transmit DMA buffer with data
5015  */
5016 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5017 {
5018         unsigned short copy_count;
5019         unsigned int i = 0;
5020         SCADESC *desc;
5021         SCADESC_EX *desc_ex;
5022
5023         if ( debug_level >= DEBUG_LEVEL_DATA )
5024                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5025
5026         /* Copy source buffer to one or more DMA buffers, starting with
5027          * the first transmit dma buffer.
5028          */
5029         for(i=0;;)
5030         {
5031                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5032
5033                 desc = &info->tx_buf_list[i];
5034                 desc_ex = &info->tx_buf_list_ex[i];
5035
5036                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5037
5038                 desc->length = copy_count;
5039                 desc->status = 0;
5040
5041                 buf += copy_count;
5042                 count -= copy_count;
5043
5044                 if (!count)
5045                         break;
5046
5047                 i++;
5048                 if (i >= info->tx_buf_count)
5049                         i = 0;
5050         }
5051
5052         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5053         info->last_tx_buf = ++i;
5054 }
5055
5056 static bool register_test(SLMP_INFO *info)
5057 {
5058         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5059         static unsigned int count = ARRAY_SIZE(testval);
5060         unsigned int i;
5061         bool rc = true;
5062         unsigned long flags;
5063
5064         spin_lock_irqsave(&info->lock,flags);
5065         reset_port(info);
5066
5067         /* assume failure */
5068         info->init_error = DiagStatus_AddressFailure;
5069
5070         /* Write bit patterns to various registers but do it out of */
5071         /* sync, then read back and verify values. */
5072
5073         for (i = 0 ; i < count ; i++) {
5074                 write_reg(info, TMC, testval[i]);
5075                 write_reg(info, IDL, testval[(i+1)%count]);
5076                 write_reg(info, SA0, testval[(i+2)%count]);
5077                 write_reg(info, SA1, testval[(i+3)%count]);
5078
5079                 if ( (read_reg(info, TMC) != testval[i]) ||
5080                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5081                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5082                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5083                 {
5084                         rc = false;
5085                         break;
5086                 }
5087         }
5088
5089         reset_port(info);
5090         spin_unlock_irqrestore(&info->lock,flags);
5091
5092         return rc;
5093 }
5094
5095 static bool irq_test(SLMP_INFO *info)
5096 {
5097         unsigned long timeout;
5098         unsigned long flags;
5099
5100         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5101
5102         spin_lock_irqsave(&info->lock,flags);
5103         reset_port(info);
5104
5105         /* assume failure */
5106         info->init_error = DiagStatus_IrqFailure;
5107         info->irq_occurred = false;
5108
5109         /* setup timer0 on SCA0 to interrupt */
5110
5111         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5112         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5113
5114         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5115         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5116
5117
5118         /* TMCS, Timer Control/Status Register
5119          *
5120          * 07      CMF, Compare match flag (read only) 1=match
5121          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5122          * 05      Reserved, must be 0
5123          * 04      TME, Timer Enable
5124          * 03..00  Reserved, must be 0
5125          *
5126          * 0101 0000
5127          */
5128         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5129
5130         spin_unlock_irqrestore(&info->lock,flags);
5131
5132         timeout=100;
5133         while( timeout-- && !info->irq_occurred ) {
5134                 msleep_interruptible(10);
5135         }
5136
5137         spin_lock_irqsave(&info->lock,flags);
5138         reset_port(info);
5139         spin_unlock_irqrestore(&info->lock,flags);
5140
5141         return info->irq_occurred;
5142 }
5143
5144 /* initialize individual SCA device (2 ports)
5145  */
5146 static bool sca_init(SLMP_INFO *info)
5147 {
5148         /* set wait controller to single mem partition (low), no wait states */
5149         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5150         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5151         write_reg(info, WCRL, 0);       /* wait controller low range */
5152         write_reg(info, WCRM, 0);       /* wait controller mid range */
5153         write_reg(info, WCRH, 0);       /* wait controller high range */
5154
5155         /* DPCR, DMA Priority Control
5156          *
5157          * 07..05  Not used, must be 0
5158          * 04      BRC, bus release condition: 0=all transfers complete
5159          * 03      CCC, channel change condition: 0=every cycle
5160          * 02..00  PR<2..0>, priority 100=round robin
5161          *
5162          * 00000100 = 0x04
5163          */
5164         write_reg(info, DPCR, dma_priority);
5165
5166         /* DMA Master Enable, BIT7: 1=enable all channels */
5167         write_reg(info, DMER, 0x80);
5168
5169         /* enable all interrupt classes */
5170         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5171         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5172         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5173
5174         /* ITCR, interrupt control register
5175          * 07      IPC, interrupt priority, 0=MSCI->DMA
5176          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5177          * 04      VOS, Vector Output, 0=unmodified vector
5178          * 03..00  Reserved, must be 0
5179          */
5180         write_reg(info, ITCR, 0);
5181
5182         return true;
5183 }
5184
5185 /* initialize adapter hardware
5186  */
5187 static bool init_adapter(SLMP_INFO *info)
5188 {
5189         int i;
5190
5191         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5192         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5193         u32 readval;
5194
5195         info->misc_ctrl_value |= BIT30;
5196         *MiscCtrl = info->misc_ctrl_value;
5197
5198         /*
5199          * Force at least 170ns delay before clearing
5200          * reset bit. Each read from LCR takes at least
5201          * 30ns so 10 times for 300ns to be safe.
5202          */
5203         for(i=0;i<10;i++)
5204                 readval = *MiscCtrl;
5205
5206         info->misc_ctrl_value &= ~BIT30;
5207         *MiscCtrl = info->misc_ctrl_value;
5208
5209         /* init control reg (all DTRs off, all clksel=input) */
5210         info->ctrlreg_value = 0xaa;
5211         write_control_reg(info);
5212
5213         {
5214                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5215                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5216
5217                 switch(read_ahead_count)
5218                 {
5219                 case 16:
5220                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5221                         break;
5222                 case 8:
5223                         lcr1_brdr_value |= BIT5 + BIT4;
5224                         break;
5225                 case 4:
5226                         lcr1_brdr_value |= BIT5 + BIT3;
5227                         break;
5228                 case 0:
5229                         lcr1_brdr_value |= BIT5;
5230                         break;
5231                 }
5232
5233                 *LCR1BRDR = lcr1_brdr_value;
5234                 *MiscCtrl = misc_ctrl_value;
5235         }
5236
5237         sca_init(info->port_array[0]);
5238         sca_init(info->port_array[2]);
5239
5240         return true;
5241 }
5242
5243 /* Loopback an HDLC frame to test the hardware
5244  * interrupt and DMA functions.
5245  */
5246 static bool loopback_test(SLMP_INFO *info)
5247 {
5248 #define TESTFRAMESIZE 20
5249
5250         unsigned long timeout;
5251         u16 count = TESTFRAMESIZE;
5252         unsigned char buf[TESTFRAMESIZE];
5253         bool rc = false;
5254         unsigned long flags;
5255
5256         struct tty_struct *oldtty = info->port.tty;
5257         u32 speed = info->params.clock_speed;
5258
5259         info->params.clock_speed = 3686400;
5260         info->port.tty = NULL;
5261
5262         /* assume failure */
5263         info->init_error = DiagStatus_DmaFailure;
5264
5265         /* build and send transmit frame */
5266         for (count = 0; count < TESTFRAMESIZE;++count)
5267                 buf[count] = (unsigned char)count;
5268
5269         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5270
5271         /* program hardware for HDLC and enabled receiver */
5272         spin_lock_irqsave(&info->lock,flags);
5273         hdlc_mode(info);
5274         enable_loopback(info,1);
5275         rx_start(info);
5276         info->tx_count = count;
5277         tx_load_dma_buffer(info,buf,count);
5278         tx_start(info);
5279         spin_unlock_irqrestore(&info->lock,flags);
5280
5281         /* wait for receive complete */
5282         /* Set a timeout for waiting for interrupt. */
5283         for ( timeout = 100; timeout; --timeout ) {
5284                 msleep_interruptible(10);
5285
5286                 if (rx_get_frame(info)) {
5287                         rc = true;
5288                         break;
5289                 }
5290         }
5291
5292         /* verify received frame length and contents */
5293         if (rc &&
5294             ( info->tmp_rx_buf_count != count ||
5295               memcmp(buf, info->tmp_rx_buf,count))) {
5296                 rc = false;
5297         }
5298
5299         spin_lock_irqsave(&info->lock,flags);
5300         reset_adapter(info);
5301         spin_unlock_irqrestore(&info->lock,flags);
5302
5303         info->params.clock_speed = speed;
5304         info->port.tty = oldtty;
5305
5306         return rc;
5307 }
5308
5309 /* Perform diagnostics on hardware
5310  */
5311 static int adapter_test( SLMP_INFO *info )
5312 {
5313         unsigned long flags;
5314         if ( debug_level >= DEBUG_LEVEL_INFO )
5315                 printk( "%s(%d):Testing device %s\n",
5316                         __FILE__,__LINE__,info->device_name );
5317
5318         spin_lock_irqsave(&info->lock,flags);
5319         init_adapter(info);
5320         spin_unlock_irqrestore(&info->lock,flags);
5321
5322         info->port_array[0]->port_count = 0;
5323
5324         if ( register_test(info->port_array[0]) &&
5325                 register_test(info->port_array[1])) {
5326
5327                 info->port_array[0]->port_count = 2;
5328
5329                 if ( register_test(info->port_array[2]) &&
5330                         register_test(info->port_array[3]) )
5331                         info->port_array[0]->port_count += 2;
5332         }
5333         else {
5334                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5335                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5336                 return -ENODEV;
5337         }
5338
5339         if ( !irq_test(info->port_array[0]) ||
5340                 !irq_test(info->port_array[1]) ||
5341                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5342                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5343                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5344                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5345                 return -ENODEV;
5346         }
5347
5348         if (!loopback_test(info->port_array[0]) ||
5349                 !loopback_test(info->port_array[1]) ||
5350                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5351                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5352                 printk( "%s(%d):DMA test failure for device %s\n",
5353                         __FILE__,__LINE__,info->device_name);
5354                 return -ENODEV;
5355         }
5356
5357         if ( debug_level >= DEBUG_LEVEL_INFO )
5358                 printk( "%s(%d):device %s passed diagnostics\n",
5359                         __FILE__,__LINE__,info->device_name );
5360
5361         info->port_array[0]->init_error = 0;
5362         info->port_array[1]->init_error = 0;
5363         if ( info->port_count > 2 ) {
5364                 info->port_array[2]->init_error = 0;
5365                 info->port_array[3]->init_error = 0;
5366         }
5367
5368         return 0;
5369 }
5370
5371 /* Test the shared memory on a PCI adapter.
5372  */
5373 static bool memory_test(SLMP_INFO *info)
5374 {
5375         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5376                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5377         unsigned long count = ARRAY_SIZE(testval);
5378         unsigned long i;
5379         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5380         unsigned long * addr = (unsigned long *)info->memory_base;
5381
5382         /* Test data lines with test pattern at one location. */
5383
5384         for ( i = 0 ; i < count ; i++ ) {
5385                 *addr = testval[i];
5386                 if ( *addr != testval[i] )
5387                         return false;
5388         }
5389
5390         /* Test address lines with incrementing pattern over */
5391         /* entire address range. */
5392
5393         for ( i = 0 ; i < limit ; i++ ) {
5394                 *addr = i * 4;
5395                 addr++;
5396         }
5397
5398         addr = (unsigned long *)info->memory_base;
5399
5400         for ( i = 0 ; i < limit ; i++ ) {
5401                 if ( *addr != i * 4 )
5402                         return false;
5403                 addr++;
5404         }
5405
5406         memset( info->memory_base, 0, SCA_MEM_SIZE );
5407         return true;
5408 }
5409
5410 /* Load data into PCI adapter shared memory.
5411  *
5412  * The PCI9050 releases control of the local bus
5413  * after completing the current read or write operation.
5414  *
5415  * While the PCI9050 write FIFO not empty, the
5416  * PCI9050 treats all of the writes as a single transaction
5417  * and does not release the bus. This causes DMA latency problems
5418  * at high speeds when copying large data blocks to the shared memory.
5419  *
5420  * This function breaks a write into multiple transations by
5421  * interleaving a read which flushes the write FIFO and 'completes'
5422  * the write transation. This allows any pending DMA request to gain control
5423  * of the local bus in a timely fasion.
5424  */
5425 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5426 {
5427         /* A load interval of 16 allows for 4 32-bit writes at */
5428         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5429
5430         unsigned short interval = count / sca_pci_load_interval;
5431         unsigned short i;
5432
5433         for ( i = 0 ; i < interval ; i++ )
5434         {
5435                 memcpy(dest, src, sca_pci_load_interval);
5436                 read_status_reg(info);
5437                 dest += sca_pci_load_interval;
5438                 src += sca_pci_load_interval;
5439         }
5440
5441         memcpy(dest, src, count % sca_pci_load_interval);
5442 }
5443
5444 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5445 {
5446         int i;
5447         int linecount;
5448         if (xmit)
5449                 printk("%s tx data:\n",info->device_name);
5450         else
5451                 printk("%s rx data:\n",info->device_name);
5452
5453         while(count) {
5454                 if (count > 16)
5455                         linecount = 16;
5456                 else
5457                         linecount = count;
5458
5459                 for(i=0;i<linecount;i++)
5460                         printk("%02X ",(unsigned char)data[i]);
5461                 for(;i<17;i++)
5462                         printk("   ");
5463                 for(i=0;i<linecount;i++) {
5464                         if (data[i]>=040 && data[i]<=0176)
5465                                 printk("%c",data[i]);
5466                         else
5467                                 printk(".");
5468                 }
5469                 printk("\n");
5470
5471                 data  += linecount;
5472                 count -= linecount;
5473         }
5474 }       /* end of trace_block() */
5475
5476 /* called when HDLC frame times out
5477  * update stats and do tx completion processing
5478  */
5479 static void tx_timeout(unsigned long context)
5480 {
5481         SLMP_INFO *info = (SLMP_INFO*)context;
5482         unsigned long flags;
5483
5484         if ( debug_level >= DEBUG_LEVEL_INFO )
5485                 printk( "%s(%d):%s tx_timeout()\n",
5486                         __FILE__,__LINE__,info->device_name);
5487         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5488                 info->icount.txtimeout++;
5489         }
5490         spin_lock_irqsave(&info->lock,flags);
5491         info->tx_active = false;
5492         info->tx_count = info->tx_put = info->tx_get = 0;
5493
5494         spin_unlock_irqrestore(&info->lock,flags);
5495
5496 #if SYNCLINK_GENERIC_HDLC
5497         if (info->netcount)
5498                 hdlcdev_tx_done(info);
5499         else
5500 #endif
5501                 bh_transmit(info);
5502 }
5503
5504 /* called to periodically check the DSR/RI modem signal input status
5505  */
5506 static void status_timeout(unsigned long context)
5507 {
5508         u16 status = 0;
5509         SLMP_INFO *info = (SLMP_INFO*)context;
5510         unsigned long flags;
5511         unsigned char delta;
5512
5513
5514         spin_lock_irqsave(&info->lock,flags);
5515         get_signals(info);
5516         spin_unlock_irqrestore(&info->lock,flags);
5517
5518         /* check for DSR/RI state change */
5519
5520         delta = info->old_signals ^ info->serial_signals;
5521         info->old_signals = info->serial_signals;
5522
5523         if (delta & SerialSignal_DSR)
5524                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5525
5526         if (delta & SerialSignal_RI)
5527                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5528
5529         if (delta & SerialSignal_DCD)
5530                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5531
5532         if (delta & SerialSignal_CTS)
5533                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5534
5535         if (status)
5536                 isr_io_pin(info,status);
5537
5538         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5539 }
5540
5541
5542 /* Register Access Routines -
5543  * All registers are memory mapped
5544  */
5545 #define CALC_REGADDR() \
5546         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5547         if (info->port_num > 1) \
5548                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5549         if ( info->port_num & 1) { \
5550                 if (Addr > 0x7f) \
5551                         RegAddr += 0x40;        /* DMA access */ \
5552                 else if (Addr > 0x1f && Addr < 0x60) \
5553                         RegAddr += 0x20;        /* MSCI access */ \
5554         }
5555
5556
5557 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5558 {
5559         CALC_REGADDR();
5560         return *RegAddr;
5561 }
5562 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5563 {
5564         CALC_REGADDR();
5565         *RegAddr = Value;
5566 }
5567
5568 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5569 {
5570         CALC_REGADDR();
5571         return *((u16 *)RegAddr);
5572 }
5573
5574 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5575 {
5576         CALC_REGADDR();
5577         *((u16 *)RegAddr) = Value;
5578 }
5579
5580 static unsigned char read_status_reg(SLMP_INFO * info)
5581 {
5582         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5583         return *RegAddr;
5584 }
5585
5586 static void write_control_reg(SLMP_INFO * info)
5587 {
5588         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5589         *RegAddr = info->port_array[0]->ctrlreg_value;
5590 }
5591
5592
5593 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5594                                           const struct pci_device_id *ent)
5595 {
5596         if (pci_enable_device(dev)) {
5597                 printk("error enabling pci device %p\n", dev);
5598                 return -EIO;
5599         }
5600         device_init( ++synclinkmp_adapter_count, dev );
5601         return 0;
5602 }
5603
5604 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5605 {
5606 }