drivers/char/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 //#define DBGTBUF(info) dump_tbufs(info)
  44 //#define DBGRBUF(info) dump_rbufs(info)
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/smp_lock.h>
  66 #include <linux/netdevice.h>
  67 #include <linux/vmalloc.h>
  68 #include <linux/init.h>
  69 #include <linux/delay.h>
  70 #include <linux/ioctl.h>
  71 #include <linux/termios.h>
  72 #include <linux/bitops.h>
  73 #include <linux/workqueue.h>
  74 #include <linux/hdlc.h>
  75 #include <linux/synclink.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  85 #define SYNCLINK_GENERIC_HDLC 1
  86 #else
  87 #define SYNCLINK_GENERIC_HDLC 0
  88 #endif
  89
  90 /*
  91  * module identification
  92  */
  93 static char *driver_name     = "SyncLink GT";
  94 static char *tty_driver_name = "synclink_gt";
  95 static char *tty_dev_prefix  = "ttySLG";
  96 MODULE_LICENSE("GPL");
  97 #define MGSL_MAGIC 0x5401
  98 #define MAX_DEVICES 32
  99
 100 static struct pci_device_id pci_table[] = {
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {0,}, /* terminate list */
 106 };
 107 MODULE_DEVICE_TABLE(pci, pci_table);
 108
 109 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 110 static void remove_one(struct pci_dev *dev);
 111 static struct pci_driver pci_driver = {
 112         .name           = "synclink_gt",
 113         .id_table       = pci_table,
 114         .probe          = init_one,
 115         .remove         = __devexit_p(remove_one),
 116 };
 117
 118 static bool pci_registered;
 119
 120 /*
 121  * module configuration and status
 122  */
 123 static struct slgt_info *slgt_device_list;
 124 static int slgt_device_count;
 125
 126 static int ttymajor;
 127 static int debug_level;
 128 static int maxframe[MAX_DEVICES];
 129
 130 module_param(ttymajor, int, 0);
 131 module_param(debug_level, int, 0);
 132 module_param_array(maxframe, int, NULL, 0);
 133
 134 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 135 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 136 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 137
 138 /*
 139  * tty support and callbacks
 140  */
 141 static struct tty_driver *serial_driver;
 142
 143 static int  open(struct tty_struct *tty, struct file * filp);
 144 static void close(struct tty_struct *tty, struct file * filp);
 145 static void hangup(struct tty_struct *tty);
 146 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 147
 148 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 149 static int put_char(struct tty_struct *tty, unsigned char ch);
 150 static void send_xchar(struct tty_struct *tty, char ch);
 151 static void wait_until_sent(struct tty_struct *tty, int timeout);
 152 static int  write_room(struct tty_struct *tty);
 153 static void flush_chars(struct tty_struct *tty);
 154 static void flush_buffer(struct tty_struct *tty);
 155 static void tx_hold(struct tty_struct *tty);
 156 static void tx_release(struct tty_struct *tty);
 157
 158 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 159 static int  chars_in_buffer(struct tty_struct *tty);
 160 static void throttle(struct tty_struct * tty);
 161 static void unthrottle(struct tty_struct * tty);
 162 static int set_break(struct tty_struct *tty, int break_state);
 163
 164 /*
 165  * generic HDLC support and callbacks
 166  */
 167 #if SYNCLINK_GENERIC_HDLC
 168 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 169 static void hdlcdev_tx_done(struct slgt_info *info);
 170 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 171 static int  hdlcdev_init(struct slgt_info *info);
 172 static void hdlcdev_exit(struct slgt_info *info);
 173 #endif
 174
 175
 176 /*
 177  * device specific structures, macros and functions
 178  */
 179
 180 #define SLGT_MAX_PORTS 4
 181 #define SLGT_REG_SIZE  256
 182
 183 /*
 184  * conditional wait facility
 185  */
 186 struct cond_wait {
 187         struct cond_wait *next;
 188         wait_queue_head_t q;
 189         wait_queue_t wait;
 190         unsigned int data;
 191 };
 192 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 193 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 194 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 195 static void flush_cond_wait(struct cond_wait **head);
 196
 197 /*
 198  * DMA buffer descriptor and access macros
 199  */
 200 struct slgt_desc
 201 {
 202         __le16 count;
 203         __le16 status;
 204         __le32 pbuf;  /* physical address of data buffer */
 205         __le32 next;  /* physical address of next descriptor */
 206
 207         /* driver book keeping */
 208         char *buf;          /* virtual  address of data buffer */
 209         unsigned int pdesc; /* physical address of this descriptor */
 210         dma_addr_t buf_dma_addr;
 211         unsigned short buf_count;
 212 };
 213
 214 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 215 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 216 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 217 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 218 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 219 #define desc_count(a)      (le16_to_cpu((a).count))
 220 #define desc_status(a)     (le16_to_cpu((a).status))
 221 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 222 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 223 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 224 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 225 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 226
 227 struct _input_signal_events {
 228         int ri_up;
 229         int ri_down;
 230         int dsr_up;
 231         int dsr_down;
 232         int dcd_up;
 233         int dcd_down;
 234         int cts_up;
 235         int cts_down;
 236 };
 237
 238 /*
 239  * device instance data structure
 240  */
 241 struct slgt_info {
 242         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 243         struct tty_port port;
 244
 245         struct slgt_info *next_device;  /* device list link */
 246
 247         int magic;
 248
 249         char device_name[25];
 250         struct pci_dev *pdev;
 251
 252         int port_count;  /* count of ports on adapter */
 253         int adapter_num; /* adapter instance number */
 254         int port_num;    /* port instance number */
 255
 256         /* array of pointers to port contexts on this adapter */
 257         struct slgt_info *port_array[SLGT_MAX_PORTS];
 258
 259         int                     line;           /* tty line instance number */
 260
 261         struct mgsl_icount      icount;
 262
 263         int                     timeout;
 264         int                     x_char;         /* xon/xoff character */
 265         unsigned int            read_status_mask;
 266         unsigned int            ignore_status_mask;
 267
 268         wait_queue_head_t       status_event_wait_q;
 269         wait_queue_head_t       event_wait_q;
 270         struct timer_list       tx_timer;
 271         struct timer_list       rx_timer;
 272
 273         unsigned int            gpio_present;
 274         struct cond_wait        *gpio_wait_q;
 275
 276         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 277
 278         struct work_struct task;
 279         u32 pending_bh;
 280         bool bh_requested;
 281         bool bh_running;
 282
 283         int isr_overflow;
 284         bool irq_requested;     /* true if IRQ requested */
 285         bool irq_occurred;      /* for diagnostics use */
 286
 287         /* device configuration */
 288
 289         unsigned int bus_type;
 290         unsigned int irq_level;
 291         unsigned long irq_flags;
 292
 293         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 294         u32 phys_reg_addr;
 295         bool reg_addr_requested;
 296
 297         MGSL_PARAMS params;       /* communications parameters */
 298         u32 idle_mode;
 299         u32 max_frame_size;       /* as set by device config */
 300
 301         unsigned int rbuf_fill_level;
 302         unsigned int rx_pio;
 303         unsigned int if_mode;
 304         unsigned int base_clock;
 305
 306         /* device status */
 307
 308         bool rx_enabled;
 309         bool rx_restart;
 310
 311         bool tx_enabled;
 312         bool tx_active;
 313
 314         unsigned char signals;    /* serial signal states */
 315         int init_error;  /* initialization error */
 316
 317         unsigned char *tx_buf;
 318         int tx_count;
 319
 320         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 321         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 322         bool drop_rts_on_tx_done;
 323         struct  _input_signal_events    input_signal_events;
 324
 325         int dcd_chkcount;       /* check counts to prevent */
 326         int cts_chkcount;       /* too many IRQs if a signal */
 327         int dsr_chkcount;       /* is floating */
 328         int ri_chkcount;
 329
 330         char *bufs;             /* virtual address of DMA buffer lists */
 331         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 332
 333         unsigned int rbuf_count;
 334         struct slgt_desc *rbufs;
 335         unsigned int rbuf_current;
 336         unsigned int rbuf_index;
 337         unsigned int rbuf_fill_index;
 338         unsigned short rbuf_fill_count;
 339
 340         unsigned int tbuf_count;
 341         struct slgt_desc *tbufs;
 342         unsigned int tbuf_current;
 343         unsigned int tbuf_start;
 344
 345         unsigned char *tmp_rbuf;
 346         unsigned int tmp_rbuf_count;
 347
 348         /* SPPP/Cisco HDLC device parts */
 349
 350         int netcount;
 351         spinlock_t netlock;
 352 #if SYNCLINK_GENERIC_HDLC
 353         struct net_device *netdev;
 354 #endif
 355
 356 };
 357
 358 static MGSL_PARAMS default_params = {
 359         .mode            = MGSL_MODE_HDLC,
 360         .loopback        = 0,
 361         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 362         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 363         .clock_speed     = 0,
 364         .addr_filter     = 0xff,
 365         .crc_type        = HDLC_CRC_16_CCITT,
 366         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 367         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 368         .data_rate       = 9600,
 369         .data_bits       = 8,
 370         .stop_bits       = 1,
 371         .parity          = ASYNC_PARITY_NONE
 372 };
 373
 374
 375 #define BH_RECEIVE  1
 376 #define BH_TRANSMIT 2
 377 #define BH_STATUS   4
 378 #define IO_PIN_SHUTDOWN_LIMIT 100
 379
 380 #define DMABUFSIZE 256
 381 #define DESC_LIST_SIZE 4096
 382
 383 #define MASK_PARITY  BIT1
 384 #define MASK_FRAMING BIT0
 385 #define MASK_BREAK   BIT14
 386 #define MASK_OVERRUN BIT4
 387
 388 #define GSR   0x00 /* global status */
 389 #define JCR   0x04 /* JTAG control */
 390 #define IODR  0x08 /* GPIO direction */
 391 #define IOER  0x0c /* GPIO interrupt enable */
 392 #define IOVR  0x10 /* GPIO value */
 393 #define IOSR  0x14 /* GPIO interrupt status */
 394 #define TDR   0x80 /* tx data */
 395 #define RDR   0x80 /* rx data */
 396 #define TCR   0x82 /* tx control */
 397 #define TIR   0x84 /* tx idle */
 398 #define TPR   0x85 /* tx preamble */
 399 #define RCR   0x86 /* rx control */
 400 #define VCR   0x88 /* V.24 control */
 401 #define CCR   0x89 /* clock control */
 402 #define BDR   0x8a /* baud divisor */
 403 #define SCR   0x8c /* serial control */
 404 #define SSR   0x8e /* serial status */
 405 #define RDCSR 0x90 /* rx DMA control/status */
 406 #define TDCSR 0x94 /* tx DMA control/status */
 407 #define RDDAR 0x98 /* rx DMA descriptor address */
 408 #define TDDAR 0x9c /* tx DMA descriptor address */
 409
 410 #define RXIDLE      BIT14
 411 #define RXBREAK     BIT14
 412 #define IRQ_TXDATA  BIT13
 413 #define IRQ_TXIDLE  BIT12
 414 #define IRQ_TXUNDER BIT11 /* HDLC */
 415 #define IRQ_RXDATA  BIT10
 416 #define IRQ_RXIDLE  BIT9  /* HDLC */
 417 #define IRQ_RXBREAK BIT9  /* async */
 418 #define IRQ_RXOVER  BIT8
 419 #define IRQ_DSR     BIT7
 420 #define IRQ_CTS     BIT6
 421 #define IRQ_DCD     BIT5
 422 #define IRQ_RI      BIT4
 423 #define IRQ_ALL     0x3ff0
 424 #define IRQ_MASTER  BIT0
 425
 426 #define slgt_irq_on(info, mask) \
 427         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 428 #define slgt_irq_off(info, mask) \
 429         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 430
 431 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 432 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 433 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 434 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 435 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 436 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 437
 438 static void  msc_set_vcr(struct slgt_info *info);
 439
 440 static int  startup(struct slgt_info *info);
 441 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 442 static void shutdown(struct slgt_info *info);
 443 static void program_hw(struct slgt_info *info);
 444 static void change_params(struct slgt_info *info);
 445
 446 static int  register_test(struct slgt_info *info);
 447 static int  irq_test(struct slgt_info *info);
 448 static int  loopback_test(struct slgt_info *info);
 449 static int  adapter_test(struct slgt_info *info);
 450
 451 static void reset_adapter(struct slgt_info *info);
 452 static void reset_port(struct slgt_info *info);
 453 static void async_mode(struct slgt_info *info);
 454 static void sync_mode(struct slgt_info *info);
 455
 456 static void rx_stop(struct slgt_info *info);
 457 static void rx_start(struct slgt_info *info);
 458 static void reset_rbufs(struct slgt_info *info);
 459 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 460 static void rdma_reset(struct slgt_info *info);
 461 static bool rx_get_frame(struct slgt_info *info);
 462 static bool rx_get_buf(struct slgt_info *info);
 463
 464 static void tx_start(struct slgt_info *info);
 465 static void tx_stop(struct slgt_info *info);
 466 static void tx_set_idle(struct slgt_info *info);
 467 static unsigned int free_tbuf_count(struct slgt_info *info);
 468 static unsigned int tbuf_bytes(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 472
 473 static void get_signals(struct slgt_info *info);
 474 static void set_signals(struct slgt_info *info);
 475 static void enable_loopback(struct slgt_info *info);
 476 static void set_rate(struct slgt_info *info, u32 data_rate);
 477
 478 static int  bh_action(struct slgt_info *info);
 479 static void bh_handler(struct work_struct *work);
 480 static void bh_transmit(struct slgt_info *info);
 481 static void isr_serial(struct slgt_info *info);
 482 static void isr_rdma(struct slgt_info *info);
 483 static void isr_txeom(struct slgt_info *info, unsigned short status);
 484 static void isr_tdma(struct slgt_info *info);
 485
 486 static int  alloc_dma_bufs(struct slgt_info *info);
 487 static void free_dma_bufs(struct slgt_info *info);
 488 static int  alloc_desc(struct slgt_info *info);
 489 static void free_desc(struct slgt_info *info);
 490 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492
 493 static int  alloc_tmp_rbuf(struct slgt_info *info);
 494 static void free_tmp_rbuf(struct slgt_info *info);
 495
 496 static void tx_timeout(unsigned long context);
 497 static void rx_timeout(unsigned long context);
 498
 499 /*
 500  * ioctl handlers
 501  */
 502 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 503 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 504 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 506 static int  set_txidle(struct slgt_info *info, int idle_mode);
 507 static int  tx_enable(struct slgt_info *info, int enable);
 508 static int  tx_abort(struct slgt_info *info);
 509 static int  rx_enable(struct slgt_info *info, int enable);
 510 static int  modem_input_wait(struct slgt_info *info,int arg);
 511 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 512 static int  tiocmget(struct tty_struct *tty, struct file *file);
 513 static int  tiocmset(struct tty_struct *tty, struct file *file,
 514                      unsigned int set, unsigned int clear);
 515 static int set_break(struct tty_struct *tty, int break_state);
 516 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 517 static int  set_interface(struct slgt_info *info, int if_mode);
 518 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521
 522 /*
 523  * driver functions
 524  */
 525 static void add_device(struct slgt_info *info);
 526 static void device_init(int adapter_num, struct pci_dev *pdev);
 527 static int  claim_resources(struct slgt_info *info);
 528 static void release_resources(struct slgt_info *info);
 529
 530 /*
 531  * DEBUG OUTPUT CODE
 532  */
 533 #ifndef DBGINFO
 534 #define DBGINFO(fmt)
 535 #endif
 536 #ifndef DBGERR
 537 #define DBGERR(fmt)
 538 #endif
 539 #ifndef DBGBH
 540 #define DBGBH(fmt)
 541 #endif
 542 #ifndef DBGISR
 543 #define DBGISR(fmt)
 544 #endif
 545
 546 #ifdef DBGDATA
 547 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 548 {
 549         int i;
 550         int linecount;
 551         printk("%s %s data:\n",info->device_name, label);
 552         while(count) {
 553                 linecount = (count > 16) ? 16 : count;
 554                 for(i=0; i < linecount; i++)
 555                         printk("%02X ",(unsigned char)data[i]);
 556                 for(;i<17;i++)
 557                         printk("   ");
 558                 for(i=0;i<linecount;i++) {
 559                         if (data[i]>=040 && data[i]<=0176)
 560                                 printk("%c",data[i]);
 561                         else
 562                                 printk(".");
 563                 }
 564                 printk("\n");
 565                 data  += linecount;
 566                 count -= linecount;
 567         }
 568 }
 569 #else
 570 #define DBGDATA(info, buf, size, label)
 571 #endif
 572
 573 #ifdef DBGTBUF
 574 static void dump_tbufs(struct slgt_info *info)
 575 {
 576         int i;
 577         printk("tbuf_current=%d\n", info->tbuf_current);
 578         for (i=0 ; i < info->tbuf_count ; i++) {
 579                 printk("%d: count=%04X status=%04X\n",
 580                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 581         }
 582 }
 583 #else
 584 #define DBGTBUF(info)
 585 #endif
 586
 587 #ifdef DBGRBUF
 588 static void dump_rbufs(struct slgt_info *info)
 589 {
 590         int i;
 591         printk("rbuf_current=%d\n", info->rbuf_current);
 592         for (i=0 ; i < info->rbuf_count ; i++) {
 593                 printk("%d: count=%04X status=%04X\n",
 594                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 595         }
 596 }
 597 #else
 598 #define DBGRBUF(info)
 599 #endif
 600
 601 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 602 {
 603 #ifdef SANITY_CHECK
 604         if (!info) {
 605                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 606                 return 1;
 607         }
 608         if (info->magic != MGSL_MAGIC) {
 609                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 610                 return 1;
 611         }
 612 #else
 613         if (!info)
 614                 return 1;
 615 #endif
 616         return 0;
 617 }
 618
 619 /**
 620  * line discipline callback wrappers
 621  *
 622  * The wrappers maintain line discipline references
 623  * while calling into the line discipline.
 624  *
 625  * ldisc_receive_buf  - pass receive data to line discipline
 626  */
 627 static void ldisc_receive_buf(struct tty_struct *tty,
 628                               const __u8 *data, char *flags, int count)
 629 {
 630         struct tty_ldisc *ld;
 631         if (!tty)
 632                 return;
 633         ld = tty_ldisc_ref(tty);
 634         if (ld) {
 635                 if (ld->ops->receive_buf)
 636                         ld->ops->receive_buf(tty, data, flags, count);
 637                 tty_ldisc_deref(ld);
 638         }
 639 }
 640
 641 /* tty callbacks */
 642
 643 static int open(struct tty_struct *tty, struct file *filp)
 644 {
 645         struct slgt_info *info;
 646         int retval, line;
 647         unsigned long flags;
 648
 649         line = tty->index;
 650         if ((line < 0) || (line >= slgt_device_count)) {
 651                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 652                 return -ENODEV;
 653         }
 654
 655         info = slgt_device_list;
 656         while(info && info->line != line)
 657                 info = info->next_device;
 658         if (sanity_check(info, tty->name, "open"))
 659                 return -ENODEV;
 660         if (info->init_error) {
 661                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 662                 return -ENODEV;
 663         }
 664
 665         tty->driver_data = info;
 666         info->port.tty = tty;
 667
 668         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 669
 670         /* If port is closing, signal caller to try again */
 671         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 672                 if (info->port.flags & ASYNC_CLOSING)
 673                         interruptible_sleep_on(&info->port.close_wait);
 674                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 675                         -EAGAIN : -ERESTARTSYS);
 676                 goto cleanup;
 677         }
 678
 679         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 680
 681         spin_lock_irqsave(&info->netlock, flags);
 682         if (info->netcount) {
 683                 retval = -EBUSY;
 684                 spin_unlock_irqrestore(&info->netlock, flags);
 685                 goto cleanup;
 686         }
 687         info->port.count++;
 688         spin_unlock_irqrestore(&info->netlock, flags);
 689
 690         if (info->port.count == 1) {
 691                 /* 1st open on this device, init hardware */
 692                 retval = startup(info);
 693                 if (retval < 0)
 694                         goto cleanup;
 695         }
 696
 697         retval = block_til_ready(tty, filp, info);
 698         if (retval) {
 699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                 goto cleanup;
 701         }
 702
 703         retval = 0;
 704
 705 cleanup:
 706         if (retval) {
 707                 if (tty->count == 1)
 708                         info->port.tty = NULL; /* tty layer will release tty struct */
 709                 if(info->port.count)
 710                         info->port.count--;
 711         }
 712
 713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714         return retval;
 715 }
 716
 717 static void close(struct tty_struct *tty, struct file *filp)
 718 {
 719         struct slgt_info *info = tty->driver_data;
 720
 721         if (sanity_check(info, tty->name, "close"))
 722                 return;
 723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725         if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                 goto cleanup;
 727
 728         if (info->port.flags & ASYNC_INITIALIZED)
 729                 wait_until_sent(tty, info->timeout);
 730         flush_buffer(tty);
 731         tty_ldisc_flush(tty);
 732
 733         shutdown(info);
 734
 735         tty_port_close_end(&info->port, tty);
 736         info->port.tty = NULL;
 737 cleanup:
 738         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 739 }
 740
 741 static void hangup(struct tty_struct *tty)
 742 {
 743         struct slgt_info *info = tty->driver_data;
 744
 745         if (sanity_check(info, tty->name, "hangup"))
 746                 return;
 747         DBGINFO(("%s hangup\n", info->device_name));
 748
 749         flush_buffer(tty);
 750         shutdown(info);
 751
 752         info->port.count = 0;
 753         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 754         info->port.tty = NULL;
 755
 756         wake_up_interruptible(&info->port.open_wait);
 757 }
 758
 759 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 760 {
 761         struct slgt_info *info = tty->driver_data;
 762         unsigned long flags;
 763
 764         DBGINFO(("%s set_termios\n", tty->driver->name));
 765
 766         change_params(info);
 767
 768         /* Handle transition to B0 status */
 769         if (old_termios->c_cflag & CBAUD &&
 770             !(tty->termios->c_cflag & CBAUD)) {
 771                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 772                 spin_lock_irqsave(&info->lock,flags);
 773                 set_signals(info);
 774                 spin_unlock_irqrestore(&info->lock,flags);
 775         }
 776
 777         /* Handle transition away from B0 status */
 778         if (!(old_termios->c_cflag & CBAUD) &&
 779             tty->termios->c_cflag & CBAUD) {
 780                 info->signals |= SerialSignal_DTR;
 781                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 782                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 783                         info->signals |= SerialSignal_RTS;
 784                 }
 785                 spin_lock_irqsave(&info->lock,flags);
 786                 set_signals(info);
 787                 spin_unlock_irqrestore(&info->lock,flags);
 788         }
 789
 790         /* Handle turning off CRTSCTS */
 791         if (old_termios->c_cflag & CRTSCTS &&
 792             !(tty->termios->c_cflag & CRTSCTS)) {
 793                 tty->hw_stopped = 0;
 794                 tx_release(tty);
 795         }
 796 }
 797
 798 static void update_tx_timer(struct slgt_info *info)
 799 {
 800         /*
 801          * use worst case speed of 1200bps to calculate transmit timeout
 802          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 803          */
 804         if (info->params.mode == MGSL_MODE_HDLC) {
 805                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 806                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 807         }
 808 }
 809
 810 static int write(struct tty_struct *tty,
 811                  const unsigned char *buf, int count)
 812 {
 813         int ret = 0;
 814         struct slgt_info *info = tty->driver_data;
 815         unsigned long flags;
 816
 817         if (sanity_check(info, tty->name, "write"))
 818                 return -EIO;
 819
 820         DBGINFO(("%s write count=%d\n", info->device_name, count));
 821
 822         if (!info->tx_buf || (count > info->max_frame_size))
 823                 return -EIO;
 824
 825         if (!count || tty->stopped || tty->hw_stopped)
 826                 return 0;
 827
 828         spin_lock_irqsave(&info->lock, flags);
 829
 830         if (info->tx_count) {
 831                 /* send accumulated data from send_char() */
 832                 if (!tx_load(info, info->tx_buf, info->tx_count))
 833                         goto cleanup;
 834                 info->tx_count = 0;
 835         }
 836
 837         if (tx_load(info, buf, count))
 838                 ret = count;
 839
 840 cleanup:
 841         spin_unlock_irqrestore(&info->lock, flags);
 842         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 843         return ret;
 844 }
 845
 846 static int put_char(struct tty_struct *tty, unsigned char ch)
 847 {
 848         struct slgt_info *info = tty->driver_data;
 849         unsigned long flags;
 850         int ret = 0;
 851
 852         if (sanity_check(info, tty->name, "put_char"))
 853                 return 0;
 854         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 855         if (!info->tx_buf)
 856                 return 0;
 857         spin_lock_irqsave(&info->lock,flags);
 858         if (info->tx_count < info->max_frame_size) {
 859                 info->tx_buf[info->tx_count++] = ch;
 860                 ret = 1;
 861         }
 862         spin_unlock_irqrestore(&info->lock,flags);
 863         return ret;
 864 }
 865
 866 static void send_xchar(struct tty_struct *tty, char ch)
 867 {
 868         struct slgt_info *info = tty->driver_data;
 869         unsigned long flags;
 870
 871         if (sanity_check(info, tty->name, "send_xchar"))
 872                 return;
 873         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 874         info->x_char = ch;
 875         if (ch) {
 876                 spin_lock_irqsave(&info->lock,flags);
 877                 if (!info->tx_enabled)
 878                         tx_start(info);
 879                 spin_unlock_irqrestore(&info->lock,flags);
 880         }
 881 }
 882
 883 static void wait_until_sent(struct tty_struct *tty, int timeout)
 884 {
 885         struct slgt_info *info = tty->driver_data;
 886         unsigned long orig_jiffies, char_time;
 887
 888         if (!info )
 889                 return;
 890         if (sanity_check(info, tty->name, "wait_until_sent"))
 891                 return;
 892         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 893         if (!(info->port.flags & ASYNC_INITIALIZED))
 894                 goto exit;
 895
 896         orig_jiffies = jiffies;
 897
 898         /* Set check interval to 1/5 of estimated time to
 899          * send a character, and make it at least 1. The check
 900          * interval should also be less than the timeout.
 901          * Note: use tight timings here to satisfy the NIST-PCTS.
 902          */
 903
 904         lock_kernel();
 905
 906         if (info->params.data_rate) {
 907                 char_time = info->timeout/(32 * 5);
 908                 if (!char_time)
 909                         char_time++;
 910         } else
 911                 char_time = 1;
 912
 913         if (timeout)
 914                 char_time = min_t(unsigned long, char_time, timeout);
 915
 916         while (info->tx_active) {
 917                 msleep_interruptible(jiffies_to_msecs(char_time));
 918                 if (signal_pending(current))
 919                         break;
 920                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 921                         break;
 922         }
 923         unlock_kernel();
 924
 925 exit:
 926         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 927 }
 928
 929 static int write_room(struct tty_struct *tty)
 930 {
 931         struct slgt_info *info = tty->driver_data;
 932         int ret;
 933
 934         if (sanity_check(info, tty->name, "write_room"))
 935                 return 0;
 936         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 937         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 938         return ret;
 939 }
 940
 941 static void flush_chars(struct tty_struct *tty)
 942 {
 943         struct slgt_info *info = tty->driver_data;
 944         unsigned long flags;
 945
 946         if (sanity_check(info, tty->name, "flush_chars"))
 947                 return;
 948         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 949
 950         if (info->tx_count <= 0 || tty->stopped ||
 951             tty->hw_stopped || !info->tx_buf)
 952                 return;
 953
 954         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 955
 956         spin_lock_irqsave(&info->lock,flags);
 957         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 958                 info->tx_count = 0;
 959         spin_unlock_irqrestore(&info->lock,flags);
 960 }
 961
 962 static void flush_buffer(struct tty_struct *tty)
 963 {
 964         struct slgt_info *info = tty->driver_data;
 965         unsigned long flags;
 966
 967         if (sanity_check(info, tty->name, "flush_buffer"))
 968                 return;
 969         DBGINFO(("%s flush_buffer\n", info->device_name));
 970
 971         spin_lock_irqsave(&info->lock, flags);
 972         info->tx_count = 0;
 973         spin_unlock_irqrestore(&info->lock, flags);
 974
 975         tty_wakeup(tty);
 976 }
 977
 978 /*
 979  * throttle (stop) transmitter
 980  */
 981 static void tx_hold(struct tty_struct *tty)
 982 {
 983         struct slgt_info *info = tty->driver_data;
 984         unsigned long flags;
 985
 986         if (sanity_check(info, tty->name, "tx_hold"))
 987                 return;
 988         DBGINFO(("%s tx_hold\n", info->device_name));
 989         spin_lock_irqsave(&info->lock,flags);
 990         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 991                 tx_stop(info);
 992         spin_unlock_irqrestore(&info->lock,flags);
 993 }
 994
 995 /*
 996  * release (start) transmitter
 997  */
 998 static void tx_release(struct tty_struct *tty)
 999 {
1000         struct slgt_info *info = tty->driver_data;
1001         unsigned long flags;
1002
1003         if (sanity_check(info, tty->name, "tx_release"))
1004                 return;
1005         DBGINFO(("%s tx_release\n", info->device_name));
1006         spin_lock_irqsave(&info->lock, flags);
1007         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1008                 info->tx_count = 0;
1009         spin_unlock_irqrestore(&info->lock, flags);
1010 }
1011
1012 /*
1013  * Service an IOCTL request
1014  *
1015  * Arguments
1016  *
1017  *      tty     pointer to tty instance data
1018  *      file    pointer to associated file object for device
1019  *      cmd     IOCTL command code
1020  *      arg     command argument/context
1021  *
1022  * Return 0 if success, otherwise error code
1023  */
1024 static int ioctl(struct tty_struct *tty, struct file *file,
1025                  unsigned int cmd, unsigned long arg)
1026 {
1027         struct slgt_info *info = tty->driver_data;
1028         struct mgsl_icount cnow;        /* kernel counter temps */
1029         struct serial_icounter_struct __user *p_cuser;  /* user space */
1030         unsigned long flags;
1031         void __user *argp = (void __user *)arg;
1032         int ret;
1033
1034         if (sanity_check(info, tty->name, "ioctl"))
1035                 return -ENODEV;
1036         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1037
1038         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1039             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1040                 if (tty->flags & (1 << TTY_IO_ERROR))
1041                     return -EIO;
1042         }
1043
1044         lock_kernel();
1045
1046         switch (cmd) {
1047         case MGSL_IOCGPARAMS:
1048                 ret = get_params(info, argp);
1049                 break;
1050         case MGSL_IOCSPARAMS:
1051                 ret = set_params(info, argp);
1052                 break;
1053         case MGSL_IOCGTXIDLE:
1054                 ret = get_txidle(info, argp);
1055                 break;
1056         case MGSL_IOCSTXIDLE:
1057                 ret = set_txidle(info, (int)arg);
1058                 break;
1059         case MGSL_IOCTXENABLE:
1060                 ret = tx_enable(info, (int)arg);
1061                 break;
1062         case MGSL_IOCRXENABLE:
1063                 ret = rx_enable(info, (int)arg);
1064                 break;
1065         case MGSL_IOCTXABORT:
1066                 ret = tx_abort(info);
1067                 break;
1068         case MGSL_IOCGSTATS:
1069                 ret = get_stats(info, argp);
1070                 break;
1071         case MGSL_IOCWAITEVENT:
1072                 ret = wait_mgsl_event(info, argp);
1073                 break;
1074         case TIOCMIWAIT:
1075                 ret = modem_input_wait(info,(int)arg);
1076                 break;
1077         case MGSL_IOCGIF:
1078                 ret = get_interface(info, argp);
1079                 break;
1080         case MGSL_IOCSIF:
1081                 ret = set_interface(info,(int)arg);
1082                 break;
1083         case MGSL_IOCSGPIO:
1084                 ret = set_gpio(info, argp);
1085                 break;
1086         case MGSL_IOCGGPIO:
1087                 ret = get_gpio(info, argp);
1088                 break;
1089         case MGSL_IOCWAITGPIO:
1090                 ret = wait_gpio(info, argp);
1091                 break;
1092         case TIOCGICOUNT:
1093                 spin_lock_irqsave(&info->lock,flags);
1094                 cnow = info->icount;
1095                 spin_unlock_irqrestore(&info->lock,flags);
1096                 p_cuser = argp;
1097                 if (put_user(cnow.cts, &p_cuser->cts) ||
1098                     put_user(cnow.dsr, &p_cuser->dsr) ||
1099                     put_user(cnow.rng, &p_cuser->rng) ||
1100                     put_user(cnow.dcd, &p_cuser->dcd) ||
1101                     put_user(cnow.rx, &p_cuser->rx) ||
1102                     put_user(cnow.tx, &p_cuser->tx) ||
1103                     put_user(cnow.frame, &p_cuser->frame) ||
1104                     put_user(cnow.overrun, &p_cuser->overrun) ||
1105                     put_user(cnow.parity, &p_cuser->parity) ||
1106                     put_user(cnow.brk, &p_cuser->brk) ||
1107                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1108                         ret = -EFAULT;
1109                 ret = 0;
1110                 break;
1111         default:
1112                 ret = -ENOIOCTLCMD;
1113         }
1114         unlock_kernel();
1115         return ret;
1116 }
1117
1118 /*
1119  * support for 32 bit ioctl calls on 64 bit systems
1120  */
1121 #ifdef CONFIG_COMPAT
1122 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1123 {
1124         struct MGSL_PARAMS32 tmp_params;
1125
1126         DBGINFO(("%s get_params32\n", info->device_name));
1127         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1128         tmp_params.loopback        = info->params.loopback;
1129         tmp_params.flags           = info->params.flags;
1130         tmp_params.encoding        = info->params.encoding;
1131         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1132         tmp_params.addr_filter     = info->params.addr_filter;
1133         tmp_params.crc_type        = info->params.crc_type;
1134         tmp_params.preamble_length = info->params.preamble_length;
1135         tmp_params.preamble        = info->params.preamble;
1136         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1137         tmp_params.data_bits       = info->params.data_bits;
1138         tmp_params.stop_bits       = info->params.stop_bits;
1139         tmp_params.parity          = info->params.parity;
1140         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1141                 return -EFAULT;
1142         return 0;
1143 }
1144
1145 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1146 {
1147         struct MGSL_PARAMS32 tmp_params;
1148
1149         DBGINFO(("%s set_params32\n", info->device_name));
1150         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1151                 return -EFAULT;
1152
1153         spin_lock(&info->lock);
1154         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1155                 info->base_clock = tmp_params.clock_speed;
1156         } else {
1157                 info->params.mode            = tmp_params.mode;
1158                 info->params.loopback        = tmp_params.loopback;
1159                 info->params.flags           = tmp_params.flags;
1160                 info->params.encoding        = tmp_params.encoding;
1161                 info->params.clock_speed     = tmp_params.clock_speed;
1162                 info->params.addr_filter     = tmp_params.addr_filter;
1163                 info->params.crc_type        = tmp_params.crc_type;
1164                 info->params.preamble_length = tmp_params.preamble_length;
1165                 info->params.preamble        = tmp_params.preamble;
1166                 info->params.data_rate       = tmp_params.data_rate;
1167                 info->params.data_bits       = tmp_params.data_bits;
1168                 info->params.stop_bits       = tmp_params.stop_bits;
1169                 info->params.parity          = tmp_params.parity;
1170         }
1171         spin_unlock(&info->lock);
1172
1173         program_hw(info);
1174
1175         return 0;
1176 }
1177
1178 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1179                          unsigned int cmd, unsigned long arg)
1180 {
1181         struct slgt_info *info = tty->driver_data;
1182         int rc = -ENOIOCTLCMD;
1183
1184         if (sanity_check(info, tty->name, "compat_ioctl"))
1185                 return -ENODEV;
1186         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1187
1188         switch (cmd) {
1189
1190         case MGSL_IOCSPARAMS32:
1191                 rc = set_params32(info, compat_ptr(arg));
1192                 break;
1193
1194         case MGSL_IOCGPARAMS32:
1195                 rc = get_params32(info, compat_ptr(arg));
1196                 break;
1197
1198         case MGSL_IOCGPARAMS:
1199         case MGSL_IOCSPARAMS:
1200         case MGSL_IOCGTXIDLE:
1201         case MGSL_IOCGSTATS:
1202         case MGSL_IOCWAITEVENT:
1203         case MGSL_IOCGIF:
1204         case MGSL_IOCSGPIO:
1205         case MGSL_IOCGGPIO:
1206         case MGSL_IOCWAITGPIO:
1207         case TIOCGICOUNT:
1208                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1209                 break;
1210
1211         case MGSL_IOCSTXIDLE:
1212         case MGSL_IOCTXENABLE:
1213         case MGSL_IOCRXENABLE:
1214         case MGSL_IOCTXABORT:
1215         case TIOCMIWAIT:
1216         case MGSL_IOCSIF:
1217                 rc = ioctl(tty, file, cmd, arg);
1218                 break;
1219         }
1220
1221         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1222         return rc;
1223 }
1224 #else
1225 #define slgt_compat_ioctl NULL
1226 #endif /* ifdef CONFIG_COMPAT */
1227
1228 /*
1229  * proc fs support
1230  */
1231 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1232 {
1233         char stat_buf[30];
1234         unsigned long flags;
1235
1236         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1237                       info->device_name, info->phys_reg_addr,
1238                       info->irq_level, info->max_frame_size);
1239
1240         /* output current serial signal states */
1241         spin_lock_irqsave(&info->lock,flags);
1242         get_signals(info);
1243         spin_unlock_irqrestore(&info->lock,flags);
1244
1245         stat_buf[0] = 0;
1246         stat_buf[1] = 0;
1247         if (info->signals & SerialSignal_RTS)
1248                 strcat(stat_buf, "|RTS");
1249         if (info->signals & SerialSignal_CTS)
1250                 strcat(stat_buf, "|CTS");
1251         if (info->signals & SerialSignal_DTR)
1252                 strcat(stat_buf, "|DTR");
1253         if (info->signals & SerialSignal_DSR)
1254                 strcat(stat_buf, "|DSR");
1255         if (info->signals & SerialSignal_DCD)
1256                 strcat(stat_buf, "|CD");
1257         if (info->signals & SerialSignal_RI)
1258                 strcat(stat_buf, "|RI");
1259
1260         if (info->params.mode != MGSL_MODE_ASYNC) {
1261                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1262                                info->icount.txok, info->icount.rxok);
1263                 if (info->icount.txunder)
1264                         seq_printf(m, " txunder:%d", info->icount.txunder);
1265                 if (info->icount.txabort)
1266                         seq_printf(m, " txabort:%d", info->icount.txabort);
1267                 if (info->icount.rxshort)
1268                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1269                 if (info->icount.rxlong)
1270                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1271                 if (info->icount.rxover)
1272                         seq_printf(m, " rxover:%d", info->icount.rxover);
1273                 if (info->icount.rxcrc)
1274                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1275         } else {
1276                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1277                                info->icount.tx, info->icount.rx);
1278                 if (info->icount.frame)
1279                         seq_printf(m, " fe:%d", info->icount.frame);
1280                 if (info->icount.parity)
1281                         seq_printf(m, " pe:%d", info->icount.parity);
1282                 if (info->icount.brk)
1283                         seq_printf(m, " brk:%d", info->icount.brk);
1284                 if (info->icount.overrun)
1285                         seq_printf(m, " oe:%d", info->icount.overrun);
1286         }
1287
1288         /* Append serial signal status to end */
1289         seq_printf(m, " %s\n", stat_buf+1);
1290
1291         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1292                        info->tx_active,info->bh_requested,info->bh_running,
1293                        info->pending_bh);
1294 }
1295
1296 /* Called to print information about devices
1297  */
1298 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1299 {
1300         struct slgt_info *info;
1301
1302         seq_puts(m, "synclink_gt driver\n");
1303
1304         info = slgt_device_list;
1305         while( info ) {
1306                 line_info(m, info);
1307                 info = info->next_device;
1308         }
1309         return 0;
1310 }
1311
1312 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1313 {
1314         return single_open(file, synclink_gt_proc_show, NULL);
1315 }
1316
1317 static const struct file_operations synclink_gt_proc_fops = {
1318         .owner          = THIS_MODULE,
1319         .open           = synclink_gt_proc_open,
1320         .read           = seq_read,
1321         .llseek         = seq_lseek,
1322         .release        = single_release,
1323 };
1324
1325 /*
1326  * return count of bytes in transmit buffer
1327  */
1328 static int chars_in_buffer(struct tty_struct *tty)
1329 {
1330         struct slgt_info *info = tty->driver_data;
1331         int count;
1332         if (sanity_check(info, tty->name, "chars_in_buffer"))
1333                 return 0;
1334         count = tbuf_bytes(info);
1335         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1336         return count;
1337 }
1338
1339 /*
1340  * signal remote device to throttle send data (our receive data)
1341  */
1342 static void throttle(struct tty_struct * tty)
1343 {
1344         struct slgt_info *info = tty->driver_data;
1345         unsigned long flags;
1346
1347         if (sanity_check(info, tty->name, "throttle"))
1348                 return;
1349         DBGINFO(("%s throttle\n", info->device_name));
1350         if (I_IXOFF(tty))
1351                 send_xchar(tty, STOP_CHAR(tty));
1352         if (tty->termios->c_cflag & CRTSCTS) {
1353                 spin_lock_irqsave(&info->lock,flags);
1354                 info->signals &= ~SerialSignal_RTS;
1355                 set_signals(info);
1356                 spin_unlock_irqrestore(&info->lock,flags);
1357         }
1358 }
1359
1360 /*
1361  * signal remote device to stop throttling send data (our receive data)
1362  */
1363 static void unthrottle(struct tty_struct * tty)
1364 {
1365         struct slgt_info *info = tty->driver_data;
1366         unsigned long flags;
1367
1368         if (sanity_check(info, tty->name, "unthrottle"))
1369                 return;
1370         DBGINFO(("%s unthrottle\n", info->device_name));
1371         if (I_IXOFF(tty)) {
1372                 if (info->x_char)
1373                         info->x_char = 0;
1374                 else
1375                         send_xchar(tty, START_CHAR(tty));
1376         }
1377         if (tty->termios->c_cflag & CRTSCTS) {
1378                 spin_lock_irqsave(&info->lock,flags);
1379                 info->signals |= SerialSignal_RTS;
1380                 set_signals(info);
1381                 spin_unlock_irqrestore(&info->lock,flags);
1382         }
1383 }
1384
1385 /*
1386  * set or clear transmit break condition
1387  * break_state  -1=set break condition, 0=clear
1388  */
1389 static int set_break(struct tty_struct *tty, int break_state)
1390 {
1391         struct slgt_info *info = tty->driver_data;
1392         unsigned short value;
1393         unsigned long flags;
1394
1395         if (sanity_check(info, tty->name, "set_break"))
1396                 return -EINVAL;
1397         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1398
1399         spin_lock_irqsave(&info->lock,flags);
1400         value = rd_reg16(info, TCR);
1401         if (break_state == -1)
1402                 value |= BIT6;
1403         else
1404                 value &= ~BIT6;
1405         wr_reg16(info, TCR, value);
1406         spin_unlock_irqrestore(&info->lock,flags);
1407         return 0;
1408 }
1409
1410 #if SYNCLINK_GENERIC_HDLC
1411
1412 /**
1413  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1414  * set encoding and frame check sequence (FCS) options
1415  *
1416  * dev       pointer to network device structure
1417  * encoding  serial encoding setting
1418  * parity    FCS setting
1419  *
1420  * returns 0 if success, otherwise error code
1421  */
1422 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1423                           unsigned short parity)
1424 {
1425         struct slgt_info *info = dev_to_port(dev);
1426         unsigned char  new_encoding;
1427         unsigned short new_crctype;
1428
1429         /* return error if TTY interface open */
1430         if (info->port.count)
1431                 return -EBUSY;
1432
1433         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1434
1435         switch (encoding)
1436         {
1437         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1438         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1439         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1440         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1441         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1442         default: return -EINVAL;
1443         }
1444
1445         switch (parity)
1446         {
1447         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1448         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1449         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1450         default: return -EINVAL;
1451         }
1452
1453         info->params.encoding = new_encoding;
1454         info->params.crc_type = new_crctype;
1455
1456         /* if network interface up, reprogram hardware */
1457         if (info->netcount)
1458                 program_hw(info);
1459
1460         return 0;
1461 }
1462
1463 /**
1464  * called by generic HDLC layer to send frame
1465  *
1466  * skb  socket buffer containing HDLC frame
1467  * dev  pointer to network device structure
1468  */
1469 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1470                                       struct net_device *dev)
1471 {
1472         struct slgt_info *info = dev_to_port(dev);
1473         unsigned long flags;
1474
1475         DBGINFO(("%s hdlc_xmit\n", dev->name));
1476
1477         if (!skb->len)
1478                 return NETDEV_TX_OK;
1479
1480         /* stop sending until this frame completes */
1481         netif_stop_queue(dev);
1482
1483         /* update network statistics */
1484         dev->stats.tx_packets++;
1485         dev->stats.tx_bytes += skb->len;
1486
1487         /* save start time for transmit timeout detection */
1488         dev->trans_start = jiffies;
1489
1490         spin_lock_irqsave(&info->lock, flags);
1491         tx_load(info, skb->data, skb->len);
1492         spin_unlock_irqrestore(&info->lock, flags);
1493
1494         /* done with socket buffer, so free it */
1495         dev_kfree_skb(skb);
1496
1497         return NETDEV_TX_OK;
1498 }
1499
1500 /**
1501  * called by network layer when interface enabled
1502  * claim resources and initialize hardware
1503  *
1504  * dev  pointer to network device structure
1505  *
1506  * returns 0 if success, otherwise error code
1507  */
1508 static int hdlcdev_open(struct net_device *dev)
1509 {
1510         struct slgt_info *info = dev_to_port(dev);
1511         int rc;
1512         unsigned long flags;
1513
1514         if (!try_module_get(THIS_MODULE))
1515                 return -EBUSY;
1516
1517         DBGINFO(("%s hdlcdev_open\n", dev->name));
1518
1519         /* generic HDLC layer open processing */
1520         if ((rc = hdlc_open(dev)))
1521                 return rc;
1522
1523         /* arbitrate between network and tty opens */
1524         spin_lock_irqsave(&info->netlock, flags);
1525         if (info->port.count != 0 || info->netcount != 0) {
1526                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1527                 spin_unlock_irqrestore(&info->netlock, flags);
1528                 return -EBUSY;
1529         }
1530         info->netcount=1;
1531         spin_unlock_irqrestore(&info->netlock, flags);
1532
1533         /* claim resources and init adapter */
1534         if ((rc = startup(info)) != 0) {
1535                 spin_lock_irqsave(&info->netlock, flags);
1536                 info->netcount=0;
1537                 spin_unlock_irqrestore(&info->netlock, flags);
1538                 return rc;
1539         }
1540
1541         /* assert DTR and RTS, apply hardware settings */
1542         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1543         program_hw(info);
1544
1545         /* enable network layer transmit */
1546         dev->trans_start = jiffies;
1547         netif_start_queue(dev);
1548
1549         /* inform generic HDLC layer of current DCD status */
1550         spin_lock_irqsave(&info->lock, flags);
1551         get_signals(info);
1552         spin_unlock_irqrestore(&info->lock, flags);
1553         if (info->signals & SerialSignal_DCD)
1554                 netif_carrier_on(dev);
1555         else
1556                 netif_carrier_off(dev);
1557         return 0;
1558 }
1559
1560 /**
1561  * called by network layer when interface is disabled
1562  * shutdown hardware and release resources
1563  *
1564  * dev  pointer to network device structure
1565  *
1566  * returns 0 if success, otherwise error code
1567  */
1568 static int hdlcdev_close(struct net_device *dev)
1569 {
1570         struct slgt_info *info = dev_to_port(dev);
1571         unsigned long flags;
1572
1573         DBGINFO(("%s hdlcdev_close\n", dev->name));
1574
1575         netif_stop_queue(dev);
1576
1577         /* shutdown adapter and release resources */
1578         shutdown(info);
1579
1580         hdlc_close(dev);
1581
1582         spin_lock_irqsave(&info->netlock, flags);
1583         info->netcount=0;
1584         spin_unlock_irqrestore(&info->netlock, flags);
1585
1586         module_put(THIS_MODULE);
1587         return 0;
1588 }
1589
1590 /**
1591  * called by network layer to process IOCTL call to network device
1592  *
1593  * dev  pointer to network device structure
1594  * ifr  pointer to network interface request structure
1595  * cmd  IOCTL command code
1596  *
1597  * returns 0 if success, otherwise error code
1598  */
1599 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1600 {
1601         const size_t size = sizeof(sync_serial_settings);
1602         sync_serial_settings new_line;
1603         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1604         struct slgt_info *info = dev_to_port(dev);
1605         unsigned int flags;
1606
1607         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1608
1609         /* return error if TTY interface open */
1610         if (info->port.count)
1611                 return -EBUSY;
1612
1613         if (cmd != SIOCWANDEV)
1614                 return hdlc_ioctl(dev, ifr, cmd);
1615
1616         switch(ifr->ifr_settings.type) {
1617         case IF_GET_IFACE: /* return current sync_serial_settings */
1618
1619                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1620                 if (ifr->ifr_settings.size < size) {
1621                         ifr->ifr_settings.size = size; /* data size wanted */
1622                         return -ENOBUFS;
1623                 }
1624
1625                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1626                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1627                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1628                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1629
1630                 switch (flags){
1631                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1632                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1633                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1634                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1635                 default: new_line.clock_type = CLOCK_DEFAULT;
1636                 }
1637
1638                 new_line.clock_rate = info->params.clock_speed;
1639                 new_line.loopback   = info->params.loopback ? 1:0;
1640
1641                 if (copy_to_user(line, &new_line, size))
1642                         return -EFAULT;
1643                 return 0;
1644
1645         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1646
1647                 if(!capable(CAP_NET_ADMIN))
1648                         return -EPERM;
1649                 if (copy_from_user(&new_line, line, size))
1650                         return -EFAULT;
1651
1652                 switch (new_line.clock_type)
1653                 {
1654                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1655                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1656                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1657                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1658                 case CLOCK_DEFAULT:  flags = info->params.flags &
1659                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1660                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1661                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1662                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1663                 default: return -EINVAL;
1664                 }
1665
1666                 if (new_line.loopback != 0 && new_line.loopback != 1)
1667                         return -EINVAL;
1668
1669                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1670                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1671                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1672                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1673                 info->params.flags |= flags;
1674
1675                 info->params.loopback = new_line.loopback;
1676
1677                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1678                         info->params.clock_speed = new_line.clock_rate;
1679                 else
1680                         info->params.clock_speed = 0;
1681
1682                 /* if network interface up, reprogram hardware */
1683                 if (info->netcount)
1684                         program_hw(info);
1685                 return 0;
1686
1687         default:
1688                 return hdlc_ioctl(dev, ifr, cmd);
1689         }
1690 }
1691
1692 /**
1693  * called by network layer when transmit timeout is detected
1694  *
1695  * dev  pointer to network device structure
1696  */
1697 static void hdlcdev_tx_timeout(struct net_device *dev)
1698 {
1699         struct slgt_info *info = dev_to_port(dev);
1700         unsigned long flags;
1701
1702         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1703
1704         dev->stats.tx_errors++;
1705         dev->stats.tx_aborted_errors++;
1706
1707         spin_lock_irqsave(&info->lock,flags);
1708         tx_stop(info);
1709         spin_unlock_irqrestore(&info->lock,flags);
1710
1711         netif_wake_queue(dev);
1712 }
1713
1714 /**
1715  * called by device driver when transmit completes
1716  * reenable network layer transmit if stopped
1717  *
1718  * info  pointer to device instance information
1719  */
1720 static void hdlcdev_tx_done(struct slgt_info *info)
1721 {
1722         if (netif_queue_stopped(info->netdev))
1723                 netif_wake_queue(info->netdev);
1724 }
1725
1726 /**
1727  * called by device driver when frame received
1728  * pass frame to network layer
1729  *
1730  * info  pointer to device instance information
1731  * buf   pointer to buffer contianing frame data
1732  * size  count of data bytes in buf
1733  */
1734 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1735 {
1736         struct sk_buff *skb = dev_alloc_skb(size);
1737         struct net_device *dev = info->netdev;
1738
1739         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1740
1741         if (skb == NULL) {
1742                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1743                 dev->stats.rx_dropped++;
1744                 return;
1745         }
1746
1747         memcpy(skb_put(skb, size), buf, size);
1748
1749         skb->protocol = hdlc_type_trans(skb, dev);
1750
1751         dev->stats.rx_packets++;
1752         dev->stats.rx_bytes += size;
1753
1754         netif_rx(skb);
1755 }
1756
1757 static const struct net_device_ops hdlcdev_ops = {
1758         .ndo_open       = hdlcdev_open,
1759         .ndo_stop       = hdlcdev_close,
1760         .ndo_change_mtu = hdlc_change_mtu,
1761         .ndo_start_xmit = hdlc_start_xmit,
1762         .ndo_do_ioctl   = hdlcdev_ioctl,
1763         .ndo_tx_timeout = hdlcdev_tx_timeout,
1764 };
1765
1766 /**
1767  * called by device driver when adding device instance
1768  * do generic HDLC initialization
1769  *
1770  * info  pointer to device instance information
1771  *
1772  * returns 0 if success, otherwise error code
1773  */
1774 static int hdlcdev_init(struct slgt_info *info)
1775 {
1776         int rc;
1777         struct net_device *dev;
1778         hdlc_device *hdlc;
1779
1780         /* allocate and initialize network and HDLC layer objects */
1781
1782         if (!(dev = alloc_hdlcdev(info))) {
1783                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1784                 return -ENOMEM;
1785         }
1786
1787         /* for network layer reporting purposes only */
1788         dev->mem_start = info->phys_reg_addr;
1789         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1790         dev->irq       = info->irq_level;
1791
1792         /* network layer callbacks and settings */
1793         dev->netdev_ops     = &hdlcdev_ops;
1794         dev->watchdog_timeo = 10 * HZ;
1795         dev->tx_queue_len   = 50;
1796
1797         /* generic HDLC layer callbacks and settings */
1798         hdlc         = dev_to_hdlc(dev);
1799         hdlc->attach = hdlcdev_attach;
1800         hdlc->xmit   = hdlcdev_xmit;
1801
1802         /* register objects with HDLC layer */
1803         if ((rc = register_hdlc_device(dev))) {
1804                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1805                 free_netdev(dev);
1806                 return rc;
1807         }
1808
1809         info->netdev = dev;
1810         return 0;
1811 }
1812
1813 /**
1814  * called by device driver when removing device instance
1815  * do generic HDLC cleanup
1816  *
1817  * info  pointer to device instance information
1818  */
1819 static void hdlcdev_exit(struct slgt_info *info)
1820 {
1821         unregister_hdlc_device(info->netdev);
1822         free_netdev(info->netdev);
1823         info->netdev = NULL;
1824 }
1825
1826 #endif /* ifdef CONFIG_HDLC */
1827
1828 /*
1829  * get async data from rx DMA buffers
1830  */
1831 static void rx_async(struct slgt_info *info)
1832 {
1833         struct tty_struct *tty = info->port.tty;
1834         struct mgsl_icount *icount = &info->icount;
1835         unsigned int start, end;
1836         unsigned char *p;
1837         unsigned char status;
1838         struct slgt_desc *bufs = info->rbufs;
1839         int i, count;
1840         int chars = 0;
1841         int stat;
1842         unsigned char ch;
1843
1844         start = end = info->rbuf_current;
1845
1846         while(desc_complete(bufs[end])) {
1847                 count = desc_count(bufs[end]) - info->rbuf_index;
1848                 p     = bufs[end].buf + info->rbuf_index;
1849
1850                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1851                 DBGDATA(info, p, count, "rx");
1852
1853                 for(i=0 ; i < count; i+=2, p+=2) {
1854                         ch = *p;
1855                         icount->rx++;
1856
1857                         stat = 0;
1858
1859                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1860                                 if (status & BIT1)
1861                                         icount->parity++;
1862                                 else if (status & BIT0)
1863                                         icount->frame++;
1864                                 /* discard char if tty control flags say so */
1865                                 if (status & info->ignore_status_mask)
1866                                         continue;
1867                                 if (status & BIT1)
1868                                         stat = TTY_PARITY;
1869                                 else if (status & BIT0)
1870                                         stat = TTY_FRAME;
1871                         }
1872                         if (tty) {
1873                                 tty_insert_flip_char(tty, ch, stat);
1874                                 chars++;
1875                         }
1876                 }
1877
1878                 if (i < count) {
1879                         /* receive buffer not completed */
1880                         info->rbuf_index += i;
1881                         mod_timer(&info->rx_timer, jiffies + 1);
1882                         break;
1883                 }
1884
1885                 info->rbuf_index = 0;
1886                 free_rbufs(info, end, end);
1887
1888                 if (++end == info->rbuf_count)
1889                         end = 0;
1890
1891                 /* if entire list searched then no frame available */
1892                 if (end == start)
1893                         break;
1894         }
1895
1896         if (tty && chars)
1897                 tty_flip_buffer_push(tty);
1898 }
1899
1900 /*
1901  * return next bottom half action to perform
1902  */
1903 static int bh_action(struct slgt_info *info)
1904 {
1905         unsigned long flags;
1906         int rc;
1907
1908         spin_lock_irqsave(&info->lock,flags);
1909
1910         if (info->pending_bh & BH_RECEIVE) {
1911                 info->pending_bh &= ~BH_RECEIVE;
1912                 rc = BH_RECEIVE;
1913         } else if (info->pending_bh & BH_TRANSMIT) {
1914                 info->pending_bh &= ~BH_TRANSMIT;
1915                 rc = BH_TRANSMIT;
1916         } else if (info->pending_bh & BH_STATUS) {
1917                 info->pending_bh &= ~BH_STATUS;
1918                 rc = BH_STATUS;
1919         } else {
1920                 /* Mark BH routine as complete */
1921                 info->bh_running = false;
1922                 info->bh_requested = false;
1923                 rc = 0;
1924         }
1925
1926         spin_unlock_irqrestore(&info->lock,flags);
1927
1928         return rc;
1929 }
1930
1931 /*
1932  * perform bottom half processing
1933  */
1934 static void bh_handler(struct work_struct *work)
1935 {
1936         struct slgt_info *info = container_of(work, struct slgt_info, task);
1937         int action;
1938
1939         if (!info)
1940                 return;
1941         info->bh_running = true;
1942
1943         while((action = bh_action(info))) {
1944                 switch (action) {
1945                 case BH_RECEIVE:
1946                         DBGBH(("%s bh receive\n", info->device_name));
1947                         switch(info->params.mode) {
1948                         case MGSL_MODE_ASYNC:
1949                                 rx_async(info);
1950                                 break;
1951                         case MGSL_MODE_HDLC:
1952                                 while(rx_get_frame(info));
1953                                 break;
1954                         case MGSL_MODE_RAW:
1955                         case MGSL_MODE_MONOSYNC:
1956                         case MGSL_MODE_BISYNC:
1957                                 while(rx_get_buf(info));
1958                                 break;
1959                         }
1960                         /* restart receiver if rx DMA buffers exhausted */
1961                         if (info->rx_restart)
1962                                 rx_start(info);
1963                         break;
1964                 case BH_TRANSMIT:
1965                         bh_transmit(info);
1966                         break;
1967                 case BH_STATUS:
1968                         DBGBH(("%s bh status\n", info->device_name));
1969                         info->ri_chkcount = 0;
1970                         info->dsr_chkcount = 0;
1971                         info->dcd_chkcount = 0;
1972                         info->cts_chkcount = 0;
1973                         break;
1974                 default:
1975                         DBGBH(("%s unknown action\n", info->device_name));
1976                         break;
1977                 }
1978         }
1979         DBGBH(("%s bh_handler exit\n", info->device_name));
1980 }
1981
1982 static void bh_transmit(struct slgt_info *info)
1983 {
1984         struct tty_struct *tty = info->port.tty;
1985
1986         DBGBH(("%s bh_transmit\n", info->device_name));
1987         if (tty)
1988                 tty_wakeup(tty);
1989 }
1990
1991 static void dsr_change(struct slgt_info *info, unsigned short status)
1992 {
1993         if (status & BIT3) {
1994                 info->signals |= SerialSignal_DSR;
1995                 info->input_signal_events.dsr_up++;
1996         } else {
1997                 info->signals &= ~SerialSignal_DSR;
1998                 info->input_signal_events.dsr_down++;
1999         }
2000         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2001         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2002                 slgt_irq_off(info, IRQ_DSR);
2003                 return;
2004         }
2005         info->icount.dsr++;
2006         wake_up_interruptible(&info->status_event_wait_q);
2007         wake_up_interruptible(&info->event_wait_q);
2008         info->pending_bh |= BH_STATUS;
2009 }
2010
2011 static void cts_change(struct slgt_info *info, unsigned short status)
2012 {
2013         if (status & BIT2) {
2014                 info->signals |= SerialSignal_CTS;
2015                 info->input_signal_events.cts_up++;
2016         } else {
2017                 info->signals &= ~SerialSignal_CTS;
2018                 info->input_signal_events.cts_down++;
2019         }
2020         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2021         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2022                 slgt_irq_off(info, IRQ_CTS);
2023                 return;
2024         }
2025         info->icount.cts++;
2026         wake_up_interruptible(&info->status_event_wait_q);
2027         wake_up_interruptible(&info->event_wait_q);
2028         info->pending_bh |= BH_STATUS;
2029
2030         if (info->port.flags & ASYNC_CTS_FLOW) {
2031                 if (info->port.tty) {
2032                         if (info->port.tty->hw_stopped) {
2033                                 if (info->signals & SerialSignal_CTS) {
2034                                         info->port.tty->hw_stopped = 0;
2035                                         info->pending_bh |= BH_TRANSMIT;
2036                                         return;
2037                                 }
2038                         } else {
2039                                 if (!(info->signals & SerialSignal_CTS))
2040                                         info->port.tty->hw_stopped = 1;
2041                         }
2042                 }
2043         }
2044 }
2045
2046 static void dcd_change(struct slgt_info *info, unsigned short status)
2047 {
2048         if (status & BIT1) {
2049                 info->signals |= SerialSignal_DCD;
2050                 info->input_signal_events.dcd_up++;
2051         } else {
2052                 info->signals &= ~SerialSignal_DCD;
2053                 info->input_signal_events.dcd_down++;
2054         }
2055         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2056         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2057                 slgt_irq_off(info, IRQ_DCD);
2058                 return;
2059         }
2060         info->icount.dcd++;
2061 #if SYNCLINK_GENERIC_HDLC
2062         if (info->netcount) {
2063                 if (info->signals & SerialSignal_DCD)
2064                         netif_carrier_on(info->netdev);
2065                 else
2066                         netif_carrier_off(info->netdev);
2067         }
2068 #endif
2069         wake_up_interruptible(&info->status_event_wait_q);
2070         wake_up_interruptible(&info->event_wait_q);
2071         info->pending_bh |= BH_STATUS;
2072
2073         if (info->port.flags & ASYNC_CHECK_CD) {
2074                 if (info->signals & SerialSignal_DCD)
2075                         wake_up_interruptible(&info->port.open_wait);
2076                 else {
2077                         if (info->port.tty)
2078                                 tty_hangup(info->port.tty);
2079                 }
2080         }
2081 }
2082
2083 static void ri_change(struct slgt_info *info, unsigned short status)
2084 {
2085         if (status & BIT0) {
2086                 info->signals |= SerialSignal_RI;
2087                 info->input_signal_events.ri_up++;
2088         } else {
2089                 info->signals &= ~SerialSignal_RI;
2090                 info->input_signal_events.ri_down++;
2091         }
2092         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2093         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2094                 slgt_irq_off(info, IRQ_RI);
2095                 return;
2096         }
2097         info->icount.rng++;
2098         wake_up_interruptible(&info->status_event_wait_q);
2099         wake_up_interruptible(&info->event_wait_q);
2100         info->pending_bh |= BH_STATUS;
2101 }
2102
2103 static void isr_rxdata(struct slgt_info *info)
2104 {
2105         unsigned int count = info->rbuf_fill_count;
2106         unsigned int i = info->rbuf_fill_index;
2107         unsigned short reg;
2108
2109         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2110                 reg = rd_reg16(info, RDR);
2111                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2112                 if (desc_complete(info->rbufs[i])) {
2113                         /* all buffers full */
2114                         rx_stop(info);
2115                         info->rx_restart = 1;
2116                         continue;
2117                 }
2118                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2119                 /* async mode saves status byte to buffer for each data byte */
2120                 if (info->params.mode == MGSL_MODE_ASYNC)
2121                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2122                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2123                         /* buffer full or end of frame */
2124                         set_desc_count(info->rbufs[i], count);
2125                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2126                         info->rbuf_fill_count = count = 0;
2127                         if (++i == info->rbuf_count)
2128                                 i = 0;
2129                         info->pending_bh |= BH_RECEIVE;
2130                 }
2131         }
2132
2133         info->rbuf_fill_index = i;
2134         info->rbuf_fill_count = count;
2135 }
2136
2137 static void isr_serial(struct slgt_info *info)
2138 {
2139         unsigned short status = rd_reg16(info, SSR);
2140
2141         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2142
2143         wr_reg16(info, SSR, status); /* clear pending */
2144
2145         info->irq_occurred = true;
2146
2147         if (info->params.mode == MGSL_MODE_ASYNC) {
2148                 if (status & IRQ_TXIDLE) {
2149                         if (info->tx_active)
2150                                 isr_txeom(info, status);
2151                 }
2152                 if (info->rx_pio && (status & IRQ_RXDATA))
2153                         isr_rxdata(info);
2154                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2155                         info->icount.brk++;
2156                         /* process break detection if tty control allows */
2157                         if (info->port.tty) {
2158                                 if (!(status & info->ignore_status_mask)) {
2159                                         if (info->read_status_mask & MASK_BREAK) {
2160                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2161                                                 if (info->port.flags & ASYNC_SAK)
2162                                                         do_SAK(info->port.tty);
2163                                         }
2164                                 }
2165                         }
2166                 }
2167         } else {
2168                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2169                         isr_txeom(info, status);
2170                 if (info->rx_pio && (status & IRQ_RXDATA))
2171                         isr_rxdata(info);
2172                 if (status & IRQ_RXIDLE) {
2173                         if (status & RXIDLE)
2174                                 info->icount.rxidle++;
2175                         else
2176                                 info->icount.exithunt++;
2177                         wake_up_interruptible(&info->event_wait_q);
2178                 }
2179
2180                 if (status & IRQ_RXOVER)
2181                         rx_start(info);
2182         }
2183
2184         if (status & IRQ_DSR)
2185                 dsr_change(info, status);
2186         if (status & IRQ_CTS)
2187                 cts_change(info, status);
2188         if (status & IRQ_DCD)
2189                 dcd_change(info, status);
2190         if (status & IRQ_RI)
2191                 ri_change(info, status);
2192 }
2193
2194 static void isr_rdma(struct slgt_info *info)
2195 {
2196         unsigned int status = rd_reg32(info, RDCSR);
2197
2198         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2199
2200         /* RDCSR (rx DMA control/status)
2201          *
2202          * 31..07  reserved
2203          * 06      save status byte to DMA buffer
2204          * 05      error
2205          * 04      eol (end of list)
2206          * 03      eob (end of buffer)
2207          * 02      IRQ enable
2208          * 01      reset
2209          * 00      enable
2210          */
2211         wr_reg32(info, RDCSR, status);  /* clear pending */
2212
2213         if (status & (BIT5 + BIT4)) {
2214                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2215                 info->rx_restart = true;
2216         }
2217         info->pending_bh |= BH_RECEIVE;
2218 }
2219
2220 static void isr_tdma(struct slgt_info *info)
2221 {
2222         unsigned int status = rd_reg32(info, TDCSR);
2223
2224         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2225
2226         /* TDCSR (tx DMA control/status)
2227          *
2228          * 31..06  reserved
2229          * 05      error
2230          * 04      eol (end of list)
2231          * 03      eob (end of buffer)
2232          * 02      IRQ enable
2233          * 01      reset
2234          * 00      enable
2235          */
2236         wr_reg32(info, TDCSR, status);  /* clear pending */
2237
2238         if (status & (BIT5 + BIT4 + BIT3)) {
2239                 // another transmit buffer has completed
2240                 // run bottom half to get more send data from user
2241                 info->pending_bh |= BH_TRANSMIT;
2242         }
2243 }
2244
2245 /*
2246  * return true if there are unsent tx DMA buffers, otherwise false
2247  *
2248  * if there are unsent buffers then info->tbuf_start
2249  * is set to index of first unsent buffer
2250  */
2251 static bool unsent_tbufs(struct slgt_info *info)
2252 {
2253         unsigned int i = info->tbuf_current;
2254         bool rc = false;
2255
2256         /*
2257          * search backwards from last loaded buffer (precedes tbuf_current)
2258          * for first unsent buffer (desc_count > 0)
2259          */
2260
2261         do {
2262                 if (i)
2263                         i--;
2264                 else
2265                         i = info->tbuf_count - 1;
2266                 if (!desc_count(info->tbufs[i]))
2267                         break;
2268                 info->tbuf_start = i;
2269                 rc = true;
2270         } while (i != info->tbuf_current);
2271
2272         return rc;
2273 }
2274
2275 static void isr_txeom(struct slgt_info *info, unsigned short status)
2276 {
2277         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2278
2279         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2280         tdma_reset(info);
2281         if (status & IRQ_TXUNDER) {
2282                 unsigned short val = rd_reg16(info, TCR);
2283                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2284                 wr_reg16(info, TCR, val); /* clear reset bit */
2285         }
2286
2287         if (info->tx_active) {
2288                 if (info->params.mode != MGSL_MODE_ASYNC) {
2289                         if (status & IRQ_TXUNDER)
2290                                 info->icount.txunder++;
2291                         else if (status & IRQ_TXIDLE)
2292                                 info->icount.txok++;
2293                 }
2294
2295                 if (unsent_tbufs(info)) {
2296                         tx_start(info);
2297                         update_tx_timer(info);
2298                         return;
2299                 }
2300                 info->tx_active = false;
2301
2302                 del_timer(&info->tx_timer);
2303
2304                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2305                         info->signals &= ~SerialSignal_RTS;
2306                         info->drop_rts_on_tx_done = false;
2307                         set_signals(info);
2308                 }
2309
2310 #if SYNCLINK_GENERIC_HDLC
2311                 if (info->netcount)
2312                         hdlcdev_tx_done(info);
2313                 else
2314 #endif
2315                 {
2316                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2317                                 tx_stop(info);
2318                                 return;
2319                         }
2320                         info->pending_bh |= BH_TRANSMIT;
2321                 }
2322         }
2323 }
2324
2325 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2326 {
2327         struct cond_wait *w, *prev;
2328
2329         /* wake processes waiting for specific transitions */
2330         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2331                 if (w->data & changed) {
2332                         w->data = state;
2333                         wake_up_interruptible(&w->q);
2334                         if (prev != NULL)
2335                                 prev->next = w->next;
2336                         else
2337                                 info->gpio_wait_q = w->next;
2338                 } else
2339                         prev = w;
2340         }
2341 }
2342
2343 /* interrupt service routine
2344  *
2345  *      irq     interrupt number
2346  *      dev_id  device ID supplied during interrupt registration
2347  */
2348 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2349 {
2350         struct slgt_info *info = dev_id;
2351         unsigned int gsr;
2352         unsigned int i;
2353
2354         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2355
2356         spin_lock(&info->lock);
2357
2358         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2359                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2360                 info->irq_occurred = true;
2361                 for(i=0; i < info->port_count ; i++) {
2362                         if (info->port_array[i] == NULL)
2363                                 continue;
2364                         if (gsr & (BIT8 << i))
2365                                 isr_serial(info->port_array[i]);
2366                         if (gsr & (BIT16 << (i*2)))
2367                                 isr_rdma(info->port_array[i]);
2368                         if (gsr & (BIT17 << (i*2)))
2369                                 isr_tdma(info->port_array[i]);
2370                 }
2371         }
2372
2373         if (info->gpio_present) {
2374                 unsigned int state;
2375                 unsigned int changed;
2376                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2377                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2378                         /* read latched state of GPIO signals */
2379                         state = rd_reg32(info, IOVR);
2380                         /* clear pending GPIO interrupt bits */
2381                         wr_reg32(info, IOSR, changed);
2382                         for (i=0 ; i < info->port_count ; i++) {
2383                                 if (info->port_array[i] != NULL)
2384                                         isr_gpio(info->port_array[i], changed, state);
2385                         }
2386                 }
2387         }
2388
2389         for(i=0; i < info->port_count ; i++) {
2390                 struct slgt_info *port = info->port_array[i];
2391
2392                 if (port && (port->port.count || port->netcount) &&
2393                     port->pending_bh && !port->bh_running &&
2394                     !port->bh_requested) {
2395                         DBGISR(("%s bh queued\n", port->device_name));
2396                         schedule_work(&port->task);
2397                         port->bh_requested = true;
2398                 }
2399         }
2400
2401         spin_unlock(&info->lock);
2402
2403         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2404         return IRQ_HANDLED;
2405 }
2406
2407 static int startup(struct slgt_info *info)
2408 {
2409         DBGINFO(("%s startup\n", info->device_name));
2410
2411         if (info->port.flags & ASYNC_INITIALIZED)
2412                 return 0;
2413
2414         if (!info->tx_buf) {
2415                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2416                 if (!info->tx_buf) {
2417                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2418                         return -ENOMEM;
2419                 }
2420         }
2421
2422         info->pending_bh = 0;
2423
2424         memset(&info->icount, 0, sizeof(info->icount));
2425
2426         /* program hardware for current parameters */
2427         change_params(info);
2428
2429         if (info->port.tty)
2430                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2431
2432         info->port.flags |= ASYNC_INITIALIZED;
2433
2434         return 0;
2435 }
2436
2437 /*
2438  *  called by close() and hangup() to shutdown hardware
2439  */
2440 static void shutdown(struct slgt_info *info)
2441 {
2442         unsigned long flags;
2443
2444         if (!(info->port.flags & ASYNC_INITIALIZED))
2445                 return;
2446
2447         DBGINFO(("%s shutdown\n", info->device_name));
2448
2449         /* clear status wait queue because status changes */
2450         /* can't happen after shutting down the hardware */
2451         wake_up_interruptible(&info->status_event_wait_q);
2452         wake_up_interruptible(&info->event_wait_q);
2453
2454         del_timer_sync(&info->tx_timer);
2455         del_timer_sync(&info->rx_timer);
2456
2457         kfree(info->tx_buf);
2458         info->tx_buf = NULL;
2459
2460         spin_lock_irqsave(&info->lock,flags);
2461
2462         tx_stop(info);
2463         rx_stop(info);
2464
2465         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2466
2467         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2468                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2469                 set_signals(info);
2470         }
2471
2472         flush_cond_wait(&info->gpio_wait_q);
2473
2474         spin_unlock_irqrestore(&info->lock,flags);
2475
2476         if (info->port.tty)
2477                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2478
2479         info->port.flags &= ~ASYNC_INITIALIZED;
2480 }
2481
2482 static void program_hw(struct slgt_info *info)
2483 {
2484         unsigned long flags;
2485
2486         spin_lock_irqsave(&info->lock,flags);
2487
2488         rx_stop(info);
2489         tx_stop(info);
2490
2491         if (info->params.mode != MGSL_MODE_ASYNC ||
2492             info->netcount)
2493                 sync_mode(info);
2494         else
2495                 async_mode(info);
2496
2497         set_signals(info);
2498
2499         info->dcd_chkcount = 0;
2500         info->cts_chkcount = 0;
2501         info->ri_chkcount = 0;
2502         info->dsr_chkcount = 0;
2503
2504         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2505         get_signals(info);
2506
2507         if (info->netcount ||
2508             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2509                 rx_start(info);
2510
2511         spin_unlock_irqrestore(&info->lock,flags);
2512 }
2513
2514 /*
2515  * reconfigure adapter based on new parameters
2516  */
2517 static void change_params(struct slgt_info *info)
2518 {
2519         unsigned cflag;
2520         int bits_per_char;
2521
2522         if (!info->port.tty || !info->port.tty->termios)
2523                 return;
2524         DBGINFO(("%s change_params\n", info->device_name));
2525
2526         cflag = info->port.tty->termios->c_cflag;
2527
2528         /* if B0 rate (hangup) specified then negate DTR and RTS */
2529         /* otherwise assert DTR and RTS */
2530         if (cflag & CBAUD)
2531                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2532         else
2533                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2534
2535         /* byte size and parity */
2536
2537         switch (cflag & CSIZE) {
2538         case CS5: info->params.data_bits = 5; break;
2539         case CS6: info->params.data_bits = 6; break;
2540         case CS7: info->params.data_bits = 7; break;
2541         case CS8: info->params.data_bits = 8; break;
2542         default:  info->params.data_bits = 7; break;
2543         }
2544
2545         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2546
2547         if (cflag & PARENB)
2548                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2549         else
2550                 info->params.parity = ASYNC_PARITY_NONE;
2551
2552         /* calculate number of jiffies to transmit a full
2553          * FIFO (32 bytes) at specified data rate
2554          */
2555         bits_per_char = info->params.data_bits +
2556                         info->params.stop_bits + 1;
2557
2558         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2559
2560         if (info->params.data_rate) {
2561                 info->timeout = (32*HZ*bits_per_char) /
2562                                 info->params.data_rate;
2563         }
2564         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2565
2566         if (cflag & CRTSCTS)
2567                 info->port.flags |= ASYNC_CTS_FLOW;
2568         else
2569                 info->port.flags &= ~ASYNC_CTS_FLOW;
2570
2571         if (cflag & CLOCAL)
2572                 info->port.flags &= ~ASYNC_CHECK_CD;
2573         else
2574                 info->port.flags |= ASYNC_CHECK_CD;
2575
2576         /* process tty input control flags */
2577
2578         info->read_status_mask = IRQ_RXOVER;
2579         if (I_INPCK(info->port.tty))
2580                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2581         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2582                 info->read_status_mask |= MASK_BREAK;
2583         if (I_IGNPAR(info->port.tty))
2584                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2585         if (I_IGNBRK(info->port.tty)) {
2586                 info->ignore_status_mask |= MASK_BREAK;
2587                 /* If ignoring parity and break indicators, ignore
2588                  * overruns too.  (For real raw support).
2589                  */
2590                 if (I_IGNPAR(info->port.tty))
2591                         info->ignore_status_mask |= MASK_OVERRUN;
2592         }
2593
2594         program_hw(info);
2595 }
2596
2597 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2598 {
2599         DBGINFO(("%s get_stats\n",  info->device_name));
2600         if (!user_icount) {
2601                 memset(&info->icount, 0, sizeof(info->icount));
2602         } else {
2603                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2604                         return -EFAULT;
2605         }
2606         return 0;
2607 }
2608
2609 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2610 {
2611         DBGINFO(("%s get_params\n", info->device_name));
2612         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2613                 return -EFAULT;
2614         return 0;
2615 }
2616
2617 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2618 {
2619         unsigned long flags;
2620         MGSL_PARAMS tmp_params;
2621
2622         DBGINFO(("%s set_params\n", info->device_name));
2623         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2624                 return -EFAULT;
2625
2626         spin_lock_irqsave(&info->lock, flags);
2627         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2628                 info->base_clock = tmp_params.clock_speed;
2629         else
2630                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2631         spin_unlock_irqrestore(&info->lock, flags);
2632
2633         program_hw(info);
2634
2635         return 0;
2636 }
2637
2638 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2639 {
2640         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2641         if (put_user(info->idle_mode, idle_mode))
2642                 return -EFAULT;
2643         return 0;
2644 }
2645
2646 static int set_txidle(struct slgt_info *info, int idle_mode)
2647 {
2648         unsigned long flags;
2649         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2650         spin_lock_irqsave(&info->lock,flags);
2651         info->idle_mode = idle_mode;
2652         if (info->params.mode != MGSL_MODE_ASYNC)
2653                 tx_set_idle(info);
2654         spin_unlock_irqrestore(&info->lock,flags);
2655         return 0;
2656 }
2657
2658 static int tx_enable(struct slgt_info *info, int enable)
2659 {
2660         unsigned long flags;
2661         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2662         spin_lock_irqsave(&info->lock,flags);
2663         if (enable) {
2664                 if (!info->tx_enabled)
2665                         tx_start(info);
2666         } else {
2667                 if (info->tx_enabled)
2668                         tx_stop(info);
2669         }
2670         spin_unlock_irqrestore(&info->lock,flags);
2671         return 0;
2672 }
2673
2674 /*
2675  * abort transmit HDLC frame
2676  */
2677 static int tx_abort(struct slgt_info *info)
2678 {
2679         unsigned long flags;
2680         DBGINFO(("%s tx_abort\n", info->device_name));
2681         spin_lock_irqsave(&info->lock,flags);
2682         tdma_reset(info);
2683         spin_unlock_irqrestore(&info->lock,flags);
2684         return 0;
2685 }
2686
2687 static int rx_enable(struct slgt_info *info, int enable)
2688 {
2689         unsigned long flags;
2690         unsigned int rbuf_fill_level;
2691         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2692         spin_lock_irqsave(&info->lock,flags);
2693         /*
2694          * enable[31..16] = receive DMA buffer fill level
2695          * 0 = noop (leave fill level unchanged)
2696          * fill level must be multiple of 4 and <= buffer size
2697          */
2698         rbuf_fill_level = ((unsigned int)enable) >> 16;
2699         if (rbuf_fill_level) {
2700                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2701                         spin_unlock_irqrestore(&info->lock, flags);
2702                         return -EINVAL;
2703                 }
2704                 info->rbuf_fill_level = rbuf_fill_level;
2705                 if (rbuf_fill_level < 128)
2706                         info->rx_pio = 1; /* PIO mode */
2707                 else
2708                         info->rx_pio = 0; /* DMA mode */
2709                 rx_stop(info); /* restart receiver to use new fill level */
2710         }
2711
2712         /*
2713          * enable[1..0] = receiver enable command
2714          * 0 = disable
2715          * 1 = enable
2716          * 2 = enable or force hunt mode if already enabled
2717          */
2718         enable &= 3;
2719         if (enable) {
2720                 if (!info->rx_enabled)
2721                         rx_start(info);
2722                 else if (enable == 2) {
2723                         /* force hunt mode (write 1 to RCR[3]) */
2724                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2725                 }
2726         } else {
2727                 if (info->rx_enabled)
2728                         rx_stop(info);
2729         }
2730         spin_unlock_irqrestore(&info->lock,flags);
2731         return 0;
2732 }
2733
2734 /*
2735  *  wait for specified event to occur
2736  */
2737 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2738 {
2739         unsigned long flags;
2740         int s;
2741         int rc=0;
2742         struct mgsl_icount cprev, cnow;
2743         int events;
2744         int mask;
2745         struct  _input_signal_events oldsigs, newsigs;
2746         DECLARE_WAITQUEUE(wait, current);
2747
2748         if (get_user(mask, mask_ptr))
2749                 return -EFAULT;
2750
2751         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2752
2753         spin_lock_irqsave(&info->lock,flags);
2754
2755         /* return immediately if state matches requested events */
2756         get_signals(info);
2757         s = info->signals;
2758
2759         events = mask &
2760                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2761                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2762                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2763                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2764         if (events) {
2765                 spin_unlock_irqrestore(&info->lock,flags);
2766                 goto exit;
2767         }
2768
2769         /* save current irq counts */
2770         cprev = info->icount;
2771         oldsigs = info->input_signal_events;
2772
2773         /* enable hunt and idle irqs if needed */
2774         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2775                 unsigned short val = rd_reg16(info, SCR);
2776                 if (!(val & IRQ_RXIDLE))
2777                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2778         }
2779
2780         set_current_state(TASK_INTERRUPTIBLE);
2781         add_wait_queue(&info->event_wait_q, &wait);
2782
2783         spin_unlock_irqrestore(&info->lock,flags);
2784
2785         for(;;) {
2786                 schedule();
2787                 if (signal_pending(current)) {
2788                         rc = -ERESTARTSYS;
2789                         break;
2790                 }
2791
2792                 /* get current irq counts */
2793                 spin_lock_irqsave(&info->lock,flags);
2794                 cnow = info->icount;
2795                 newsigs = info->input_signal_events;
2796                 set_current_state(TASK_INTERRUPTIBLE);
2797                 spin_unlock_irqrestore(&info->lock,flags);
2798
2799                 /* if no change, wait aborted for some reason */
2800                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2801                     newsigs.dsr_down == oldsigs.dsr_down &&
2802                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2803                     newsigs.dcd_down == oldsigs.dcd_down &&
2804                     newsigs.cts_up   == oldsigs.cts_up   &&
2805                     newsigs.cts_down == oldsigs.cts_down &&
2806                     newsigs.ri_up    == oldsigs.ri_up    &&
2807                     newsigs.ri_down  == oldsigs.ri_down  &&
2808                     cnow.exithunt    == cprev.exithunt   &&
2809                     cnow.rxidle      == cprev.rxidle) {
2810                         rc = -EIO;
2811                         break;
2812                 }
2813
2814                 events = mask &
2815                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2816                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2817                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2818                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2819                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2820                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2821                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2822                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2823                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2824                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2825                 if (events)
2826                         break;
2827
2828                 cprev = cnow;
2829                 oldsigs = newsigs;
2830         }
2831
2832         remove_wait_queue(&info->event_wait_q, &wait);
2833         set_current_state(TASK_RUNNING);
2834
2835
2836         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2837                 spin_lock_irqsave(&info->lock,flags);
2838                 if (!waitqueue_active(&info->event_wait_q)) {
2839                         /* disable enable exit hunt mode/idle rcvd IRQs */
2840                         wr_reg16(info, SCR,
2841                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2842                 }
2843                 spin_unlock_irqrestore(&info->lock,flags);
2844         }
2845 exit:
2846         if (rc == 0)
2847                 rc = put_user(events, mask_ptr);
2848         return rc;
2849 }
2850
2851 static int get_interface(struct slgt_info *info, int __user *if_mode)
2852 {
2853         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2854         if (put_user(info->if_mode, if_mode))
2855                 return -EFAULT;
2856         return 0;
2857 }
2858
2859 static int set_interface(struct slgt_info *info, int if_mode)
2860 {
2861         unsigned long flags;
2862         unsigned short val;
2863
2864         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2865         spin_lock_irqsave(&info->lock,flags);
2866         info->if_mode = if_mode;
2867
2868         msc_set_vcr(info);
2869
2870         /* TCR (tx control) 07  1=RTS driver control */
2871         val = rd_reg16(info, TCR);
2872         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2873                 val |= BIT7;
2874         else
2875                 val &= ~BIT7;
2876         wr_reg16(info, TCR, val);
2877
2878         spin_unlock_irqrestore(&info->lock,flags);
2879         return 0;
2880 }
2881
2882 /*
2883  * set general purpose IO pin state and direction
2884  *
2885  * user_gpio fields:
2886  * state   each bit indicates a pin state
2887  * smask   set bit indicates pin state to set
2888  * dir     each bit indicates a pin direction (0=input, 1=output)
2889  * dmask   set bit indicates pin direction to set
2890  */
2891 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2892 {
2893         unsigned long flags;
2894         struct gpio_desc gpio;
2895         __u32 data;
2896
2897         if (!info->gpio_present)
2898                 return -EINVAL;
2899         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2900                 return -EFAULT;
2901         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2902                  info->device_name, gpio.state, gpio.smask,
2903                  gpio.dir, gpio.dmask));
2904
2905         spin_lock_irqsave(&info->lock,flags);
2906         if (gpio.dmask) {
2907                 data = rd_reg32(info, IODR);
2908                 data |= gpio.dmask & gpio.dir;
2909                 data &= ~(gpio.dmask & ~gpio.dir);
2910                 wr_reg32(info, IODR, data);
2911         }
2912         if (gpio.smask) {
2913                 data = rd_reg32(info, IOVR);
2914                 data |= gpio.smask & gpio.state;
2915                 data &= ~(gpio.smask & ~gpio.state);
2916                 wr_reg32(info, IOVR, data);
2917         }
2918         spin_unlock_irqrestore(&info->lock,flags);
2919
2920         return 0;
2921 }
2922
2923 /*
2924  * get general purpose IO pin state and direction
2925  */
2926 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2927 {
2928         struct gpio_desc gpio;
2929         if (!info->gpio_present)
2930                 return -EINVAL;
2931         gpio.state = rd_reg32(info, IOVR);
2932         gpio.smask = 0xffffffff;
2933         gpio.dir   = rd_reg32(info, IODR);
2934         gpio.dmask = 0xffffffff;
2935         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2936                 return -EFAULT;
2937         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2938                  info->device_name, gpio.state, gpio.dir));
2939         return 0;
2940 }
2941
2942 /*
2943  * conditional wait facility
2944  */
2945 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2946 {
2947         init_waitqueue_head(&w->q);
2948         init_waitqueue_entry(&w->wait, current);
2949         w->data = data;
2950 }
2951
2952 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2953 {
2954         set_current_state(TASK_INTERRUPTIBLE);
2955         add_wait_queue(&w->q, &w->wait);
2956         w->next = *head;
2957         *head = w;
2958 }
2959
2960 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2961 {
2962         struct cond_wait *w, *prev;
2963         remove_wait_queue(&cw->q, &cw->wait);
2964         set_current_state(TASK_RUNNING);
2965         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2966                 if (w == cw) {
2967                         if (prev != NULL)
2968                                 prev->next = w->next;
2969                         else
2970                                 *head = w->next;
2971                         break;
2972                 }
2973         }
2974 }
2975
2976 static void flush_cond_wait(struct cond_wait **head)
2977 {
2978         while (*head != NULL) {
2979                 wake_up_interruptible(&(*head)->q);
2980                 *head = (*head)->next;
2981         }
2982 }
2983
2984 /*
2985  * wait for general purpose I/O pin(s) to enter specified state
2986  *
2987  * user_gpio fields:
2988  * state - bit indicates target pin state
2989  * smask - set bit indicates watched pin
2990  *
2991  * The wait ends when at least one watched pin enters the specified
2992  * state. When 0 (no error) is returned, user_gpio->state is set to the
2993  * state of all GPIO pins when the wait ends.
2994  *
2995  * Note: Each pin may be a dedicated input, dedicated output, or
2996  * configurable input/output. The number and configuration of pins
2997  * varies with the specific adapter model. Only input pins (dedicated
2998  * or configured) can be monitored with this function.
2999  */
3000 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3001 {
3002         unsigned long flags;
3003         int rc = 0;
3004         struct gpio_desc gpio;
3005         struct cond_wait wait;
3006         u32 state;
3007
3008         if (!info->gpio_present)
3009                 return -EINVAL;
3010         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3011                 return -EFAULT;
3012         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3013                  info->device_name, gpio.state, gpio.smask));
3014         /* ignore output pins identified by set IODR bit */
3015         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3016                 return -EINVAL;
3017         init_cond_wait(&wait, gpio.smask);
3018
3019         spin_lock_irqsave(&info->lock, flags);
3020         /* enable interrupts for watched pins */
3021         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3022         /* get current pin states */
3023         state = rd_reg32(info, IOVR);
3024
3025         if (gpio.smask & ~(state ^ gpio.state)) {
3026                 /* already in target state */
3027                 gpio.state = state;
3028         } else {
3029                 /* wait for target state */
3030                 add_cond_wait(&info->gpio_wait_q, &wait);
3031                 spin_unlock_irqrestore(&info->lock, flags);
3032                 schedule();
3033                 if (signal_pending(current))
3034                         rc = -ERESTARTSYS;
3035                 else
3036                         gpio.state = wait.data;
3037                 spin_lock_irqsave(&info->lock, flags);
3038                 remove_cond_wait(&info->gpio_wait_q, &wait);
3039         }
3040
3041         /* disable all GPIO interrupts if no waiting processes */
3042         if (info->gpio_wait_q == NULL)
3043                 wr_reg32(info, IOER, 0);
3044         spin_unlock_irqrestore(&info->lock,flags);
3045
3046         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3047                 rc = -EFAULT;
3048         return rc;
3049 }
3050
3051 static int modem_input_wait(struct slgt_info *info,int arg)
3052 {
3053         unsigned long flags;
3054         int rc;
3055         struct mgsl_icount cprev, cnow;
3056         DECLARE_WAITQUEUE(wait, current);
3057
3058         /* save current irq counts */
3059         spin_lock_irqsave(&info->lock,flags);
3060         cprev = info->icount;
3061         add_wait_queue(&info->status_event_wait_q, &wait);
3062         set_current_state(TASK_INTERRUPTIBLE);
3063         spin_unlock_irqrestore(&info->lock,flags);
3064
3065         for(;;) {
3066                 schedule();
3067                 if (signal_pending(current)) {
3068                         rc = -ERESTARTSYS;
3069                         break;
3070                 }
3071
3072                 /* get new irq counts */
3073                 spin_lock_irqsave(&info->lock,flags);
3074                 cnow = info->icount;
3075                 set_current_state(TASK_INTERRUPTIBLE);
3076                 spin_unlock_irqrestore(&info->lock,flags);
3077
3078                 /* if no change, wait aborted for some reason */
3079                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3080                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3081                         rc = -EIO;
3082                         break;
3083                 }
3084
3085                 /* check for change in caller specified modem input */
3086                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3087                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3088                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3089                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3090                         rc = 0;
3091                         break;
3092                 }
3093
3094                 cprev = cnow;
3095         }
3096         remove_wait_queue(&info->status_event_wait_q, &wait);
3097         set_current_state(TASK_RUNNING);
3098         return rc;
3099 }
3100
3101 /*
3102  *  return state of serial control and status signals
3103  */
3104 static int tiocmget(struct tty_struct *tty, struct file *file)
3105 {
3106         struct slgt_info *info = tty->driver_data;
3107         unsigned int result;
3108         unsigned long flags;
3109
3110         spin_lock_irqsave(&info->lock,flags);
3111         get_signals(info);
3112         spin_unlock_irqrestore(&info->lock,flags);
3113
3114         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3115                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3116                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3117                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3118                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3119                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3120
3121         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3122         return result;
3123 }
3124
3125 /*
3126  * set modem control signals (DTR/RTS)
3127  *
3128  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3129  *              TIOCMSET = set/clear signal values
3130  *      value   bit mask for command
3131  */
3132 static int tiocmset(struct tty_struct *tty, struct file *file,
3133                     unsigned int set, unsigned int clear)
3134 {
3135         struct slgt_info *info = tty->driver_data;
3136         unsigned long flags;
3137
3138         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3139
3140         if (set & TIOCM_RTS)
3141                 info->signals |= SerialSignal_RTS;
3142         if (set & TIOCM_DTR)
3143                 info->signals |= SerialSignal_DTR;
3144         if (clear & TIOCM_RTS)
3145                 info->signals &= ~SerialSignal_RTS;
3146         if (clear & TIOCM_DTR)
3147                 info->signals &= ~SerialSignal_DTR;
3148
3149         spin_lock_irqsave(&info->lock,flags);
3150         set_signals(info);
3151         spin_unlock_irqrestore(&info->lock,flags);
3152         return 0;
3153 }
3154
3155 static int carrier_raised(struct tty_port *port)
3156 {
3157         unsigned long flags;
3158         struct slgt_info *info = container_of(port, struct slgt_info, port);
3159
3160         spin_lock_irqsave(&info->lock,flags);
3161         get_signals(info);
3162         spin_unlock_irqrestore(&info->lock,flags);
3163         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3164 }
3165
3166 static void dtr_rts(struct tty_port *port, int on)
3167 {
3168         unsigned long flags;
3169         struct slgt_info *info = container_of(port, struct slgt_info, port);
3170
3171         spin_lock_irqsave(&info->lock,flags);
3172         if (on)
3173                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3174         else
3175                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3176         set_signals(info);
3177         spin_unlock_irqrestore(&info->lock,flags);
3178 }
3179
3180
3181 /*
3182  *  block current process until the device is ready to open
3183  */
3184 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3185                            struct slgt_info *info)
3186 {
3187         DECLARE_WAITQUEUE(wait, current);
3188         int             retval;
3189         bool            do_clocal = false;
3190         bool            extra_count = false;
3191         unsigned long   flags;
3192         int             cd;
3193         struct tty_port *port = &info->port;
3194
3195         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3196
3197         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3198                 /* nonblock mode is set or port is not enabled */
3199                 port->flags |= ASYNC_NORMAL_ACTIVE;
3200                 return 0;
3201         }
3202
3203         if (tty->termios->c_cflag & CLOCAL)
3204                 do_clocal = true;
3205
3206         /* Wait for carrier detect and the line to become
3207          * free (i.e., not in use by the callout).  While we are in
3208          * this loop, port->count is dropped by one, so that
3209          * close() knows when to free things.  We restore it upon
3210          * exit, either normal or abnormal.
3211          */
3212
3213         retval = 0;
3214         add_wait_queue(&port->open_wait, &wait);
3215
3216         spin_lock_irqsave(&info->lock, flags);
3217         if (!tty_hung_up_p(filp)) {
3218                 extra_count = true;
3219                 port->count--;
3220         }
3221         spin_unlock_irqrestore(&info->lock, flags);
3222         port->blocked_open++;
3223
3224         while (1) {
3225                 if ((tty->termios->c_cflag & CBAUD))
3226                         tty_port_raise_dtr_rts(port);
3227
3228                 set_current_state(TASK_INTERRUPTIBLE);
3229
3230                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3231                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3232                                         -EAGAIN : -ERESTARTSYS;
3233                         break;
3234                 }
3235
3236                 cd = tty_port_carrier_raised(port);
3237
3238                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3239                         break;
3240
3241                 if (signal_pending(current)) {
3242                         retval = -ERESTARTSYS;
3243                         break;
3244                 }
3245
3246                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3247                 schedule();
3248         }
3249
3250         set_current_state(TASK_RUNNING);
3251         remove_wait_queue(&port->open_wait, &wait);
3252
3253         if (extra_count)
3254                 port->count++;
3255         port->blocked_open--;
3256
3257         if (!retval)
3258                 port->flags |= ASYNC_NORMAL_ACTIVE;
3259
3260         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3261         return retval;
3262 }
3263
3264 static int alloc_tmp_rbuf(struct slgt_info *info)
3265 {
3266         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3267         if (info->tmp_rbuf == NULL)
3268                 return -ENOMEM;
3269         return 0;
3270 }
3271
3272 static void free_tmp_rbuf(struct slgt_info *info)
3273 {
3274         kfree(info->tmp_rbuf);
3275         info->tmp_rbuf = NULL;
3276 }
3277
3278 /*
3279  * allocate DMA descriptor lists.
3280  */
3281 static int alloc_desc(struct slgt_info *info)
3282 {
3283         unsigned int i;
3284         unsigned int pbufs;
3285
3286         /* allocate memory to hold descriptor lists */
3287         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3288         if (info->bufs == NULL)
3289                 return -ENOMEM;
3290
3291         memset(info->bufs, 0, DESC_LIST_SIZE);
3292
3293         info->rbufs = (struct slgt_desc*)info->bufs;
3294         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3295
3296         pbufs = (unsigned int)info->bufs_dma_addr;
3297
3298         /*
3299          * Build circular lists of descriptors
3300          */
3301
3302         for (i=0; i < info->rbuf_count; i++) {
3303                 /* physical address of this descriptor */
3304                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3305
3306                 /* physical address of next descriptor */
3307                 if (i == info->rbuf_count - 1)
3308                         info->rbufs[i].next = cpu_to_le32(pbufs);
3309                 else
3310                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3311                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3312         }
3313
3314         for (i=0; i < info->tbuf_count; i++) {
3315                 /* physical address of this descriptor */
3316                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3317
3318                 /* physical address of next descriptor */
3319                 if (i == info->tbuf_count - 1)
3320                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3321                 else
3322                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3323         }
3324
3325         return 0;
3326 }
3327
3328 static void free_desc(struct slgt_info *info)
3329 {
3330         if (info->bufs != NULL) {
3331                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3332                 info->bufs  = NULL;
3333                 info->rbufs = NULL;
3334                 info->tbufs = NULL;
3335         }
3336 }
3337
3338 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3339 {
3340         int i;
3341         for (i=0; i < count; i++) {
3342                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3343                         return -ENOMEM;
3344                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3345         }
3346         return 0;
3347 }
3348
3349 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3350 {
3351         int i;
3352         for (i=0; i < count; i++) {
3353                 if (bufs[i].buf == NULL)
3354                         continue;
3355                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3356                 bufs[i].buf = NULL;
3357         }
3358 }
3359
3360 static int alloc_dma_bufs(struct slgt_info *info)
3361 {
3362         info->rbuf_count = 32;
3363         info->tbuf_count = 32;
3364
3365         if (alloc_desc(info) < 0 ||
3366             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3367             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3368             alloc_tmp_rbuf(info) < 0) {
3369                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3370                 return -ENOMEM;
3371         }
3372         reset_rbufs(info);
3373         return 0;
3374 }
3375
3376 static void free_dma_bufs(struct slgt_info *info)
3377 {
3378         if (info->bufs) {
3379                 free_bufs(info, info->rbufs, info->rbuf_count);
3380                 free_bufs(info, info->tbufs, info->tbuf_count);
3381                 free_desc(info);
3382         }
3383         free_tmp_rbuf(info);
3384 }
3385
3386 static int claim_resources(struct slgt_info *info)
3387 {
3388         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3389                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3390                         info->device_name, info->phys_reg_addr));
3391                 info->init_error = DiagStatus_AddressConflict;
3392                 goto errout;
3393         }
3394         else
3395                 info->reg_addr_requested = true;
3396
3397         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3398         if (!info->reg_addr) {
3399                 DBGERR(("%s cant map device registers, addr=%08X\n",
3400                         info->device_name, info->phys_reg_addr));
3401                 info->init_error = DiagStatus_CantAssignPciResources;
3402                 goto errout;
3403         }
3404         return 0;
3405
3406 errout:
3407         release_resources(info);
3408         return -ENODEV;
3409 }
3410
3411 static void release_resources(struct slgt_info *info)
3412 {
3413         if (info->irq_requested) {
3414                 free_irq(info->irq_level, info);
3415                 info->irq_requested = false;
3416         }
3417
3418         if (info->reg_addr_requested) {
3419                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3420                 info->reg_addr_requested = false;
3421         }
3422
3423         if (info->reg_addr) {
3424                 iounmap(info->reg_addr);
3425                 info->reg_addr = NULL;
3426         }
3427 }
3428
3429 /* Add the specified device instance data structure to the
3430  * global linked list of devices and increment the device count.
3431  */
3432 static void add_device(struct slgt_info *info)
3433 {
3434         char *devstr;
3435
3436         info->next_device = NULL;
3437         info->line = slgt_device_count;
3438         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3439
3440         if (info->line < MAX_DEVICES) {
3441                 if (maxframe[info->line])
3442                         info->max_frame_size = maxframe[info->line];
3443         }
3444
3445         slgt_device_count++;
3446
3447         if (!slgt_device_list)
3448                 slgt_device_list = info;
3449         else {
3450                 struct slgt_info *current_dev = slgt_device_list;
3451                 while(current_dev->next_device)
3452                         current_dev = current_dev->next_device;
3453                 current_dev->next_device = info;
3454         }
3455
3456         if (info->max_frame_size < 4096)
3457                 info->max_frame_size = 4096;
3458         else if (info->max_frame_size > 65535)
3459                 info->max_frame_size = 65535;
3460
3461         switch(info->pdev->device) {
3462         case SYNCLINK_GT_DEVICE_ID:
3463                 devstr = "GT";
3464                 break;
3465         case SYNCLINK_GT2_DEVICE_ID:
3466                 devstr = "GT2";
3467                 break;
3468         case SYNCLINK_GT4_DEVICE_ID:
3469                 devstr = "GT4";
3470                 break;
3471         case SYNCLINK_AC_DEVICE_ID:
3472                 devstr = "AC";
3473                 info->params.mode = MGSL_MODE_ASYNC;
3474                 break;
3475         default:
3476                 devstr = "(unknown model)";
3477         }
3478         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3479                 devstr, info->device_name, info->phys_reg_addr,
3480                 info->irq_level, info->max_frame_size);
3481
3482 #if SYNCLINK_GENERIC_HDLC
3483         hdlcdev_init(info);
3484 #endif
3485 }
3486
3487 static const struct tty_port_operations slgt_port_ops = {
3488         .carrier_raised = carrier_raised,
3489         .dtr_rts = dtr_rts,
3490 };
3491
3492 /*
3493  *  allocate device instance structure, return NULL on failure
3494  */
3495 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3496 {
3497         struct slgt_info *info;
3498
3499         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3500
3501         if (!info) {
3502                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3503                         driver_name, adapter_num, port_num));
3504         } else {
3505                 tty_port_init(&info->port);
3506                 info->port.ops = &slgt_port_ops;
3507                 info->magic = MGSL_MAGIC;
3508                 INIT_WORK(&info->task, bh_handler);
3509                 info->max_frame_size = 4096;
3510                 info->base_clock = 14745600;
3511                 info->rbuf_fill_level = DMABUFSIZE;
3512                 info->port.close_delay = 5*HZ/10;
3513                 info->port.closing_wait = 30*HZ;
3514                 init_waitqueue_head(&info->status_event_wait_q);
3515                 init_waitqueue_head(&info->event_wait_q);
3516                 spin_lock_init(&info->netlock);
3517                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3518                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3519                 info->adapter_num = adapter_num;
3520                 info->port_num = port_num;
3521
3522                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3523                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3524
3525                 /* Copy configuration info to device instance data */
3526                 info->pdev = pdev;
3527                 info->irq_level = pdev->irq;
3528                 info->phys_reg_addr = pci_resource_start(pdev,0);
3529
3530                 info->bus_type = MGSL_BUS_TYPE_PCI;
3531                 info->irq_flags = IRQF_SHARED;
3532
3533                 info->init_error = -1; /* assume error, set to 0 on successful init */
3534         }
3535
3536         return info;
3537 }
3538
3539 static void device_init(int adapter_num, struct pci_dev *pdev)
3540 {
3541         struct slgt_info *port_array[SLGT_MAX_PORTS];
3542         int i;
3543         int port_count = 1;
3544
3545         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3546                 port_count = 2;
3547         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3548                 port_count = 4;
3549
3550         /* allocate device instances for all ports */
3551         for (i=0; i < port_count; ++i) {
3552                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3553                 if (port_array[i] == NULL) {
3554                         for (--i; i >= 0; --i)
3555                                 kfree(port_array[i]);
3556                         return;
3557                 }
3558         }
3559
3560         /* give copy of port_array to all ports and add to device list  */
3561         for (i=0; i < port_count; ++i) {
3562                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3563                 add_device(port_array[i]);
3564                 port_array[i]->port_count = port_count;
3565                 spin_lock_init(&port_array[i]->lock);
3566         }
3567
3568         /* Allocate and claim adapter resources */
3569         if (!claim_resources(port_array[0])) {
3570
3571                 alloc_dma_bufs(port_array[0]);
3572
3573                 /* copy resource information from first port to others */
3574                 for (i = 1; i < port_count; ++i) {
3575                         port_array[i]->lock      = port_array[0]->lock;
3576                         port_array[i]->irq_level = port_array[0]->irq_level;
3577                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3578                         alloc_dma_bufs(port_array[i]);
3579                 }
3580
3581                 if (request_irq(port_array[0]->irq_level,
3582                                         slgt_interrupt,
3583                                         port_array[0]->irq_flags,
3584                                         port_array[0]->device_name,
3585                                         port_array[0]) < 0) {
3586                         DBGERR(("%s request_irq failed IRQ=%d\n",
3587                                 port_array[0]->device_name,
3588                                 port_array[0]->irq_level));
3589                 } else {
3590                         port_array[0]->irq_requested = true;
3591                         adapter_test(port_array[0]);
3592                         for (i=1 ; i < port_count ; i++) {
3593                                 port_array[i]->init_error = port_array[0]->init_error;
3594                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3595                         }
3596                 }
3597         }
3598
3599         for (i=0; i < port_count; ++i)
3600                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3601 }
3602
3603 static int __devinit init_one(struct pci_dev *dev,
3604                               const struct pci_device_id *ent)
3605 {
3606         if (pci_enable_device(dev)) {
3607                 printk("error enabling pci device %p\n", dev);
3608                 return -EIO;
3609         }
3610         pci_set_master(dev);
3611         device_init(slgt_device_count, dev);
3612         return 0;
3613 }
3614
3615 static void __devexit remove_one(struct pci_dev *dev)
3616 {
3617 }
3618
3619 static const struct tty_operations ops = {
3620         .open = open,
3621         .close = close,
3622         .write = write,
3623         .put_char = put_char,
3624         .flush_chars = flush_chars,
3625         .write_room = write_room,
3626         .chars_in_buffer = chars_in_buffer,
3627         .flush_buffer = flush_buffer,
3628         .ioctl = ioctl,
3629         .compat_ioctl = slgt_compat_ioctl,
3630         .throttle = throttle,
3631         .unthrottle = unthrottle,
3632         .send_xchar = send_xchar,
3633         .break_ctl = set_break,
3634         .wait_until_sent = wait_until_sent,
3635         .set_termios = set_termios,
3636         .stop = tx_hold,
3637         .start = tx_release,
3638         .hangup = hangup,
3639         .tiocmget = tiocmget,
3640         .tiocmset = tiocmset,
3641         .proc_fops = &synclink_gt_proc_fops,
3642 };
3643
3644 static void slgt_cleanup(void)
3645 {
3646         int rc;
3647         struct slgt_info *info;
3648         struct slgt_info *tmp;
3649
3650         printk(KERN_INFO "unload %s\n", driver_name);
3651
3652         if (serial_driver) {
3653                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3654                         tty_unregister_device(serial_driver, info->line);
3655                 if ((rc = tty_unregister_driver(serial_driver)))
3656                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3657                 put_tty_driver(serial_driver);
3658         }
3659
3660         /* reset devices */
3661         info = slgt_device_list;
3662         while(info) {
3663                 reset_port(info);
3664                 info = info->next_device;
3665         }
3666
3667         /* release devices */
3668         info = slgt_device_list;
3669         while(info) {
3670 #if SYNCLINK_GENERIC_HDLC
3671                 hdlcdev_exit(info);
3672 #endif
3673                 free_dma_bufs(info);
3674                 free_tmp_rbuf(info);
3675                 if (info->port_num == 0)
3676                         release_resources(info);
3677                 tmp = info;
3678                 info = info->next_device;
3679                 kfree(tmp);
3680         }
3681
3682         if (pci_registered)
3683                 pci_unregister_driver(&pci_driver);
3684 }
3685
3686 /*
3687  *  Driver initialization entry point.
3688  */
3689 static int __init slgt_init(void)
3690 {
3691         int rc;
3692
3693         printk(KERN_INFO "%s\n", driver_name);
3694
3695         serial_driver = alloc_tty_driver(MAX_DEVICES);
3696         if (!serial_driver) {
3697                 printk("%s can't allocate tty driver\n", driver_name);
3698                 return -ENOMEM;
3699         }
3700
3701         /* Initialize the tty_driver structure */
3702
3703         serial_driver->owner = THIS_MODULE;
3704         serial_driver->driver_name = tty_driver_name;
3705         serial_driver->name = tty_dev_prefix;
3706         serial_driver->major = ttymajor;
3707         serial_driver->minor_start = 64;
3708         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3709         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3710         serial_driver->init_termios = tty_std_termios;
3711         serial_driver->init_termios.c_cflag =
3712                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3713         serial_driver->init_termios.c_ispeed = 9600;
3714         serial_driver->init_termios.c_ospeed = 9600;
3715         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3716         tty_set_operations(serial_driver, &ops);
3717         if ((rc = tty_register_driver(serial_driver)) < 0) {
3718                 DBGERR(("%s can't register serial driver\n", driver_name));
3719                 put_tty_driver(serial_driver);
3720                 serial_driver = NULL;
3721                 goto error;
3722         }
3723
3724         printk(KERN_INFO "%s, tty major#%d\n",
3725                driver_name, serial_driver->major);
3726
3727         slgt_device_count = 0;
3728         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3729                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3730                 goto error;
3731         }
3732         pci_registered = true;
3733
3734         if (!slgt_device_list)
3735                 printk("%s no devices found\n",driver_name);
3736
3737         return 0;
3738
3739 error:
3740         slgt_cleanup();
3741         return rc;
3742 }
3743
3744 static void __exit slgt_exit(void)
3745 {
3746         slgt_cleanup();
3747 }
3748
3749 module_init(slgt_init);
3750 module_exit(slgt_exit);
3751
3752 /*
3753  * register access routines
3754  */
3755
3756 #define CALC_REGADDR() \
3757         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3758         if (addr >= 0x80) \
3759                 reg_addr += (info->port_num) * 32;
3760
3761 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3762 {
3763         CALC_REGADDR();
3764         return readb((void __iomem *)reg_addr);
3765 }
3766
3767 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3768 {
3769         CALC_REGADDR();
3770         writeb(value, (void __iomem *)reg_addr);
3771 }
3772
3773 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3774 {
3775         CALC_REGADDR();
3776         return readw((void __iomem *)reg_addr);
3777 }
3778
3779 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3780 {
3781         CALC_REGADDR();
3782         writew(value, (void __iomem *)reg_addr);
3783 }
3784
3785 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3786 {
3787         CALC_REGADDR();
3788         return readl((void __iomem *)reg_addr);
3789 }
3790
3791 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3792 {
3793         CALC_REGADDR();
3794         writel(value, (void __iomem *)reg_addr);
3795 }
3796
3797 static void rdma_reset(struct slgt_info *info)
3798 {
3799         unsigned int i;
3800
3801         /* set reset bit */
3802         wr_reg32(info, RDCSR, BIT1);
3803
3804         /* wait for enable bit cleared */
3805         for(i=0 ; i < 1000 ; i++)
3806                 if (!(rd_reg32(info, RDCSR) & BIT0))
3807                         break;
3808 }
3809
3810 static void tdma_reset(struct slgt_info *info)
3811 {
3812         unsigned int i;
3813
3814         /* set reset bit */
3815         wr_reg32(info, TDCSR, BIT1);
3816
3817         /* wait for enable bit cleared */
3818         for(i=0 ; i < 1000 ; i++)
3819                 if (!(rd_reg32(info, TDCSR) & BIT0))
3820                         break;
3821 }
3822
3823 /*
3824  * enable internal loopback
3825  * TxCLK and RxCLK are generated from BRG
3826  * and TxD is looped back to RxD internally.
3827  */
3828 static void enable_loopback(struct slgt_info *info)
3829 {
3830         /* SCR (serial control) BIT2=looopback enable */
3831         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3832
3833         if (info->params.mode != MGSL_MODE_ASYNC) {
3834                 /* CCR (clock control)
3835                  * 07..05  tx clock source (010 = BRG)
3836                  * 04..02  rx clock source (010 = BRG)
3837                  * 01      auxclk enable   (0 = disable)
3838                  * 00      BRG enable      (1 = enable)
3839                  *
3840                  * 0100 1001
3841                  */
3842                 wr_reg8(info, CCR, 0x49);
3843
3844                 /* set speed if available, otherwise use default */
3845                 if (info->params.clock_speed)
3846                         set_rate(info, info->params.clock_speed);
3847                 else
3848                         set_rate(info, 3686400);
3849         }
3850 }
3851
3852 /*
3853  *  set baud rate generator to specified rate
3854  */
3855 static void set_rate(struct slgt_info *info, u32 rate)
3856 {
3857         unsigned int div;
3858         unsigned int osc = info->base_clock;
3859
3860         /* div = osc/rate - 1
3861          *
3862          * Round div up if osc/rate is not integer to
3863          * force to next slowest rate.
3864          */
3865
3866         if (rate) {
3867                 div = osc/rate;
3868                 if (!(osc % rate) && div)
3869                         div--;
3870                 wr_reg16(info, BDR, (unsigned short)div);
3871         }
3872 }
3873
3874 static void rx_stop(struct slgt_info *info)
3875 {
3876         unsigned short val;
3877
3878         /* disable and reset receiver */
3879         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3880         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3881         wr_reg16(info, RCR, val);                  /* clear reset bit */
3882
3883         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3884
3885         /* clear pending rx interrupts */
3886         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3887
3888         rdma_reset(info);
3889
3890         info->rx_enabled = false;
3891         info->rx_restart = false;
3892 }
3893
3894 static void rx_start(struct slgt_info *info)
3895 {
3896         unsigned short val;
3897
3898         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3899
3900         /* clear pending rx overrun IRQ */
3901         wr_reg16(info, SSR, IRQ_RXOVER);
3902
3903         /* reset and disable receiver */
3904         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3905         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3906         wr_reg16(info, RCR, val);                  /* clear reset bit */
3907
3908         rdma_reset(info);
3909         reset_rbufs(info);
3910
3911         if (info->rx_pio) {
3912                 /* rx request when rx FIFO not empty */
3913                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3914                 slgt_irq_on(info, IRQ_RXDATA);
3915                 if (info->params.mode == MGSL_MODE_ASYNC) {
3916                         /* enable saving of rx status */
3917                         wr_reg32(info, RDCSR, BIT6);
3918                 }
3919         } else {
3920                 /* rx request when rx FIFO half full */
3921                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3922                 /* set 1st descriptor address */
3923                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3924
3925                 if (info->params.mode != MGSL_MODE_ASYNC) {
3926                         /* enable rx DMA and DMA interrupt */
3927                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3928                 } else {
3929                         /* enable saving of rx status, rx DMA and DMA interrupt */
3930                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3931                 }
3932         }
3933
3934         slgt_irq_on(info, IRQ_RXOVER);
3935
3936         /* enable receiver */
3937         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3938
3939         info->rx_restart = false;
3940         info->rx_enabled = true;
3941 }
3942
3943 static void tx_start(struct slgt_info *info)
3944 {
3945         if (!info->tx_enabled) {
3946                 wr_reg16(info, TCR,
3947                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3948                 info->tx_enabled = true;
3949         }
3950
3951         if (desc_count(info->tbufs[info->tbuf_start])) {
3952                 info->drop_rts_on_tx_done = false;
3953
3954                 if (info->params.mode != MGSL_MODE_ASYNC) {
3955                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3956                                 get_signals(info);
3957                                 if (!(info->signals & SerialSignal_RTS)) {
3958                                         info->signals |= SerialSignal_RTS;
3959                                         set_signals(info);
3960                                         info->drop_rts_on_tx_done = true;
3961                                 }
3962                         }
3963
3964                         slgt_irq_off(info, IRQ_TXDATA);
3965                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3966                         /* clear tx idle and underrun status bits */
3967                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3968                 } else {
3969                         slgt_irq_off(info, IRQ_TXDATA);
3970                         slgt_irq_on(info, IRQ_TXIDLE);
3971                         /* clear tx idle status bit */
3972                         wr_reg16(info, SSR, IRQ_TXIDLE);
3973                 }
3974                 /* set 1st descriptor address and start DMA */
3975                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3976                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3977                 info->tx_active = true;
3978         }
3979 }
3980
3981 static void tx_stop(struct slgt_info *info)
3982 {
3983         unsigned short val;
3984
3985         del_timer(&info->tx_timer);
3986
3987         tdma_reset(info);
3988
3989         /* reset and disable transmitter */
3990         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3991         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3992
3993         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3994
3995         /* clear tx idle and underrun status bit */
3996         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3997
3998         reset_tbufs(info);
3999
4000         info->tx_enabled = false;
4001         info->tx_active = false;
4002 }
4003
4004 static void reset_port(struct slgt_info *info)
4005 {
4006         if (!info->reg_addr)
4007                 return;
4008
4009         tx_stop(info);
4010         rx_stop(info);
4011
4012         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4013         set_signals(info);
4014
4015         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4016 }
4017
4018 static void reset_adapter(struct slgt_info *info)
4019 {
4020         int i;
4021         for (i=0; i < info->port_count; ++i) {
4022                 if (info->port_array[i])
4023                         reset_port(info->port_array[i]);
4024         }
4025 }
4026
4027 static void async_mode(struct slgt_info *info)
4028 {
4029         unsigned short val;
4030
4031         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4032         tx_stop(info);
4033         rx_stop(info);
4034
4035         /* TCR (tx control)
4036          *
4037          * 15..13  mode, 010=async
4038          * 12..10  encoding, 000=NRZ
4039          * 09      parity enable
4040          * 08      1=odd parity, 0=even parity
4041          * 07      1=RTS driver control
4042          * 06      1=break enable
4043          * 05..04  character length
4044          *         00=5 bits
4045          *         01=6 bits
4046          *         10=7 bits
4047          *         11=8 bits
4048          * 03      0=1 stop bit, 1=2 stop bits
4049          * 02      reset
4050          * 01      enable
4051          * 00      auto-CTS enable
4052          */
4053         val = 0x4000;
4054
4055         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4056                 val |= BIT7;
4057
4058         if (info->params.parity != ASYNC_PARITY_NONE) {
4059                 val |= BIT9;
4060                 if (info->params.parity == ASYNC_PARITY_ODD)
4061                         val |= BIT8;
4062         }
4063
4064         switch (info->params.data_bits)
4065         {
4066         case 6: val |= BIT4; break;
4067         case 7: val |= BIT5; break;
4068         case 8: val |= BIT5 + BIT4; break;
4069         }
4070
4071         if (info->params.stop_bits != 1)
4072                 val |= BIT3;
4073
4074         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4075                 val |= BIT0;
4076
4077         wr_reg16(info, TCR, val);
4078
4079         /* RCR (rx control)
4080          *
4081          * 15..13  mode, 010=async
4082          * 12..10  encoding, 000=NRZ
4083          * 09      parity enable
4084          * 08      1=odd parity, 0=even parity
4085          * 07..06  reserved, must be 0
4086          * 05..04  character length
4087          *         00=5 bits
4088          *         01=6 bits
4089          *         10=7 bits
4090          *         11=8 bits
4091          * 03      reserved, must be zero
4092          * 02      reset
4093          * 01      enable
4094          * 00      auto-DCD enable
4095          */
4096         val = 0x4000;
4097
4098         if (info->params.parity != ASYNC_PARITY_NONE) {
4099                 val |= BIT9;
4100                 if (info->params.parity == ASYNC_PARITY_ODD)
4101                         val |= BIT8;
4102         }
4103
4104         switch (info->params.data_bits)
4105         {
4106         case 6: val |= BIT4; break;
4107         case 7: val |= BIT5; break;
4108         case 8: val |= BIT5 + BIT4; break;
4109         }
4110
4111         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4112                 val |= BIT0;
4113
4114         wr_reg16(info, RCR, val);
4115
4116         /* CCR (clock control)
4117          *
4118          * 07..05  011 = tx clock source is BRG/16
4119          * 04..02  010 = rx clock source is BRG
4120          * 01      0 = auxclk disabled
4121          * 00      1 = BRG enabled
4122          *
4123          * 0110 1001
4124          */
4125         wr_reg8(info, CCR, 0x69);
4126
4127         msc_set_vcr(info);
4128
4129         /* SCR (serial control)
4130          *
4131          * 15  1=tx req on FIFO half empty
4132          * 14  1=rx req on FIFO half full
4133          * 13  tx data  IRQ enable
4134          * 12  tx idle  IRQ enable
4135          * 11  rx break on IRQ enable
4136          * 10  rx data  IRQ enable
4137          * 09  rx break off IRQ enable
4138          * 08  overrun  IRQ enable
4139          * 07  DSR      IRQ enable
4140          * 06  CTS      IRQ enable
4141          * 05  DCD      IRQ enable
4142          * 04  RI       IRQ enable
4143          * 03  0=16x sampling, 1=8x sampling
4144          * 02  1=txd->rxd internal loopback enable
4145          * 01  reserved, must be zero
4146          * 00  1=master IRQ enable
4147          */
4148         val = BIT15 + BIT14 + BIT0;
4149         /* JCR[8] : 1 = x8 async mode feature available */
4150         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4151             ((info->base_clock < (info->params.data_rate * 16)) ||
4152              (info->base_clock % (info->params.data_rate * 16)))) {
4153                 /* use 8x sampling */
4154                 val |= BIT3;
4155                 set_rate(info, info->params.data_rate * 8);
4156         } else {
4157                 /* use 16x sampling */
4158                 set_rate(info, info->params.data_rate * 16);
4159         }
4160         wr_reg16(info, SCR, val);
4161
4162         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4163
4164         if (info->params.loopback)
4165                 enable_loopback(info);
4166 }
4167
4168 static void sync_mode(struct slgt_info *info)
4169 {
4170         unsigned short val;
4171
4172         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4173         tx_stop(info);
4174         rx_stop(info);
4175
4176         /* TCR (tx control)
4177          *
4178          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4179          * 12..10  encoding
4180          * 09      CRC enable
4181          * 08      CRC32
4182          * 07      1=RTS driver control
4183          * 06      preamble enable
4184          * 05..04  preamble length
4185          * 03      share open/close flag
4186          * 02      reset
4187          * 01      enable
4188          * 00      auto-CTS enable
4189          */
4190         val = BIT2;
4191
4192         switch(info->params.mode) {
4193         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4194         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4195         case MGSL_MODE_RAW:      val |= BIT13; break;
4196         }
4197         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4198                 val |= BIT7;
4199
4200         switch(info->params.encoding)
4201         {
4202         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4203         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4204         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4205         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4206         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4207         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4208         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4209         }
4210
4211         switch (info->params.crc_type & HDLC_CRC_MASK)
4212         {
4213         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4214         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4215         }
4216
4217         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4218                 val |= BIT6;
4219
4220         switch (info->params.preamble_length)
4221         {
4222         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4223         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4224         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4225         }
4226
4227         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4228                 val |= BIT0;
4229
4230         wr_reg16(info, TCR, val);
4231
4232         /* TPR (transmit preamble) */
4233
4234         switch (info->params.preamble)
4235         {
4236         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4237         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4238         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4239         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4240         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4241         default:                          val = 0x7e; break;
4242         }
4243         wr_reg8(info, TPR, (unsigned char)val);
4244
4245         /* RCR (rx control)
4246          *
4247          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4248          * 12..10  encoding
4249          * 09      CRC enable
4250          * 08      CRC32
4251          * 07..03  reserved, must be 0
4252          * 02      reset
4253          * 01      enable
4254          * 00      auto-DCD enable
4255          */
4256         val = 0;
4257
4258         switch(info->params.mode) {
4259         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4260         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4261         case MGSL_MODE_RAW:      val |= BIT13; break;
4262         }
4263
4264         switch(info->params.encoding)
4265         {
4266         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4267         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4268         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4269         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4270         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4271         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4272         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4273         }
4274
4275         switch (info->params.crc_type & HDLC_CRC_MASK)
4276         {
4277         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4278         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4279         }
4280
4281         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4282                 val |= BIT0;
4283
4284         wr_reg16(info, RCR, val);
4285
4286         /* CCR (clock control)
4287          *
4288          * 07..05  tx clock source
4289          * 04..02  rx clock source
4290          * 01      auxclk enable
4291          * 00      BRG enable
4292          */
4293         val = 0;
4294
4295         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4296         {
4297                 // when RxC source is DPLL, BRG generates 16X DPLL
4298                 // reference clock, so take TxC from BRG/16 to get
4299                 // transmit clock at actual data rate
4300                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4301                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4302                 else
4303                         val |= BIT6;    /* 010, txclk = BRG */
4304         }
4305         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4306                 val |= BIT7;    /* 100, txclk = DPLL Input */
4307         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4308                 val |= BIT5;    /* 001, txclk = RXC Input */
4309
4310         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4311                 val |= BIT3;    /* 010, rxclk = BRG */
4312         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4313                 val |= BIT4;    /* 100, rxclk = DPLL */
4314         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4315                 val |= BIT2;    /* 001, rxclk = TXC Input */
4316
4317         if (info->params.clock_speed)
4318                 val |= BIT1 + BIT0;
4319
4320         wr_reg8(info, CCR, (unsigned char)val);
4321
4322         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4323         {
4324                 // program DPLL mode
4325                 switch(info->params.encoding)
4326                 {
4327                 case HDLC_ENCODING_BIPHASE_MARK:
4328                 case HDLC_ENCODING_BIPHASE_SPACE:
4329                         val = BIT7; break;
4330                 case HDLC_ENCODING_BIPHASE_LEVEL:
4331                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4332                         val = BIT7 + BIT6; break;
4333                 default: val = BIT6;    // NRZ encodings
4334                 }
4335                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4336
4337                 // DPLL requires a 16X reference clock from BRG
4338                 set_rate(info, info->params.clock_speed * 16);
4339         }
4340         else
4341                 set_rate(info, info->params.clock_speed);
4342
4343         tx_set_idle(info);
4344
4345         msc_set_vcr(info);
4346
4347         /* SCR (serial control)
4348          *
4349          * 15  1=tx req on FIFO half empty
4350          * 14  1=rx req on FIFO half full
4351          * 13  tx data  IRQ enable
4352          * 12  tx idle  IRQ enable
4353          * 11  underrun IRQ enable
4354          * 10  rx data  IRQ enable
4355          * 09  rx idle  IRQ enable
4356          * 08  overrun  IRQ enable
4357          * 07  DSR      IRQ enable
4358          * 06  CTS      IRQ enable
4359          * 05  DCD      IRQ enable
4360          * 04  RI       IRQ enable
4361          * 03  reserved, must be zero
4362          * 02  1=txd->rxd internal loopback enable
4363          * 01  reserved, must be zero
4364          * 00  1=master IRQ enable
4365          */
4366         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4367
4368         if (info->params.loopback)
4369                 enable_loopback(info);
4370 }
4371
4372 /*
4373  *  set transmit idle mode
4374  */
4375 static void tx_set_idle(struct slgt_info *info)
4376 {
4377         unsigned char val;
4378         unsigned short tcr;
4379
4380         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4381          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4382          */
4383         tcr = rd_reg16(info, TCR);
4384         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4385                 /* disable preamble, set idle size to 16 bits */
4386                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4387                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4388                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4389         } else if (!(tcr & BIT6)) {
4390                 /* preamble is disabled, set idle size to 8 bits */
4391                 tcr &= ~(BIT5 + BIT4);
4392         }
4393         wr_reg16(info, TCR, tcr);
4394
4395         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4396                 /* LSB of custom tx idle specified in tx idle register */
4397                 val = (unsigned char)(info->idle_mode & 0xff);
4398         } else {
4399                 /* standard 8 bit idle patterns */
4400                 switch(info->idle_mode)
4401                 {
4402                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4403                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4404                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4405                 case HDLC_TXIDLE_ZEROS:
4406                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4407                 default:                         val = 0xff;
4408                 }
4409         }
4410
4411         wr_reg8(info, TIR, val);
4412 }
4413
4414 /*
4415  * get state of V24 status (input) signals
4416  */
4417 static void get_signals(struct slgt_info *info)
4418 {
4419         unsigned short status = rd_reg16(info, SSR);
4420
4421         /* clear all serial signals except DTR and RTS */
4422         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4423
4424         if (status & BIT3)
4425                 info->signals |= SerialSignal_DSR;
4426         if (status & BIT2)
4427                 info->signals |= SerialSignal_CTS;
4428         if (status & BIT1)
4429                 info->signals |= SerialSignal_DCD;
4430         if (status & BIT0)
4431                 info->signals |= SerialSignal_RI;
4432 }
4433
4434 /*
4435  * set V.24 Control Register based on current configuration
4436  */
4437 static void msc_set_vcr(struct slgt_info *info)
4438 {
4439         unsigned char val = 0;
4440
4441         /* VCR (V.24 control)
4442          *
4443          * 07..04  serial IF select
4444          * 03      DTR
4445          * 02      RTS
4446          * 01      LL
4447          * 00      RL
4448          */
4449
4450         switch(info->if_mode & MGSL_INTERFACE_MASK)
4451         {
4452         case MGSL_INTERFACE_RS232:
4453                 val |= BIT5; /* 0010 */
4454                 break;
4455         case MGSL_INTERFACE_V35:
4456                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4457                 break;
4458         case MGSL_INTERFACE_RS422:
4459                 val |= BIT6; /* 0100 */
4460                 break;
4461         }
4462
4463         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4464                 val |= BIT4;
4465         if (info->signals & SerialSignal_DTR)
4466                 val |= BIT3;
4467         if (info->signals & SerialSignal_RTS)
4468                 val |= BIT2;
4469         if (info->if_mode & MGSL_INTERFACE_LL)
4470                 val |= BIT1;
4471         if (info->if_mode & MGSL_INTERFACE_RL)
4472                 val |= BIT0;
4473         wr_reg8(info, VCR, val);
4474 }
4475
4476 /*
4477  * set state of V24 control (output) signals
4478  */
4479 static void set_signals(struct slgt_info *info)
4480 {
4481         unsigned char val = rd_reg8(info, VCR);
4482         if (info->signals & SerialSignal_DTR)
4483                 val |= BIT3;
4484         else
4485                 val &= ~BIT3;
4486         if (info->signals & SerialSignal_RTS)
4487                 val |= BIT2;
4488         else
4489                 val &= ~BIT2;
4490         wr_reg8(info, VCR, val);
4491 }
4492
4493 /*
4494  * free range of receive DMA buffers (i to last)
4495  */
4496 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4497 {
4498         int done = 0;
4499
4500         while(!done) {
4501                 /* reset current buffer for reuse */
4502                 info->rbufs[i].status = 0;
4503                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4504                 if (i == last)
4505                         done = 1;
4506                 if (++i == info->rbuf_count)
4507                         i = 0;
4508         }
4509         info->rbuf_current = i;
4510 }
4511
4512 /*
4513  * mark all receive DMA buffers as free
4514  */
4515 static void reset_rbufs(struct slgt_info *info)
4516 {
4517         free_rbufs(info, 0, info->rbuf_count - 1);
4518         info->rbuf_fill_index = 0;
4519         info->rbuf_fill_count = 0;
4520 }
4521
4522 /*
4523  * pass receive HDLC frame to upper layer
4524  *
4525  * return true if frame available, otherwise false
4526  */
4527 static bool rx_get_frame(struct slgt_info *info)
4528 {
4529         unsigned int start, end;
4530         unsigned short status;
4531         unsigned int framesize = 0;
4532         unsigned long flags;
4533         struct tty_struct *tty = info->port.tty;
4534         unsigned char addr_field = 0xff;
4535         unsigned int crc_size = 0;
4536
4537         switch (info->params.crc_type & HDLC_CRC_MASK) {
4538         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4539         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4540         }
4541
4542 check_again:
4543
4544         framesize = 0;
4545         addr_field = 0xff;
4546         start = end = info->rbuf_current;
4547
4548         for (;;) {
4549                 if (!desc_complete(info->rbufs[end]))
4550                         goto cleanup;
4551
4552                 if (framesize == 0 && info->params.addr_filter != 0xff)
4553                         addr_field = info->rbufs[end].buf[0];
4554
4555                 framesize += desc_count(info->rbufs[end]);
4556
4557                 if (desc_eof(info->rbufs[end]))
4558                         break;
4559
4560                 if (++end == info->rbuf_count)
4561                         end = 0;
4562
4563                 if (end == info->rbuf_current) {
4564                         if (info->rx_enabled){
4565                                 spin_lock_irqsave(&info->lock,flags);
4566                                 rx_start(info);
4567                                 spin_unlock_irqrestore(&info->lock,flags);
4568                         }
4569                         goto cleanup;
4570                 }
4571         }
4572
4573         /* status
4574          *
4575          * 15      buffer complete
4576          * 14..06  reserved
4577          * 05..04  residue
4578          * 02      eof (end of frame)
4579          * 01      CRC error
4580          * 00      abort
4581          */
4582         status = desc_status(info->rbufs[end]);
4583
4584         /* ignore CRC bit if not using CRC (bit is undefined) */
4585         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4586                 status &= ~BIT1;
4587
4588         if (framesize == 0 ||
4589                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4590                 free_rbufs(info, start, end);
4591                 goto check_again;
4592         }
4593
4594         if (framesize < (2 + crc_size) || status & BIT0) {
4595                 info->icount.rxshort++;
4596                 framesize = 0;
4597         } else if (status & BIT1) {
4598                 info->icount.rxcrc++;
4599                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4600                         framesize = 0;
4601         }
4602
4603 #if SYNCLINK_GENERIC_HDLC
4604         if (framesize == 0) {
4605                 info->netdev->stats.rx_errors++;
4606                 info->netdev->stats.rx_frame_errors++;
4607         }
4608 #endif
4609
4610         DBGBH(("%s rx frame status=%04X size=%d\n",
4611                 info->device_name, status, framesize));
4612         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4613
4614         if (framesize) {
4615                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4616                         framesize -= crc_size;
4617                         crc_size = 0;
4618                 }
4619
4620                 if (framesize > info->max_frame_size + crc_size)
4621                         info->icount.rxlong++;
4622                 else {
4623                         /* copy dma buffer(s) to contiguous temp buffer */
4624                         int copy_count = framesize;
4625                         int i = start;
4626                         unsigned char *p = info->tmp_rbuf;
4627                         info->tmp_rbuf_count = framesize;
4628
4629                         info->icount.rxok++;
4630
4631                         while(copy_count) {
4632                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4633                                 memcpy(p, info->rbufs[i].buf, partial_count);
4634                                 p += partial_count;
4635                                 copy_count -= partial_count;
4636                                 if (++i == info->rbuf_count)
4637                                         i = 0;
4638                         }
4639
4640                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4641                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4642                                 framesize++;
4643                         }
4644
4645 #if SYNCLINK_GENERIC_HDLC
4646                         if (info->netcount)
4647                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4648                         else
4649 #endif
4650                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4651                 }
4652         }
4653         free_rbufs(info, start, end);
4654         return true;
4655
4656 cleanup:
4657         return false;
4658 }
4659
4660 /*
4661  * pass receive buffer (RAW synchronous mode) to tty layer
4662  * return true if buffer available, otherwise false
4663  */
4664 static bool rx_get_buf(struct slgt_info *info)
4665 {
4666         unsigned int i = info->rbuf_current;
4667         unsigned int count;
4668
4669         if (!desc_complete(info->rbufs[i]))
4670                 return false;
4671         count = desc_count(info->rbufs[i]);
4672         switch(info->params.mode) {
4673         case MGSL_MODE_MONOSYNC:
4674         case MGSL_MODE_BISYNC:
4675                 /* ignore residue in byte synchronous modes */
4676                 if (desc_residue(info->rbufs[i]))
4677                         count--;
4678                 break;
4679         }
4680         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4681         DBGINFO(("rx_get_buf size=%d\n", count));
4682         if (count)
4683                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4684                                   info->flag_buf, count);
4685         free_rbufs(info, i, i);
4686         return true;
4687 }
4688
4689 static void reset_tbufs(struct slgt_info *info)
4690 {
4691         unsigned int i;
4692         info->tbuf_current = 0;
4693         for (i=0 ; i < info->tbuf_count ; i++) {
4694                 info->tbufs[i].status = 0;
4695                 info->tbufs[i].count  = 0;
4696         }
4697 }
4698
4699 /*
4700  * return number of free transmit DMA buffers
4701  */
4702 static unsigned int free_tbuf_count(struct slgt_info *info)
4703 {
4704         unsigned int count = 0;
4705         unsigned int i = info->tbuf_current;
4706
4707         do
4708         {
4709                 if (desc_count(info->tbufs[i]))
4710                         break; /* buffer in use */
4711                 ++count;
4712                 if (++i == info->tbuf_count)
4713                         i=0;
4714         } while (i != info->tbuf_current);
4715
4716         /* if tx DMA active, last zero count buffer is in use */
4717         if (count && (rd_reg32(info, TDCSR) & BIT0))
4718                 --count;
4719
4720         return count;
4721 }
4722
4723 /*
4724  * return number of bytes in unsent transmit DMA buffers
4725  * and the serial controller tx FIFO
4726  */
4727 static unsigned int tbuf_bytes(struct slgt_info *info)
4728 {
4729         unsigned int total_count = 0;
4730         unsigned int i = info->tbuf_current;
4731         unsigned int reg_value;
4732         unsigned int count;
4733         unsigned int active_buf_count = 0;
4734
4735         /*
4736          * Add descriptor counts for all tx DMA buffers.
4737          * If count is zero (cleared by DMA controller after read),
4738          * the buffer is complete or is actively being read from.
4739          *
4740          * Record buf_count of last buffer with zero count starting
4741          * from current ring position. buf_count is mirror
4742          * copy of count and is not cleared by serial controller.
4743          * If DMA controller is active, that buffer is actively
4744          * being read so add to total.
4745          */
4746         do {
4747                 count = desc_count(info->tbufs[i]);
4748                 if (count)
4749                         total_count += count;
4750                 else if (!total_count)
4751                         active_buf_count = info->tbufs[i].buf_count;
4752                 if (++i == info->tbuf_count)
4753                         i = 0;
4754         } while (i != info->tbuf_current);
4755
4756         /* read tx DMA status register */
4757         reg_value = rd_reg32(info, TDCSR);
4758
4759         /* if tx DMA active, last zero count buffer is in use */
4760         if (reg_value & BIT0)
4761                 total_count += active_buf_count;
4762
4763         /* add tx FIFO count = reg_value[15..8] */
4764         total_count += (reg_value >> 8) & 0xff;
4765
4766         /* if transmitter active add one byte for shift register */
4767         if (info->tx_active)
4768                 total_count++;
4769
4770         return total_count;
4771 }
4772
4773 /*
4774  * load data into transmit DMA buffer ring and start transmitter if needed
4775  * return true if data accepted, otherwise false (buffers full)
4776  */
4777 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4778 {
4779         unsigned short count;
4780         unsigned int i;
4781         struct slgt_desc *d;
4782
4783         /* check required buffer space */
4784         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4785                 return false;
4786
4787         DBGDATA(info, buf, size, "tx");
4788
4789         /*
4790          * copy data to one or more DMA buffers in circular ring
4791          * tbuf_start   = first buffer for this data
4792          * tbuf_current = next free buffer
4793          *
4794          * Copy all data before making data visible to DMA controller by
4795          * setting descriptor count of the first buffer.
4796          * This prevents an active DMA controller from reading the first DMA
4797          * buffers of a frame and stopping before the final buffers are filled.
4798          */
4799
4800         info->tbuf_start = i = info->tbuf_current;
4801
4802         while (size) {
4803                 d = &info->tbufs[i];
4804
4805                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4806                 memcpy(d->buf, buf, count);
4807
4808                 size -= count;
4809                 buf  += count;
4810
4811                 /*
4812                  * set EOF bit for last buffer of HDLC frame or
4813                  * for every buffer in raw mode
4814                  */
4815                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4816                     info->params.mode == MGSL_MODE_RAW)
4817                         set_desc_eof(*d, 1);
4818                 else
4819                         set_desc_eof(*d, 0);
4820
4821                 /* set descriptor count for all but first buffer */
4822                 if (i != info->tbuf_start)
4823                         set_desc_count(*d, count);
4824                 d->buf_count = count;
4825
4826                 if (++i == info->tbuf_count)
4827                         i = 0;
4828         }
4829
4830         info->tbuf_current = i;
4831
4832         /* set first buffer count to make new data visible to DMA controller */
4833         d = &info->tbufs[info->tbuf_start];
4834         set_desc_count(*d, d->buf_count);
4835
4836         /* start transmitter if needed and update transmit timeout */
4837         if (!info->tx_active)
4838                 tx_start(info);
4839         update_tx_timer(info);
4840
4841         return true;
4842 }
4843
4844 static int register_test(struct slgt_info *info)
4845 {
4846         static unsigned short patterns[] =
4847                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4848         static unsigned int count = ARRAY_SIZE(patterns);
4849         unsigned int i;
4850         int rc = 0;
4851
4852         for (i=0 ; i < count ; i++) {
4853                 wr_reg16(info, TIR, patterns[i]);
4854                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4855                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4856                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4857                         rc = -ENODEV;
4858                         break;
4859                 }
4860         }
4861         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4862         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4863         return rc;
4864 }
4865
4866 static int irq_test(struct slgt_info *info)
4867 {
4868         unsigned long timeout;
4869         unsigned long flags;
4870         struct tty_struct *oldtty = info->port.tty;
4871         u32 speed = info->params.data_rate;
4872
4873         info->params.data_rate = 921600;
4874         info->port.tty = NULL;
4875
4876         spin_lock_irqsave(&info->lock, flags);
4877         async_mode(info);
4878         slgt_irq_on(info, IRQ_TXIDLE);
4879
4880         /* enable transmitter */
4881         wr_reg16(info, TCR,
4882                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4883
4884         /* write one byte and wait for tx idle */
4885         wr_reg16(info, TDR, 0);
4886
4887         /* assume failure */
4888         info->init_error = DiagStatus_IrqFailure;
4889         info->irq_occurred = false;
4890
4891         spin_unlock_irqrestore(&info->lock, flags);
4892
4893         timeout=100;
4894         while(timeout-- && !info->irq_occurred)
4895                 msleep_interruptible(10);
4896
4897         spin_lock_irqsave(&info->lock,flags);
4898         reset_port(info);
4899         spin_unlock_irqrestore(&info->lock,flags);
4900
4901         info->params.data_rate = speed;
4902         info->port.tty = oldtty;
4903
4904         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4905         return info->irq_occurred ? 0 : -ENODEV;
4906 }
4907
4908 static int loopback_test_rx(struct slgt_info *info)
4909 {
4910         unsigned char *src, *dest;
4911         int count;
4912
4913         if (desc_complete(info->rbufs[0])) {
4914                 count = desc_count(info->rbufs[0]);
4915                 src   = info->rbufs[0].buf;
4916                 dest  = info->tmp_rbuf;
4917
4918                 for( ; count ; count-=2, src+=2) {
4919                         /* src=data byte (src+1)=status byte */
4920                         if (!(*(src+1) & (BIT9 + BIT8))) {
4921                                 *dest = *src;
4922                                 dest++;
4923                                 info->tmp_rbuf_count++;
4924                         }
4925                 }
4926                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4927                 return 1;
4928         }
4929         return 0;
4930 }
4931
4932 static int loopback_test(struct slgt_info *info)
4933 {
4934 #define TESTFRAMESIZE 20
4935
4936         unsigned long timeout;
4937         u16 count = TESTFRAMESIZE;
4938         unsigned char buf[TESTFRAMESIZE];
4939         int rc = -ENODEV;
4940         unsigned long flags;
4941
4942         struct tty_struct *oldtty = info->port.tty;
4943         MGSL_PARAMS params;
4944
4945         memcpy(&params, &info->params, sizeof(params));
4946
4947         info->params.mode = MGSL_MODE_ASYNC;
4948         info->params.data_rate = 921600;
4949         info->params.loopback = 1;
4950         info->port.tty = NULL;
4951
4952         /* build and send transmit frame */
4953         for (count = 0; count < TESTFRAMESIZE; ++count)
4954                 buf[count] = (unsigned char)count;
4955
4956         info->tmp_rbuf_count = 0;
4957         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4958
4959         /* program hardware for HDLC and enabled receiver */
4960         spin_lock_irqsave(&info->lock,flags);
4961         async_mode(info);
4962         rx_start(info);
4963         tx_load(info, buf, count);
4964         spin_unlock_irqrestore(&info->lock, flags);
4965
4966         /* wait for receive complete */
4967         for (timeout = 100; timeout; --timeout) {
4968                 msleep_interruptible(10);
4969                 if (loopback_test_rx(info)) {
4970                         rc = 0;
4971                         break;
4972                 }
4973         }
4974
4975         /* verify received frame length and contents */
4976         if (!rc && (info->tmp_rbuf_count != count ||
4977                   memcmp(buf, info->tmp_rbuf, count))) {
4978                 rc = -ENODEV;
4979         }
4980
4981         spin_lock_irqsave(&info->lock,flags);
4982         reset_adapter(info);
4983         spin_unlock_irqrestore(&info->lock,flags);
4984
4985         memcpy(&info->params, &params, sizeof(info->params));
4986         info->port.tty = oldtty;
4987
4988         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4989         return rc;
4990 }
4991
4992 static int adapter_test(struct slgt_info *info)
4993 {
4994         DBGINFO(("testing %s\n", info->device_name));
4995         if (register_test(info) < 0) {
4996                 printk("register test failure %s addr=%08X\n",
4997                         info->device_name, info->phys_reg_addr);
4998         } else if (irq_test(info) < 0) {
4999                 printk("IRQ test failure %s IRQ=%d\n",
5000                         info->device_name, info->irq_level);
5001         } else if (loopback_test(info) < 0) {
5002                 printk("loopback test failure %s\n", info->device_name);
5003         }
5004         return info->init_error;
5005 }
5006
5007 /*
5008  * transmit timeout handler
5009  */
5010 static void tx_timeout(unsigned long context)
5011 {
5012         struct slgt_info *info = (struct slgt_info*)context;
5013         unsigned long flags;
5014
5015         DBGINFO(("%s tx_timeout\n", info->device_name));
5016         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5017                 info->icount.txtimeout++;
5018         }
5019         spin_lock_irqsave(&info->lock,flags);
5020         tx_stop(info);
5021         spin_unlock_irqrestore(&info->lock,flags);
5022
5023 #if SYNCLINK_GENERIC_HDLC
5024         if (info->netcount)
5025                 hdlcdev_tx_done(info);
5026         else
5027 #endif
5028                 bh_transmit(info);
5029 }
5030
5031 /*
5032  * receive buffer polling timer
5033  */
5034 static void rx_timeout(unsigned long context)
5035 {
5036         struct slgt_info *info = (struct slgt_info*)context;
5037         unsigned long flags;
5038
5039         DBGINFO(("%s rx_timeout\n", info->device_name));
5040         spin_lock_irqsave(&info->lock, flags);
5041         info->pending_bh |= BH_RECEIVE;
5042         spin_unlock_irqrestore(&info->lock, flags);
5043         bh_handler(&info->task);
5044 }
5045