drivers/char/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 /*#define DBGTBUF(info) dump_tbufs(info)*/
  44 /*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/system.h>
  77 #include <asm/io.h>
  78 #include <asm/irq.h>
  79 #include <asm/dma.h>
  80 #include <asm/types.h>
  81 #include <asm/uaccess.h>
  82
  83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  84 #define SYNCLINK_GENERIC_HDLC 1
  85 #else
  86 #define SYNCLINK_GENERIC_HDLC 0
  87 #endif
  88
  89 /*
  90  * module identification
  91  */
  92 static char *driver_name     = "SyncLink GT";
  93 static char *tty_driver_name = "synclink_gt";
  94 static char *tty_dev_prefix  = "ttySLG";
  95 MODULE_LICENSE("GPL");
  96 #define MGSL_MAGIC 0x5401
  97 #define MAX_DEVICES 32
  98
  99 static struct pci_device_id pci_table[] = {
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {0,}, /* terminate list */
 105 };
 106 MODULE_DEVICE_TABLE(pci, pci_table);
 107
 108 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 109 static void remove_one(struct pci_dev *dev);
 110 static struct pci_driver pci_driver = {
 111         .name           = "synclink_gt",
 112         .id_table       = pci_table,
 113         .probe          = init_one,
 114         .remove         = __devexit_p(remove_one),
 115 };
 116
 117 static bool pci_registered;
 118
 119 /*
 120  * module configuration and status
 121  */
 122 static struct slgt_info *slgt_device_list;
 123 static int slgt_device_count;
 124
 125 static int ttymajor;
 126 static int debug_level;
 127 static int maxframe[MAX_DEVICES];
 128
 129 module_param(ttymajor, int, 0);
 130 module_param(debug_level, int, 0);
 131 module_param_array(maxframe, int, NULL, 0);
 132
 133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 136
 137 /*
 138  * tty support and callbacks
 139  */
 140 static struct tty_driver *serial_driver;
 141
 142 static int  open(struct tty_struct *tty, struct file * filp);
 143 static void close(struct tty_struct *tty, struct file * filp);
 144 static void hangup(struct tty_struct *tty);
 145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 146
 147 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 148 static int put_char(struct tty_struct *tty, unsigned char ch);
 149 static void send_xchar(struct tty_struct *tty, char ch);
 150 static void wait_until_sent(struct tty_struct *tty, int timeout);
 151 static int  write_room(struct tty_struct *tty);
 152 static void flush_chars(struct tty_struct *tty);
 153 static void flush_buffer(struct tty_struct *tty);
 154 static void tx_hold(struct tty_struct *tty);
 155 static void tx_release(struct tty_struct *tty);
 156
 157 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 158 static int  chars_in_buffer(struct tty_struct *tty);
 159 static void throttle(struct tty_struct * tty);
 160 static void unthrottle(struct tty_struct * tty);
 161 static int set_break(struct tty_struct *tty, int break_state);
 162
 163 /*
 164  * generic HDLC support and callbacks
 165  */
 166 #if SYNCLINK_GENERIC_HDLC
 167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 168 static void hdlcdev_tx_done(struct slgt_info *info);
 169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 170 static int  hdlcdev_init(struct slgt_info *info);
 171 static void hdlcdev_exit(struct slgt_info *info);
 172 #endif
 173
 174
 175 /*
 176  * device specific structures, macros and functions
 177  */
 178
 179 #define SLGT_MAX_PORTS 4
 180 #define SLGT_REG_SIZE  256
 181
 182 /*
 183  * conditional wait facility
 184  */
 185 struct cond_wait {
 186         struct cond_wait *next;
 187         wait_queue_head_t q;
 188         wait_queue_t wait;
 189         unsigned int data;
 190 };
 191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 194 static void flush_cond_wait(struct cond_wait **head);
 195
 196 /*
 197  * DMA buffer descriptor and access macros
 198  */
 199 struct slgt_desc
 200 {
 201         __le16 count;
 202         __le16 status;
 203         __le32 pbuf;  /* physical address of data buffer */
 204         __le32 next;  /* physical address of next descriptor */
 205
 206         /* driver book keeping */
 207         char *buf;          /* virtual  address of data buffer */
 208         unsigned int pdesc; /* physical address of this descriptor */
 209         dma_addr_t buf_dma_addr;
 210         unsigned short buf_count;
 211 };
 212
 213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 215 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 216 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 217 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 218 #define desc_count(a)      (le16_to_cpu((a).count))
 219 #define desc_status(a)     (le16_to_cpu((a).status))
 220 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 221 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 222 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 223 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 224 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 225
 226 struct _input_signal_events {
 227         int ri_up;
 228         int ri_down;
 229         int dsr_up;
 230         int dsr_down;
 231         int dcd_up;
 232         int dcd_down;
 233         int cts_up;
 234         int cts_down;
 235 };
 236
 237 /*
 238  * device instance data structure
 239  */
 240 struct slgt_info {
 241         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 242         struct tty_port port;
 243
 244         struct slgt_info *next_device;  /* device list link */
 245
 246         int magic;
 247
 248         char device_name[25];
 249         struct pci_dev *pdev;
 250
 251         int port_count;  /* count of ports on adapter */
 252         int adapter_num; /* adapter instance number */
 253         int port_num;    /* port instance number */
 254
 255         /* array of pointers to port contexts on this adapter */
 256         struct slgt_info *port_array[SLGT_MAX_PORTS];
 257
 258         int                     line;           /* tty line instance number */
 259
 260         struct mgsl_icount      icount;
 261
 262         int                     timeout;
 263         int                     x_char;         /* xon/xoff character */
 264         unsigned int            read_status_mask;
 265         unsigned int            ignore_status_mask;
 266
 267         wait_queue_head_t       status_event_wait_q;
 268         wait_queue_head_t       event_wait_q;
 269         struct timer_list       tx_timer;
 270         struct timer_list       rx_timer;
 271
 272         unsigned int            gpio_present;
 273         struct cond_wait        *gpio_wait_q;
 274
 275         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 276
 277         struct work_struct task;
 278         u32 pending_bh;
 279         bool bh_requested;
 280         bool bh_running;
 281
 282         int isr_overflow;
 283         bool irq_requested;     /* true if IRQ requested */
 284         bool irq_occurred;      /* for diagnostics use */
 285
 286         /* device configuration */
 287
 288         unsigned int bus_type;
 289         unsigned int irq_level;
 290         unsigned long irq_flags;
 291
 292         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 293         u32 phys_reg_addr;
 294         bool reg_addr_requested;
 295
 296         MGSL_PARAMS params;       /* communications parameters */
 297         u32 idle_mode;
 298         u32 max_frame_size;       /* as set by device config */
 299
 300         unsigned int rbuf_fill_level;
 301         unsigned int rx_pio;
 302         unsigned int if_mode;
 303         unsigned int base_clock;
 304
 305         /* device status */
 306
 307         bool rx_enabled;
 308         bool rx_restart;
 309
 310         bool tx_enabled;
 311         bool tx_active;
 312
 313         unsigned char signals;    /* serial signal states */
 314         int init_error;  /* initialization error */
 315
 316         unsigned char *tx_buf;
 317         int tx_count;
 318
 319         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 320         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336         unsigned int rbuf_fill_index;
 337         unsigned short rbuf_fill_count;
 338
 339         unsigned int tbuf_count;
 340         struct slgt_desc *tbufs;
 341         unsigned int tbuf_current;
 342         unsigned int tbuf_start;
 343
 344         unsigned char *tmp_rbuf;
 345         unsigned int tmp_rbuf_count;
 346
 347         /* SPPP/Cisco HDLC device parts */
 348
 349         int netcount;
 350         spinlock_t netlock;
 351 #if SYNCLINK_GENERIC_HDLC
 352         struct net_device *netdev;
 353 #endif
 354
 355 };
 356
 357 static MGSL_PARAMS default_params = {
 358         .mode            = MGSL_MODE_HDLC,
 359         .loopback        = 0,
 360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362         .clock_speed     = 0,
 363         .addr_filter     = 0xff,
 364         .crc_type        = HDLC_CRC_16_CCITT,
 365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367         .data_rate       = 9600,
 368         .data_bits       = 8,
 369         .stop_bits       = 1,
 370         .parity          = ASYNC_PARITY_NONE
 371 };
 372
 373
 374 #define BH_RECEIVE  1
 375 #define BH_TRANSMIT 2
 376 #define BH_STATUS   4
 377 #define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379 #define DMABUFSIZE 256
 380 #define DESC_LIST_SIZE 4096
 381
 382 #define MASK_PARITY  BIT1
 383 #define MASK_FRAMING BIT0
 384 #define MASK_BREAK   BIT14
 385 #define MASK_OVERRUN BIT4
 386
 387 #define GSR   0x00 /* global status */
 388 #define JCR   0x04 /* JTAG control */
 389 #define IODR  0x08 /* GPIO direction */
 390 #define IOER  0x0c /* GPIO interrupt enable */
 391 #define IOVR  0x10 /* GPIO value */
 392 #define IOSR  0x14 /* GPIO interrupt status */
 393 #define TDR   0x80 /* tx data */
 394 #define RDR   0x80 /* rx data */
 395 #define TCR   0x82 /* tx control */
 396 #define TIR   0x84 /* tx idle */
 397 #define TPR   0x85 /* tx preamble */
 398 #define RCR   0x86 /* rx control */
 399 #define VCR   0x88 /* V.24 control */
 400 #define CCR   0x89 /* clock control */
 401 #define BDR   0x8a /* baud divisor */
 402 #define SCR   0x8c /* serial control */
 403 #define SSR   0x8e /* serial status */
 404 #define RDCSR 0x90 /* rx DMA control/status */
 405 #define TDCSR 0x94 /* tx DMA control/status */
 406 #define RDDAR 0x98 /* rx DMA descriptor address */
 407 #define TDDAR 0x9c /* tx DMA descriptor address */
 408
 409 #define RXIDLE      BIT14
 410 #define RXBREAK     BIT14
 411 #define IRQ_TXDATA  BIT13
 412 #define IRQ_TXIDLE  BIT12
 413 #define IRQ_TXUNDER BIT11 /* HDLC */
 414 #define IRQ_RXDATA  BIT10
 415 #define IRQ_RXIDLE  BIT9  /* HDLC */
 416 #define IRQ_RXBREAK BIT9  /* async */
 417 #define IRQ_RXOVER  BIT8
 418 #define IRQ_DSR     BIT7
 419 #define IRQ_CTS     BIT6
 420 #define IRQ_DCD     BIT5
 421 #define IRQ_RI      BIT4
 422 #define IRQ_ALL     0x3ff0
 423 #define IRQ_MASTER  BIT0
 424
 425 #define slgt_irq_on(info, mask) \
 426         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 427 #define slgt_irq_off(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 429
 430 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 431 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 432 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 434 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 436
 437 static void  msc_set_vcr(struct slgt_info *info);
 438
 439 static int  startup(struct slgt_info *info);
 440 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 441 static void shutdown(struct slgt_info *info);
 442 static void program_hw(struct slgt_info *info);
 443 static void change_params(struct slgt_info *info);
 444
 445 static int  register_test(struct slgt_info *info);
 446 static int  irq_test(struct slgt_info *info);
 447 static int  loopback_test(struct slgt_info *info);
 448 static int  adapter_test(struct slgt_info *info);
 449
 450 static void reset_adapter(struct slgt_info *info);
 451 static void reset_port(struct slgt_info *info);
 452 static void async_mode(struct slgt_info *info);
 453 static void sync_mode(struct slgt_info *info);
 454
 455 static void rx_stop(struct slgt_info *info);
 456 static void rx_start(struct slgt_info *info);
 457 static void reset_rbufs(struct slgt_info *info);
 458 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 459 static void rdma_reset(struct slgt_info *info);
 460 static bool rx_get_frame(struct slgt_info *info);
 461 static bool rx_get_buf(struct slgt_info *info);
 462
 463 static void tx_start(struct slgt_info *info);
 464 static void tx_stop(struct slgt_info *info);
 465 static void tx_set_idle(struct slgt_info *info);
 466 static unsigned int free_tbuf_count(struct slgt_info *info);
 467 static unsigned int tbuf_bytes(struct slgt_info *info);
 468 static void reset_tbufs(struct slgt_info *info);
 469 static void tdma_reset(struct slgt_info *info);
 470 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 471
 472 static void get_signals(struct slgt_info *info);
 473 static void set_signals(struct slgt_info *info);
 474 static void enable_loopback(struct slgt_info *info);
 475 static void set_rate(struct slgt_info *info, u32 data_rate);
 476
 477 static int  bh_action(struct slgt_info *info);
 478 static void bh_handler(struct work_struct *work);
 479 static void bh_transmit(struct slgt_info *info);
 480 static void isr_serial(struct slgt_info *info);
 481 static void isr_rdma(struct slgt_info *info);
 482 static void isr_txeom(struct slgt_info *info, unsigned short status);
 483 static void isr_tdma(struct slgt_info *info);
 484
 485 static int  alloc_dma_bufs(struct slgt_info *info);
 486 static void free_dma_bufs(struct slgt_info *info);
 487 static int  alloc_desc(struct slgt_info *info);
 488 static void free_desc(struct slgt_info *info);
 489 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 490 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 491
 492 static int  alloc_tmp_rbuf(struct slgt_info *info);
 493 static void free_tmp_rbuf(struct slgt_info *info);
 494
 495 static void tx_timeout(unsigned long context);
 496 static void rx_timeout(unsigned long context);
 497
 498 /*
 499  * ioctl handlers
 500  */
 501 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 502 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 503 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 504 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 505 static int  set_txidle(struct slgt_info *info, int idle_mode);
 506 static int  tx_enable(struct slgt_info *info, int enable);
 507 static int  tx_abort(struct slgt_info *info);
 508 static int  rx_enable(struct slgt_info *info, int enable);
 509 static int  modem_input_wait(struct slgt_info *info,int arg);
 510 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 511 static int  tiocmget(struct tty_struct *tty, struct file *file);
 512 static int  tiocmset(struct tty_struct *tty, struct file *file,
 513                      unsigned int set, unsigned int clear);
 514 static int set_break(struct tty_struct *tty, int break_state);
 515 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 516 static int  set_interface(struct slgt_info *info, int if_mode);
 517 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 518 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520
 521 /*
 522  * driver functions
 523  */
 524 static void add_device(struct slgt_info *info);
 525 static void device_init(int adapter_num, struct pci_dev *pdev);
 526 static int  claim_resources(struct slgt_info *info);
 527 static void release_resources(struct slgt_info *info);
 528
 529 /*
 530  * DEBUG OUTPUT CODE
 531  */
 532 #ifndef DBGINFO
 533 #define DBGINFO(fmt)
 534 #endif
 535 #ifndef DBGERR
 536 #define DBGERR(fmt)
 537 #endif
 538 #ifndef DBGBH
 539 #define DBGBH(fmt)
 540 #endif
 541 #ifndef DBGISR
 542 #define DBGISR(fmt)
 543 #endif
 544
 545 #ifdef DBGDATA
 546 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 547 {
 548         int i;
 549         int linecount;
 550         printk("%s %s data:\n",info->device_name, label);
 551         while(count) {
 552                 linecount = (count > 16) ? 16 : count;
 553                 for(i=0; i < linecount; i++)
 554                         printk("%02X ",(unsigned char)data[i]);
 555                 for(;i<17;i++)
 556                         printk("   ");
 557                 for(i=0;i<linecount;i++) {
 558                         if (data[i]>=040 && data[i]<=0176)
 559                                 printk("%c",data[i]);
 560                         else
 561                                 printk(".");
 562                 }
 563                 printk("\n");
 564                 data  += linecount;
 565                 count -= linecount;
 566         }
 567 }
 568 #else
 569 #define DBGDATA(info, buf, size, label)
 570 #endif
 571
 572 #ifdef DBGTBUF
 573 static void dump_tbufs(struct slgt_info *info)
 574 {
 575         int i;
 576         printk("tbuf_current=%d\n", info->tbuf_current);
 577         for (i=0 ; i < info->tbuf_count ; i++) {
 578                 printk("%d: count=%04X status=%04X\n",
 579                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 580         }
 581 }
 582 #else
 583 #define DBGTBUF(info)
 584 #endif
 585
 586 #ifdef DBGRBUF
 587 static void dump_rbufs(struct slgt_info *info)
 588 {
 589         int i;
 590         printk("rbuf_current=%d\n", info->rbuf_current);
 591         for (i=0 ; i < info->rbuf_count ; i++) {
 592                 printk("%d: count=%04X status=%04X\n",
 593                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 594         }
 595 }
 596 #else
 597 #define DBGRBUF(info)
 598 #endif
 599
 600 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 601 {
 602 #ifdef SANITY_CHECK
 603         if (!info) {
 604                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 605                 return 1;
 606         }
 607         if (info->magic != MGSL_MAGIC) {
 608                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 609                 return 1;
 610         }
 611 #else
 612         if (!info)
 613                 return 1;
 614 #endif
 615         return 0;
 616 }
 617
 618 /**
 619  * line discipline callback wrappers
 620  *
 621  * The wrappers maintain line discipline references
 622  * while calling into the line discipline.
 623  *
 624  * ldisc_receive_buf  - pass receive data to line discipline
 625  */
 626 static void ldisc_receive_buf(struct tty_struct *tty,
 627                               const __u8 *data, char *flags, int count)
 628 {
 629         struct tty_ldisc *ld;
 630         if (!tty)
 631                 return;
 632         ld = tty_ldisc_ref(tty);
 633         if (ld) {
 634                 if (ld->ops->receive_buf)
 635                         ld->ops->receive_buf(tty, data, flags, count);
 636                 tty_ldisc_deref(ld);
 637         }
 638 }
 639
 640 /* tty callbacks */
 641
 642 static int open(struct tty_struct *tty, struct file *filp)
 643 {
 644         struct slgt_info *info;
 645         int retval, line;
 646         unsigned long flags;
 647
 648         line = tty->index;
 649         if ((line < 0) || (line >= slgt_device_count)) {
 650                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 651                 return -ENODEV;
 652         }
 653
 654         info = slgt_device_list;
 655         while(info && info->line != line)
 656                 info = info->next_device;
 657         if (sanity_check(info, tty->name, "open"))
 658                 return -ENODEV;
 659         if (info->init_error) {
 660                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 661                 return -ENODEV;
 662         }
 663
 664         tty->driver_data = info;
 665         info->port.tty = tty;
 666
 667         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 668
 669         /* If port is closing, signal caller to try again */
 670         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 671                 if (info->port.flags & ASYNC_CLOSING)
 672                         interruptible_sleep_on(&info->port.close_wait);
 673                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 674                         -EAGAIN : -ERESTARTSYS);
 675                 goto cleanup;
 676         }
 677
 678         mutex_lock(&info->port.mutex);
 679         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 680
 681         spin_lock_irqsave(&info->netlock, flags);
 682         if (info->netcount) {
 683                 retval = -EBUSY;
 684                 spin_unlock_irqrestore(&info->netlock, flags);
 685                 mutex_unlock(&info->port.mutex);
 686                 goto cleanup;
 687         }
 688         info->port.count++;
 689         spin_unlock_irqrestore(&info->netlock, flags);
 690
 691         if (info->port.count == 1) {
 692                 /* 1st open on this device, init hardware */
 693                 retval = startup(info);
 694                 if (retval < 0) {
 695                         mutex_unlock(&info->port.mutex);
 696                         goto cleanup;
 697                 }
 698         }
 699         mutex_unlock(&info->port.mutex);
 700         retval = block_til_ready(tty, filp, info);
 701         if (retval) {
 702                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 703                 goto cleanup;
 704         }
 705
 706         retval = 0;
 707
 708 cleanup:
 709         if (retval) {
 710                 if (tty->count == 1)
 711                         info->port.tty = NULL; /* tty layer will release tty struct */
 712                 if(info->port.count)
 713                         info->port.count--;
 714         }
 715
 716         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 717         return retval;
 718 }
 719
 720 static void close(struct tty_struct *tty, struct file *filp)
 721 {
 722         struct slgt_info *info = tty->driver_data;
 723
 724         if (sanity_check(info, tty->name, "close"))
 725                 return;
 726         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 727
 728         if (tty_port_close_start(&info->port, tty, filp) == 0)
 729                 goto cleanup;
 730
 731         mutex_lock(&info->port.mutex);
 732         if (info->port.flags & ASYNC_INITIALIZED)
 733                 wait_until_sent(tty, info->timeout);
 734         flush_buffer(tty);
 735         tty_ldisc_flush(tty);
 736
 737         shutdown(info);
 738         mutex_unlock(&info->port.mutex);
 739
 740         tty_port_close_end(&info->port, tty);
 741         info->port.tty = NULL;
 742 cleanup:
 743         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 744 }
 745
 746 static void hangup(struct tty_struct *tty)
 747 {
 748         struct slgt_info *info = tty->driver_data;
 749         unsigned long flags;
 750
 751         if (sanity_check(info, tty->name, "hangup"))
 752                 return;
 753         DBGINFO(("%s hangup\n", info->device_name));
 754
 755         flush_buffer(tty);
 756
 757         mutex_lock(&info->port.mutex);
 758         shutdown(info);
 759
 760         spin_lock_irqsave(&info->port.lock, flags);
 761         info->port.count = 0;
 762         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 763         info->port.tty = NULL;
 764         spin_unlock_irqrestore(&info->port.lock, flags);
 765         mutex_unlock(&info->port.mutex);
 766
 767         wake_up_interruptible(&info->port.open_wait);
 768 }
 769
 770 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 771 {
 772         struct slgt_info *info = tty->driver_data;
 773         unsigned long flags;
 774
 775         DBGINFO(("%s set_termios\n", tty->driver->name));
 776
 777         change_params(info);
 778
 779         /* Handle transition to B0 status */
 780         if (old_termios->c_cflag & CBAUD &&
 781             !(tty->termios->c_cflag & CBAUD)) {
 782                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 783                 spin_lock_irqsave(&info->lock,flags);
 784                 set_signals(info);
 785                 spin_unlock_irqrestore(&info->lock,flags);
 786         }
 787
 788         /* Handle transition away from B0 status */
 789         if (!(old_termios->c_cflag & CBAUD) &&
 790             tty->termios->c_cflag & CBAUD) {
 791                 info->signals |= SerialSignal_DTR;
 792                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 793                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 794                         info->signals |= SerialSignal_RTS;
 795                 }
 796                 spin_lock_irqsave(&info->lock,flags);
 797                 set_signals(info);
 798                 spin_unlock_irqrestore(&info->lock,flags);
 799         }
 800
 801         /* Handle turning off CRTSCTS */
 802         if (old_termios->c_cflag & CRTSCTS &&
 803             !(tty->termios->c_cflag & CRTSCTS)) {
 804                 tty->hw_stopped = 0;
 805                 tx_release(tty);
 806         }
 807 }
 808
 809 static void update_tx_timer(struct slgt_info *info)
 810 {
 811         /*
 812          * use worst case speed of 1200bps to calculate transmit timeout
 813          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 814          */
 815         if (info->params.mode == MGSL_MODE_HDLC) {
 816                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 817                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 818         }
 819 }
 820
 821 static int write(struct tty_struct *tty,
 822                  const unsigned char *buf, int count)
 823 {
 824         int ret = 0;
 825         struct slgt_info *info = tty->driver_data;
 826         unsigned long flags;
 827
 828         if (sanity_check(info, tty->name, "write"))
 829                 return -EIO;
 830
 831         DBGINFO(("%s write count=%d\n", info->device_name, count));
 832
 833         if (!info->tx_buf || (count > info->max_frame_size))
 834                 return -EIO;
 835
 836         if (!count || tty->stopped || tty->hw_stopped)
 837                 return 0;
 838
 839         spin_lock_irqsave(&info->lock, flags);
 840
 841         if (info->tx_count) {
 842                 /* send accumulated data from send_char() */
 843                 if (!tx_load(info, info->tx_buf, info->tx_count))
 844                         goto cleanup;
 845                 info->tx_count = 0;
 846         }
 847
 848         if (tx_load(info, buf, count))
 849                 ret = count;
 850
 851 cleanup:
 852         spin_unlock_irqrestore(&info->lock, flags);
 853         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 854         return ret;
 855 }
 856
 857 static int put_char(struct tty_struct *tty, unsigned char ch)
 858 {
 859         struct slgt_info *info = tty->driver_data;
 860         unsigned long flags;
 861         int ret = 0;
 862
 863         if (sanity_check(info, tty->name, "put_char"))
 864                 return 0;
 865         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 866         if (!info->tx_buf)
 867                 return 0;
 868         spin_lock_irqsave(&info->lock,flags);
 869         if (info->tx_count < info->max_frame_size) {
 870                 info->tx_buf[info->tx_count++] = ch;
 871                 ret = 1;
 872         }
 873         spin_unlock_irqrestore(&info->lock,flags);
 874         return ret;
 875 }
 876
 877 static void send_xchar(struct tty_struct *tty, char ch)
 878 {
 879         struct slgt_info *info = tty->driver_data;
 880         unsigned long flags;
 881
 882         if (sanity_check(info, tty->name, "send_xchar"))
 883                 return;
 884         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 885         info->x_char = ch;
 886         if (ch) {
 887                 spin_lock_irqsave(&info->lock,flags);
 888                 if (!info->tx_enabled)
 889                         tx_start(info);
 890                 spin_unlock_irqrestore(&info->lock,flags);
 891         }
 892 }
 893
 894 static void wait_until_sent(struct tty_struct *tty, int timeout)
 895 {
 896         struct slgt_info *info = tty->driver_data;
 897         unsigned long orig_jiffies, char_time;
 898
 899         if (!info )
 900                 return;
 901         if (sanity_check(info, tty->name, "wait_until_sent"))
 902                 return;
 903         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 904         if (!(info->port.flags & ASYNC_INITIALIZED))
 905                 goto exit;
 906
 907         orig_jiffies = jiffies;
 908
 909         /* Set check interval to 1/5 of estimated time to
 910          * send a character, and make it at least 1. The check
 911          * interval should also be less than the timeout.
 912          * Note: use tight timings here to satisfy the NIST-PCTS.
 913          */
 914
 915         if (info->params.data_rate) {
 916                 char_time = info->timeout/(32 * 5);
 917                 if (!char_time)
 918                         char_time++;
 919         } else
 920                 char_time = 1;
 921
 922         if (timeout)
 923                 char_time = min_t(unsigned long, char_time, timeout);
 924
 925         while (info->tx_active) {
 926                 msleep_interruptible(jiffies_to_msecs(char_time));
 927                 if (signal_pending(current))
 928                         break;
 929                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 930                         break;
 931         }
 932 exit:
 933         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 934 }
 935
 936 static int write_room(struct tty_struct *tty)
 937 {
 938         struct slgt_info *info = tty->driver_data;
 939         int ret;
 940
 941         if (sanity_check(info, tty->name, "write_room"))
 942                 return 0;
 943         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 944         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 945         return ret;
 946 }
 947
 948 static void flush_chars(struct tty_struct *tty)
 949 {
 950         struct slgt_info *info = tty->driver_data;
 951         unsigned long flags;
 952
 953         if (sanity_check(info, tty->name, "flush_chars"))
 954                 return;
 955         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 956
 957         if (info->tx_count <= 0 || tty->stopped ||
 958             tty->hw_stopped || !info->tx_buf)
 959                 return;
 960
 961         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 962
 963         spin_lock_irqsave(&info->lock,flags);
 964         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 965                 info->tx_count = 0;
 966         spin_unlock_irqrestore(&info->lock,flags);
 967 }
 968
 969 static void flush_buffer(struct tty_struct *tty)
 970 {
 971         struct slgt_info *info = tty->driver_data;
 972         unsigned long flags;
 973
 974         if (sanity_check(info, tty->name, "flush_buffer"))
 975                 return;
 976         DBGINFO(("%s flush_buffer\n", info->device_name));
 977
 978         spin_lock_irqsave(&info->lock, flags);
 979         info->tx_count = 0;
 980         spin_unlock_irqrestore(&info->lock, flags);
 981
 982         tty_wakeup(tty);
 983 }
 984
 985 /*
 986  * throttle (stop) transmitter
 987  */
 988 static void tx_hold(struct tty_struct *tty)
 989 {
 990         struct slgt_info *info = tty->driver_data;
 991         unsigned long flags;
 992
 993         if (sanity_check(info, tty->name, "tx_hold"))
 994                 return;
 995         DBGINFO(("%s tx_hold\n", info->device_name));
 996         spin_lock_irqsave(&info->lock,flags);
 997         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 998                 tx_stop(info);
 999         spin_unlock_irqrestore(&info->lock,flags);
1000 }
1001
1002 /*
1003  * release (start) transmitter
1004  */
1005 static void tx_release(struct tty_struct *tty)
1006 {
1007         struct slgt_info *info = tty->driver_data;
1008         unsigned long flags;
1009
1010         if (sanity_check(info, tty->name, "tx_release"))
1011                 return;
1012         DBGINFO(("%s tx_release\n", info->device_name));
1013         spin_lock_irqsave(&info->lock, flags);
1014         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1015                 info->tx_count = 0;
1016         spin_unlock_irqrestore(&info->lock, flags);
1017 }
1018
1019 /*
1020  * Service an IOCTL request
1021  *
1022  * Arguments
1023  *
1024  *      tty     pointer to tty instance data
1025  *      file    pointer to associated file object for device
1026  *      cmd     IOCTL command code
1027  *      arg     command argument/context
1028  *
1029  * Return 0 if success, otherwise error code
1030  */
1031 static int ioctl(struct tty_struct *tty, struct file *file,
1032                  unsigned int cmd, unsigned long arg)
1033 {
1034         struct slgt_info *info = tty->driver_data;
1035         void __user *argp = (void __user *)arg;
1036         int ret;
1037
1038         if (sanity_check(info, tty->name, "ioctl"))
1039                 return -ENODEV;
1040         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1041
1042         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1043             (cmd != TIOCMIWAIT)) {
1044                 if (tty->flags & (1 << TTY_IO_ERROR))
1045                     return -EIO;
1046         }
1047
1048         switch (cmd) {
1049         case MGSL_IOCWAITEVENT:
1050                 return wait_mgsl_event(info, argp);
1051         case TIOCMIWAIT:
1052                 return modem_input_wait(info,(int)arg);
1053         case MGSL_IOCSGPIO:
1054                 return set_gpio(info, argp);
1055         case MGSL_IOCGGPIO:
1056                 return get_gpio(info, argp);
1057         case MGSL_IOCWAITGPIO:
1058                 return wait_gpio(info, argp);
1059         }
1060         mutex_lock(&info->port.mutex);
1061         switch (cmd) {
1062         case MGSL_IOCGPARAMS:
1063                 ret = get_params(info, argp);
1064                 break;
1065         case MGSL_IOCSPARAMS:
1066                 ret = set_params(info, argp);
1067                 break;
1068         case MGSL_IOCGTXIDLE:
1069                 ret = get_txidle(info, argp);
1070                 break;
1071         case MGSL_IOCSTXIDLE:
1072                 ret = set_txidle(info, (int)arg);
1073                 break;
1074         case MGSL_IOCTXENABLE:
1075                 ret = tx_enable(info, (int)arg);
1076                 break;
1077         case MGSL_IOCRXENABLE:
1078                 ret = rx_enable(info, (int)arg);
1079                 break;
1080         case MGSL_IOCTXABORT:
1081                 ret = tx_abort(info);
1082                 break;
1083         case MGSL_IOCGSTATS:
1084                 ret = get_stats(info, argp);
1085                 break;
1086         case MGSL_IOCGIF:
1087                 ret = get_interface(info, argp);
1088                 break;
1089         case MGSL_IOCSIF:
1090                 ret = set_interface(info,(int)arg);
1091                 break;
1092         default:
1093                 ret = -ENOIOCTLCMD;
1094         }
1095         mutex_unlock(&info->port.mutex);
1096         return ret;
1097 }
1098
1099 static int get_icount(struct tty_struct *tty,
1100                                 struct serial_icounter_struct *icount)
1101
1102 {
1103         struct slgt_info *info = tty->driver_data;
1104         struct mgsl_icount cnow;        /* kernel counter temps */
1105         unsigned long flags;
1106
1107         spin_lock_irqsave(&info->lock,flags);
1108         cnow = info->icount;
1109         spin_unlock_irqrestore(&info->lock,flags);
1110
1111         icount->cts = cnow.cts;
1112         icount->dsr = cnow.dsr;
1113         icount->rng = cnow.rng;
1114         icount->dcd = cnow.dcd;
1115         icount->rx = cnow.rx;
1116         icount->tx = cnow.tx;
1117         icount->frame = cnow.frame;
1118         icount->overrun = cnow.overrun;
1119         icount->parity = cnow.parity;
1120         icount->brk = cnow.brk;
1121         icount->buf_overrun = cnow.buf_overrun;
1122
1123         return 0;
1124 }
1125
1126 /*
1127  * support for 32 bit ioctl calls on 64 bit systems
1128  */
1129 #ifdef CONFIG_COMPAT
1130 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1131 {
1132         struct MGSL_PARAMS32 tmp_params;
1133
1134         DBGINFO(("%s get_params32\n", info->device_name));
1135         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1136         tmp_params.loopback        = info->params.loopback;
1137         tmp_params.flags           = info->params.flags;
1138         tmp_params.encoding        = info->params.encoding;
1139         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1140         tmp_params.addr_filter     = info->params.addr_filter;
1141         tmp_params.crc_type        = info->params.crc_type;
1142         tmp_params.preamble_length = info->params.preamble_length;
1143         tmp_params.preamble        = info->params.preamble;
1144         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1145         tmp_params.data_bits       = info->params.data_bits;
1146         tmp_params.stop_bits       = info->params.stop_bits;
1147         tmp_params.parity          = info->params.parity;
1148         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149                 return -EFAULT;
1150         return 0;
1151 }
1152
1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154 {
1155         struct MGSL_PARAMS32 tmp_params;
1156
1157         DBGINFO(("%s set_params32\n", info->device_name));
1158         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159                 return -EFAULT;
1160
1161         spin_lock(&info->lock);
1162         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163                 info->base_clock = tmp_params.clock_speed;
1164         } else {
1165                 info->params.mode            = tmp_params.mode;
1166                 info->params.loopback        = tmp_params.loopback;
1167                 info->params.flags           = tmp_params.flags;
1168                 info->params.encoding        = tmp_params.encoding;
1169                 info->params.clock_speed     = tmp_params.clock_speed;
1170                 info->params.addr_filter     = tmp_params.addr_filter;
1171                 info->params.crc_type        = tmp_params.crc_type;
1172                 info->params.preamble_length = tmp_params.preamble_length;
1173                 info->params.preamble        = tmp_params.preamble;
1174                 info->params.data_rate       = tmp_params.data_rate;
1175                 info->params.data_bits       = tmp_params.data_bits;
1176                 info->params.stop_bits       = tmp_params.stop_bits;
1177                 info->params.parity          = tmp_params.parity;
1178         }
1179         spin_unlock(&info->lock);
1180
1181         program_hw(info);
1182
1183         return 0;
1184 }
1185
1186 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1187                          unsigned int cmd, unsigned long arg)
1188 {
1189         struct slgt_info *info = tty->driver_data;
1190         int rc = -ENOIOCTLCMD;
1191
1192         if (sanity_check(info, tty->name, "compat_ioctl"))
1193                 return -ENODEV;
1194         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1195
1196         switch (cmd) {
1197
1198         case MGSL_IOCSPARAMS32:
1199                 rc = set_params32(info, compat_ptr(arg));
1200                 break;
1201
1202         case MGSL_IOCGPARAMS32:
1203                 rc = get_params32(info, compat_ptr(arg));
1204                 break;
1205
1206         case MGSL_IOCGPARAMS:
1207         case MGSL_IOCSPARAMS:
1208         case MGSL_IOCGTXIDLE:
1209         case MGSL_IOCGSTATS:
1210         case MGSL_IOCWAITEVENT:
1211         case MGSL_IOCGIF:
1212         case MGSL_IOCSGPIO:
1213         case MGSL_IOCGGPIO:
1214         case MGSL_IOCWAITGPIO:
1215         case MGSL_IOCSTXIDLE:
1216         case MGSL_IOCTXENABLE:
1217         case MGSL_IOCRXENABLE:
1218         case MGSL_IOCTXABORT:
1219         case TIOCMIWAIT:
1220         case MGSL_IOCSIF:
1221                 rc = ioctl(tty, file, cmd, arg);
1222                 break;
1223         }
1224
1225         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1226         return rc;
1227 }
1228 #else
1229 #define slgt_compat_ioctl NULL
1230 #endif /* ifdef CONFIG_COMPAT */
1231
1232 /*
1233  * proc fs support
1234  */
1235 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1236 {
1237         char stat_buf[30];
1238         unsigned long flags;
1239
1240         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1241                       info->device_name, info->phys_reg_addr,
1242                       info->irq_level, info->max_frame_size);
1243
1244         /* output current serial signal states */
1245         spin_lock_irqsave(&info->lock,flags);
1246         get_signals(info);
1247         spin_unlock_irqrestore(&info->lock,flags);
1248
1249         stat_buf[0] = 0;
1250         stat_buf[1] = 0;
1251         if (info->signals & SerialSignal_RTS)
1252                 strcat(stat_buf, "|RTS");
1253         if (info->signals & SerialSignal_CTS)
1254                 strcat(stat_buf, "|CTS");
1255         if (info->signals & SerialSignal_DTR)
1256                 strcat(stat_buf, "|DTR");
1257         if (info->signals & SerialSignal_DSR)
1258                 strcat(stat_buf, "|DSR");
1259         if (info->signals & SerialSignal_DCD)
1260                 strcat(stat_buf, "|CD");
1261         if (info->signals & SerialSignal_RI)
1262                 strcat(stat_buf, "|RI");
1263
1264         if (info->params.mode != MGSL_MODE_ASYNC) {
1265                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1266                                info->icount.txok, info->icount.rxok);
1267                 if (info->icount.txunder)
1268                         seq_printf(m, " txunder:%d", info->icount.txunder);
1269                 if (info->icount.txabort)
1270                         seq_printf(m, " txabort:%d", info->icount.txabort);
1271                 if (info->icount.rxshort)
1272                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1273                 if (info->icount.rxlong)
1274                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1275                 if (info->icount.rxover)
1276                         seq_printf(m, " rxover:%d", info->icount.rxover);
1277                 if (info->icount.rxcrc)
1278                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1279         } else {
1280                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1281                                info->icount.tx, info->icount.rx);
1282                 if (info->icount.frame)
1283                         seq_printf(m, " fe:%d", info->icount.frame);
1284                 if (info->icount.parity)
1285                         seq_printf(m, " pe:%d", info->icount.parity);
1286                 if (info->icount.brk)
1287                         seq_printf(m, " brk:%d", info->icount.brk);
1288                 if (info->icount.overrun)
1289                         seq_printf(m, " oe:%d", info->icount.overrun);
1290         }
1291
1292         /* Append serial signal status to end */
1293         seq_printf(m, " %s\n", stat_buf+1);
1294
1295         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1296                        info->tx_active,info->bh_requested,info->bh_running,
1297                        info->pending_bh);
1298 }
1299
1300 /* Called to print information about devices
1301  */
1302 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1303 {
1304         struct slgt_info *info;
1305
1306         seq_puts(m, "synclink_gt driver\n");
1307
1308         info = slgt_device_list;
1309         while( info ) {
1310                 line_info(m, info);
1311                 info = info->next_device;
1312         }
1313         return 0;
1314 }
1315
1316 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1317 {
1318         return single_open(file, synclink_gt_proc_show, NULL);
1319 }
1320
1321 static const struct file_operations synclink_gt_proc_fops = {
1322         .owner          = THIS_MODULE,
1323         .open           = synclink_gt_proc_open,
1324         .read           = seq_read,
1325         .llseek         = seq_lseek,
1326         .release        = single_release,
1327 };
1328
1329 /*
1330  * return count of bytes in transmit buffer
1331  */
1332 static int chars_in_buffer(struct tty_struct *tty)
1333 {
1334         struct slgt_info *info = tty->driver_data;
1335         int count;
1336         if (sanity_check(info, tty->name, "chars_in_buffer"))
1337                 return 0;
1338         count = tbuf_bytes(info);
1339         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1340         return count;
1341 }
1342
1343 /*
1344  * signal remote device to throttle send data (our receive data)
1345  */
1346 static void throttle(struct tty_struct * tty)
1347 {
1348         struct slgt_info *info = tty->driver_data;
1349         unsigned long flags;
1350
1351         if (sanity_check(info, tty->name, "throttle"))
1352                 return;
1353         DBGINFO(("%s throttle\n", info->device_name));
1354         if (I_IXOFF(tty))
1355                 send_xchar(tty, STOP_CHAR(tty));
1356         if (tty->termios->c_cflag & CRTSCTS) {
1357                 spin_lock_irqsave(&info->lock,flags);
1358                 info->signals &= ~SerialSignal_RTS;
1359                 set_signals(info);
1360                 spin_unlock_irqrestore(&info->lock,flags);
1361         }
1362 }
1363
1364 /*
1365  * signal remote device to stop throttling send data (our receive data)
1366  */
1367 static void unthrottle(struct tty_struct * tty)
1368 {
1369         struct slgt_info *info = tty->driver_data;
1370         unsigned long flags;
1371
1372         if (sanity_check(info, tty->name, "unthrottle"))
1373                 return;
1374         DBGINFO(("%s unthrottle\n", info->device_name));
1375         if (I_IXOFF(tty)) {
1376                 if (info->x_char)
1377                         info->x_char = 0;
1378                 else
1379                         send_xchar(tty, START_CHAR(tty));
1380         }
1381         if (tty->termios->c_cflag & CRTSCTS) {
1382                 spin_lock_irqsave(&info->lock,flags);
1383                 info->signals |= SerialSignal_RTS;
1384                 set_signals(info);
1385                 spin_unlock_irqrestore(&info->lock,flags);
1386         }
1387 }
1388
1389 /*
1390  * set or clear transmit break condition
1391  * break_state  -1=set break condition, 0=clear
1392  */
1393 static int set_break(struct tty_struct *tty, int break_state)
1394 {
1395         struct slgt_info *info = tty->driver_data;
1396         unsigned short value;
1397         unsigned long flags;
1398
1399         if (sanity_check(info, tty->name, "set_break"))
1400                 return -EINVAL;
1401         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1402
1403         spin_lock_irqsave(&info->lock,flags);
1404         value = rd_reg16(info, TCR);
1405         if (break_state == -1)
1406                 value |= BIT6;
1407         else
1408                 value &= ~BIT6;
1409         wr_reg16(info, TCR, value);
1410         spin_unlock_irqrestore(&info->lock,flags);
1411         return 0;
1412 }
1413
1414 #if SYNCLINK_GENERIC_HDLC
1415
1416 /**
1417  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1418  * set encoding and frame check sequence (FCS) options
1419  *
1420  * dev       pointer to network device structure
1421  * encoding  serial encoding setting
1422  * parity    FCS setting
1423  *
1424  * returns 0 if success, otherwise error code
1425  */
1426 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1427                           unsigned short parity)
1428 {
1429         struct slgt_info *info = dev_to_port(dev);
1430         unsigned char  new_encoding;
1431         unsigned short new_crctype;
1432
1433         /* return error if TTY interface open */
1434         if (info->port.count)
1435                 return -EBUSY;
1436
1437         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1438
1439         switch (encoding)
1440         {
1441         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1442         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1443         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1444         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1445         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1446         default: return -EINVAL;
1447         }
1448
1449         switch (parity)
1450         {
1451         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1452         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1453         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1454         default: return -EINVAL;
1455         }
1456
1457         info->params.encoding = new_encoding;
1458         info->params.crc_type = new_crctype;
1459
1460         /* if network interface up, reprogram hardware */
1461         if (info->netcount)
1462                 program_hw(info);
1463
1464         return 0;
1465 }
1466
1467 /**
1468  * called by generic HDLC layer to send frame
1469  *
1470  * skb  socket buffer containing HDLC frame
1471  * dev  pointer to network device structure
1472  */
1473 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1474                                       struct net_device *dev)
1475 {
1476         struct slgt_info *info = dev_to_port(dev);
1477         unsigned long flags;
1478
1479         DBGINFO(("%s hdlc_xmit\n", dev->name));
1480
1481         if (!skb->len)
1482                 return NETDEV_TX_OK;
1483
1484         /* stop sending until this frame completes */
1485         netif_stop_queue(dev);
1486
1487         /* update network statistics */
1488         dev->stats.tx_packets++;
1489         dev->stats.tx_bytes += skb->len;
1490
1491         /* save start time for transmit timeout detection */
1492         dev->trans_start = jiffies;
1493
1494         spin_lock_irqsave(&info->lock, flags);
1495         tx_load(info, skb->data, skb->len);
1496         spin_unlock_irqrestore(&info->lock, flags);
1497
1498         /* done with socket buffer, so free it */
1499         dev_kfree_skb(skb);
1500
1501         return NETDEV_TX_OK;
1502 }
1503
1504 /**
1505  * called by network layer when interface enabled
1506  * claim resources and initialize hardware
1507  *
1508  * dev  pointer to network device structure
1509  *
1510  * returns 0 if success, otherwise error code
1511  */
1512 static int hdlcdev_open(struct net_device *dev)
1513 {
1514         struct slgt_info *info = dev_to_port(dev);
1515         int rc;
1516         unsigned long flags;
1517
1518         if (!try_module_get(THIS_MODULE))
1519                 return -EBUSY;
1520
1521         DBGINFO(("%s hdlcdev_open\n", dev->name));
1522
1523         /* generic HDLC layer open processing */
1524         if ((rc = hdlc_open(dev)))
1525                 return rc;
1526
1527         /* arbitrate between network and tty opens */
1528         spin_lock_irqsave(&info->netlock, flags);
1529         if (info->port.count != 0 || info->netcount != 0) {
1530                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1531                 spin_unlock_irqrestore(&info->netlock, flags);
1532                 return -EBUSY;
1533         }
1534         info->netcount=1;
1535         spin_unlock_irqrestore(&info->netlock, flags);
1536
1537         /* claim resources and init adapter */
1538         if ((rc = startup(info)) != 0) {
1539                 spin_lock_irqsave(&info->netlock, flags);
1540                 info->netcount=0;
1541                 spin_unlock_irqrestore(&info->netlock, flags);
1542                 return rc;
1543         }
1544
1545         /* assert DTR and RTS, apply hardware settings */
1546         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1547         program_hw(info);
1548
1549         /* enable network layer transmit */
1550         dev->trans_start = jiffies;
1551         netif_start_queue(dev);
1552
1553         /* inform generic HDLC layer of current DCD status */
1554         spin_lock_irqsave(&info->lock, flags);
1555         get_signals(info);
1556         spin_unlock_irqrestore(&info->lock, flags);
1557         if (info->signals & SerialSignal_DCD)
1558                 netif_carrier_on(dev);
1559         else
1560                 netif_carrier_off(dev);
1561         return 0;
1562 }
1563
1564 /**
1565  * called by network layer when interface is disabled
1566  * shutdown hardware and release resources
1567  *
1568  * dev  pointer to network device structure
1569  *
1570  * returns 0 if success, otherwise error code
1571  */
1572 static int hdlcdev_close(struct net_device *dev)
1573 {
1574         struct slgt_info *info = dev_to_port(dev);
1575         unsigned long flags;
1576
1577         DBGINFO(("%s hdlcdev_close\n", dev->name));
1578
1579         netif_stop_queue(dev);
1580
1581         /* shutdown adapter and release resources */
1582         shutdown(info);
1583
1584         hdlc_close(dev);
1585
1586         spin_lock_irqsave(&info->netlock, flags);
1587         info->netcount=0;
1588         spin_unlock_irqrestore(&info->netlock, flags);
1589
1590         module_put(THIS_MODULE);
1591         return 0;
1592 }
1593
1594 /**
1595  * called by network layer to process IOCTL call to network device
1596  *
1597  * dev  pointer to network device structure
1598  * ifr  pointer to network interface request structure
1599  * cmd  IOCTL command code
1600  *
1601  * returns 0 if success, otherwise error code
1602  */
1603 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1604 {
1605         const size_t size = sizeof(sync_serial_settings);
1606         sync_serial_settings new_line;
1607         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1608         struct slgt_info *info = dev_to_port(dev);
1609         unsigned int flags;
1610
1611         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1612
1613         /* return error if TTY interface open */
1614         if (info->port.count)
1615                 return -EBUSY;
1616
1617         if (cmd != SIOCWANDEV)
1618                 return hdlc_ioctl(dev, ifr, cmd);
1619
1620         switch(ifr->ifr_settings.type) {
1621         case IF_GET_IFACE: /* return current sync_serial_settings */
1622
1623                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1624                 if (ifr->ifr_settings.size < size) {
1625                         ifr->ifr_settings.size = size; /* data size wanted */
1626                         return -ENOBUFS;
1627                 }
1628
1629                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1630                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1631                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1632                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1633
1634                 switch (flags){
1635                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1636                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1637                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1638                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1639                 default: new_line.clock_type = CLOCK_DEFAULT;
1640                 }
1641
1642                 new_line.clock_rate = info->params.clock_speed;
1643                 new_line.loopback   = info->params.loopback ? 1:0;
1644
1645                 if (copy_to_user(line, &new_line, size))
1646                         return -EFAULT;
1647                 return 0;
1648
1649         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1650
1651                 if(!capable(CAP_NET_ADMIN))
1652                         return -EPERM;
1653                 if (copy_from_user(&new_line, line, size))
1654                         return -EFAULT;
1655
1656                 switch (new_line.clock_type)
1657                 {
1658                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1659                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1660                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1661                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1662                 case CLOCK_DEFAULT:  flags = info->params.flags &
1663                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1664                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1665                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1666                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1667                 default: return -EINVAL;
1668                 }
1669
1670                 if (new_line.loopback != 0 && new_line.loopback != 1)
1671                         return -EINVAL;
1672
1673                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1674                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1675                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1676                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1677                 info->params.flags |= flags;
1678
1679                 info->params.loopback = new_line.loopback;
1680
1681                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1682                         info->params.clock_speed = new_line.clock_rate;
1683                 else
1684                         info->params.clock_speed = 0;
1685
1686                 /* if network interface up, reprogram hardware */
1687                 if (info->netcount)
1688                         program_hw(info);
1689                 return 0;
1690
1691         default:
1692                 return hdlc_ioctl(dev, ifr, cmd);
1693         }
1694 }
1695
1696 /**
1697  * called by network layer when transmit timeout is detected
1698  *
1699  * dev  pointer to network device structure
1700  */
1701 static void hdlcdev_tx_timeout(struct net_device *dev)
1702 {
1703         struct slgt_info *info = dev_to_port(dev);
1704         unsigned long flags;
1705
1706         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1707
1708         dev->stats.tx_errors++;
1709         dev->stats.tx_aborted_errors++;
1710
1711         spin_lock_irqsave(&info->lock,flags);
1712         tx_stop(info);
1713         spin_unlock_irqrestore(&info->lock,flags);
1714
1715         netif_wake_queue(dev);
1716 }
1717
1718 /**
1719  * called by device driver when transmit completes
1720  * reenable network layer transmit if stopped
1721  *
1722  * info  pointer to device instance information
1723  */
1724 static void hdlcdev_tx_done(struct slgt_info *info)
1725 {
1726         if (netif_queue_stopped(info->netdev))
1727                 netif_wake_queue(info->netdev);
1728 }
1729
1730 /**
1731  * called by device driver when frame received
1732  * pass frame to network layer
1733  *
1734  * info  pointer to device instance information
1735  * buf   pointer to buffer contianing frame data
1736  * size  count of data bytes in buf
1737  */
1738 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1739 {
1740         struct sk_buff *skb = dev_alloc_skb(size);
1741         struct net_device *dev = info->netdev;
1742
1743         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1744
1745         if (skb == NULL) {
1746                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1747                 dev->stats.rx_dropped++;
1748                 return;
1749         }
1750
1751         memcpy(skb_put(skb, size), buf, size);
1752
1753         skb->protocol = hdlc_type_trans(skb, dev);
1754
1755         dev->stats.rx_packets++;
1756         dev->stats.rx_bytes += size;
1757
1758         netif_rx(skb);
1759 }
1760
1761 static const struct net_device_ops hdlcdev_ops = {
1762         .ndo_open       = hdlcdev_open,
1763         .ndo_stop       = hdlcdev_close,
1764         .ndo_change_mtu = hdlc_change_mtu,
1765         .ndo_start_xmit = hdlc_start_xmit,
1766         .ndo_do_ioctl   = hdlcdev_ioctl,
1767         .ndo_tx_timeout = hdlcdev_tx_timeout,
1768 };
1769
1770 /**
1771  * called by device driver when adding device instance
1772  * do generic HDLC initialization
1773  *
1774  * info  pointer to device instance information
1775  *
1776  * returns 0 if success, otherwise error code
1777  */
1778 static int hdlcdev_init(struct slgt_info *info)
1779 {
1780         int rc;
1781         struct net_device *dev;
1782         hdlc_device *hdlc;
1783
1784         /* allocate and initialize network and HDLC layer objects */
1785
1786         if (!(dev = alloc_hdlcdev(info))) {
1787                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1788                 return -ENOMEM;
1789         }
1790
1791         /* for network layer reporting purposes only */
1792         dev->mem_start = info->phys_reg_addr;
1793         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1794         dev->irq       = info->irq_level;
1795
1796         /* network layer callbacks and settings */
1797         dev->netdev_ops     = &hdlcdev_ops;
1798         dev->watchdog_timeo = 10 * HZ;
1799         dev->tx_queue_len   = 50;
1800
1801         /* generic HDLC layer callbacks and settings */
1802         hdlc         = dev_to_hdlc(dev);
1803         hdlc->attach = hdlcdev_attach;
1804         hdlc->xmit   = hdlcdev_xmit;
1805
1806         /* register objects with HDLC layer */
1807         if ((rc = register_hdlc_device(dev))) {
1808                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1809                 free_netdev(dev);
1810                 return rc;
1811         }
1812
1813         info->netdev = dev;
1814         return 0;
1815 }
1816
1817 /**
1818  * called by device driver when removing device instance
1819  * do generic HDLC cleanup
1820  *
1821  * info  pointer to device instance information
1822  */
1823 static void hdlcdev_exit(struct slgt_info *info)
1824 {
1825         unregister_hdlc_device(info->netdev);
1826         free_netdev(info->netdev);
1827         info->netdev = NULL;
1828 }
1829
1830 #endif /* ifdef CONFIG_HDLC */
1831
1832 /*
1833  * get async data from rx DMA buffers
1834  */
1835 static void rx_async(struct slgt_info *info)
1836 {
1837         struct tty_struct *tty = info->port.tty;
1838         struct mgsl_icount *icount = &info->icount;
1839         unsigned int start, end;
1840         unsigned char *p;
1841         unsigned char status;
1842         struct slgt_desc *bufs = info->rbufs;
1843         int i, count;
1844         int chars = 0;
1845         int stat;
1846         unsigned char ch;
1847
1848         start = end = info->rbuf_current;
1849
1850         while(desc_complete(bufs[end])) {
1851                 count = desc_count(bufs[end]) - info->rbuf_index;
1852                 p     = bufs[end].buf + info->rbuf_index;
1853
1854                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1855                 DBGDATA(info, p, count, "rx");
1856
1857                 for(i=0 ; i < count; i+=2, p+=2) {
1858                         ch = *p;
1859                         icount->rx++;
1860
1861                         stat = 0;
1862
1863                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1864                                 if (status & BIT1)
1865                                         icount->parity++;
1866                                 else if (status & BIT0)
1867                                         icount->frame++;
1868                                 /* discard char if tty control flags say so */
1869                                 if (status & info->ignore_status_mask)
1870                                         continue;
1871                                 if (status & BIT1)
1872                                         stat = TTY_PARITY;
1873                                 else if (status & BIT0)
1874                                         stat = TTY_FRAME;
1875                         }
1876                         if (tty) {
1877                                 tty_insert_flip_char(tty, ch, stat);
1878                                 chars++;
1879                         }
1880                 }
1881
1882                 if (i < count) {
1883                         /* receive buffer not completed */
1884                         info->rbuf_index += i;
1885                         mod_timer(&info->rx_timer, jiffies + 1);
1886                         break;
1887                 }
1888
1889                 info->rbuf_index = 0;
1890                 free_rbufs(info, end, end);
1891
1892                 if (++end == info->rbuf_count)
1893                         end = 0;
1894
1895                 /* if entire list searched then no frame available */
1896                 if (end == start)
1897                         break;
1898         }
1899
1900         if (tty && chars)
1901                 tty_flip_buffer_push(tty);
1902 }
1903
1904 /*
1905  * return next bottom half action to perform
1906  */
1907 static int bh_action(struct slgt_info *info)
1908 {
1909         unsigned long flags;
1910         int rc;
1911
1912         spin_lock_irqsave(&info->lock,flags);
1913
1914         if (info->pending_bh & BH_RECEIVE) {
1915                 info->pending_bh &= ~BH_RECEIVE;
1916                 rc = BH_RECEIVE;
1917         } else if (info->pending_bh & BH_TRANSMIT) {
1918                 info->pending_bh &= ~BH_TRANSMIT;
1919                 rc = BH_TRANSMIT;
1920         } else if (info->pending_bh & BH_STATUS) {
1921                 info->pending_bh &= ~BH_STATUS;
1922                 rc = BH_STATUS;
1923         } else {
1924                 /* Mark BH routine as complete */
1925                 info->bh_running = false;
1926                 info->bh_requested = false;
1927                 rc = 0;
1928         }
1929
1930         spin_unlock_irqrestore(&info->lock,flags);
1931
1932         return rc;
1933 }
1934
1935 /*
1936  * perform bottom half processing
1937  */
1938 static void bh_handler(struct work_struct *work)
1939 {
1940         struct slgt_info *info = container_of(work, struct slgt_info, task);
1941         int action;
1942
1943         if (!info)
1944                 return;
1945         info->bh_running = true;
1946
1947         while((action = bh_action(info))) {
1948                 switch (action) {
1949                 case BH_RECEIVE:
1950                         DBGBH(("%s bh receive\n", info->device_name));
1951                         switch(info->params.mode) {
1952                         case MGSL_MODE_ASYNC:
1953                                 rx_async(info);
1954                                 break;
1955                         case MGSL_MODE_HDLC:
1956                                 while(rx_get_frame(info));
1957                                 break;
1958                         case MGSL_MODE_RAW:
1959                         case MGSL_MODE_MONOSYNC:
1960                         case MGSL_MODE_BISYNC:
1961                                 while(rx_get_buf(info));
1962                                 break;
1963                         }
1964                         /* restart receiver if rx DMA buffers exhausted */
1965                         if (info->rx_restart)
1966                                 rx_start(info);
1967                         break;
1968                 case BH_TRANSMIT:
1969                         bh_transmit(info);
1970                         break;
1971                 case BH_STATUS:
1972                         DBGBH(("%s bh status\n", info->device_name));
1973                         info->ri_chkcount = 0;
1974                         info->dsr_chkcount = 0;
1975                         info->dcd_chkcount = 0;
1976                         info->cts_chkcount = 0;
1977                         break;
1978                 default:
1979                         DBGBH(("%s unknown action\n", info->device_name));
1980                         break;
1981                 }
1982         }
1983         DBGBH(("%s bh_handler exit\n", info->device_name));
1984 }
1985
1986 static void bh_transmit(struct slgt_info *info)
1987 {
1988         struct tty_struct *tty = info->port.tty;
1989
1990         DBGBH(("%s bh_transmit\n", info->device_name));
1991         if (tty)
1992                 tty_wakeup(tty);
1993 }
1994
1995 static void dsr_change(struct slgt_info *info, unsigned short status)
1996 {
1997         if (status & BIT3) {
1998                 info->signals |= SerialSignal_DSR;
1999                 info->input_signal_events.dsr_up++;
2000         } else {
2001                 info->signals &= ~SerialSignal_DSR;
2002                 info->input_signal_events.dsr_down++;
2003         }
2004         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2005         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2006                 slgt_irq_off(info, IRQ_DSR);
2007                 return;
2008         }
2009         info->icount.dsr++;
2010         wake_up_interruptible(&info->status_event_wait_q);
2011         wake_up_interruptible(&info->event_wait_q);
2012         info->pending_bh |= BH_STATUS;
2013 }
2014
2015 static void cts_change(struct slgt_info *info, unsigned short status)
2016 {
2017         if (status & BIT2) {
2018                 info->signals |= SerialSignal_CTS;
2019                 info->input_signal_events.cts_up++;
2020         } else {
2021                 info->signals &= ~SerialSignal_CTS;
2022                 info->input_signal_events.cts_down++;
2023         }
2024         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2025         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2026                 slgt_irq_off(info, IRQ_CTS);
2027                 return;
2028         }
2029         info->icount.cts++;
2030         wake_up_interruptible(&info->status_event_wait_q);
2031         wake_up_interruptible(&info->event_wait_q);
2032         info->pending_bh |= BH_STATUS;
2033
2034         if (info->port.flags & ASYNC_CTS_FLOW) {
2035                 if (info->port.tty) {
2036                         if (info->port.tty->hw_stopped) {
2037                                 if (info->signals & SerialSignal_CTS) {
2038                                         info->port.tty->hw_stopped = 0;
2039                                         info->pending_bh |= BH_TRANSMIT;
2040                                         return;
2041                                 }
2042                         } else {
2043                                 if (!(info->signals & SerialSignal_CTS))
2044                                         info->port.tty->hw_stopped = 1;
2045                         }
2046                 }
2047         }
2048 }
2049
2050 static void dcd_change(struct slgt_info *info, unsigned short status)
2051 {
2052         if (status & BIT1) {
2053                 info->signals |= SerialSignal_DCD;
2054                 info->input_signal_events.dcd_up++;
2055         } else {
2056                 info->signals &= ~SerialSignal_DCD;
2057                 info->input_signal_events.dcd_down++;
2058         }
2059         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2060         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2061                 slgt_irq_off(info, IRQ_DCD);
2062                 return;
2063         }
2064         info->icount.dcd++;
2065 #if SYNCLINK_GENERIC_HDLC
2066         if (info->netcount) {
2067                 if (info->signals & SerialSignal_DCD)
2068                         netif_carrier_on(info->netdev);
2069                 else
2070                         netif_carrier_off(info->netdev);
2071         }
2072 #endif
2073         wake_up_interruptible(&info->status_event_wait_q);
2074         wake_up_interruptible(&info->event_wait_q);
2075         info->pending_bh |= BH_STATUS;
2076
2077         if (info->port.flags & ASYNC_CHECK_CD) {
2078                 if (info->signals & SerialSignal_DCD)
2079                         wake_up_interruptible(&info->port.open_wait);
2080                 else {
2081                         if (info->port.tty)
2082                                 tty_hangup(info->port.tty);
2083                 }
2084         }
2085 }
2086
2087 static void ri_change(struct slgt_info *info, unsigned short status)
2088 {
2089         if (status & BIT0) {
2090                 info->signals |= SerialSignal_RI;
2091                 info->input_signal_events.ri_up++;
2092         } else {
2093                 info->signals &= ~SerialSignal_RI;
2094                 info->input_signal_events.ri_down++;
2095         }
2096         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2097         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2098                 slgt_irq_off(info, IRQ_RI);
2099                 return;
2100         }
2101         info->icount.rng++;
2102         wake_up_interruptible(&info->status_event_wait_q);
2103         wake_up_interruptible(&info->event_wait_q);
2104         info->pending_bh |= BH_STATUS;
2105 }
2106
2107 static void isr_rxdata(struct slgt_info *info)
2108 {
2109         unsigned int count = info->rbuf_fill_count;
2110         unsigned int i = info->rbuf_fill_index;
2111         unsigned short reg;
2112
2113         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2114                 reg = rd_reg16(info, RDR);
2115                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2116                 if (desc_complete(info->rbufs[i])) {
2117                         /* all buffers full */
2118                         rx_stop(info);
2119                         info->rx_restart = 1;
2120                         continue;
2121                 }
2122                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2123                 /* async mode saves status byte to buffer for each data byte */
2124                 if (info->params.mode == MGSL_MODE_ASYNC)
2125                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2126                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2127                         /* buffer full or end of frame */
2128                         set_desc_count(info->rbufs[i], count);
2129                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2130                         info->rbuf_fill_count = count = 0;
2131                         if (++i == info->rbuf_count)
2132                                 i = 0;
2133                         info->pending_bh |= BH_RECEIVE;
2134                 }
2135         }
2136
2137         info->rbuf_fill_index = i;
2138         info->rbuf_fill_count = count;
2139 }
2140
2141 static void isr_serial(struct slgt_info *info)
2142 {
2143         unsigned short status = rd_reg16(info, SSR);
2144
2145         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2146
2147         wr_reg16(info, SSR, status); /* clear pending */
2148
2149         info->irq_occurred = true;
2150
2151         if (info->params.mode == MGSL_MODE_ASYNC) {
2152                 if (status & IRQ_TXIDLE) {
2153                         if (info->tx_active)
2154                                 isr_txeom(info, status);
2155                 }
2156                 if (info->rx_pio && (status & IRQ_RXDATA))
2157                         isr_rxdata(info);
2158                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2159                         info->icount.brk++;
2160                         /* process break detection if tty control allows */
2161                         if (info->port.tty) {
2162                                 if (!(status & info->ignore_status_mask)) {
2163                                         if (info->read_status_mask & MASK_BREAK) {
2164                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2165                                                 if (info->port.flags & ASYNC_SAK)
2166                                                         do_SAK(info->port.tty);
2167                                         }
2168                                 }
2169                         }
2170                 }
2171         } else {
2172                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2173                         isr_txeom(info, status);
2174                 if (info->rx_pio && (status & IRQ_RXDATA))
2175                         isr_rxdata(info);
2176                 if (status & IRQ_RXIDLE) {
2177                         if (status & RXIDLE)
2178                                 info->icount.rxidle++;
2179                         else
2180                                 info->icount.exithunt++;
2181                         wake_up_interruptible(&info->event_wait_q);
2182                 }
2183
2184                 if (status & IRQ_RXOVER)
2185                         rx_start(info);
2186         }
2187
2188         if (status & IRQ_DSR)
2189                 dsr_change(info, status);
2190         if (status & IRQ_CTS)
2191                 cts_change(info, status);
2192         if (status & IRQ_DCD)
2193                 dcd_change(info, status);
2194         if (status & IRQ_RI)
2195                 ri_change(info, status);
2196 }
2197
2198 static void isr_rdma(struct slgt_info *info)
2199 {
2200         unsigned int status = rd_reg32(info, RDCSR);
2201
2202         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2203
2204         /* RDCSR (rx DMA control/status)
2205          *
2206          * 31..07  reserved
2207          * 06      save status byte to DMA buffer
2208          * 05      error
2209          * 04      eol (end of list)
2210          * 03      eob (end of buffer)
2211          * 02      IRQ enable
2212          * 01      reset
2213          * 00      enable
2214          */
2215         wr_reg32(info, RDCSR, status);  /* clear pending */
2216
2217         if (status & (BIT5 + BIT4)) {
2218                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2219                 info->rx_restart = true;
2220         }
2221         info->pending_bh |= BH_RECEIVE;
2222 }
2223
2224 static void isr_tdma(struct slgt_info *info)
2225 {
2226         unsigned int status = rd_reg32(info, TDCSR);
2227
2228         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2229
2230         /* TDCSR (tx DMA control/status)
2231          *
2232          * 31..06  reserved
2233          * 05      error
2234          * 04      eol (end of list)
2235          * 03      eob (end of buffer)
2236          * 02      IRQ enable
2237          * 01      reset
2238          * 00      enable
2239          */
2240         wr_reg32(info, TDCSR, status);  /* clear pending */
2241
2242         if (status & (BIT5 + BIT4 + BIT3)) {
2243                 // another transmit buffer has completed
2244                 // run bottom half to get more send data from user
2245                 info->pending_bh |= BH_TRANSMIT;
2246         }
2247 }
2248
2249 /*
2250  * return true if there are unsent tx DMA buffers, otherwise false
2251  *
2252  * if there are unsent buffers then info->tbuf_start
2253  * is set to index of first unsent buffer
2254  */
2255 static bool unsent_tbufs(struct slgt_info *info)
2256 {
2257         unsigned int i = info->tbuf_current;
2258         bool rc = false;
2259
2260         /*
2261          * search backwards from last loaded buffer (precedes tbuf_current)
2262          * for first unsent buffer (desc_count > 0)
2263          */
2264
2265         do {
2266                 if (i)
2267                         i--;
2268                 else
2269                         i = info->tbuf_count - 1;
2270                 if (!desc_count(info->tbufs[i]))
2271                         break;
2272                 info->tbuf_start = i;
2273                 rc = true;
2274         } while (i != info->tbuf_current);
2275
2276         return rc;
2277 }
2278
2279 static void isr_txeom(struct slgt_info *info, unsigned short status)
2280 {
2281         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2282
2283         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2284         tdma_reset(info);
2285         if (status & IRQ_TXUNDER) {
2286                 unsigned short val = rd_reg16(info, TCR);
2287                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2288                 wr_reg16(info, TCR, val); /* clear reset bit */
2289         }
2290
2291         if (info->tx_active) {
2292                 if (info->params.mode != MGSL_MODE_ASYNC) {
2293                         if (status & IRQ_TXUNDER)
2294                                 info->icount.txunder++;
2295                         else if (status & IRQ_TXIDLE)
2296                                 info->icount.txok++;
2297                 }
2298
2299                 if (unsent_tbufs(info)) {
2300                         tx_start(info);
2301                         update_tx_timer(info);
2302                         return;
2303                 }
2304                 info->tx_active = false;
2305
2306                 del_timer(&info->tx_timer);
2307
2308                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2309                         info->signals &= ~SerialSignal_RTS;
2310                         info->drop_rts_on_tx_done = false;
2311                         set_signals(info);
2312                 }
2313
2314 #if SYNCLINK_GENERIC_HDLC
2315                 if (info->netcount)
2316                         hdlcdev_tx_done(info);
2317                 else
2318 #endif
2319                 {
2320                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2321                                 tx_stop(info);
2322                                 return;
2323                         }
2324                         info->pending_bh |= BH_TRANSMIT;
2325                 }
2326         }
2327 }
2328
2329 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2330 {
2331         struct cond_wait *w, *prev;
2332
2333         /* wake processes waiting for specific transitions */
2334         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2335                 if (w->data & changed) {
2336                         w->data = state;
2337                         wake_up_interruptible(&w->q);
2338                         if (prev != NULL)
2339                                 prev->next = w->next;
2340                         else
2341                                 info->gpio_wait_q = w->next;
2342                 } else
2343                         prev = w;
2344         }
2345 }
2346
2347 /* interrupt service routine
2348  *
2349  *      irq     interrupt number
2350  *      dev_id  device ID supplied during interrupt registration
2351  */
2352 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2353 {
2354         struct slgt_info *info = dev_id;
2355         unsigned int gsr;
2356         unsigned int i;
2357
2358         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2359
2360         spin_lock(&info->lock);
2361
2362         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2363                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2364                 info->irq_occurred = true;
2365                 for(i=0; i < info->port_count ; i++) {
2366                         if (info->port_array[i] == NULL)
2367                                 continue;
2368                         if (gsr & (BIT8 << i))
2369                                 isr_serial(info->port_array[i]);
2370                         if (gsr & (BIT16 << (i*2)))
2371                                 isr_rdma(info->port_array[i]);
2372                         if (gsr & (BIT17 << (i*2)))
2373                                 isr_tdma(info->port_array[i]);
2374                 }
2375         }
2376
2377         if (info->gpio_present) {
2378                 unsigned int state;
2379                 unsigned int changed;
2380                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2381                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2382                         /* read latched state of GPIO signals */
2383                         state = rd_reg32(info, IOVR);
2384                         /* clear pending GPIO interrupt bits */
2385                         wr_reg32(info, IOSR, changed);
2386                         for (i=0 ; i < info->port_count ; i++) {
2387                                 if (info->port_array[i] != NULL)
2388                                         isr_gpio(info->port_array[i], changed, state);
2389                         }
2390                 }
2391         }
2392
2393         for(i=0; i < info->port_count ; i++) {
2394                 struct slgt_info *port = info->port_array[i];
2395
2396                 if (port && (port->port.count || port->netcount) &&
2397                     port->pending_bh && !port->bh_running &&
2398                     !port->bh_requested) {
2399                         DBGISR(("%s bh queued\n", port->device_name));
2400                         schedule_work(&port->task);
2401                         port->bh_requested = true;
2402                 }
2403         }
2404
2405         spin_unlock(&info->lock);
2406
2407         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2408         return IRQ_HANDLED;
2409 }
2410
2411 static int startup(struct slgt_info *info)
2412 {
2413         DBGINFO(("%s startup\n", info->device_name));
2414
2415         if (info->port.flags & ASYNC_INITIALIZED)
2416                 return 0;
2417
2418         if (!info->tx_buf) {
2419                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2420                 if (!info->tx_buf) {
2421                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2422                         return -ENOMEM;
2423                 }
2424         }
2425
2426         info->pending_bh = 0;
2427
2428         memset(&info->icount, 0, sizeof(info->icount));
2429
2430         /* program hardware for current parameters */
2431         change_params(info);
2432
2433         if (info->port.tty)
2434                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2435
2436         info->port.flags |= ASYNC_INITIALIZED;
2437
2438         return 0;
2439 }
2440
2441 /*
2442  *  called by close() and hangup() to shutdown hardware
2443  */
2444 static void shutdown(struct slgt_info *info)
2445 {
2446         unsigned long flags;
2447
2448         if (!(info->port.flags & ASYNC_INITIALIZED))
2449                 return;
2450
2451         DBGINFO(("%s shutdown\n", info->device_name));
2452
2453         /* clear status wait queue because status changes */
2454         /* can't happen after shutting down the hardware */
2455         wake_up_interruptible(&info->status_event_wait_q);
2456         wake_up_interruptible(&info->event_wait_q);
2457
2458         del_timer_sync(&info->tx_timer);
2459         del_timer_sync(&info->rx_timer);
2460
2461         kfree(info->tx_buf);
2462         info->tx_buf = NULL;
2463
2464         spin_lock_irqsave(&info->lock,flags);
2465
2466         tx_stop(info);
2467         rx_stop(info);
2468
2469         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2470
2471         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2472                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2473                 set_signals(info);
2474         }
2475
2476         flush_cond_wait(&info->gpio_wait_q);
2477
2478         spin_unlock_irqrestore(&info->lock,flags);
2479
2480         if (info->port.tty)
2481                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2482
2483         info->port.flags &= ~ASYNC_INITIALIZED;
2484 }
2485
2486 static void program_hw(struct slgt_info *info)
2487 {
2488         unsigned long flags;
2489
2490         spin_lock_irqsave(&info->lock,flags);
2491
2492         rx_stop(info);
2493         tx_stop(info);
2494
2495         if (info->params.mode != MGSL_MODE_ASYNC ||
2496             info->netcount)
2497                 sync_mode(info);
2498         else
2499                 async_mode(info);
2500
2501         set_signals(info);
2502
2503         info->dcd_chkcount = 0;
2504         info->cts_chkcount = 0;
2505         info->ri_chkcount = 0;
2506         info->dsr_chkcount = 0;
2507
2508         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2509         get_signals(info);
2510
2511         if (info->netcount ||
2512             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2513                 rx_start(info);
2514
2515         spin_unlock_irqrestore(&info->lock,flags);
2516 }
2517
2518 /*
2519  * reconfigure adapter based on new parameters
2520  */
2521 static void change_params(struct slgt_info *info)
2522 {
2523         unsigned cflag;
2524         int bits_per_char;
2525
2526         if (!info->port.tty || !info->port.tty->termios)
2527                 return;
2528         DBGINFO(("%s change_params\n", info->device_name));
2529
2530         cflag = info->port.tty->termios->c_cflag;
2531
2532         /* if B0 rate (hangup) specified then negate DTR and RTS */
2533         /* otherwise assert DTR and RTS */
2534         if (cflag & CBAUD)
2535                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2536         else
2537                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2538
2539         /* byte size and parity */
2540
2541         switch (cflag & CSIZE) {
2542         case CS5: info->params.data_bits = 5; break;
2543         case CS6: info->params.data_bits = 6; break;
2544         case CS7: info->params.data_bits = 7; break;
2545         case CS8: info->params.data_bits = 8; break;
2546         default:  info->params.data_bits = 7; break;
2547         }
2548
2549         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2550
2551         if (cflag & PARENB)
2552                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2553         else
2554                 info->params.parity = ASYNC_PARITY_NONE;
2555
2556         /* calculate number of jiffies to transmit a full
2557          * FIFO (32 bytes) at specified data rate
2558          */
2559         bits_per_char = info->params.data_bits +
2560                         info->params.stop_bits + 1;
2561
2562         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2563
2564         if (info->params.data_rate) {
2565                 info->timeout = (32*HZ*bits_per_char) /
2566                                 info->params.data_rate;
2567         }
2568         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2569
2570         if (cflag & CRTSCTS)
2571                 info->port.flags |= ASYNC_CTS_FLOW;
2572         else
2573                 info->port.flags &= ~ASYNC_CTS_FLOW;
2574
2575         if (cflag & CLOCAL)
2576                 info->port.flags &= ~ASYNC_CHECK_CD;
2577         else
2578                 info->port.flags |= ASYNC_CHECK_CD;
2579
2580         /* process tty input control flags */
2581
2582         info->read_status_mask = IRQ_RXOVER;
2583         if (I_INPCK(info->port.tty))
2584                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2585         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2586                 info->read_status_mask |= MASK_BREAK;
2587         if (I_IGNPAR(info->port.tty))
2588                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2589         if (I_IGNBRK(info->port.tty)) {
2590                 info->ignore_status_mask |= MASK_BREAK;
2591                 /* If ignoring parity and break indicators, ignore
2592                  * overruns too.  (For real raw support).
2593                  */
2594                 if (I_IGNPAR(info->port.tty))
2595                         info->ignore_status_mask |= MASK_OVERRUN;
2596         }
2597
2598         program_hw(info);
2599 }
2600
2601 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2602 {
2603         DBGINFO(("%s get_stats\n",  info->device_name));
2604         if (!user_icount) {
2605                 memset(&info->icount, 0, sizeof(info->icount));
2606         } else {
2607                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2608                         return -EFAULT;
2609         }
2610         return 0;
2611 }
2612
2613 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2614 {
2615         DBGINFO(("%s get_params\n", info->device_name));
2616         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2617                 return -EFAULT;
2618         return 0;
2619 }
2620
2621 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2622 {
2623         unsigned long flags;
2624         MGSL_PARAMS tmp_params;
2625
2626         DBGINFO(("%s set_params\n", info->device_name));
2627         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2628                 return -EFAULT;
2629
2630         spin_lock_irqsave(&info->lock, flags);
2631         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2632                 info->base_clock = tmp_params.clock_speed;
2633         else
2634                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2635         spin_unlock_irqrestore(&info->lock, flags);
2636
2637         program_hw(info);
2638
2639         return 0;
2640 }
2641
2642 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2643 {
2644         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2645         if (put_user(info->idle_mode, idle_mode))
2646                 return -EFAULT;
2647         return 0;
2648 }
2649
2650 static int set_txidle(struct slgt_info *info, int idle_mode)
2651 {
2652         unsigned long flags;
2653         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2654         spin_lock_irqsave(&info->lock,flags);
2655         info->idle_mode = idle_mode;
2656         if (info->params.mode != MGSL_MODE_ASYNC)
2657                 tx_set_idle(info);
2658         spin_unlock_irqrestore(&info->lock,flags);
2659         return 0;
2660 }
2661
2662 static int tx_enable(struct slgt_info *info, int enable)
2663 {
2664         unsigned long flags;
2665         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2666         spin_lock_irqsave(&info->lock,flags);
2667         if (enable) {
2668                 if (!info->tx_enabled)
2669                         tx_start(info);
2670         } else {
2671                 if (info->tx_enabled)
2672                         tx_stop(info);
2673         }
2674         spin_unlock_irqrestore(&info->lock,flags);
2675         return 0;
2676 }
2677
2678 /*
2679  * abort transmit HDLC frame
2680  */
2681 static int tx_abort(struct slgt_info *info)
2682 {
2683         unsigned long flags;
2684         DBGINFO(("%s tx_abort\n", info->device_name));
2685         spin_lock_irqsave(&info->lock,flags);
2686         tdma_reset(info);
2687         spin_unlock_irqrestore(&info->lock,flags);
2688         return 0;
2689 }
2690
2691 static int rx_enable(struct slgt_info *info, int enable)
2692 {
2693         unsigned long flags;
2694         unsigned int rbuf_fill_level;
2695         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2696         spin_lock_irqsave(&info->lock,flags);
2697         /*
2698          * enable[31..16] = receive DMA buffer fill level
2699          * 0 = noop (leave fill level unchanged)
2700          * fill level must be multiple of 4 and <= buffer size
2701          */
2702         rbuf_fill_level = ((unsigned int)enable) >> 16;
2703         if (rbuf_fill_level) {
2704                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2705                         spin_unlock_irqrestore(&info->lock, flags);
2706                         return -EINVAL;
2707                 }
2708                 info->rbuf_fill_level = rbuf_fill_level;
2709                 if (rbuf_fill_level < 128)
2710                         info->rx_pio = 1; /* PIO mode */
2711                 else
2712                         info->rx_pio = 0; /* DMA mode */
2713                 rx_stop(info); /* restart receiver to use new fill level */
2714         }
2715
2716         /*
2717          * enable[1..0] = receiver enable command
2718          * 0 = disable
2719          * 1 = enable
2720          * 2 = enable or force hunt mode if already enabled
2721          */
2722         enable &= 3;
2723         if (enable) {
2724                 if (!info->rx_enabled)
2725                         rx_start(info);
2726                 else if (enable == 2) {
2727                         /* force hunt mode (write 1 to RCR[3]) */
2728                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2729                 }
2730         } else {
2731                 if (info->rx_enabled)
2732                         rx_stop(info);
2733         }
2734         spin_unlock_irqrestore(&info->lock,flags);
2735         return 0;
2736 }
2737
2738 /*
2739  *  wait for specified event to occur
2740  */
2741 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2742 {
2743         unsigned long flags;
2744         int s;
2745         int rc=0;
2746         struct mgsl_icount cprev, cnow;
2747         int events;
2748         int mask;
2749         struct  _input_signal_events oldsigs, newsigs;
2750         DECLARE_WAITQUEUE(wait, current);
2751
2752         if (get_user(mask, mask_ptr))
2753                 return -EFAULT;
2754
2755         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2756
2757         spin_lock_irqsave(&info->lock,flags);
2758
2759         /* return immediately if state matches requested events */
2760         get_signals(info);
2761         s = info->signals;
2762
2763         events = mask &
2764                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2765                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2766                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2767                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2768         if (events) {
2769                 spin_unlock_irqrestore(&info->lock,flags);
2770                 goto exit;
2771         }
2772
2773         /* save current irq counts */
2774         cprev = info->icount;
2775         oldsigs = info->input_signal_events;
2776
2777         /* enable hunt and idle irqs if needed */
2778         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2779                 unsigned short val = rd_reg16(info, SCR);
2780                 if (!(val & IRQ_RXIDLE))
2781                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2782         }
2783
2784         set_current_state(TASK_INTERRUPTIBLE);
2785         add_wait_queue(&info->event_wait_q, &wait);
2786
2787         spin_unlock_irqrestore(&info->lock,flags);
2788
2789         for(;;) {
2790                 schedule();
2791                 if (signal_pending(current)) {
2792                         rc = -ERESTARTSYS;
2793                         break;
2794                 }
2795
2796                 /* get current irq counts */
2797                 spin_lock_irqsave(&info->lock,flags);
2798                 cnow = info->icount;
2799                 newsigs = info->input_signal_events;
2800                 set_current_state(TASK_INTERRUPTIBLE);
2801                 spin_unlock_irqrestore(&info->lock,flags);
2802
2803                 /* if no change, wait aborted for some reason */
2804                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2805                     newsigs.dsr_down == oldsigs.dsr_down &&
2806                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2807                     newsigs.dcd_down == oldsigs.dcd_down &&
2808                     newsigs.cts_up   == oldsigs.cts_up   &&
2809                     newsigs.cts_down == oldsigs.cts_down &&
2810                     newsigs.ri_up    == oldsigs.ri_up    &&
2811                     newsigs.ri_down  == oldsigs.ri_down  &&
2812                     cnow.exithunt    == cprev.exithunt   &&
2813                     cnow.rxidle      == cprev.rxidle) {
2814                         rc = -EIO;
2815                         break;
2816                 }
2817
2818                 events = mask &
2819                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2820                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2821                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2822                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2823                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2824                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2825                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2826                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2827                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2828                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2829                 if (events)
2830                         break;
2831
2832                 cprev = cnow;
2833                 oldsigs = newsigs;
2834         }
2835
2836         remove_wait_queue(&info->event_wait_q, &wait);
2837         set_current_state(TASK_RUNNING);
2838
2839
2840         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2841                 spin_lock_irqsave(&info->lock,flags);
2842                 if (!waitqueue_active(&info->event_wait_q)) {
2843                         /* disable enable exit hunt mode/idle rcvd IRQs */
2844                         wr_reg16(info, SCR,
2845                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2846                 }
2847                 spin_unlock_irqrestore(&info->lock,flags);
2848         }
2849 exit:
2850         if (rc == 0)
2851                 rc = put_user(events, mask_ptr);
2852         return rc;
2853 }
2854
2855 static int get_interface(struct slgt_info *info, int __user *if_mode)
2856 {
2857         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2858         if (put_user(info->if_mode, if_mode))
2859                 return -EFAULT;
2860         return 0;
2861 }
2862
2863 static int set_interface(struct slgt_info *info, int if_mode)
2864 {
2865         unsigned long flags;
2866         unsigned short val;
2867
2868         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2869         spin_lock_irqsave(&info->lock,flags);
2870         info->if_mode = if_mode;
2871
2872         msc_set_vcr(info);
2873
2874         /* TCR (tx control) 07  1=RTS driver control */
2875         val = rd_reg16(info, TCR);
2876         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2877                 val |= BIT7;
2878         else
2879                 val &= ~BIT7;
2880         wr_reg16(info, TCR, val);
2881
2882         spin_unlock_irqrestore(&info->lock,flags);
2883         return 0;
2884 }
2885
2886 /*
2887  * set general purpose IO pin state and direction
2888  *
2889  * user_gpio fields:
2890  * state   each bit indicates a pin state
2891  * smask   set bit indicates pin state to set
2892  * dir     each bit indicates a pin direction (0=input, 1=output)
2893  * dmask   set bit indicates pin direction to set
2894  */
2895 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2896 {
2897         unsigned long flags;
2898         struct gpio_desc gpio;
2899         __u32 data;
2900
2901         if (!info->gpio_present)
2902                 return -EINVAL;
2903         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2904                 return -EFAULT;
2905         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2906                  info->device_name, gpio.state, gpio.smask,
2907                  gpio.dir, gpio.dmask));
2908
2909         spin_lock_irqsave(&info->lock,flags);
2910         if (gpio.dmask) {
2911                 data = rd_reg32(info, IODR);
2912                 data |= gpio.dmask & gpio.dir;
2913                 data &= ~(gpio.dmask & ~gpio.dir);
2914                 wr_reg32(info, IODR, data);
2915         }
2916         if (gpio.smask) {
2917                 data = rd_reg32(info, IOVR);
2918                 data |= gpio.smask & gpio.state;
2919                 data &= ~(gpio.smask & ~gpio.state);
2920                 wr_reg32(info, IOVR, data);
2921         }
2922         spin_unlock_irqrestore(&info->lock,flags);
2923
2924         return 0;
2925 }
2926
2927 /*
2928  * get general purpose IO pin state and direction
2929  */
2930 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2931 {
2932         struct gpio_desc gpio;
2933         if (!info->gpio_present)
2934                 return -EINVAL;
2935         gpio.state = rd_reg32(info, IOVR);
2936         gpio.smask = 0xffffffff;
2937         gpio.dir   = rd_reg32(info, IODR);
2938         gpio.dmask = 0xffffffff;
2939         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2940                 return -EFAULT;
2941         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2942                  info->device_name, gpio.state, gpio.dir));
2943         return 0;
2944 }
2945
2946 /*
2947  * conditional wait facility
2948  */
2949 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2950 {
2951         init_waitqueue_head(&w->q);
2952         init_waitqueue_entry(&w->wait, current);
2953         w->data = data;
2954 }
2955
2956 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2957 {
2958         set_current_state(TASK_INTERRUPTIBLE);
2959         add_wait_queue(&w->q, &w->wait);
2960         w->next = *head;
2961         *head = w;
2962 }
2963
2964 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2965 {
2966         struct cond_wait *w, *prev;
2967         remove_wait_queue(&cw->q, &cw->wait);
2968         set_current_state(TASK_RUNNING);
2969         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2970                 if (w == cw) {
2971                         if (prev != NULL)
2972                                 prev->next = w->next;
2973                         else
2974                                 *head = w->next;
2975                         break;
2976                 }
2977         }
2978 }
2979
2980 static void flush_cond_wait(struct cond_wait **head)
2981 {
2982         while (*head != NULL) {
2983                 wake_up_interruptible(&(*head)->q);
2984                 *head = (*head)->next;
2985         }
2986 }
2987
2988 /*
2989  * wait for general purpose I/O pin(s) to enter specified state
2990  *
2991  * user_gpio fields:
2992  * state - bit indicates target pin state
2993  * smask - set bit indicates watched pin
2994  *
2995  * The wait ends when at least one watched pin enters the specified
2996  * state. When 0 (no error) is returned, user_gpio->state is set to the
2997  * state of all GPIO pins when the wait ends.
2998  *
2999  * Note: Each pin may be a dedicated input, dedicated output, or
3000  * configurable input/output. The number and configuration of pins
3001  * varies with the specific adapter model. Only input pins (dedicated
3002  * or configured) can be monitored with this function.
3003  */
3004 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3005 {
3006         unsigned long flags;
3007         int rc = 0;
3008         struct gpio_desc gpio;
3009         struct cond_wait wait;
3010         u32 state;
3011
3012         if (!info->gpio_present)
3013                 return -EINVAL;
3014         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3015                 return -EFAULT;
3016         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3017                  info->device_name, gpio.state, gpio.smask));
3018         /* ignore output pins identified by set IODR bit */
3019         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3020                 return -EINVAL;
3021         init_cond_wait(&wait, gpio.smask);
3022
3023         spin_lock_irqsave(&info->lock, flags);
3024         /* enable interrupts for watched pins */
3025         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3026         /* get current pin states */
3027         state = rd_reg32(info, IOVR);
3028
3029         if (gpio.smask & ~(state ^ gpio.state)) {
3030                 /* already in target state */
3031                 gpio.state = state;
3032         } else {
3033                 /* wait for target state */
3034                 add_cond_wait(&info->gpio_wait_q, &wait);
3035                 spin_unlock_irqrestore(&info->lock, flags);
3036                 schedule();
3037                 if (signal_pending(current))
3038                         rc = -ERESTARTSYS;
3039                 else
3040                         gpio.state = wait.data;
3041                 spin_lock_irqsave(&info->lock, flags);
3042                 remove_cond_wait(&info->gpio_wait_q, &wait);
3043         }
3044
3045         /* disable all GPIO interrupts if no waiting processes */
3046         if (info->gpio_wait_q == NULL)
3047                 wr_reg32(info, IOER, 0);
3048         spin_unlock_irqrestore(&info->lock,flags);
3049
3050         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3051                 rc = -EFAULT;
3052         return rc;
3053 }
3054
3055 static int modem_input_wait(struct slgt_info *info,int arg)
3056 {
3057         unsigned long flags;
3058         int rc;
3059         struct mgsl_icount cprev, cnow;
3060         DECLARE_WAITQUEUE(wait, current);
3061
3062         /* save current irq counts */
3063         spin_lock_irqsave(&info->lock,flags);
3064         cprev = info->icount;
3065         add_wait_queue(&info->status_event_wait_q, &wait);
3066         set_current_state(TASK_INTERRUPTIBLE);
3067         spin_unlock_irqrestore(&info->lock,flags);
3068
3069         for(;;) {
3070                 schedule();
3071                 if (signal_pending(current)) {
3072                         rc = -ERESTARTSYS;
3073                         break;
3074                 }
3075
3076                 /* get new irq counts */
3077                 spin_lock_irqsave(&info->lock,flags);
3078                 cnow = info->icount;
3079                 set_current_state(TASK_INTERRUPTIBLE);
3080                 spin_unlock_irqrestore(&info->lock,flags);
3081
3082                 /* if no change, wait aborted for some reason */
3083                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3084                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3085                         rc = -EIO;
3086                         break;
3087                 }
3088
3089                 /* check for change in caller specified modem input */
3090                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3091                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3092                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3093                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3094                         rc = 0;
3095                         break;
3096                 }
3097
3098                 cprev = cnow;
3099         }
3100         remove_wait_queue(&info->status_event_wait_q, &wait);
3101         set_current_state(TASK_RUNNING);
3102         return rc;
3103 }
3104
3105 /*
3106  *  return state of serial control and status signals
3107  */
3108 static int tiocmget(struct tty_struct *tty, struct file *file)
3109 {
3110         struct slgt_info *info = tty->driver_data;
3111         unsigned int result;
3112         unsigned long flags;
3113
3114         spin_lock_irqsave(&info->lock,flags);
3115         get_signals(info);
3116         spin_unlock_irqrestore(&info->lock,flags);
3117
3118         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3119                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3120                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3121                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3122                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3123                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3124
3125         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3126         return result;
3127 }
3128
3129 /*
3130  * set modem control signals (DTR/RTS)
3131  *
3132  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3133  *              TIOCMSET = set/clear signal values
3134  *      value   bit mask for command
3135  */
3136 static int tiocmset(struct tty_struct *tty, struct file *file,
3137                     unsigned int set, unsigned int clear)
3138 {
3139         struct slgt_info *info = tty->driver_data;
3140         unsigned long flags;
3141
3142         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3143
3144         if (set & TIOCM_RTS)
3145                 info->signals |= SerialSignal_RTS;
3146         if (set & TIOCM_DTR)
3147                 info->signals |= SerialSignal_DTR;
3148         if (clear & TIOCM_RTS)
3149                 info->signals &= ~SerialSignal_RTS;
3150         if (clear & TIOCM_DTR)
3151                 info->signals &= ~SerialSignal_DTR;
3152
3153         spin_lock_irqsave(&info->lock,flags);
3154         set_signals(info);
3155         spin_unlock_irqrestore(&info->lock,flags);
3156         return 0;
3157 }
3158
3159 static int carrier_raised(struct tty_port *port)
3160 {
3161         unsigned long flags;
3162         struct slgt_info *info = container_of(port, struct slgt_info, port);
3163
3164         spin_lock_irqsave(&info->lock,flags);
3165         get_signals(info);
3166         spin_unlock_irqrestore(&info->lock,flags);
3167         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3168 }
3169
3170 static void dtr_rts(struct tty_port *port, int on)
3171 {
3172         unsigned long flags;
3173         struct slgt_info *info = container_of(port, struct slgt_info, port);
3174
3175         spin_lock_irqsave(&info->lock,flags);
3176         if (on)
3177                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3178         else
3179                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3180         set_signals(info);
3181         spin_unlock_irqrestore(&info->lock,flags);
3182 }
3183
3184
3185 /*
3186  *  block current process until the device is ready to open
3187  */
3188 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3189                            struct slgt_info *info)
3190 {
3191         DECLARE_WAITQUEUE(wait, current);
3192         int             retval;
3193         bool            do_clocal = false;
3194         bool            extra_count = false;
3195         unsigned long   flags;
3196         int             cd;
3197         struct tty_port *port = &info->port;
3198
3199         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3200
3201         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3202                 /* nonblock mode is set or port is not enabled */
3203                 port->flags |= ASYNC_NORMAL_ACTIVE;
3204                 return 0;
3205         }
3206
3207         if (tty->termios->c_cflag & CLOCAL)
3208                 do_clocal = true;
3209
3210         /* Wait for carrier detect and the line to become
3211          * free (i.e., not in use by the callout).  While we are in
3212          * this loop, port->count is dropped by one, so that
3213          * close() knows when to free things.  We restore it upon
3214          * exit, either normal or abnormal.
3215          */
3216
3217         retval = 0;
3218         add_wait_queue(&port->open_wait, &wait);
3219
3220         spin_lock_irqsave(&info->lock, flags);
3221         if (!tty_hung_up_p(filp)) {
3222                 extra_count = true;
3223                 port->count--;
3224         }
3225         spin_unlock_irqrestore(&info->lock, flags);
3226         port->blocked_open++;
3227
3228         while (1) {
3229                 if ((tty->termios->c_cflag & CBAUD))
3230                         tty_port_raise_dtr_rts(port);
3231
3232                 set_current_state(TASK_INTERRUPTIBLE);
3233
3234                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3235                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3236                                         -EAGAIN : -ERESTARTSYS;
3237                         break;
3238                 }
3239
3240                 cd = tty_port_carrier_raised(port);
3241
3242                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3243                         break;
3244
3245                 if (signal_pending(current)) {
3246                         retval = -ERESTARTSYS;
3247                         break;
3248                 }
3249
3250                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3251                 tty_unlock();
3252                 schedule();
3253                 tty_lock();
3254         }
3255
3256         set_current_state(TASK_RUNNING);
3257         remove_wait_queue(&port->open_wait, &wait);
3258
3259         if (extra_count)
3260                 port->count++;
3261         port->blocked_open--;
3262
3263         if (!retval)
3264                 port->flags |= ASYNC_NORMAL_ACTIVE;
3265
3266         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3267         return retval;
3268 }
3269
3270 static int alloc_tmp_rbuf(struct slgt_info *info)
3271 {
3272         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3273         if (info->tmp_rbuf == NULL)
3274                 return -ENOMEM;
3275         return 0;
3276 }
3277
3278 static void free_tmp_rbuf(struct slgt_info *info)
3279 {
3280         kfree(info->tmp_rbuf);
3281         info->tmp_rbuf = NULL;
3282 }
3283
3284 /*
3285  * allocate DMA descriptor lists.
3286  */
3287 static int alloc_desc(struct slgt_info *info)
3288 {
3289         unsigned int i;
3290         unsigned int pbufs;
3291
3292         /* allocate memory to hold descriptor lists */
3293         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3294         if (info->bufs == NULL)
3295                 return -ENOMEM;
3296
3297         memset(info->bufs, 0, DESC_LIST_SIZE);
3298
3299         info->rbufs = (struct slgt_desc*)info->bufs;
3300         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3301
3302         pbufs = (unsigned int)info->bufs_dma_addr;
3303
3304         /*
3305          * Build circular lists of descriptors
3306          */
3307
3308         for (i=0; i < info->rbuf_count; i++) {
3309                 /* physical address of this descriptor */
3310                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3311
3312                 /* physical address of next descriptor */
3313                 if (i == info->rbuf_count - 1)
3314                         info->rbufs[i].next = cpu_to_le32(pbufs);
3315                 else
3316                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3317                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3318         }
3319
3320         for (i=0; i < info->tbuf_count; i++) {
3321                 /* physical address of this descriptor */
3322                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3323
3324                 /* physical address of next descriptor */
3325                 if (i == info->tbuf_count - 1)
3326                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3327                 else
3328                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3329         }
3330
3331         return 0;
3332 }
3333
3334 static void free_desc(struct slgt_info *info)
3335 {
3336         if (info->bufs != NULL) {
3337                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3338                 info->bufs  = NULL;
3339                 info->rbufs = NULL;
3340                 info->tbufs = NULL;
3341         }
3342 }
3343
3344 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3345 {
3346         int i;
3347         for (i=0; i < count; i++) {
3348                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3349                         return -ENOMEM;
3350                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3351         }
3352         return 0;
3353 }
3354
3355 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3356 {
3357         int i;
3358         for (i=0; i < count; i++) {
3359                 if (bufs[i].buf == NULL)
3360                         continue;
3361                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3362                 bufs[i].buf = NULL;
3363         }
3364 }
3365
3366 static int alloc_dma_bufs(struct slgt_info *info)
3367 {
3368         info->rbuf_count = 32;
3369         info->tbuf_count = 32;
3370
3371         if (alloc_desc(info) < 0 ||
3372             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3373             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3374             alloc_tmp_rbuf(info) < 0) {
3375                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3376                 return -ENOMEM;
3377         }
3378         reset_rbufs(info);
3379         return 0;
3380 }
3381
3382 static void free_dma_bufs(struct slgt_info *info)
3383 {
3384         if (info->bufs) {
3385                 free_bufs(info, info->rbufs, info->rbuf_count);
3386                 free_bufs(info, info->tbufs, info->tbuf_count);
3387                 free_desc(info);
3388         }
3389         free_tmp_rbuf(info);
3390 }
3391
3392 static int claim_resources(struct slgt_info *info)
3393 {
3394         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3395                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3396                         info->device_name, info->phys_reg_addr));
3397                 info->init_error = DiagStatus_AddressConflict;
3398                 goto errout;
3399         }
3400         else
3401                 info->reg_addr_requested = true;
3402
3403         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3404         if (!info->reg_addr) {
3405                 DBGERR(("%s cant map device registers, addr=%08X\n",
3406                         info->device_name, info->phys_reg_addr));
3407                 info->init_error = DiagStatus_CantAssignPciResources;
3408                 goto errout;
3409         }
3410         return 0;
3411
3412 errout:
3413         release_resources(info);
3414         return -ENODEV;
3415 }
3416
3417 static void release_resources(struct slgt_info *info)
3418 {
3419         if (info->irq_requested) {
3420                 free_irq(info->irq_level, info);
3421                 info->irq_requested = false;
3422         }
3423
3424         if (info->reg_addr_requested) {
3425                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3426                 info->reg_addr_requested = false;
3427         }
3428
3429         if (info->reg_addr) {
3430                 iounmap(info->reg_addr);
3431                 info->reg_addr = NULL;
3432         }
3433 }
3434
3435 /* Add the specified device instance data structure to the
3436  * global linked list of devices and increment the device count.
3437  */
3438 static void add_device(struct slgt_info *info)
3439 {
3440         char *devstr;
3441
3442         info->next_device = NULL;
3443         info->line = slgt_device_count;
3444         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3445
3446         if (info->line < MAX_DEVICES) {
3447                 if (maxframe[info->line])
3448                         info->max_frame_size = maxframe[info->line];
3449         }
3450
3451         slgt_device_count++;
3452
3453         if (!slgt_device_list)
3454                 slgt_device_list = info;
3455         else {
3456                 struct slgt_info *current_dev = slgt_device_list;
3457                 while(current_dev->next_device)
3458                         current_dev = current_dev->next_device;
3459                 current_dev->next_device = info;
3460         }
3461
3462         if (info->max_frame_size < 4096)
3463                 info->max_frame_size = 4096;
3464         else if (info->max_frame_size > 65535)
3465                 info->max_frame_size = 65535;
3466
3467         switch(info->pdev->device) {
3468         case SYNCLINK_GT_DEVICE_ID:
3469                 devstr = "GT";
3470                 break;
3471         case SYNCLINK_GT2_DEVICE_ID:
3472                 devstr = "GT2";
3473                 break;
3474         case SYNCLINK_GT4_DEVICE_ID:
3475                 devstr = "GT4";
3476                 break;
3477         case SYNCLINK_AC_DEVICE_ID:
3478                 devstr = "AC";
3479                 info->params.mode = MGSL_MODE_ASYNC;
3480                 break;
3481         default:
3482                 devstr = "(unknown model)";
3483         }
3484         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3485                 devstr, info->device_name, info->phys_reg_addr,
3486                 info->irq_level, info->max_frame_size);
3487
3488 #if SYNCLINK_GENERIC_HDLC
3489         hdlcdev_init(info);
3490 #endif
3491 }
3492
3493 static const struct tty_port_operations slgt_port_ops = {
3494         .carrier_raised = carrier_raised,
3495         .dtr_rts = dtr_rts,
3496 };
3497
3498 /*
3499  *  allocate device instance structure, return NULL on failure
3500  */
3501 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3502 {
3503         struct slgt_info *info;
3504
3505         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3506
3507         if (!info) {
3508                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3509                         driver_name, adapter_num, port_num));
3510         } else {
3511                 tty_port_init(&info->port);
3512                 info->port.ops = &slgt_port_ops;
3513                 info->magic = MGSL_MAGIC;
3514                 INIT_WORK(&info->task, bh_handler);
3515                 info->max_frame_size = 4096;
3516                 info->base_clock = 14745600;
3517                 info->rbuf_fill_level = DMABUFSIZE;
3518                 info->port.close_delay = 5*HZ/10;
3519                 info->port.closing_wait = 30*HZ;
3520                 init_waitqueue_head(&info->status_event_wait_q);
3521                 init_waitqueue_head(&info->event_wait_q);
3522                 spin_lock_init(&info->netlock);
3523                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3524                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3525                 info->adapter_num = adapter_num;
3526                 info->port_num = port_num;
3527
3528                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3529                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3530
3531                 /* Copy configuration info to device instance data */
3532                 info->pdev = pdev;
3533                 info->irq_level = pdev->irq;
3534                 info->phys_reg_addr = pci_resource_start(pdev,0);
3535
3536                 info->bus_type = MGSL_BUS_TYPE_PCI;
3537                 info->irq_flags = IRQF_SHARED;
3538
3539                 info->init_error = -1; /* assume error, set to 0 on successful init */
3540         }
3541
3542         return info;
3543 }
3544
3545 static void device_init(int adapter_num, struct pci_dev *pdev)
3546 {
3547         struct slgt_info *port_array[SLGT_MAX_PORTS];
3548         int i;
3549         int port_count = 1;
3550
3551         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3552                 port_count = 2;
3553         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3554                 port_count = 4;
3555
3556         /* allocate device instances for all ports */
3557         for (i=0; i < port_count; ++i) {
3558                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3559                 if (port_array[i] == NULL) {
3560                         for (--i; i >= 0; --i)
3561                                 kfree(port_array[i]);
3562                         return;
3563                 }
3564         }
3565
3566         /* give copy of port_array to all ports and add to device list  */
3567         for (i=0; i < port_count; ++i) {
3568                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3569                 add_device(port_array[i]);
3570                 port_array[i]->port_count = port_count;
3571                 spin_lock_init(&port_array[i]->lock);
3572         }
3573
3574         /* Allocate and claim adapter resources */
3575         if (!claim_resources(port_array[0])) {
3576
3577                 alloc_dma_bufs(port_array[0]);
3578
3579                 /* copy resource information from first port to others */
3580                 for (i = 1; i < port_count; ++i) {
3581                         port_array[i]->lock      = port_array[0]->lock;
3582                         port_array[i]->irq_level = port_array[0]->irq_level;
3583                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3584                         alloc_dma_bufs(port_array[i]);
3585                 }
3586
3587                 if (request_irq(port_array[0]->irq_level,
3588                                         slgt_interrupt,
3589                                         port_array[0]->irq_flags,
3590                                         port_array[0]->device_name,
3591                                         port_array[0]) < 0) {
3592                         DBGERR(("%s request_irq failed IRQ=%d\n",
3593                                 port_array[0]->device_name,
3594                                 port_array[0]->irq_level));
3595                 } else {
3596                         port_array[0]->irq_requested = true;
3597                         adapter_test(port_array[0]);
3598                         for (i=1 ; i < port_count ; i++) {
3599                                 port_array[i]->init_error = port_array[0]->init_error;
3600                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3601                         }
3602                 }
3603         }
3604
3605         for (i=0; i < port_count; ++i)
3606                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3607 }
3608
3609 static int __devinit init_one(struct pci_dev *dev,
3610                               const struct pci_device_id *ent)
3611 {
3612         if (pci_enable_device(dev)) {
3613                 printk("error enabling pci device %p\n", dev);
3614                 return -EIO;
3615         }
3616         pci_set_master(dev);
3617         device_init(slgt_device_count, dev);
3618         return 0;
3619 }
3620
3621 static void __devexit remove_one(struct pci_dev *dev)
3622 {
3623 }
3624
3625 static const struct tty_operations ops = {
3626         .open = open,
3627         .close = close,
3628         .write = write,
3629         .put_char = put_char,
3630         .flush_chars = flush_chars,
3631         .write_room = write_room,
3632         .chars_in_buffer = chars_in_buffer,
3633         .flush_buffer = flush_buffer,
3634         .ioctl = ioctl,
3635         .compat_ioctl = slgt_compat_ioctl,
3636         .throttle = throttle,
3637         .unthrottle = unthrottle,
3638         .send_xchar = send_xchar,
3639         .break_ctl = set_break,
3640         .wait_until_sent = wait_until_sent,
3641         .set_termios = set_termios,
3642         .stop = tx_hold,
3643         .start = tx_release,
3644         .hangup = hangup,
3645         .tiocmget = tiocmget,
3646         .tiocmset = tiocmset,
3647         .get_icount = get_icount,
3648         .proc_fops = &synclink_gt_proc_fops,
3649 };
3650
3651 static void slgt_cleanup(void)
3652 {
3653         int rc;
3654         struct slgt_info *info;
3655         struct slgt_info *tmp;
3656
3657         printk(KERN_INFO "unload %s\n", driver_name);
3658
3659         if (serial_driver) {
3660                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3661                         tty_unregister_device(serial_driver, info->line);
3662                 if ((rc = tty_unregister_driver(serial_driver)))
3663                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3664                 put_tty_driver(serial_driver);
3665         }
3666
3667         /* reset devices */
3668         info = slgt_device_list;
3669         while(info) {
3670                 reset_port(info);
3671                 info = info->next_device;
3672         }
3673
3674         /* release devices */
3675         info = slgt_device_list;
3676         while(info) {
3677 #if SYNCLINK_GENERIC_HDLC
3678                 hdlcdev_exit(info);
3679 #endif
3680                 free_dma_bufs(info);
3681                 free_tmp_rbuf(info);
3682                 if (info->port_num == 0)
3683                         release_resources(info);
3684                 tmp = info;
3685                 info = info->next_device;
3686                 kfree(tmp);
3687         }
3688
3689         if (pci_registered)
3690                 pci_unregister_driver(&pci_driver);
3691 }
3692
3693 /*
3694  *  Driver initialization entry point.
3695  */
3696 static int __init slgt_init(void)
3697 {
3698         int rc;
3699
3700         printk(KERN_INFO "%s\n", driver_name);
3701
3702         serial_driver = alloc_tty_driver(MAX_DEVICES);
3703         if (!serial_driver) {
3704                 printk("%s can't allocate tty driver\n", driver_name);
3705                 return -ENOMEM;
3706         }
3707
3708         /* Initialize the tty_driver structure */
3709
3710         serial_driver->owner = THIS_MODULE;
3711         serial_driver->driver_name = tty_driver_name;
3712         serial_driver->name = tty_dev_prefix;
3713         serial_driver->major = ttymajor;
3714         serial_driver->minor_start = 64;
3715         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3716         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3717         serial_driver->init_termios = tty_std_termios;
3718         serial_driver->init_termios.c_cflag =
3719                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3720         serial_driver->init_termios.c_ispeed = 9600;
3721         serial_driver->init_termios.c_ospeed = 9600;
3722         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3723         tty_set_operations(serial_driver, &ops);
3724         if ((rc = tty_register_driver(serial_driver)) < 0) {
3725                 DBGERR(("%s can't register serial driver\n", driver_name));
3726                 put_tty_driver(serial_driver);
3727                 serial_driver = NULL;
3728                 goto error;
3729         }
3730
3731         printk(KERN_INFO "%s, tty major#%d\n",
3732                driver_name, serial_driver->major);
3733
3734         slgt_device_count = 0;
3735         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3736                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3737                 goto error;
3738         }
3739         pci_registered = true;
3740
3741         if (!slgt_device_list)
3742                 printk("%s no devices found\n",driver_name);
3743
3744         return 0;
3745
3746 error:
3747         slgt_cleanup();
3748         return rc;
3749 }
3750
3751 static void __exit slgt_exit(void)
3752 {
3753         slgt_cleanup();
3754 }
3755
3756 module_init(slgt_init);
3757 module_exit(slgt_exit);
3758
3759 /*
3760  * register access routines
3761  */
3762
3763 #define CALC_REGADDR() \
3764         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3765         if (addr >= 0x80) \
3766                 reg_addr += (info->port_num) * 32;
3767
3768 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3769 {
3770         CALC_REGADDR();
3771         return readb((void __iomem *)reg_addr);
3772 }
3773
3774 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3775 {
3776         CALC_REGADDR();
3777         writeb(value, (void __iomem *)reg_addr);
3778 }
3779
3780 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3781 {
3782         CALC_REGADDR();
3783         return readw((void __iomem *)reg_addr);
3784 }
3785
3786 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3787 {
3788         CALC_REGADDR();
3789         writew(value, (void __iomem *)reg_addr);
3790 }
3791
3792 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3793 {
3794         CALC_REGADDR();
3795         return readl((void __iomem *)reg_addr);
3796 }
3797
3798 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3799 {
3800         CALC_REGADDR();
3801         writel(value, (void __iomem *)reg_addr);
3802 }
3803
3804 static void rdma_reset(struct slgt_info *info)
3805 {
3806         unsigned int i;
3807
3808         /* set reset bit */
3809         wr_reg32(info, RDCSR, BIT1);
3810
3811         /* wait for enable bit cleared */
3812         for(i=0 ; i < 1000 ; i++)
3813                 if (!(rd_reg32(info, RDCSR) & BIT0))
3814                         break;
3815 }
3816
3817 static void tdma_reset(struct slgt_info *info)
3818 {
3819         unsigned int i;
3820
3821         /* set reset bit */
3822         wr_reg32(info, TDCSR, BIT1);
3823
3824         /* wait for enable bit cleared */
3825         for(i=0 ; i < 1000 ; i++)
3826                 if (!(rd_reg32(info, TDCSR) & BIT0))
3827                         break;
3828 }
3829
3830 /*
3831  * enable internal loopback
3832  * TxCLK and RxCLK are generated from BRG
3833  * and TxD is looped back to RxD internally.
3834  */
3835 static void enable_loopback(struct slgt_info *info)
3836 {
3837         /* SCR (serial control) BIT2=looopback enable */
3838         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3839
3840         if (info->params.mode != MGSL_MODE_ASYNC) {
3841                 /* CCR (clock control)
3842                  * 07..05  tx clock source (010 = BRG)
3843                  * 04..02  rx clock source (010 = BRG)
3844                  * 01      auxclk enable   (0 = disable)
3845                  * 00      BRG enable      (1 = enable)
3846                  *
3847                  * 0100 1001
3848                  */
3849                 wr_reg8(info, CCR, 0x49);
3850
3851                 /* set speed if available, otherwise use default */
3852                 if (info->params.clock_speed)
3853                         set_rate(info, info->params.clock_speed);
3854                 else
3855                         set_rate(info, 3686400);
3856         }
3857 }
3858
3859 /*
3860  *  set baud rate generator to specified rate
3861  */
3862 static void set_rate(struct slgt_info *info, u32 rate)
3863 {
3864         unsigned int div;
3865         unsigned int osc = info->base_clock;
3866
3867         /* div = osc/rate - 1
3868          *
3869          * Round div up if osc/rate is not integer to
3870          * force to next slowest rate.
3871          */
3872
3873         if (rate) {
3874                 div = osc/rate;
3875                 if (!(osc % rate) && div)
3876                         div--;
3877                 wr_reg16(info, BDR, (unsigned short)div);
3878         }
3879 }
3880
3881 static void rx_stop(struct slgt_info *info)
3882 {
3883         unsigned short val;
3884
3885         /* disable and reset receiver */
3886         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3887         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3888         wr_reg16(info, RCR, val);                  /* clear reset bit */
3889
3890         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3891
3892         /* clear pending rx interrupts */
3893         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3894
3895         rdma_reset(info);
3896
3897         info->rx_enabled = false;
3898         info->rx_restart = false;
3899 }
3900
3901 static void rx_start(struct slgt_info *info)
3902 {
3903         unsigned short val;
3904
3905         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3906
3907         /* clear pending rx overrun IRQ */
3908         wr_reg16(info, SSR, IRQ_RXOVER);
3909
3910         /* reset and disable receiver */
3911         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3912         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3913         wr_reg16(info, RCR, val);                  /* clear reset bit */
3914
3915         rdma_reset(info);
3916         reset_rbufs(info);
3917
3918         if (info->rx_pio) {
3919                 /* rx request when rx FIFO not empty */
3920                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3921                 slgt_irq_on(info, IRQ_RXDATA);
3922                 if (info->params.mode == MGSL_MODE_ASYNC) {
3923                         /* enable saving of rx status */
3924                         wr_reg32(info, RDCSR, BIT6);
3925                 }
3926         } else {
3927                 /* rx request when rx FIFO half full */
3928                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3929                 /* set 1st descriptor address */
3930                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3931
3932                 if (info->params.mode != MGSL_MODE_ASYNC) {
3933                         /* enable rx DMA and DMA interrupt */
3934                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3935                 } else {
3936                         /* enable saving of rx status, rx DMA and DMA interrupt */
3937                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3938                 }
3939         }
3940
3941         slgt_irq_on(info, IRQ_RXOVER);
3942
3943         /* enable receiver */
3944         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3945
3946         info->rx_restart = false;
3947         info->rx_enabled = true;
3948 }
3949
3950 static void tx_start(struct slgt_info *info)
3951 {
3952         if (!info->tx_enabled) {
3953                 wr_reg16(info, TCR,
3954                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3955                 info->tx_enabled = true;
3956         }
3957
3958         if (desc_count(info->tbufs[info->tbuf_start])) {
3959                 info->drop_rts_on_tx_done = false;
3960
3961                 if (info->params.mode != MGSL_MODE_ASYNC) {
3962                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3963                                 get_signals(info);
3964                                 if (!(info->signals & SerialSignal_RTS)) {
3965                                         info->signals |= SerialSignal_RTS;
3966                                         set_signals(info);
3967                                         info->drop_rts_on_tx_done = true;
3968                                 }
3969                         }
3970
3971                         slgt_irq_off(info, IRQ_TXDATA);
3972                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3973                         /* clear tx idle and underrun status bits */
3974                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3975                 } else {
3976                         slgt_irq_off(info, IRQ_TXDATA);
3977                         slgt_irq_on(info, IRQ_TXIDLE);
3978                         /* clear tx idle status bit */
3979                         wr_reg16(info, SSR, IRQ_TXIDLE);
3980                 }
3981                 /* set 1st descriptor address and start DMA */
3982                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3983                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3984                 info->tx_active = true;
3985         }
3986 }
3987
3988 static void tx_stop(struct slgt_info *info)
3989 {
3990         unsigned short val;
3991
3992         del_timer(&info->tx_timer);
3993
3994         tdma_reset(info);
3995
3996         /* reset and disable transmitter */
3997         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3998         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3999
4000         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4001
4002         /* clear tx idle and underrun status bit */
4003         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4004
4005         reset_tbufs(info);
4006
4007         info->tx_enabled = false;
4008         info->tx_active = false;
4009 }
4010
4011 static void reset_port(struct slgt_info *info)
4012 {
4013         if (!info->reg_addr)
4014                 return;
4015
4016         tx_stop(info);
4017         rx_stop(info);
4018
4019         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4020         set_signals(info);
4021
4022         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4023 }
4024
4025 static void reset_adapter(struct slgt_info *info)
4026 {
4027         int i;
4028         for (i=0; i < info->port_count; ++i) {
4029                 if (info->port_array[i])
4030                         reset_port(info->port_array[i]);
4031         }
4032 }
4033
4034 static void async_mode(struct slgt_info *info)
4035 {
4036         unsigned short val;
4037
4038         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4039         tx_stop(info);
4040         rx_stop(info);
4041
4042         /* TCR (tx control)
4043          *
4044          * 15..13  mode, 010=async
4045          * 12..10  encoding, 000=NRZ
4046          * 09      parity enable
4047          * 08      1=odd parity, 0=even parity
4048          * 07      1=RTS driver control
4049          * 06      1=break enable
4050          * 05..04  character length
4051          *         00=5 bits
4052          *         01=6 bits
4053          *         10=7 bits
4054          *         11=8 bits
4055          * 03      0=1 stop bit, 1=2 stop bits
4056          * 02      reset
4057          * 01      enable
4058          * 00      auto-CTS enable
4059          */
4060         val = 0x4000;
4061
4062         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4063                 val |= BIT7;
4064
4065         if (info->params.parity != ASYNC_PARITY_NONE) {
4066                 val |= BIT9;
4067                 if (info->params.parity == ASYNC_PARITY_ODD)
4068                         val |= BIT8;
4069         }
4070
4071         switch (info->params.data_bits)
4072         {
4073         case 6: val |= BIT4; break;
4074         case 7: val |= BIT5; break;
4075         case 8: val |= BIT5 + BIT4; break;
4076         }
4077
4078         if (info->params.stop_bits != 1)
4079                 val |= BIT3;
4080
4081         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4082                 val |= BIT0;
4083
4084         wr_reg16(info, TCR, val);
4085
4086         /* RCR (rx control)
4087          *
4088          * 15..13  mode, 010=async
4089          * 12..10  encoding, 000=NRZ
4090          * 09      parity enable
4091          * 08      1=odd parity, 0=even parity
4092          * 07..06  reserved, must be 0
4093          * 05..04  character length
4094          *         00=5 bits
4095          *         01=6 bits
4096          *         10=7 bits
4097          *         11=8 bits
4098          * 03      reserved, must be zero
4099          * 02      reset
4100          * 01      enable
4101          * 00      auto-DCD enable
4102          */
4103         val = 0x4000;
4104
4105         if (info->params.parity != ASYNC_PARITY_NONE) {
4106                 val |= BIT9;
4107                 if (info->params.parity == ASYNC_PARITY_ODD)
4108                         val |= BIT8;
4109         }
4110
4111         switch (info->params.data_bits)
4112         {
4113         case 6: val |= BIT4; break;
4114         case 7: val |= BIT5; break;
4115         case 8: val |= BIT5 + BIT4; break;
4116         }
4117
4118         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4119                 val |= BIT0;
4120
4121         wr_reg16(info, RCR, val);
4122
4123         /* CCR (clock control)
4124          *
4125          * 07..05  011 = tx clock source is BRG/16
4126          * 04..02  010 = rx clock source is BRG
4127          * 01      0 = auxclk disabled
4128          * 00      1 = BRG enabled
4129          *
4130          * 0110 1001
4131          */
4132         wr_reg8(info, CCR, 0x69);
4133
4134         msc_set_vcr(info);
4135
4136         /* SCR (serial control)
4137          *
4138          * 15  1=tx req on FIFO half empty
4139          * 14  1=rx req on FIFO half full
4140          * 13  tx data  IRQ enable
4141          * 12  tx idle  IRQ enable
4142          * 11  rx break on IRQ enable
4143          * 10  rx data  IRQ enable
4144          * 09  rx break off IRQ enable
4145          * 08  overrun  IRQ enable
4146          * 07  DSR      IRQ enable
4147          * 06  CTS      IRQ enable
4148          * 05  DCD      IRQ enable
4149          * 04  RI       IRQ enable
4150          * 03  0=16x sampling, 1=8x sampling
4151          * 02  1=txd->rxd internal loopback enable
4152          * 01  reserved, must be zero
4153          * 00  1=master IRQ enable
4154          */
4155         val = BIT15 + BIT14 + BIT0;
4156         /* JCR[8] : 1 = x8 async mode feature available */
4157         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4158             ((info->base_clock < (info->params.data_rate * 16)) ||
4159              (info->base_clock % (info->params.data_rate * 16)))) {
4160                 /* use 8x sampling */
4161                 val |= BIT3;
4162                 set_rate(info, info->params.data_rate * 8);
4163         } else {
4164                 /* use 16x sampling */
4165                 set_rate(info, info->params.data_rate * 16);
4166         }
4167         wr_reg16(info, SCR, val);
4168
4169         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4170
4171         if (info->params.loopback)
4172                 enable_loopback(info);
4173 }
4174
4175 static void sync_mode(struct slgt_info *info)
4176 {
4177         unsigned short val;
4178
4179         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4180         tx_stop(info);
4181         rx_stop(info);
4182
4183         /* TCR (tx control)
4184          *
4185          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4186          * 12..10  encoding
4187          * 09      CRC enable
4188          * 08      CRC32
4189          * 07      1=RTS driver control
4190          * 06      preamble enable
4191          * 05..04  preamble length
4192          * 03      share open/close flag
4193          * 02      reset
4194          * 01      enable
4195          * 00      auto-CTS enable
4196          */
4197         val = BIT2;
4198
4199         switch(info->params.mode) {
4200         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4201         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4202         case MGSL_MODE_RAW:      val |= BIT13; break;
4203         }
4204         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4205                 val |= BIT7;
4206
4207         switch(info->params.encoding)
4208         {
4209         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4210         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4211         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4212         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4213         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4214         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4215         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4216         }
4217
4218         switch (info->params.crc_type & HDLC_CRC_MASK)
4219         {
4220         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4221         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4222         }
4223
4224         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4225                 val |= BIT6;
4226
4227         switch (info->params.preamble_length)
4228         {
4229         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4230         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4231         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4232         }
4233
4234         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4235                 val |= BIT0;
4236
4237         wr_reg16(info, TCR, val);
4238
4239         /* TPR (transmit preamble) */
4240
4241         switch (info->params.preamble)
4242         {
4243         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4244         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4245         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4246         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4247         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4248         default:                          val = 0x7e; break;
4249         }
4250         wr_reg8(info, TPR, (unsigned char)val);
4251
4252         /* RCR (rx control)
4253          *
4254          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4255          * 12..10  encoding
4256          * 09      CRC enable
4257          * 08      CRC32
4258          * 07..03  reserved, must be 0
4259          * 02      reset
4260          * 01      enable
4261          * 00      auto-DCD enable
4262          */
4263         val = 0;
4264
4265         switch(info->params.mode) {
4266         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4267         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4268         case MGSL_MODE_RAW:      val |= BIT13; break;
4269         }
4270
4271         switch(info->params.encoding)
4272         {
4273         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4274         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4275         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4276         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4277         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4278         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4279         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4280         }
4281
4282         switch (info->params.crc_type & HDLC_CRC_MASK)
4283         {
4284         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4285         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4286         }
4287
4288         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4289                 val |= BIT0;
4290
4291         wr_reg16(info, RCR, val);
4292
4293         /* CCR (clock control)
4294          *
4295          * 07..05  tx clock source
4296          * 04..02  rx clock source
4297          * 01      auxclk enable
4298          * 00      BRG enable
4299          */
4300         val = 0;
4301
4302         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4303         {
4304                 // when RxC source is DPLL, BRG generates 16X DPLL
4305                 // reference clock, so take TxC from BRG/16 to get
4306                 // transmit clock at actual data rate
4307                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4308                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4309                 else
4310                         val |= BIT6;    /* 010, txclk = BRG */
4311         }
4312         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4313                 val |= BIT7;    /* 100, txclk = DPLL Input */
4314         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4315                 val |= BIT5;    /* 001, txclk = RXC Input */
4316
4317         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4318                 val |= BIT3;    /* 010, rxclk = BRG */
4319         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4320                 val |= BIT4;    /* 100, rxclk = DPLL */
4321         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4322                 val |= BIT2;    /* 001, rxclk = TXC Input */
4323
4324         if (info->params.clock_speed)
4325                 val |= BIT1 + BIT0;
4326
4327         wr_reg8(info, CCR, (unsigned char)val);
4328
4329         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4330         {
4331                 // program DPLL mode
4332                 switch(info->params.encoding)
4333                 {
4334                 case HDLC_ENCODING_BIPHASE_MARK:
4335                 case HDLC_ENCODING_BIPHASE_SPACE:
4336                         val = BIT7; break;
4337                 case HDLC_ENCODING_BIPHASE_LEVEL:
4338                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4339                         val = BIT7 + BIT6; break;
4340                 default: val = BIT6;    // NRZ encodings
4341                 }
4342                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4343
4344                 // DPLL requires a 16X reference clock from BRG
4345                 set_rate(info, info->params.clock_speed * 16);
4346         }
4347         else
4348                 set_rate(info, info->params.clock_speed);
4349
4350         tx_set_idle(info);
4351
4352         msc_set_vcr(info);
4353
4354         /* SCR (serial control)
4355          *
4356          * 15  1=tx req on FIFO half empty
4357          * 14  1=rx req on FIFO half full
4358          * 13  tx data  IRQ enable
4359          * 12  tx idle  IRQ enable
4360          * 11  underrun IRQ enable
4361          * 10  rx data  IRQ enable
4362          * 09  rx idle  IRQ enable
4363          * 08  overrun  IRQ enable
4364          * 07  DSR      IRQ enable
4365          * 06  CTS      IRQ enable
4366          * 05  DCD      IRQ enable
4367          * 04  RI       IRQ enable
4368          * 03  reserved, must be zero
4369          * 02  1=txd->rxd internal loopback enable
4370          * 01  reserved, must be zero
4371          * 00  1=master IRQ enable
4372          */
4373         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4374
4375         if (info->params.loopback)
4376                 enable_loopback(info);
4377 }
4378
4379 /*
4380  *  set transmit idle mode
4381  */
4382 static void tx_set_idle(struct slgt_info *info)
4383 {
4384         unsigned char val;
4385         unsigned short tcr;
4386
4387         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4388          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4389          */
4390         tcr = rd_reg16(info, TCR);
4391         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4392                 /* disable preamble, set idle size to 16 bits */
4393                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4394                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4395                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4396         } else if (!(tcr & BIT6)) {
4397                 /* preamble is disabled, set idle size to 8 bits */
4398                 tcr &= ~(BIT5 + BIT4);
4399         }
4400         wr_reg16(info, TCR, tcr);
4401
4402         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4403                 /* LSB of custom tx idle specified in tx idle register */
4404                 val = (unsigned char)(info->idle_mode & 0xff);
4405         } else {
4406                 /* standard 8 bit idle patterns */
4407                 switch(info->idle_mode)
4408                 {
4409                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4410                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4411                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4412                 case HDLC_TXIDLE_ZEROS:
4413                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4414                 default:                         val = 0xff;
4415                 }
4416         }
4417
4418         wr_reg8(info, TIR, val);
4419 }
4420
4421 /*
4422  * get state of V24 status (input) signals
4423  */
4424 static void get_signals(struct slgt_info *info)
4425 {
4426         unsigned short status = rd_reg16(info, SSR);
4427
4428         /* clear all serial signals except DTR and RTS */
4429         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4430
4431         if (status & BIT3)
4432                 info->signals |= SerialSignal_DSR;
4433         if (status & BIT2)
4434                 info->signals |= SerialSignal_CTS;
4435         if (status & BIT1)
4436                 info->signals |= SerialSignal_DCD;
4437         if (status & BIT0)
4438                 info->signals |= SerialSignal_RI;
4439 }
4440
4441 /*
4442  * set V.24 Control Register based on current configuration
4443  */
4444 static void msc_set_vcr(struct slgt_info *info)
4445 {
4446         unsigned char val = 0;
4447
4448         /* VCR (V.24 control)
4449          *
4450          * 07..04  serial IF select
4451          * 03      DTR
4452          * 02      RTS
4453          * 01      LL
4454          * 00      RL
4455          */
4456
4457         switch(info->if_mode & MGSL_INTERFACE_MASK)
4458         {
4459         case MGSL_INTERFACE_RS232:
4460                 val |= BIT5; /* 0010 */
4461                 break;
4462         case MGSL_INTERFACE_V35:
4463                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4464                 break;
4465         case MGSL_INTERFACE_RS422:
4466                 val |= BIT6; /* 0100 */
4467                 break;
4468         }
4469
4470         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4471                 val |= BIT4;
4472         if (info->signals & SerialSignal_DTR)
4473                 val |= BIT3;
4474         if (info->signals & SerialSignal_RTS)
4475                 val |= BIT2;
4476         if (info->if_mode & MGSL_INTERFACE_LL)
4477                 val |= BIT1;
4478         if (info->if_mode & MGSL_INTERFACE_RL)
4479                 val |= BIT0;
4480         wr_reg8(info, VCR, val);
4481 }
4482
4483 /*
4484  * set state of V24 control (output) signals
4485  */
4486 static void set_signals(struct slgt_info *info)
4487 {
4488         unsigned char val = rd_reg8(info, VCR);
4489         if (info->signals & SerialSignal_DTR)
4490                 val |= BIT3;
4491         else
4492                 val &= ~BIT3;
4493         if (info->signals & SerialSignal_RTS)
4494                 val |= BIT2;
4495         else
4496                 val &= ~BIT2;
4497         wr_reg8(info, VCR, val);
4498 }
4499
4500 /*
4501  * free range of receive DMA buffers (i to last)
4502  */
4503 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4504 {
4505         int done = 0;
4506
4507         while(!done) {
4508                 /* reset current buffer for reuse */
4509                 info->rbufs[i].status = 0;
4510                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4511                 if (i == last)
4512                         done = 1;
4513                 if (++i == info->rbuf_count)
4514                         i = 0;
4515         }
4516         info->rbuf_current = i;
4517 }
4518
4519 /*
4520  * mark all receive DMA buffers as free
4521  */
4522 static void reset_rbufs(struct slgt_info *info)
4523 {
4524         free_rbufs(info, 0, info->rbuf_count - 1);
4525         info->rbuf_fill_index = 0;
4526         info->rbuf_fill_count = 0;
4527 }
4528
4529 /*
4530  * pass receive HDLC frame to upper layer
4531  *
4532  * return true if frame available, otherwise false
4533  */
4534 static bool rx_get_frame(struct slgt_info *info)
4535 {
4536         unsigned int start, end;
4537         unsigned short status;
4538         unsigned int framesize = 0;
4539         unsigned long flags;
4540         struct tty_struct *tty = info->port.tty;
4541         unsigned char addr_field = 0xff;
4542         unsigned int crc_size = 0;
4543
4544         switch (info->params.crc_type & HDLC_CRC_MASK) {
4545         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4546         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4547         }
4548
4549 check_again:
4550
4551         framesize = 0;
4552         addr_field = 0xff;
4553         start = end = info->rbuf_current;
4554
4555         for (;;) {
4556                 if (!desc_complete(info->rbufs[end]))
4557                         goto cleanup;
4558
4559                 if (framesize == 0 && info->params.addr_filter != 0xff)
4560                         addr_field = info->rbufs[end].buf[0];
4561
4562                 framesize += desc_count(info->rbufs[end]);
4563
4564                 if (desc_eof(info->rbufs[end]))
4565                         break;
4566
4567                 if (++end == info->rbuf_count)
4568                         end = 0;
4569
4570                 if (end == info->rbuf_current) {
4571                         if (info->rx_enabled){
4572                                 spin_lock_irqsave(&info->lock,flags);
4573                                 rx_start(info);
4574                                 spin_unlock_irqrestore(&info->lock,flags);
4575                         }
4576                         goto cleanup;
4577                 }
4578         }
4579
4580         /* status
4581          *
4582          * 15      buffer complete
4583          * 14..06  reserved
4584          * 05..04  residue
4585          * 02      eof (end of frame)
4586          * 01      CRC error
4587          * 00      abort
4588          */
4589         status = desc_status(info->rbufs[end]);
4590
4591         /* ignore CRC bit if not using CRC (bit is undefined) */
4592         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4593                 status &= ~BIT1;
4594
4595         if (framesize == 0 ||
4596                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4597                 free_rbufs(info, start, end);
4598                 goto check_again;
4599         }
4600
4601         if (framesize < (2 + crc_size) || status & BIT0) {
4602                 info->icount.rxshort++;
4603                 framesize = 0;
4604         } else if (status & BIT1) {
4605                 info->icount.rxcrc++;
4606                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4607                         framesize = 0;
4608         }
4609
4610 #if SYNCLINK_GENERIC_HDLC
4611         if (framesize == 0) {
4612                 info->netdev->stats.rx_errors++;
4613                 info->netdev->stats.rx_frame_errors++;
4614         }
4615 #endif
4616
4617         DBGBH(("%s rx frame status=%04X size=%d\n",
4618                 info->device_name, status, framesize));
4619         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4620
4621         if (framesize) {
4622                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4623                         framesize -= crc_size;
4624                         crc_size = 0;
4625                 }
4626
4627                 if (framesize > info->max_frame_size + crc_size)
4628                         info->icount.rxlong++;
4629                 else {
4630                         /* copy dma buffer(s) to contiguous temp buffer */
4631                         int copy_count = framesize;
4632                         int i = start;
4633                         unsigned char *p = info->tmp_rbuf;
4634                         info->tmp_rbuf_count = framesize;
4635
4636                         info->icount.rxok++;
4637
4638                         while(copy_count) {
4639                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4640                                 memcpy(p, info->rbufs[i].buf, partial_count);
4641                                 p += partial_count;
4642                                 copy_count -= partial_count;
4643                                 if (++i == info->rbuf_count)
4644                                         i = 0;
4645                         }
4646
4647                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4648                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4649                                 framesize++;
4650                         }
4651
4652 #if SYNCLINK_GENERIC_HDLC
4653                         if (info->netcount)
4654                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4655                         else
4656 #endif
4657                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4658                 }
4659         }
4660         free_rbufs(info, start, end);
4661         return true;
4662
4663 cleanup:
4664         return false;
4665 }
4666
4667 /*
4668  * pass receive buffer (RAW synchronous mode) to tty layer
4669  * return true if buffer available, otherwise false
4670  */
4671 static bool rx_get_buf(struct slgt_info *info)
4672 {
4673         unsigned int i = info->rbuf_current;
4674         unsigned int count;
4675
4676         if (!desc_complete(info->rbufs[i]))
4677                 return false;
4678         count = desc_count(info->rbufs[i]);
4679         switch(info->params.mode) {
4680         case MGSL_MODE_MONOSYNC:
4681         case MGSL_MODE_BISYNC:
4682                 /* ignore residue in byte synchronous modes */
4683                 if (desc_residue(info->rbufs[i]))
4684                         count--;
4685                 break;
4686         }
4687         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4688         DBGINFO(("rx_get_buf size=%d\n", count));
4689         if (count)
4690                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4691                                   info->flag_buf, count);
4692         free_rbufs(info, i, i);
4693         return true;
4694 }
4695
4696 static void reset_tbufs(struct slgt_info *info)
4697 {
4698         unsigned int i;
4699         info->tbuf_current = 0;
4700         for (i=0 ; i < info->tbuf_count ; i++) {
4701                 info->tbufs[i].status = 0;
4702                 info->tbufs[i].count  = 0;
4703         }
4704 }
4705
4706 /*
4707  * return number of free transmit DMA buffers
4708  */
4709 static unsigned int free_tbuf_count(struct slgt_info *info)
4710 {
4711         unsigned int count = 0;
4712         unsigned int i = info->tbuf_current;
4713
4714         do
4715         {
4716                 if (desc_count(info->tbufs[i]))
4717                         break; /* buffer in use */
4718                 ++count;
4719                 if (++i == info->tbuf_count)
4720                         i=0;
4721         } while (i != info->tbuf_current);
4722
4723         /* if tx DMA active, last zero count buffer is in use */
4724         if (count && (rd_reg32(info, TDCSR) & BIT0))
4725                 --count;
4726
4727         return count;
4728 }
4729
4730 /*
4731  * return number of bytes in unsent transmit DMA buffers
4732  * and the serial controller tx FIFO
4733  */
4734 static unsigned int tbuf_bytes(struct slgt_info *info)
4735 {
4736         unsigned int total_count = 0;
4737         unsigned int i = info->tbuf_current;
4738         unsigned int reg_value;
4739         unsigned int count;
4740         unsigned int active_buf_count = 0;
4741
4742         /*
4743          * Add descriptor counts for all tx DMA buffers.
4744          * If count is zero (cleared by DMA controller after read),
4745          * the buffer is complete or is actively being read from.
4746          *
4747          * Record buf_count of last buffer with zero count starting
4748          * from current ring position. buf_count is mirror
4749          * copy of count and is not cleared by serial controller.
4750          * If DMA controller is active, that buffer is actively
4751          * being read so add to total.
4752          */
4753         do {
4754                 count = desc_count(info->tbufs[i]);
4755                 if (count)
4756                         total_count += count;
4757                 else if (!total_count)
4758                         active_buf_count = info->tbufs[i].buf_count;
4759                 if (++i == info->tbuf_count)
4760                         i = 0;
4761         } while (i != info->tbuf_current);
4762
4763         /* read tx DMA status register */
4764         reg_value = rd_reg32(info, TDCSR);
4765
4766         /* if tx DMA active, last zero count buffer is in use */
4767         if (reg_value & BIT0)
4768                 total_count += active_buf_count;
4769
4770         /* add tx FIFO count = reg_value[15..8] */
4771         total_count += (reg_value >> 8) & 0xff;
4772
4773         /* if transmitter active add one byte for shift register */
4774         if (info->tx_active)
4775                 total_count++;
4776
4777         return total_count;
4778 }
4779
4780 /*
4781  * load data into transmit DMA buffer ring and start transmitter if needed
4782  * return true if data accepted, otherwise false (buffers full)
4783  */
4784 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4785 {
4786         unsigned short count;
4787         unsigned int i;
4788         struct slgt_desc *d;
4789
4790         /* check required buffer space */
4791         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4792                 return false;
4793
4794         DBGDATA(info, buf, size, "tx");
4795
4796         /*
4797          * copy data to one or more DMA buffers in circular ring
4798          * tbuf_start   = first buffer for this data
4799          * tbuf_current = next free buffer
4800          *
4801          * Copy all data before making data visible to DMA controller by
4802          * setting descriptor count of the first buffer.
4803          * This prevents an active DMA controller from reading the first DMA
4804          * buffers of a frame and stopping before the final buffers are filled.
4805          */
4806
4807         info->tbuf_start = i = info->tbuf_current;
4808
4809         while (size) {
4810                 d = &info->tbufs[i];
4811
4812                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4813                 memcpy(d->buf, buf, count);
4814
4815                 size -= count;
4816                 buf  += count;
4817
4818                 /*
4819                  * set EOF bit for last buffer of HDLC frame or
4820                  * for every buffer in raw mode
4821                  */
4822                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4823                     info->params.mode == MGSL_MODE_RAW)
4824                         set_desc_eof(*d, 1);
4825                 else
4826                         set_desc_eof(*d, 0);
4827
4828                 /* set descriptor count for all but first buffer */
4829                 if (i != info->tbuf_start)
4830                         set_desc_count(*d, count);
4831                 d->buf_count = count;
4832
4833                 if (++i == info->tbuf_count)
4834                         i = 0;
4835         }
4836
4837         info->tbuf_current = i;
4838
4839         /* set first buffer count to make new data visible to DMA controller */
4840         d = &info->tbufs[info->tbuf_start];
4841         set_desc_count(*d, d->buf_count);
4842
4843         /* start transmitter if needed and update transmit timeout */
4844         if (!info->tx_active)
4845                 tx_start(info);
4846         update_tx_timer(info);
4847
4848         return true;
4849 }
4850
4851 static int register_test(struct slgt_info *info)
4852 {
4853         static unsigned short patterns[] =
4854                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4855         static unsigned int count = ARRAY_SIZE(patterns);
4856         unsigned int i;
4857         int rc = 0;
4858
4859         for (i=0 ; i < count ; i++) {
4860                 wr_reg16(info, TIR, patterns[i]);
4861                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4862                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4863                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4864                         rc = -ENODEV;
4865                         break;
4866                 }
4867         }
4868         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4869         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4870         return rc;
4871 }
4872
4873 static int irq_test(struct slgt_info *info)
4874 {
4875         unsigned long timeout;
4876         unsigned long flags;
4877         struct tty_struct *oldtty = info->port.tty;
4878         u32 speed = info->params.data_rate;
4879
4880         info->params.data_rate = 921600;
4881         info->port.tty = NULL;
4882
4883         spin_lock_irqsave(&info->lock, flags);
4884         async_mode(info);
4885         slgt_irq_on(info, IRQ_TXIDLE);
4886
4887         /* enable transmitter */
4888         wr_reg16(info, TCR,
4889                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4890
4891         /* write one byte and wait for tx idle */
4892         wr_reg16(info, TDR, 0);
4893
4894         /* assume failure */
4895         info->init_error = DiagStatus_IrqFailure;
4896         info->irq_occurred = false;
4897
4898         spin_unlock_irqrestore(&info->lock, flags);
4899
4900         timeout=100;
4901         while(timeout-- && !info->irq_occurred)
4902                 msleep_interruptible(10);
4903
4904         spin_lock_irqsave(&info->lock,flags);
4905         reset_port(info);
4906         spin_unlock_irqrestore(&info->lock,flags);
4907
4908         info->params.data_rate = speed;
4909         info->port.tty = oldtty;
4910
4911         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4912         return info->irq_occurred ? 0 : -ENODEV;
4913 }
4914
4915 static int loopback_test_rx(struct slgt_info *info)
4916 {
4917         unsigned char *src, *dest;
4918         int count;
4919
4920         if (desc_complete(info->rbufs[0])) {
4921                 count = desc_count(info->rbufs[0]);
4922                 src   = info->rbufs[0].buf;
4923                 dest  = info->tmp_rbuf;
4924
4925                 for( ; count ; count-=2, src+=2) {
4926                         /* src=data byte (src+1)=status byte */
4927                         if (!(*(src+1) & (BIT9 + BIT8))) {
4928                                 *dest = *src;
4929                                 dest++;
4930                                 info->tmp_rbuf_count++;
4931                         }
4932                 }
4933                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4934                 return 1;
4935         }
4936         return 0;
4937 }
4938
4939 static int loopback_test(struct slgt_info *info)
4940 {
4941 #define TESTFRAMESIZE 20
4942
4943         unsigned long timeout;
4944         u16 count = TESTFRAMESIZE;
4945         unsigned char buf[TESTFRAMESIZE];
4946         int rc = -ENODEV;
4947         unsigned long flags;
4948
4949         struct tty_struct *oldtty = info->port.tty;
4950         MGSL_PARAMS params;
4951
4952         memcpy(&params, &info->params, sizeof(params));
4953
4954         info->params.mode = MGSL_MODE_ASYNC;
4955         info->params.data_rate = 921600;
4956         info->params.loopback = 1;
4957         info->port.tty = NULL;
4958
4959         /* build and send transmit frame */
4960         for (count = 0; count < TESTFRAMESIZE; ++count)
4961                 buf[count] = (unsigned char)count;
4962
4963         info->tmp_rbuf_count = 0;
4964         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4965
4966         /* program hardware for HDLC and enabled receiver */
4967         spin_lock_irqsave(&info->lock,flags);
4968         async_mode(info);
4969         rx_start(info);
4970         tx_load(info, buf, count);
4971         spin_unlock_irqrestore(&info->lock, flags);
4972
4973         /* wait for receive complete */
4974         for (timeout = 100; timeout; --timeout) {
4975                 msleep_interruptible(10);
4976                 if (loopback_test_rx(info)) {
4977                         rc = 0;
4978                         break;
4979                 }
4980         }
4981
4982         /* verify received frame length and contents */
4983         if (!rc && (info->tmp_rbuf_count != count ||
4984                   memcmp(buf, info->tmp_rbuf, count))) {
4985                 rc = -ENODEV;
4986         }
4987
4988         spin_lock_irqsave(&info->lock,flags);
4989         reset_adapter(info);
4990         spin_unlock_irqrestore(&info->lock,flags);
4991
4992         memcpy(&info->params, &params, sizeof(info->params));
4993         info->port.tty = oldtty;
4994
4995         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4996         return rc;
4997 }
4998
4999 static int adapter_test(struct slgt_info *info)
5000 {
5001         DBGINFO(("testing %s\n", info->device_name));
5002         if (register_test(info) < 0) {
5003                 printk("register test failure %s addr=%08X\n",
5004                         info->device_name, info->phys_reg_addr);
5005         } else if (irq_test(info) < 0) {
5006                 printk("IRQ test failure %s IRQ=%d\n",
5007                         info->device_name, info->irq_level);
5008         } else if (loopback_test(info) < 0) {
5009                 printk("loopback test failure %s\n", info->device_name);
5010         }
5011         return info->init_error;
5012 }
5013
5014 /*
5015  * transmit timeout handler
5016  */
5017 static void tx_timeout(unsigned long context)
5018 {
5019         struct slgt_info *info = (struct slgt_info*)context;
5020         unsigned long flags;
5021
5022         DBGINFO(("%s tx_timeout\n", info->device_name));
5023         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5024                 info->icount.txtimeout++;
5025         }
5026         spin_lock_irqsave(&info->lock,flags);
5027         tx_stop(info);
5028         spin_unlock_irqrestore(&info->lock,flags);
5029
5030 #if SYNCLINK_GENERIC_HDLC
5031         if (info->netcount)
5032                 hdlcdev_tx_done(info);
5033         else
5034 #endif
5035                 bh_transmit(info);
5036 }
5037
5038 /*
5039  * receive buffer polling timer
5040  */
5041 static void rx_timeout(unsigned long context)
5042 {
5043         struct slgt_info *info = (struct slgt_info*)context;
5044         unsigned long flags;
5045
5046         DBGINFO(("%s rx_timeout\n", info->device_name));
5047         spin_lock_irqsave(&info->lock, flags);
5048         info->pending_bh |= BH_RECEIVE;
5049         spin_unlock_irqrestore(&info->lock, flags);
5050         bh_handler(&info->task);
5051 }
5052