drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.36 2006/08/28 20:47:14 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #include "linux/synclink.h"
  85
  86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  87 #define SYNCLINK_GENERIC_HDLC 1
  88 #else
  89 #define SYNCLINK_GENERIC_HDLC 0
  90 #endif
  91
  92 /*
  93  * module identification
  94  */
  95 static char *driver_name     = "SyncLink GT";
  96 static char *driver_version  = "$Revision: 4.36 $";
  97 static char *tty_driver_name = "synclink_gt";
  98 static char *tty_dev_prefix  = "ttySLG";
  99 MODULE_LICENSE("GPL");
 100 #define MGSL_MAGIC 0x5401
 101 #define MAX_DEVICES 32
 102
 103 static struct pci_device_id pci_table[] = {
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 108         {0,}, /* terminate list */
 109 };
 110 MODULE_DEVICE_TABLE(pci, pci_table);
 111
 112 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 113 static void remove_one(struct pci_dev *dev);
 114 static struct pci_driver pci_driver = {
 115         .name           = "synclink_gt",
 116         .id_table       = pci_table,
 117         .probe          = init_one,
 118         .remove         = __devexit_p(remove_one),
 119 };
 120
 121 static int pci_registered;
 122
 123 /*
 124  * module configuration and status
 125  */
 126 static struct slgt_info *slgt_device_list;
 127 static int slgt_device_count;
 128
 129 static int ttymajor;
 130 static int debug_level;
 131 static int maxframe[MAX_DEVICES];
 132 static int dosyncppp[MAX_DEVICES];
 133
 134 module_param(ttymajor, int, 0);
 135 module_param(debug_level, int, 0);
 136 module_param_array(maxframe, int, NULL, 0);
 137 module_param_array(dosyncppp, int, NULL, 0);
 138
 139 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 140 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 141 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 142 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 143
 144 /*
 145  * tty support and callbacks
 146  */
 147 static struct tty_driver *serial_driver;
 148
 149 static int  open(struct tty_struct *tty, struct file * filp);
 150 static void close(struct tty_struct *tty, struct file * filp);
 151 static void hangup(struct tty_struct *tty);
 152 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 153
 154 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 155 static void put_char(struct tty_struct *tty, unsigned char ch);
 156 static void send_xchar(struct tty_struct *tty, char ch);
 157 static void wait_until_sent(struct tty_struct *tty, int timeout);
 158 static int  write_room(struct tty_struct *tty);
 159 static void flush_chars(struct tty_struct *tty);
 160 static void flush_buffer(struct tty_struct *tty);
 161 static void tx_hold(struct tty_struct *tty);
 162 static void tx_release(struct tty_struct *tty);
 163
 164 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 165 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 166 static int  chars_in_buffer(struct tty_struct *tty);
 167 static void throttle(struct tty_struct * tty);
 168 static void unthrottle(struct tty_struct * tty);
 169 static void set_break(struct tty_struct *tty, int break_state);
 170
 171 /*
 172  * generic HDLC support and callbacks
 173  */
 174 #if SYNCLINK_GENERIC_HDLC
 175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 176 static void hdlcdev_tx_done(struct slgt_info *info);
 177 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 178 static int  hdlcdev_init(struct slgt_info *info);
 179 static void hdlcdev_exit(struct slgt_info *info);
 180 #endif
 181
 182
 183 /*
 184  * device specific structures, macros and functions
 185  */
 186
 187 #define SLGT_MAX_PORTS 4
 188 #define SLGT_REG_SIZE  256
 189
 190 /*
 191  * conditional wait facility
 192  */
 193 struct cond_wait {
 194         struct cond_wait *next;
 195         wait_queue_head_t q;
 196         wait_queue_t wait;
 197         unsigned int data;
 198 };
 199 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 200 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 202 static void flush_cond_wait(struct cond_wait **head);
 203
 204 /*
 205  * DMA buffer descriptor and access macros
 206  */
 207 struct slgt_desc
 208 {
 209         unsigned short count;
 210         unsigned short status;
 211         unsigned int pbuf;  /* physical address of data buffer */
 212         unsigned int next;  /* physical address of next descriptor */
 213
 214         /* driver book keeping */
 215         char *buf;          /* virtual  address of data buffer */
 216         unsigned int pdesc; /* physical address of this descriptor */
 217         dma_addr_t buf_dma_addr;
 218 };
 219
 220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 222 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 223 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 224 #define desc_count(a)      (le16_to_cpu((a).count))
 225 #define desc_status(a)     (le16_to_cpu((a).status))
 226 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 227 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 228 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 229 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 230 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 231
 232 struct _input_signal_events {
 233         int ri_up;
 234         int ri_down;
 235         int dsr_up;
 236         int dsr_down;
 237         int dcd_up;
 238         int dcd_down;
 239         int cts_up;
 240         int cts_down;
 241 };
 242
 243 /*
 244  * device instance data structure
 245  */
 246 struct slgt_info {
 247         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252         int flags;
 253
 254         char device_name[25];
 255         struct pci_dev *pdev;
 256
 257         int port_count;  /* count of ports on adapter */
 258         int adapter_num; /* adapter instance number */
 259         int port_num;    /* port instance number */
 260
 261         /* array of pointers to port contexts on this adapter */
 262         struct slgt_info *port_array[SLGT_MAX_PORTS];
 263
 264         int                     count;          /* count of opens */
 265         int                     line;           /* tty line instance number */
 266         unsigned short          close_delay;
 267         unsigned short          closing_wait;   /* time to wait before closing */
 268
 269         struct mgsl_icount      icount;
 270
 271         struct tty_struct       *tty;
 272         int                     timeout;
 273         int                     x_char;         /* xon/xoff character */
 274         int                     blocked_open;   /* # of blocked opens */
 275         unsigned int            read_status_mask;
 276         unsigned int            ignore_status_mask;
 277
 278         wait_queue_head_t       open_wait;
 279         wait_queue_head_t       close_wait;
 280
 281         wait_queue_head_t       status_event_wait_q;
 282         wait_queue_head_t       event_wait_q;
 283         struct timer_list       tx_timer;
 284         struct timer_list       rx_timer;
 285
 286         unsigned int            gpio_present;
 287         struct cond_wait        *gpio_wait_q;
 288
 289         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 290
 291         struct work_struct task;
 292         u32 pending_bh;
 293         int bh_requested;
 294         int bh_running;
 295
 296         int isr_overflow;
 297         int irq_requested;      /* nonzero if IRQ requested */
 298         int irq_occurred;       /* for diagnostics use */
 299
 300         /* device configuration */
 301
 302         unsigned int bus_type;
 303         unsigned int irq_level;
 304         unsigned long irq_flags;
 305
 306         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 307         u32 phys_reg_addr;
 308         int reg_addr_requested;
 309
 310         MGSL_PARAMS params;       /* communications parameters */
 311         u32 idle_mode;
 312         u32 max_frame_size;       /* as set by device config */
 313
 314         unsigned int raw_rx_size;
 315         unsigned int if_mode;
 316
 317         /* device status */
 318
 319         int rx_enabled;
 320         int rx_restart;
 321
 322         int tx_enabled;
 323         int tx_active;
 324
 325         unsigned char signals;    /* serial signal states */
 326         int init_error;  /* initialization error */
 327
 328         unsigned char *tx_buf;
 329         int tx_count;
 330
 331         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 332         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 333         BOOLEAN drop_rts_on_tx_done;
 334         struct  _input_signal_events    input_signal_events;
 335
 336         int dcd_chkcount;       /* check counts to prevent */
 337         int cts_chkcount;       /* too many IRQs if a signal */
 338         int dsr_chkcount;       /* is floating */
 339         int ri_chkcount;
 340
 341         char *bufs;             /* virtual address of DMA buffer lists */
 342         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 343
 344         unsigned int rbuf_count;
 345         struct slgt_desc *rbufs;
 346         unsigned int rbuf_current;
 347         unsigned int rbuf_index;
 348
 349         unsigned int tbuf_count;
 350         struct slgt_desc *tbufs;
 351         unsigned int tbuf_current;
 352         unsigned int tbuf_start;
 353
 354         unsigned char *tmp_rbuf;
 355         unsigned int tmp_rbuf_count;
 356
 357         /* SPPP/Cisco HDLC device parts */
 358
 359         int netcount;
 360         int dosyncppp;
 361         spinlock_t netlock;
 362 #if SYNCLINK_GENERIC_HDLC
 363         struct net_device *netdev;
 364 #endif
 365
 366 };
 367
 368 static MGSL_PARAMS default_params = {
 369         .mode            = MGSL_MODE_HDLC,
 370         .loopback        = 0,
 371         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 372         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 373         .clock_speed     = 0,
 374         .addr_filter     = 0xff,
 375         .crc_type        = HDLC_CRC_16_CCITT,
 376         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 377         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 378         .data_rate       = 9600,
 379         .data_bits       = 8,
 380         .stop_bits       = 1,
 381         .parity          = ASYNC_PARITY_NONE
 382 };
 383
 384
 385 #define BH_RECEIVE  1
 386 #define BH_TRANSMIT 2
 387 #define BH_STATUS   4
 388 #define IO_PIN_SHUTDOWN_LIMIT 100
 389
 390 #define DMABUFSIZE 256
 391 #define DESC_LIST_SIZE 4096
 392
 393 #define MASK_PARITY  BIT1
 394 #define MASK_FRAMING BIT0
 395 #define MASK_BREAK   BIT14
 396 #define MASK_OVERRUN BIT4
 397
 398 #define GSR   0x00 /* global status */
 399 #define JCR   0x04 /* JTAG control */
 400 #define IODR  0x08 /* GPIO direction */
 401 #define IOER  0x0c /* GPIO interrupt enable */
 402 #define IOVR  0x10 /* GPIO value */
 403 #define IOSR  0x14 /* GPIO interrupt status */
 404 #define TDR   0x80 /* tx data */
 405 #define RDR   0x80 /* rx data */
 406 #define TCR   0x82 /* tx control */
 407 #define TIR   0x84 /* tx idle */
 408 #define TPR   0x85 /* tx preamble */
 409 #define RCR   0x86 /* rx control */
 410 #define VCR   0x88 /* V.24 control */
 411 #define CCR   0x89 /* clock control */
 412 #define BDR   0x8a /* baud divisor */
 413 #define SCR   0x8c /* serial control */
 414 #define SSR   0x8e /* serial status */
 415 #define RDCSR 0x90 /* rx DMA control/status */
 416 #define TDCSR 0x94 /* tx DMA control/status */
 417 #define RDDAR 0x98 /* rx DMA descriptor address */
 418 #define TDDAR 0x9c /* tx DMA descriptor address */
 419
 420 #define RXIDLE      BIT14
 421 #define RXBREAK     BIT14
 422 #define IRQ_TXDATA  BIT13
 423 #define IRQ_TXIDLE  BIT12
 424 #define IRQ_TXUNDER BIT11 /* HDLC */
 425 #define IRQ_RXDATA  BIT10
 426 #define IRQ_RXIDLE  BIT9  /* HDLC */
 427 #define IRQ_RXBREAK BIT9  /* async */
 428 #define IRQ_RXOVER  BIT8
 429 #define IRQ_DSR     BIT7
 430 #define IRQ_CTS     BIT6
 431 #define IRQ_DCD     BIT5
 432 #define IRQ_RI      BIT4
 433 #define IRQ_ALL     0x3ff0
 434 #define IRQ_MASTER  BIT0
 435
 436 #define slgt_irq_on(info, mask) \
 437         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 438 #define slgt_irq_off(info, mask) \
 439         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 440
 441 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 442 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 443 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 444 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 445 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 446 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 447
 448 static void  msc_set_vcr(struct slgt_info *info);
 449
 450 static int  startup(struct slgt_info *info);
 451 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 452 static void shutdown(struct slgt_info *info);
 453 static void program_hw(struct slgt_info *info);
 454 static void change_params(struct slgt_info *info);
 455
 456 static int  register_test(struct slgt_info *info);
 457 static int  irq_test(struct slgt_info *info);
 458 static int  loopback_test(struct slgt_info *info);
 459 static int  adapter_test(struct slgt_info *info);
 460
 461 static void reset_adapter(struct slgt_info *info);
 462 static void reset_port(struct slgt_info *info);
 463 static void async_mode(struct slgt_info *info);
 464 static void sync_mode(struct slgt_info *info);
 465
 466 static void rx_stop(struct slgt_info *info);
 467 static void rx_start(struct slgt_info *info);
 468 static void reset_rbufs(struct slgt_info *info);
 469 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 470 static void rdma_reset(struct slgt_info *info);
 471 static int  rx_get_frame(struct slgt_info *info);
 472 static int  rx_get_buf(struct slgt_info *info);
 473
 474 static void tx_start(struct slgt_info *info);
 475 static void tx_stop(struct slgt_info *info);
 476 static void tx_set_idle(struct slgt_info *info);
 477 static unsigned int free_tbuf_count(struct slgt_info *info);
 478 static void reset_tbufs(struct slgt_info *info);
 479 static void tdma_reset(struct slgt_info *info);
 480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 481
 482 static void get_signals(struct slgt_info *info);
 483 static void set_signals(struct slgt_info *info);
 484 static void enable_loopback(struct slgt_info *info);
 485 static void set_rate(struct slgt_info *info, u32 data_rate);
 486
 487 static int  bh_action(struct slgt_info *info);
 488 static void bh_handler(struct work_struct *work);
 489 static void bh_transmit(struct slgt_info *info);
 490 static void isr_serial(struct slgt_info *info);
 491 static void isr_rdma(struct slgt_info *info);
 492 static void isr_txeom(struct slgt_info *info, unsigned short status);
 493 static void isr_tdma(struct slgt_info *info);
 494 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
 495
 496 static int  alloc_dma_bufs(struct slgt_info *info);
 497 static void free_dma_bufs(struct slgt_info *info);
 498 static int  alloc_desc(struct slgt_info *info);
 499 static void free_desc(struct slgt_info *info);
 500 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 501 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 502
 503 static int  alloc_tmp_rbuf(struct slgt_info *info);
 504 static void free_tmp_rbuf(struct slgt_info *info);
 505
 506 static void tx_timeout(unsigned long context);
 507 static void rx_timeout(unsigned long context);
 508
 509 /*
 510  * ioctl handlers
 511  */
 512 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 513 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 514 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 515 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 516 static int  set_txidle(struct slgt_info *info, int idle_mode);
 517 static int  tx_enable(struct slgt_info *info, int enable);
 518 static int  tx_abort(struct slgt_info *info);
 519 static int  rx_enable(struct slgt_info *info, int enable);
 520 static int  modem_input_wait(struct slgt_info *info,int arg);
 521 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 522 static int  tiocmget(struct tty_struct *tty, struct file *file);
 523 static int  tiocmset(struct tty_struct *tty, struct file *file,
 524                      unsigned int set, unsigned int clear);
 525 static void set_break(struct tty_struct *tty, int break_state);
 526 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 527 static int  set_interface(struct slgt_info *info, int if_mode);
 528 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 529 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 530 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 531
 532 /*
 533  * driver functions
 534  */
 535 static void add_device(struct slgt_info *info);
 536 static void device_init(int adapter_num, struct pci_dev *pdev);
 537 static int  claim_resources(struct slgt_info *info);
 538 static void release_resources(struct slgt_info *info);
 539
 540 /*
 541  * DEBUG OUTPUT CODE
 542  */
 543 #ifndef DBGINFO
 544 #define DBGINFO(fmt)
 545 #endif
 546 #ifndef DBGERR
 547 #define DBGERR(fmt)
 548 #endif
 549 #ifndef DBGBH
 550 #define DBGBH(fmt)
 551 #endif
 552 #ifndef DBGISR
 553 #define DBGISR(fmt)
 554 #endif
 555
 556 #ifdef DBGDATA
 557 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 558 {
 559         int i;
 560         int linecount;
 561         printk("%s %s data:\n",info->device_name, label);
 562         while(count) {
 563                 linecount = (count > 16) ? 16 : count;
 564                 for(i=0; i < linecount; i++)
 565                         printk("%02X ",(unsigned char)data[i]);
 566                 for(;i<17;i++)
 567                         printk("   ");
 568                 for(i=0;i<linecount;i++) {
 569                         if (data[i]>=040 && data[i]<=0176)
 570                                 printk("%c",data[i]);
 571                         else
 572                                 printk(".");
 573                 }
 574                 printk("\n");
 575                 data  += linecount;
 576                 count -= linecount;
 577         }
 578 }
 579 #else
 580 #define DBGDATA(info, buf, size, label)
 581 #endif
 582
 583 #ifdef DBGTBUF
 584 static void dump_tbufs(struct slgt_info *info)
 585 {
 586         int i;
 587         printk("tbuf_current=%d\n", info->tbuf_current);
 588         for (i=0 ; i < info->tbuf_count ; i++) {
 589                 printk("%d: count=%04X status=%04X\n",
 590                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 591         }
 592 }
 593 #else
 594 #define DBGTBUF(info)
 595 #endif
 596
 597 #ifdef DBGRBUF
 598 static void dump_rbufs(struct slgt_info *info)
 599 {
 600         int i;
 601         printk("rbuf_current=%d\n", info->rbuf_current);
 602         for (i=0 ; i < info->rbuf_count ; i++) {
 603                 printk("%d: count=%04X status=%04X\n",
 604                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 605         }
 606 }
 607 #else
 608 #define DBGRBUF(info)
 609 #endif
 610
 611 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 612 {
 613 #ifdef SANITY_CHECK
 614         if (!info) {
 615                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 616                 return 1;
 617         }
 618         if (info->magic != MGSL_MAGIC) {
 619                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 620                 return 1;
 621         }
 622 #else
 623         if (!info)
 624                 return 1;
 625 #endif
 626         return 0;
 627 }
 628
 629 /**
 630  * line discipline callback wrappers
 631  *
 632  * The wrappers maintain line discipline references
 633  * while calling into the line discipline.
 634  *
 635  * ldisc_receive_buf  - pass receive data to line discipline
 636  */
 637 static void ldisc_receive_buf(struct tty_struct *tty,
 638                               const __u8 *data, char *flags, int count)
 639 {
 640         struct tty_ldisc *ld;
 641         if (!tty)
 642                 return;
 643         ld = tty_ldisc_ref(tty);
 644         if (ld) {
 645                 if (ld->receive_buf)
 646                         ld->receive_buf(tty, data, flags, count);
 647                 tty_ldisc_deref(ld);
 648         }
 649 }
 650
 651 /* tty callbacks */
 652
 653 static int open(struct tty_struct *tty, struct file *filp)
 654 {
 655         struct slgt_info *info;
 656         int retval, line;
 657         unsigned long flags;
 658
 659         line = tty->index;
 660         if ((line < 0) || (line >= slgt_device_count)) {
 661                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 662                 return -ENODEV;
 663         }
 664
 665         info = slgt_device_list;
 666         while(info && info->line != line)
 667                 info = info->next_device;
 668         if (sanity_check(info, tty->name, "open"))
 669                 return -ENODEV;
 670         if (info->init_error) {
 671                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 672                 return -ENODEV;
 673         }
 674
 675         tty->driver_data = info;
 676         info->tty = tty;
 677
 678         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 679
 680         /* If port is closing, signal caller to try again */
 681         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 682                 if (info->flags & ASYNC_CLOSING)
 683                         interruptible_sleep_on(&info->close_wait);
 684                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 685                         -EAGAIN : -ERESTARTSYS);
 686                 goto cleanup;
 687         }
 688
 689         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 690
 691         spin_lock_irqsave(&info->netlock, flags);
 692         if (info->netcount) {
 693                 retval = -EBUSY;
 694                 spin_unlock_irqrestore(&info->netlock, flags);
 695                 goto cleanup;
 696         }
 697         info->count++;
 698         spin_unlock_irqrestore(&info->netlock, flags);
 699
 700         if (info->count == 1) {
 701                 /* 1st open on this device, init hardware */
 702                 retval = startup(info);
 703                 if (retval < 0)
 704                         goto cleanup;
 705         }
 706
 707         retval = block_til_ready(tty, filp, info);
 708         if (retval) {
 709                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 710                 goto cleanup;
 711         }
 712
 713         retval = 0;
 714
 715 cleanup:
 716         if (retval) {
 717                 if (tty->count == 1)
 718                         info->tty = NULL; /* tty layer will release tty struct */
 719                 if(info->count)
 720                         info->count--;
 721         }
 722
 723         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 724         return retval;
 725 }
 726
 727 static void close(struct tty_struct *tty, struct file *filp)
 728 {
 729         struct slgt_info *info = tty->driver_data;
 730
 731         if (sanity_check(info, tty->name, "close"))
 732                 return;
 733         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 734
 735         if (!info->count)
 736                 return;
 737
 738         if (tty_hung_up_p(filp))
 739                 goto cleanup;
 740
 741         if ((tty->count == 1) && (info->count != 1)) {
 742                 /*
 743                  * tty->count is 1 and the tty structure will be freed.
 744                  * info->count should be one in this case.
 745                  * if it's not, correct it so that the port is shutdown.
 746                  */
 747                 DBGERR(("%s close: bad refcount; tty->count=1, "
 748                        "info->count=%d\n", info->device_name, info->count));
 749                 info->count = 1;
 750         }
 751
 752         info->count--;
 753
 754         /* if at least one open remaining, leave hardware active */
 755         if (info->count)
 756                 goto cleanup;
 757
 758         info->flags |= ASYNC_CLOSING;
 759
 760         /* set tty->closing to notify line discipline to
 761          * only process XON/XOFF characters. Only the N_TTY
 762          * discipline appears to use this (ppp does not).
 763          */
 764         tty->closing = 1;
 765
 766         /* wait for transmit data to clear all layers */
 767
 768         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 769                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 770                 tty_wait_until_sent(tty, info->closing_wait);
 771         }
 772
 773         if (info->flags & ASYNC_INITIALIZED)
 774                 wait_until_sent(tty, info->timeout);
 775         if (tty->driver->flush_buffer)
 776                 tty->driver->flush_buffer(tty);
 777         tty_ldisc_flush(tty);
 778
 779         shutdown(info);
 780
 781         tty->closing = 0;
 782         info->tty = NULL;
 783
 784         if (info->blocked_open) {
 785                 if (info->close_delay) {
 786                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 787                 }
 788                 wake_up_interruptible(&info->open_wait);
 789         }
 790
 791         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 792
 793         wake_up_interruptible(&info->close_wait);
 794
 795 cleanup:
 796         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 797 }
 798
 799 static void hangup(struct tty_struct *tty)
 800 {
 801         struct slgt_info *info = tty->driver_data;
 802
 803         if (sanity_check(info, tty->name, "hangup"))
 804                 return;
 805         DBGINFO(("%s hangup\n", info->device_name));
 806
 807         flush_buffer(tty);
 808         shutdown(info);
 809
 810         info->count = 0;
 811         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 812         info->tty = NULL;
 813
 814         wake_up_interruptible(&info->open_wait);
 815 }
 816
 817 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 818 {
 819         struct slgt_info *info = tty->driver_data;
 820         unsigned long flags;
 821
 822         DBGINFO(("%s set_termios\n", tty->driver->name));
 823
 824         change_params(info);
 825
 826         /* Handle transition to B0 status */
 827         if (old_termios->c_cflag & CBAUD &&
 828             !(tty->termios->c_cflag & CBAUD)) {
 829                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 830                 spin_lock_irqsave(&info->lock,flags);
 831                 set_signals(info);
 832                 spin_unlock_irqrestore(&info->lock,flags);
 833         }
 834
 835         /* Handle transition away from B0 status */
 836         if (!(old_termios->c_cflag & CBAUD) &&
 837             tty->termios->c_cflag & CBAUD) {
 838                 info->signals |= SerialSignal_DTR;
 839                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 840                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 841                         info->signals |= SerialSignal_RTS;
 842                 }
 843                 spin_lock_irqsave(&info->lock,flags);
 844                 set_signals(info);
 845                 spin_unlock_irqrestore(&info->lock,flags);
 846         }
 847
 848         /* Handle turning off CRTSCTS */
 849         if (old_termios->c_cflag & CRTSCTS &&
 850             !(tty->termios->c_cflag & CRTSCTS)) {
 851                 tty->hw_stopped = 0;
 852                 tx_release(tty);
 853         }
 854 }
 855
 856 static int write(struct tty_struct *tty,
 857                  const unsigned char *buf, int count)
 858 {
 859         int ret = 0;
 860         struct slgt_info *info = tty->driver_data;
 861         unsigned long flags;
 862
 863         if (sanity_check(info, tty->name, "write"))
 864                 goto cleanup;
 865         DBGINFO(("%s write count=%d\n", info->device_name, count));
 866
 867         if (!info->tx_buf)
 868                 goto cleanup;
 869
 870         if (count > info->max_frame_size) {
 871                 ret = -EIO;
 872                 goto cleanup;
 873         }
 874
 875         if (!count)
 876                 goto cleanup;
 877
 878         if (info->params.mode == MGSL_MODE_RAW ||
 879             info->params.mode == MGSL_MODE_MONOSYNC ||
 880             info->params.mode == MGSL_MODE_BISYNC) {
 881                 unsigned int bufs_needed = (count/DMABUFSIZE);
 882                 unsigned int bufs_free = free_tbuf_count(info);
 883                 if (count % DMABUFSIZE)
 884                         ++bufs_needed;
 885                 if (bufs_needed > bufs_free)
 886                         goto cleanup;
 887         } else {
 888                 if (info->tx_active)
 889                         goto cleanup;
 890                 if (info->tx_count) {
 891                         /* send accumulated data from send_char() calls */
 892                         /* as frame and wait before accepting more data. */
 893                         tx_load(info, info->tx_buf, info->tx_count);
 894                         goto start;
 895                 }
 896         }
 897
 898         ret = info->tx_count = count;
 899         tx_load(info, buf, count);
 900         goto start;
 901
 902 start:
 903         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 904                 spin_lock_irqsave(&info->lock,flags);
 905                 if (!info->tx_active)
 906                         tx_start(info);
 907                 spin_unlock_irqrestore(&info->lock,flags);
 908         }
 909
 910 cleanup:
 911         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 912         return ret;
 913 }
 914
 915 static void put_char(struct tty_struct *tty, unsigned char ch)
 916 {
 917         struct slgt_info *info = tty->driver_data;
 918         unsigned long flags;
 919
 920         if (sanity_check(info, tty->name, "put_char"))
 921                 return;
 922         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 923         if (!info->tx_buf)
 924                 return;
 925         spin_lock_irqsave(&info->lock,flags);
 926         if (!info->tx_active && (info->tx_count < info->max_frame_size))
 927                 info->tx_buf[info->tx_count++] = ch;
 928         spin_unlock_irqrestore(&info->lock,flags);
 929 }
 930
 931 static void send_xchar(struct tty_struct *tty, char ch)
 932 {
 933         struct slgt_info *info = tty->driver_data;
 934         unsigned long flags;
 935
 936         if (sanity_check(info, tty->name, "send_xchar"))
 937                 return;
 938         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 939         info->x_char = ch;
 940         if (ch) {
 941                 spin_lock_irqsave(&info->lock,flags);
 942                 if (!info->tx_enabled)
 943                         tx_start(info);
 944                 spin_unlock_irqrestore(&info->lock,flags);
 945         }
 946 }
 947
 948 static void wait_until_sent(struct tty_struct *tty, int timeout)
 949 {
 950         struct slgt_info *info = tty->driver_data;
 951         unsigned long orig_jiffies, char_time;
 952
 953         if (!info )
 954                 return;
 955         if (sanity_check(info, tty->name, "wait_until_sent"))
 956                 return;
 957         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 958         if (!(info->flags & ASYNC_INITIALIZED))
 959                 goto exit;
 960
 961         orig_jiffies = jiffies;
 962
 963         /* Set check interval to 1/5 of estimated time to
 964          * send a character, and make it at least 1. The check
 965          * interval should also be less than the timeout.
 966          * Note: use tight timings here to satisfy the NIST-PCTS.
 967          */
 968
 969         if (info->params.data_rate) {
 970                 char_time = info->timeout/(32 * 5);
 971                 if (!char_time)
 972                         char_time++;
 973         } else
 974                 char_time = 1;
 975
 976         if (timeout)
 977                 char_time = min_t(unsigned long, char_time, timeout);
 978
 979         while (info->tx_active) {
 980                 msleep_interruptible(jiffies_to_msecs(char_time));
 981                 if (signal_pending(current))
 982                         break;
 983                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 984                         break;
 985         }
 986
 987 exit:
 988         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 989 }
 990
 991 static int write_room(struct tty_struct *tty)
 992 {
 993         struct slgt_info *info = tty->driver_data;
 994         int ret;
 995
 996         if (sanity_check(info, tty->name, "write_room"))
 997                 return 0;
 998         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 999         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1000         return ret;
1001 }
1002
1003 static void flush_chars(struct tty_struct *tty)
1004 {
1005         struct slgt_info *info = tty->driver_data;
1006         unsigned long flags;
1007
1008         if (sanity_check(info, tty->name, "flush_chars"))
1009                 return;
1010         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1011
1012         if (info->tx_count <= 0 || tty->stopped ||
1013             tty->hw_stopped || !info->tx_buf)
1014                 return;
1015
1016         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1017
1018         spin_lock_irqsave(&info->lock,flags);
1019         if (!info->tx_active && info->tx_count) {
1020                 tx_load(info, info->tx_buf,info->tx_count);
1021                 tx_start(info);
1022         }
1023         spin_unlock_irqrestore(&info->lock,flags);
1024 }
1025
1026 static void flush_buffer(struct tty_struct *tty)
1027 {
1028         struct slgt_info *info = tty->driver_data;
1029         unsigned long flags;
1030
1031         if (sanity_check(info, tty->name, "flush_buffer"))
1032                 return;
1033         DBGINFO(("%s flush_buffer\n", info->device_name));
1034
1035         spin_lock_irqsave(&info->lock,flags);
1036         if (!info->tx_active)
1037                 info->tx_count = 0;
1038         spin_unlock_irqrestore(&info->lock,flags);
1039
1040         tty_wakeup(tty);
1041 }
1042
1043 /*
1044  * throttle (stop) transmitter
1045  */
1046 static void tx_hold(struct tty_struct *tty)
1047 {
1048         struct slgt_info *info = tty->driver_data;
1049         unsigned long flags;
1050
1051         if (sanity_check(info, tty->name, "tx_hold"))
1052                 return;
1053         DBGINFO(("%s tx_hold\n", info->device_name));
1054         spin_lock_irqsave(&info->lock,flags);
1055         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1056                 tx_stop(info);
1057         spin_unlock_irqrestore(&info->lock,flags);
1058 }
1059
1060 /*
1061  * release (start) transmitter
1062  */
1063 static void tx_release(struct tty_struct *tty)
1064 {
1065         struct slgt_info *info = tty->driver_data;
1066         unsigned long flags;
1067
1068         if (sanity_check(info, tty->name, "tx_release"))
1069                 return;
1070         DBGINFO(("%s tx_release\n", info->device_name));
1071         spin_lock_irqsave(&info->lock,flags);
1072         if (!info->tx_active && info->tx_count) {
1073                 tx_load(info, info->tx_buf, info->tx_count);
1074                 tx_start(info);
1075         }
1076         spin_unlock_irqrestore(&info->lock,flags);
1077 }
1078
1079 /*
1080  * Service an IOCTL request
1081  *
1082  * Arguments
1083  *
1084  *      tty     pointer to tty instance data
1085  *      file    pointer to associated file object for device
1086  *      cmd     IOCTL command code
1087  *      arg     command argument/context
1088  *
1089  * Return 0 if success, otherwise error code
1090  */
1091 static int ioctl(struct tty_struct *tty, struct file *file,
1092                  unsigned int cmd, unsigned long arg)
1093 {
1094         struct slgt_info *info = tty->driver_data;
1095         struct mgsl_icount cnow;        /* kernel counter temps */
1096         struct serial_icounter_struct __user *p_cuser;  /* user space */
1097         unsigned long flags;
1098         void __user *argp = (void __user *)arg;
1099
1100         if (sanity_check(info, tty->name, "ioctl"))
1101                 return -ENODEV;
1102         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1103
1104         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1105             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1106                 if (tty->flags & (1 << TTY_IO_ERROR))
1107                     return -EIO;
1108         }
1109
1110         switch (cmd) {
1111         case MGSL_IOCGPARAMS:
1112                 return get_params(info, argp);
1113         case MGSL_IOCSPARAMS:
1114                 return set_params(info, argp);
1115         case MGSL_IOCGTXIDLE:
1116                 return get_txidle(info, argp);
1117         case MGSL_IOCSTXIDLE:
1118                 return set_txidle(info, (int)arg);
1119         case MGSL_IOCTXENABLE:
1120                 return tx_enable(info, (int)arg);
1121         case MGSL_IOCRXENABLE:
1122                 return rx_enable(info, (int)arg);
1123         case MGSL_IOCTXABORT:
1124                 return tx_abort(info);
1125         case MGSL_IOCGSTATS:
1126                 return get_stats(info, argp);
1127         case MGSL_IOCWAITEVENT:
1128                 return wait_mgsl_event(info, argp);
1129         case TIOCMIWAIT:
1130                 return modem_input_wait(info,(int)arg);
1131         case MGSL_IOCGIF:
1132                 return get_interface(info, argp);
1133         case MGSL_IOCSIF:
1134                 return set_interface(info,(int)arg);
1135         case MGSL_IOCSGPIO:
1136                 return set_gpio(info, argp);
1137         case MGSL_IOCGGPIO:
1138                 return get_gpio(info, argp);
1139         case MGSL_IOCWAITGPIO:
1140                 return wait_gpio(info, argp);
1141         case TIOCGICOUNT:
1142                 spin_lock_irqsave(&info->lock,flags);
1143                 cnow = info->icount;
1144                 spin_unlock_irqrestore(&info->lock,flags);
1145                 p_cuser = argp;
1146                 if (put_user(cnow.cts, &p_cuser->cts) ||
1147                     put_user(cnow.dsr, &p_cuser->dsr) ||
1148                     put_user(cnow.rng, &p_cuser->rng) ||
1149                     put_user(cnow.dcd, &p_cuser->dcd) ||
1150                     put_user(cnow.rx, &p_cuser->rx) ||
1151                     put_user(cnow.tx, &p_cuser->tx) ||
1152                     put_user(cnow.frame, &p_cuser->frame) ||
1153                     put_user(cnow.overrun, &p_cuser->overrun) ||
1154                     put_user(cnow.parity, &p_cuser->parity) ||
1155                     put_user(cnow.brk, &p_cuser->brk) ||
1156                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1157                         return -EFAULT;
1158                 return 0;
1159         default:
1160                 return -ENOIOCTLCMD;
1161         }
1162         return 0;
1163 }
1164
1165 /*
1166  * support for 32 bit ioctl calls on 64 bit systems
1167  */
1168 #ifdef CONFIG_COMPAT
1169 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1170 {
1171         struct MGSL_PARAMS32 tmp_params;
1172
1173         DBGINFO(("%s get_params32\n", info->device_name));
1174         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1175         tmp_params.loopback        = info->params.loopback;
1176         tmp_params.flags           = info->params.flags;
1177         tmp_params.encoding        = info->params.encoding;
1178         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1179         tmp_params.addr_filter     = info->params.addr_filter;
1180         tmp_params.crc_type        = info->params.crc_type;
1181         tmp_params.preamble_length = info->params.preamble_length;
1182         tmp_params.preamble        = info->params.preamble;
1183         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1184         tmp_params.data_bits       = info->params.data_bits;
1185         tmp_params.stop_bits       = info->params.stop_bits;
1186         tmp_params.parity          = info->params.parity;
1187         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1188                 return -EFAULT;
1189         return 0;
1190 }
1191
1192 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1193 {
1194         struct MGSL_PARAMS32 tmp_params;
1195
1196         DBGINFO(("%s set_params32\n", info->device_name));
1197         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1198                 return -EFAULT;
1199
1200         spin_lock(&info->lock);
1201         info->params.mode            = tmp_params.mode;
1202         info->params.loopback        = tmp_params.loopback;
1203         info->params.flags           = tmp_params.flags;
1204         info->params.encoding        = tmp_params.encoding;
1205         info->params.clock_speed     = tmp_params.clock_speed;
1206         info->params.addr_filter     = tmp_params.addr_filter;
1207         info->params.crc_type        = tmp_params.crc_type;
1208         info->params.preamble_length = tmp_params.preamble_length;
1209         info->params.preamble        = tmp_params.preamble;
1210         info->params.data_rate       = tmp_params.data_rate;
1211         info->params.data_bits       = tmp_params.data_bits;
1212         info->params.stop_bits       = tmp_params.stop_bits;
1213         info->params.parity          = tmp_params.parity;
1214         spin_unlock(&info->lock);
1215
1216         change_params(info);
1217
1218         return 0;
1219 }
1220
1221 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1222                          unsigned int cmd, unsigned long arg)
1223 {
1224         struct slgt_info *info = tty->driver_data;
1225         int rc = -ENOIOCTLCMD;
1226
1227         if (sanity_check(info, tty->name, "compat_ioctl"))
1228                 return -ENODEV;
1229         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1230
1231         switch (cmd) {
1232
1233         case MGSL_IOCSPARAMS32:
1234                 rc = set_params32(info, compat_ptr(arg));
1235                 break;
1236
1237         case MGSL_IOCGPARAMS32:
1238                 rc = get_params32(info, compat_ptr(arg));
1239                 break;
1240
1241         case MGSL_IOCGPARAMS:
1242         case MGSL_IOCSPARAMS:
1243         case MGSL_IOCGTXIDLE:
1244         case MGSL_IOCGSTATS:
1245         case MGSL_IOCWAITEVENT:
1246         case MGSL_IOCGIF:
1247         case MGSL_IOCSGPIO:
1248         case MGSL_IOCGGPIO:
1249         case MGSL_IOCWAITGPIO:
1250         case TIOCGICOUNT:
1251                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1252                 break;
1253
1254         case MGSL_IOCSTXIDLE:
1255         case MGSL_IOCTXENABLE:
1256         case MGSL_IOCRXENABLE:
1257         case MGSL_IOCTXABORT:
1258         case TIOCMIWAIT:
1259         case MGSL_IOCSIF:
1260                 rc = ioctl(tty, file, cmd, arg);
1261                 break;
1262         }
1263
1264         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1265         return rc;
1266 }
1267 #else
1268 #define slgt_compat_ioctl NULL
1269 #endif /* ifdef CONFIG_COMPAT */
1270
1271 /*
1272  * proc fs support
1273  */
1274 static inline int line_info(char *buf, struct slgt_info *info)
1275 {
1276         char stat_buf[30];
1277         int ret;
1278         unsigned long flags;
1279
1280         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1281                       info->device_name, info->phys_reg_addr,
1282                       info->irq_level, info->max_frame_size);
1283
1284         /* output current serial signal states */
1285         spin_lock_irqsave(&info->lock,flags);
1286         get_signals(info);
1287         spin_unlock_irqrestore(&info->lock,flags);
1288
1289         stat_buf[0] = 0;
1290         stat_buf[1] = 0;
1291         if (info->signals & SerialSignal_RTS)
1292                 strcat(stat_buf, "|RTS");
1293         if (info->signals & SerialSignal_CTS)
1294                 strcat(stat_buf, "|CTS");
1295         if (info->signals & SerialSignal_DTR)
1296                 strcat(stat_buf, "|DTR");
1297         if (info->signals & SerialSignal_DSR)
1298                 strcat(stat_buf, "|DSR");
1299         if (info->signals & SerialSignal_DCD)
1300                 strcat(stat_buf, "|CD");
1301         if (info->signals & SerialSignal_RI)
1302                 strcat(stat_buf, "|RI");
1303
1304         if (info->params.mode != MGSL_MODE_ASYNC) {
1305                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1306                                info->icount.txok, info->icount.rxok);
1307                 if (info->icount.txunder)
1308                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1309                 if (info->icount.txabort)
1310                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1311                 if (info->icount.rxshort)
1312                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1313                 if (info->icount.rxlong)
1314                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1315                 if (info->icount.rxover)
1316                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1317                 if (info->icount.rxcrc)
1318                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1319         } else {
1320                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1321                                info->icount.tx, info->icount.rx);
1322                 if (info->icount.frame)
1323                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1324                 if (info->icount.parity)
1325                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1326                 if (info->icount.brk)
1327                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1328                 if (info->icount.overrun)
1329                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1330         }
1331
1332         /* Append serial signal status to end */
1333         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1334
1335         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1336                        info->tx_active,info->bh_requested,info->bh_running,
1337                        info->pending_bh);
1338
1339         return ret;
1340 }
1341
1342 /* Called to print information about devices
1343  */
1344 static int read_proc(char *page, char **start, off_t off, int count,
1345                      int *eof, void *data)
1346 {
1347         int len = 0, l;
1348         off_t   begin = 0;
1349         struct slgt_info *info;
1350
1351         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1352
1353         info = slgt_device_list;
1354         while( info ) {
1355                 l = line_info(page + len, info);
1356                 len += l;
1357                 if (len+begin > off+count)
1358                         goto done;
1359                 if (len+begin < off) {
1360                         begin += len;
1361                         len = 0;
1362                 }
1363                 info = info->next_device;
1364         }
1365
1366         *eof = 1;
1367 done:
1368         if (off >= len+begin)
1369                 return 0;
1370         *start = page + (off-begin);
1371         return ((count < begin+len-off) ? count : begin+len-off);
1372 }
1373
1374 /*
1375  * return count of bytes in transmit buffer
1376  */
1377 static int chars_in_buffer(struct tty_struct *tty)
1378 {
1379         struct slgt_info *info = tty->driver_data;
1380         if (sanity_check(info, tty->name, "chars_in_buffer"))
1381                 return 0;
1382         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1383         return info->tx_count;
1384 }
1385
1386 /*
1387  * signal remote device to throttle send data (our receive data)
1388  */
1389 static void throttle(struct tty_struct * tty)
1390 {
1391         struct slgt_info *info = tty->driver_data;
1392         unsigned long flags;
1393
1394         if (sanity_check(info, tty->name, "throttle"))
1395                 return;
1396         DBGINFO(("%s throttle\n", info->device_name));
1397         if (I_IXOFF(tty))
1398                 send_xchar(tty, STOP_CHAR(tty));
1399         if (tty->termios->c_cflag & CRTSCTS) {
1400                 spin_lock_irqsave(&info->lock,flags);
1401                 info->signals &= ~SerialSignal_RTS;
1402                 set_signals(info);
1403                 spin_unlock_irqrestore(&info->lock,flags);
1404         }
1405 }
1406
1407 /*
1408  * signal remote device to stop throttling send data (our receive data)
1409  */
1410 static void unthrottle(struct tty_struct * tty)
1411 {
1412         struct slgt_info *info = tty->driver_data;
1413         unsigned long flags;
1414
1415         if (sanity_check(info, tty->name, "unthrottle"))
1416                 return;
1417         DBGINFO(("%s unthrottle\n", info->device_name));
1418         if (I_IXOFF(tty)) {
1419                 if (info->x_char)
1420                         info->x_char = 0;
1421                 else
1422                         send_xchar(tty, START_CHAR(tty));
1423         }
1424         if (tty->termios->c_cflag & CRTSCTS) {
1425                 spin_lock_irqsave(&info->lock,flags);
1426                 info->signals |= SerialSignal_RTS;
1427                 set_signals(info);
1428                 spin_unlock_irqrestore(&info->lock,flags);
1429         }
1430 }
1431
1432 /*
1433  * set or clear transmit break condition
1434  * break_state  -1=set break condition, 0=clear
1435  */
1436 static void set_break(struct tty_struct *tty, int break_state)
1437 {
1438         struct slgt_info *info = tty->driver_data;
1439         unsigned short value;
1440         unsigned long flags;
1441
1442         if (sanity_check(info, tty->name, "set_break"))
1443                 return;
1444         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1445
1446         spin_lock_irqsave(&info->lock,flags);
1447         value = rd_reg16(info, TCR);
1448         if (break_state == -1)
1449                 value |= BIT6;
1450         else
1451                 value &= ~BIT6;
1452         wr_reg16(info, TCR, value);
1453         spin_unlock_irqrestore(&info->lock,flags);
1454 }
1455
1456 #if SYNCLINK_GENERIC_HDLC
1457
1458 /**
1459  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1460  * set encoding and frame check sequence (FCS) options
1461  *
1462  * dev       pointer to network device structure
1463  * encoding  serial encoding setting
1464  * parity    FCS setting
1465  *
1466  * returns 0 if success, otherwise error code
1467  */
1468 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1469                           unsigned short parity)
1470 {
1471         struct slgt_info *info = dev_to_port(dev);
1472         unsigned char  new_encoding;
1473         unsigned short new_crctype;
1474
1475         /* return error if TTY interface open */
1476         if (info->count)
1477                 return -EBUSY;
1478
1479         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1480
1481         switch (encoding)
1482         {
1483         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1484         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1485         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1486         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1487         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1488         default: return -EINVAL;
1489         }
1490
1491         switch (parity)
1492         {
1493         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1494         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1495         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1496         default: return -EINVAL;
1497         }
1498
1499         info->params.encoding = new_encoding;
1500         info->params.crc_type = new_crctype;
1501
1502         /* if network interface up, reprogram hardware */
1503         if (info->netcount)
1504                 program_hw(info);
1505
1506         return 0;
1507 }
1508
1509 /**
1510  * called by generic HDLC layer to send frame
1511  *
1512  * skb  socket buffer containing HDLC frame
1513  * dev  pointer to network device structure
1514  *
1515  * returns 0 if success, otherwise error code
1516  */
1517 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1518 {
1519         struct slgt_info *info = dev_to_port(dev);
1520         struct net_device_stats *stats = hdlc_stats(dev);
1521         unsigned long flags;
1522
1523         DBGINFO(("%s hdlc_xmit\n", dev->name));
1524
1525         /* stop sending until this frame completes */
1526         netif_stop_queue(dev);
1527
1528         /* copy data to device buffers */
1529         info->tx_count = skb->len;
1530         tx_load(info, skb->data, skb->len);
1531
1532         /* update network statistics */
1533         stats->tx_packets++;
1534         stats->tx_bytes += skb->len;
1535
1536         /* done with socket buffer, so free it */
1537         dev_kfree_skb(skb);
1538
1539         /* save start time for transmit timeout detection */
1540         dev->trans_start = jiffies;
1541
1542         /* start hardware transmitter if necessary */
1543         spin_lock_irqsave(&info->lock,flags);
1544         if (!info->tx_active)
1545                 tx_start(info);
1546         spin_unlock_irqrestore(&info->lock,flags);
1547
1548         return 0;
1549 }
1550
1551 /**
1552  * called by network layer when interface enabled
1553  * claim resources and initialize hardware
1554  *
1555  * dev  pointer to network device structure
1556  *
1557  * returns 0 if success, otherwise error code
1558  */
1559 static int hdlcdev_open(struct net_device *dev)
1560 {
1561         struct slgt_info *info = dev_to_port(dev);
1562         int rc;
1563         unsigned long flags;
1564
1565         DBGINFO(("%s hdlcdev_open\n", dev->name));
1566
1567         /* generic HDLC layer open processing */
1568         if ((rc = hdlc_open(dev)))
1569                 return rc;
1570
1571         /* arbitrate between network and tty opens */
1572         spin_lock_irqsave(&info->netlock, flags);
1573         if (info->count != 0 || info->netcount != 0) {
1574                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1575                 spin_unlock_irqrestore(&info->netlock, flags);
1576                 return -EBUSY;
1577         }
1578         info->netcount=1;
1579         spin_unlock_irqrestore(&info->netlock, flags);
1580
1581         /* claim resources and init adapter */
1582         if ((rc = startup(info)) != 0) {
1583                 spin_lock_irqsave(&info->netlock, flags);
1584                 info->netcount=0;
1585                 spin_unlock_irqrestore(&info->netlock, flags);
1586                 return rc;
1587         }
1588
1589         /* assert DTR and RTS, apply hardware settings */
1590         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1591         program_hw(info);
1592
1593         /* enable network layer transmit */
1594         dev->trans_start = jiffies;
1595         netif_start_queue(dev);
1596
1597         /* inform generic HDLC layer of current DCD status */
1598         spin_lock_irqsave(&info->lock, flags);
1599         get_signals(info);
1600         spin_unlock_irqrestore(&info->lock, flags);
1601         if (info->signals & SerialSignal_DCD)
1602                 netif_carrier_on(dev);
1603         else
1604                 netif_carrier_off(dev);
1605         return 0;
1606 }
1607
1608 /**
1609  * called by network layer when interface is disabled
1610  * shutdown hardware and release resources
1611  *
1612  * dev  pointer to network device structure
1613  *
1614  * returns 0 if success, otherwise error code
1615  */
1616 static int hdlcdev_close(struct net_device *dev)
1617 {
1618         struct slgt_info *info = dev_to_port(dev);
1619         unsigned long flags;
1620
1621         DBGINFO(("%s hdlcdev_close\n", dev->name));
1622
1623         netif_stop_queue(dev);
1624
1625         /* shutdown adapter and release resources */
1626         shutdown(info);
1627
1628         hdlc_close(dev);
1629
1630         spin_lock_irqsave(&info->netlock, flags);
1631         info->netcount=0;
1632         spin_unlock_irqrestore(&info->netlock, flags);
1633
1634         return 0;
1635 }
1636
1637 /**
1638  * called by network layer to process IOCTL call to network device
1639  *
1640  * dev  pointer to network device structure
1641  * ifr  pointer to network interface request structure
1642  * cmd  IOCTL command code
1643  *
1644  * returns 0 if success, otherwise error code
1645  */
1646 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1647 {
1648         const size_t size = sizeof(sync_serial_settings);
1649         sync_serial_settings new_line;
1650         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1651         struct slgt_info *info = dev_to_port(dev);
1652         unsigned int flags;
1653
1654         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1655
1656         /* return error if TTY interface open */
1657         if (info->count)
1658                 return -EBUSY;
1659
1660         if (cmd != SIOCWANDEV)
1661                 return hdlc_ioctl(dev, ifr, cmd);
1662
1663         switch(ifr->ifr_settings.type) {
1664         case IF_GET_IFACE: /* return current sync_serial_settings */
1665
1666                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1667                 if (ifr->ifr_settings.size < size) {
1668                         ifr->ifr_settings.size = size; /* data size wanted */
1669                         return -ENOBUFS;
1670                 }
1671
1672                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1673                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1674                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1675                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1676
1677                 switch (flags){
1678                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1679                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1680                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1681                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1682                 default: new_line.clock_type = CLOCK_DEFAULT;
1683                 }
1684
1685                 new_line.clock_rate = info->params.clock_speed;
1686                 new_line.loopback   = info->params.loopback ? 1:0;
1687
1688                 if (copy_to_user(line, &new_line, size))
1689                         return -EFAULT;
1690                 return 0;
1691
1692         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1693
1694                 if(!capable(CAP_NET_ADMIN))
1695                         return -EPERM;
1696                 if (copy_from_user(&new_line, line, size))
1697                         return -EFAULT;
1698
1699                 switch (new_line.clock_type)
1700                 {
1701                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1702                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1703                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1704                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1705                 case CLOCK_DEFAULT:  flags = info->params.flags &
1706                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1707                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1708                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1709                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1710                 default: return -EINVAL;
1711                 }
1712
1713                 if (new_line.loopback != 0 && new_line.loopback != 1)
1714                         return -EINVAL;
1715
1716                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1717                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1718                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1719                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1720                 info->params.flags |= flags;
1721
1722                 info->params.loopback = new_line.loopback;
1723
1724                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1725                         info->params.clock_speed = new_line.clock_rate;
1726                 else
1727                         info->params.clock_speed = 0;
1728
1729                 /* if network interface up, reprogram hardware */
1730                 if (info->netcount)
1731                         program_hw(info);
1732                 return 0;
1733
1734         default:
1735                 return hdlc_ioctl(dev, ifr, cmd);
1736         }
1737 }
1738
1739 /**
1740  * called by network layer when transmit timeout is detected
1741  *
1742  * dev  pointer to network device structure
1743  */
1744 static void hdlcdev_tx_timeout(struct net_device *dev)
1745 {
1746         struct slgt_info *info = dev_to_port(dev);
1747         struct net_device_stats *stats = hdlc_stats(dev);
1748         unsigned long flags;
1749
1750         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1751
1752         stats->tx_errors++;
1753         stats->tx_aborted_errors++;
1754
1755         spin_lock_irqsave(&info->lock,flags);
1756         tx_stop(info);
1757         spin_unlock_irqrestore(&info->lock,flags);
1758
1759         netif_wake_queue(dev);
1760 }
1761
1762 /**
1763  * called by device driver when transmit completes
1764  * reenable network layer transmit if stopped
1765  *
1766  * info  pointer to device instance information
1767  */
1768 static void hdlcdev_tx_done(struct slgt_info *info)
1769 {
1770         if (netif_queue_stopped(info->netdev))
1771                 netif_wake_queue(info->netdev);
1772 }
1773
1774 /**
1775  * called by device driver when frame received
1776  * pass frame to network layer
1777  *
1778  * info  pointer to device instance information
1779  * buf   pointer to buffer contianing frame data
1780  * size  count of data bytes in buf
1781  */
1782 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1783 {
1784         struct sk_buff *skb = dev_alloc_skb(size);
1785         struct net_device *dev = info->netdev;
1786         struct net_device_stats *stats = hdlc_stats(dev);
1787
1788         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1789
1790         if (skb == NULL) {
1791                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1792                 stats->rx_dropped++;
1793                 return;
1794         }
1795
1796         memcpy(skb_put(skb, size),buf,size);
1797
1798         skb->protocol = hdlc_type_trans(skb, info->netdev);
1799
1800         stats->rx_packets++;
1801         stats->rx_bytes += size;
1802
1803         netif_rx(skb);
1804
1805         info->netdev->last_rx = jiffies;
1806 }
1807
1808 /**
1809  * called by device driver when adding device instance
1810  * do generic HDLC initialization
1811  *
1812  * info  pointer to device instance information
1813  *
1814  * returns 0 if success, otherwise error code
1815  */
1816 static int hdlcdev_init(struct slgt_info *info)
1817 {
1818         int rc;
1819         struct net_device *dev;
1820         hdlc_device *hdlc;
1821
1822         /* allocate and initialize network and HDLC layer objects */
1823
1824         if (!(dev = alloc_hdlcdev(info))) {
1825                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1826                 return -ENOMEM;
1827         }
1828
1829         /* for network layer reporting purposes only */
1830         dev->mem_start = info->phys_reg_addr;
1831         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1832         dev->irq       = info->irq_level;
1833
1834         /* network layer callbacks and settings */
1835         dev->do_ioctl       = hdlcdev_ioctl;
1836         dev->open           = hdlcdev_open;
1837         dev->stop           = hdlcdev_close;
1838         dev->tx_timeout     = hdlcdev_tx_timeout;
1839         dev->watchdog_timeo = 10*HZ;
1840         dev->tx_queue_len   = 50;
1841
1842         /* generic HDLC layer callbacks and settings */
1843         hdlc         = dev_to_hdlc(dev);
1844         hdlc->attach = hdlcdev_attach;
1845         hdlc->xmit   = hdlcdev_xmit;
1846
1847         /* register objects with HDLC layer */
1848         if ((rc = register_hdlc_device(dev))) {
1849                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1850                 free_netdev(dev);
1851                 return rc;
1852         }
1853
1854         info->netdev = dev;
1855         return 0;
1856 }
1857
1858 /**
1859  * called by device driver when removing device instance
1860  * do generic HDLC cleanup
1861  *
1862  * info  pointer to device instance information
1863  */
1864 static void hdlcdev_exit(struct slgt_info *info)
1865 {
1866         unregister_hdlc_device(info->netdev);
1867         free_netdev(info->netdev);
1868         info->netdev = NULL;
1869 }
1870
1871 #endif /* ifdef CONFIG_HDLC */
1872
1873 /*
1874  * get async data from rx DMA buffers
1875  */
1876 static void rx_async(struct slgt_info *info)
1877 {
1878         struct tty_struct *tty = info->tty;
1879         struct mgsl_icount *icount = &info->icount;
1880         unsigned int start, end;
1881         unsigned char *p;
1882         unsigned char status;
1883         struct slgt_desc *bufs = info->rbufs;
1884         int i, count;
1885         int chars = 0;
1886         int stat;
1887         unsigned char ch;
1888
1889         start = end = info->rbuf_current;
1890
1891         while(desc_complete(bufs[end])) {
1892                 count = desc_count(bufs[end]) - info->rbuf_index;
1893                 p     = bufs[end].buf + info->rbuf_index;
1894
1895                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1896                 DBGDATA(info, p, count, "rx");
1897
1898                 for(i=0 ; i < count; i+=2, p+=2) {
1899                         ch = *p;
1900                         icount->rx++;
1901
1902                         stat = 0;
1903
1904                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1905                                 if (status & BIT1)
1906                                         icount->parity++;
1907                                 else if (status & BIT0)
1908                                         icount->frame++;
1909                                 /* discard char if tty control flags say so */
1910                                 if (status & info->ignore_status_mask)
1911                                         continue;
1912                                 if (status & BIT1)
1913                                         stat = TTY_PARITY;
1914                                 else if (status & BIT0)
1915                                         stat = TTY_FRAME;
1916                         }
1917                         if (tty) {
1918                                 tty_insert_flip_char(tty, ch, stat);
1919                                 chars++;
1920                         }
1921                 }
1922
1923                 if (i < count) {
1924                         /* receive buffer not completed */
1925                         info->rbuf_index += i;
1926                         mod_timer(&info->rx_timer, jiffies + 1);
1927                         break;
1928                 }
1929
1930                 info->rbuf_index = 0;
1931                 free_rbufs(info, end, end);
1932
1933                 if (++end == info->rbuf_count)
1934                         end = 0;
1935
1936                 /* if entire list searched then no frame available */
1937                 if (end == start)
1938                         break;
1939         }
1940
1941         if (tty && chars)
1942                 tty_flip_buffer_push(tty);
1943 }
1944
1945 /*
1946  * return next bottom half action to perform
1947  */
1948 static int bh_action(struct slgt_info *info)
1949 {
1950         unsigned long flags;
1951         int rc;
1952
1953         spin_lock_irqsave(&info->lock,flags);
1954
1955         if (info->pending_bh & BH_RECEIVE) {
1956                 info->pending_bh &= ~BH_RECEIVE;
1957                 rc = BH_RECEIVE;
1958         } else if (info->pending_bh & BH_TRANSMIT) {
1959                 info->pending_bh &= ~BH_TRANSMIT;
1960                 rc = BH_TRANSMIT;
1961         } else if (info->pending_bh & BH_STATUS) {
1962                 info->pending_bh &= ~BH_STATUS;
1963                 rc = BH_STATUS;
1964         } else {
1965                 /* Mark BH routine as complete */
1966                 info->bh_running   = 0;
1967                 info->bh_requested = 0;
1968                 rc = 0;
1969         }
1970
1971         spin_unlock_irqrestore(&info->lock,flags);
1972
1973         return rc;
1974 }
1975
1976 /*
1977  * perform bottom half processing
1978  */
1979 static void bh_handler(struct work_struct *work)
1980 {
1981         struct slgt_info *info = container_of(work, struct slgt_info, task);
1982         int action;
1983
1984         if (!info)
1985                 return;
1986         info->bh_running = 1;
1987
1988         while((action = bh_action(info))) {
1989                 switch (action) {
1990                 case BH_RECEIVE:
1991                         DBGBH(("%s bh receive\n", info->device_name));
1992                         switch(info->params.mode) {
1993                         case MGSL_MODE_ASYNC:
1994                                 rx_async(info);
1995                                 break;
1996                         case MGSL_MODE_HDLC:
1997                                 while(rx_get_frame(info));
1998                                 break;
1999                         case MGSL_MODE_RAW:
2000                         case MGSL_MODE_MONOSYNC:
2001                         case MGSL_MODE_BISYNC:
2002                                 while(rx_get_buf(info));
2003                                 break;
2004                         }
2005                         /* restart receiver if rx DMA buffers exhausted */
2006                         if (info->rx_restart)
2007                                 rx_start(info);
2008                         break;
2009                 case BH_TRANSMIT:
2010                         bh_transmit(info);
2011                         break;
2012                 case BH_STATUS:
2013                         DBGBH(("%s bh status\n", info->device_name));
2014                         info->ri_chkcount = 0;
2015                         info->dsr_chkcount = 0;
2016                         info->dcd_chkcount = 0;
2017                         info->cts_chkcount = 0;
2018                         break;
2019                 default:
2020                         DBGBH(("%s unknown action\n", info->device_name));
2021                         break;
2022                 }
2023         }
2024         DBGBH(("%s bh_handler exit\n", info->device_name));
2025 }
2026
2027 static void bh_transmit(struct slgt_info *info)
2028 {
2029         struct tty_struct *tty = info->tty;
2030
2031         DBGBH(("%s bh_transmit\n", info->device_name));
2032         if (tty)
2033                 tty_wakeup(tty);
2034 }
2035
2036 static void dsr_change(struct slgt_info *info)
2037 {
2038         get_signals(info);
2039         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2040         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2041                 slgt_irq_off(info, IRQ_DSR);
2042                 return;
2043         }
2044         info->icount.dsr++;
2045         if (info->signals & SerialSignal_DSR)
2046                 info->input_signal_events.dsr_up++;
2047         else
2048                 info->input_signal_events.dsr_down++;
2049         wake_up_interruptible(&info->status_event_wait_q);
2050         wake_up_interruptible(&info->event_wait_q);
2051         info->pending_bh |= BH_STATUS;
2052 }
2053
2054 static void cts_change(struct slgt_info *info)
2055 {
2056         get_signals(info);
2057         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2058         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2059                 slgt_irq_off(info, IRQ_CTS);
2060                 return;
2061         }
2062         info->icount.cts++;
2063         if (info->signals & SerialSignal_CTS)
2064                 info->input_signal_events.cts_up++;
2065         else
2066                 info->input_signal_events.cts_down++;
2067         wake_up_interruptible(&info->status_event_wait_q);
2068         wake_up_interruptible(&info->event_wait_q);
2069         info->pending_bh |= BH_STATUS;
2070
2071         if (info->flags & ASYNC_CTS_FLOW) {
2072                 if (info->tty) {
2073                         if (info->tty->hw_stopped) {
2074                                 if (info->signals & SerialSignal_CTS) {
2075                                         info->tty->hw_stopped = 0;
2076                                         info->pending_bh |= BH_TRANSMIT;
2077                                         return;
2078                                 }
2079                         } else {
2080                                 if (!(info->signals & SerialSignal_CTS))
2081                                         info->tty->hw_stopped = 1;
2082                         }
2083                 }
2084         }
2085 }
2086
2087 static void dcd_change(struct slgt_info *info)
2088 {
2089         get_signals(info);
2090         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2091         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2092                 slgt_irq_off(info, IRQ_DCD);
2093                 return;
2094         }
2095         info->icount.dcd++;
2096         if (info->signals & SerialSignal_DCD) {
2097                 info->input_signal_events.dcd_up++;
2098         } else {
2099                 info->input_signal_events.dcd_down++;
2100         }
2101 #if SYNCLINK_GENERIC_HDLC
2102         if (info->netcount) {
2103                 if (info->signals & SerialSignal_DCD)
2104                         netif_carrier_on(info->netdev);
2105                 else
2106                         netif_carrier_off(info->netdev);
2107         }
2108 #endif
2109         wake_up_interruptible(&info->status_event_wait_q);
2110         wake_up_interruptible(&info->event_wait_q);
2111         info->pending_bh |= BH_STATUS;
2112
2113         if (info->flags & ASYNC_CHECK_CD) {
2114                 if (info->signals & SerialSignal_DCD)
2115                         wake_up_interruptible(&info->open_wait);
2116                 else {
2117                         if (info->tty)
2118                                 tty_hangup(info->tty);
2119                 }
2120         }
2121 }
2122
2123 static void ri_change(struct slgt_info *info)
2124 {
2125         get_signals(info);
2126         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2127         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2128                 slgt_irq_off(info, IRQ_RI);
2129                 return;
2130         }
2131         info->icount.dcd++;
2132         if (info->signals & SerialSignal_RI) {
2133                 info->input_signal_events.ri_up++;
2134         } else {
2135                 info->input_signal_events.ri_down++;
2136         }
2137         wake_up_interruptible(&info->status_event_wait_q);
2138         wake_up_interruptible(&info->event_wait_q);
2139         info->pending_bh |= BH_STATUS;
2140 }
2141
2142 static void isr_serial(struct slgt_info *info)
2143 {
2144         unsigned short status = rd_reg16(info, SSR);
2145
2146         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2147
2148         wr_reg16(info, SSR, status); /* clear pending */
2149
2150         info->irq_occurred = 1;
2151
2152         if (info->params.mode == MGSL_MODE_ASYNC) {
2153                 if (status & IRQ_TXIDLE) {
2154                         if (info->tx_count)
2155                                 isr_txeom(info, status);
2156                 }
2157                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2158                         info->icount.brk++;
2159                         /* process break detection if tty control allows */
2160                         if (info->tty) {
2161                                 if (!(status & info->ignore_status_mask)) {
2162                                         if (info->read_status_mask & MASK_BREAK) {
2163                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2164                                                 if (info->flags & ASYNC_SAK)
2165                                                         do_SAK(info->tty);
2166                                         }
2167                                 }
2168                         }
2169                 }
2170         } else {
2171                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2172                         isr_txeom(info, status);
2173
2174                 if (status & IRQ_RXIDLE) {
2175                         if (status & RXIDLE)
2176                                 info->icount.rxidle++;
2177                         else
2178                                 info->icount.exithunt++;
2179                         wake_up_interruptible(&info->event_wait_q);
2180                 }
2181
2182                 if (status & IRQ_RXOVER)
2183                         rx_start(info);
2184         }
2185
2186         if (status & IRQ_DSR)
2187                 dsr_change(info);
2188         if (status & IRQ_CTS)
2189                 cts_change(info);
2190         if (status & IRQ_DCD)
2191                 dcd_change(info);
2192         if (status & IRQ_RI)
2193                 ri_change(info);
2194 }
2195
2196 static void isr_rdma(struct slgt_info *info)
2197 {
2198         unsigned int status = rd_reg32(info, RDCSR);
2199
2200         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2201
2202         /* RDCSR (rx DMA control/status)
2203          *
2204          * 31..07  reserved
2205          * 06      save status byte to DMA buffer
2206          * 05      error
2207          * 04      eol (end of list)
2208          * 03      eob (end of buffer)
2209          * 02      IRQ enable
2210          * 01      reset
2211          * 00      enable
2212          */
2213         wr_reg32(info, RDCSR, status);  /* clear pending */
2214
2215         if (status & (BIT5 + BIT4)) {
2216                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2217                 info->rx_restart = 1;
2218         }
2219         info->pending_bh |= BH_RECEIVE;
2220 }
2221
2222 static void isr_tdma(struct slgt_info *info)
2223 {
2224         unsigned int status = rd_reg32(info, TDCSR);
2225
2226         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2227
2228         /* TDCSR (tx DMA control/status)
2229          *
2230          * 31..06  reserved
2231          * 05      error
2232          * 04      eol (end of list)
2233          * 03      eob (end of buffer)
2234          * 02      IRQ enable
2235          * 01      reset
2236          * 00      enable
2237          */
2238         wr_reg32(info, TDCSR, status);  /* clear pending */
2239
2240         if (status & (BIT5 + BIT4 + BIT3)) {
2241                 // another transmit buffer has completed
2242                 // run bottom half to get more send data from user
2243                 info->pending_bh |= BH_TRANSMIT;
2244         }
2245 }
2246
2247 static void isr_txeom(struct slgt_info *info, unsigned short status)
2248 {
2249         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2250
2251         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2252         tdma_reset(info);
2253         reset_tbufs(info);
2254         if (status & IRQ_TXUNDER) {
2255                 unsigned short val = rd_reg16(info, TCR);
2256                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2257                 wr_reg16(info, TCR, val); /* clear reset bit */
2258         }
2259
2260         if (info->tx_active) {
2261                 if (info->params.mode != MGSL_MODE_ASYNC) {
2262                         if (status & IRQ_TXUNDER)
2263                                 info->icount.txunder++;
2264                         else if (status & IRQ_TXIDLE)
2265                                 info->icount.txok++;
2266                 }
2267
2268                 info->tx_active = 0;
2269                 info->tx_count = 0;
2270
2271                 del_timer(&info->tx_timer);
2272
2273                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2274                         info->signals &= ~SerialSignal_RTS;
2275                         info->drop_rts_on_tx_done = 0;
2276                         set_signals(info);
2277                 }
2278
2279 #if SYNCLINK_GENERIC_HDLC
2280                 if (info->netcount)
2281                         hdlcdev_tx_done(info);
2282                 else
2283 #endif
2284                 {
2285                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2286                                 tx_stop(info);
2287                                 return;
2288                         }
2289                         info->pending_bh |= BH_TRANSMIT;
2290                 }
2291         }
2292 }
2293
2294 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2295 {
2296         struct cond_wait *w, *prev;
2297
2298         /* wake processes waiting for specific transitions */
2299         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2300                 if (w->data & changed) {
2301                         w->data = state;
2302                         wake_up_interruptible(&w->q);
2303                         if (prev != NULL)
2304                                 prev->next = w->next;
2305                         else
2306                                 info->gpio_wait_q = w->next;
2307                 } else
2308                         prev = w;
2309         }
2310 }
2311
2312 /* interrupt service routine
2313  *
2314  *      irq     interrupt number
2315  *      dev_id  device ID supplied during interrupt registration
2316  */
2317 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2318 {
2319         struct slgt_info *info;
2320         unsigned int gsr;
2321         unsigned int i;
2322
2323         DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2324
2325         info = dev_id;
2326         if (!info)
2327                 return IRQ_NONE;
2328
2329         spin_lock(&info->lock);
2330
2331         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2332                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2333                 info->irq_occurred = 1;
2334                 for(i=0; i < info->port_count ; i++) {
2335                         if (info->port_array[i] == NULL)
2336                                 continue;
2337                         if (gsr & (BIT8 << i))
2338                                 isr_serial(info->port_array[i]);
2339                         if (gsr & (BIT16 << (i*2)))
2340                                 isr_rdma(info->port_array[i]);
2341                         if (gsr & (BIT17 << (i*2)))
2342                                 isr_tdma(info->port_array[i]);
2343                 }
2344         }
2345
2346         if (info->gpio_present) {
2347                 unsigned int state;
2348                 unsigned int changed;
2349                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2350                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2351                         /* read latched state of GPIO signals */
2352                         state = rd_reg32(info, IOVR);
2353                         /* clear pending GPIO interrupt bits */
2354                         wr_reg32(info, IOSR, changed);
2355                         for (i=0 ; i < info->port_count ; i++) {
2356                                 if (info->port_array[i] != NULL)
2357                                         isr_gpio(info->port_array[i], changed, state);
2358                         }
2359                 }
2360         }
2361
2362         for(i=0; i < info->port_count ; i++) {
2363                 struct slgt_info *port = info->port_array[i];
2364
2365                 if (port && (port->count || port->netcount) &&
2366                     port->pending_bh && !port->bh_running &&
2367                     !port->bh_requested) {
2368                         DBGISR(("%s bh queued\n", port->device_name));
2369                         schedule_work(&port->task);
2370                         port->bh_requested = 1;
2371                 }
2372         }
2373
2374         spin_unlock(&info->lock);
2375
2376         DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2377         return IRQ_HANDLED;
2378 }
2379
2380 static int startup(struct slgt_info *info)
2381 {
2382         DBGINFO(("%s startup\n", info->device_name));
2383
2384         if (info->flags & ASYNC_INITIALIZED)
2385                 return 0;
2386
2387         if (!info->tx_buf) {
2388                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2389                 if (!info->tx_buf) {
2390                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2391                         return -ENOMEM;
2392                 }
2393         }
2394
2395         info->pending_bh = 0;
2396
2397         memset(&info->icount, 0, sizeof(info->icount));
2398
2399         /* program hardware for current parameters */
2400         change_params(info);
2401
2402         if (info->tty)
2403                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2404
2405         info->flags |= ASYNC_INITIALIZED;
2406
2407         return 0;
2408 }
2409
2410 /*
2411  *  called by close() and hangup() to shutdown hardware
2412  */
2413 static void shutdown(struct slgt_info *info)
2414 {
2415         unsigned long flags;
2416
2417         if (!(info->flags & ASYNC_INITIALIZED))
2418                 return;
2419
2420         DBGINFO(("%s shutdown\n", info->device_name));
2421
2422         /* clear status wait queue because status changes */
2423         /* can't happen after shutting down the hardware */
2424         wake_up_interruptible(&info->status_event_wait_q);
2425         wake_up_interruptible(&info->event_wait_q);
2426
2427         del_timer_sync(&info->tx_timer);
2428         del_timer_sync(&info->rx_timer);
2429
2430         kfree(info->tx_buf);
2431         info->tx_buf = NULL;
2432
2433         spin_lock_irqsave(&info->lock,flags);
2434
2435         tx_stop(info);
2436         rx_stop(info);
2437
2438         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2439
2440         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2441                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2442                 set_signals(info);
2443         }
2444
2445         flush_cond_wait(&info->gpio_wait_q);
2446
2447         spin_unlock_irqrestore(&info->lock,flags);
2448
2449         if (info->tty)
2450                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2451
2452         info->flags &= ~ASYNC_INITIALIZED;
2453 }
2454
2455 static void program_hw(struct slgt_info *info)
2456 {
2457         unsigned long flags;
2458
2459         spin_lock_irqsave(&info->lock,flags);
2460
2461         rx_stop(info);
2462         tx_stop(info);
2463
2464         if (info->params.mode != MGSL_MODE_ASYNC ||
2465             info->netcount)
2466                 sync_mode(info);
2467         else
2468                 async_mode(info);
2469
2470         set_signals(info);
2471
2472         info->dcd_chkcount = 0;
2473         info->cts_chkcount = 0;
2474         info->ri_chkcount = 0;
2475         info->dsr_chkcount = 0;
2476
2477         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2478         get_signals(info);
2479
2480         if (info->netcount ||
2481             (info->tty && info->tty->termios->c_cflag & CREAD))
2482                 rx_start(info);
2483
2484         spin_unlock_irqrestore(&info->lock,flags);
2485 }
2486
2487 /*
2488  * reconfigure adapter based on new parameters
2489  */
2490 static void change_params(struct slgt_info *info)
2491 {
2492         unsigned cflag;
2493         int bits_per_char;
2494
2495         if (!info->tty || !info->tty->termios)
2496                 return;
2497         DBGINFO(("%s change_params\n", info->device_name));
2498
2499         cflag = info->tty->termios->c_cflag;
2500
2501         /* if B0 rate (hangup) specified then negate DTR and RTS */
2502         /* otherwise assert DTR and RTS */
2503         if (cflag & CBAUD)
2504                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2505         else
2506                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2507
2508         /* byte size and parity */
2509
2510         switch (cflag & CSIZE) {
2511         case CS5: info->params.data_bits = 5; break;
2512         case CS6: info->params.data_bits = 6; break;
2513         case CS7: info->params.data_bits = 7; break;
2514         case CS8: info->params.data_bits = 8; break;
2515         default:  info->params.data_bits = 7; break;
2516         }
2517
2518         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2519
2520         if (cflag & PARENB)
2521                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2522         else
2523                 info->params.parity = ASYNC_PARITY_NONE;
2524
2525         /* calculate number of jiffies to transmit a full
2526          * FIFO (32 bytes) at specified data rate
2527          */
2528         bits_per_char = info->params.data_bits +
2529                         info->params.stop_bits + 1;
2530
2531         info->params.data_rate = tty_get_baud_rate(info->tty);
2532
2533         if (info->params.data_rate) {
2534                 info->timeout = (32*HZ*bits_per_char) /
2535                                 info->params.data_rate;
2536         }
2537         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2538
2539         if (cflag & CRTSCTS)
2540                 info->flags |= ASYNC_CTS_FLOW;
2541         else
2542                 info->flags &= ~ASYNC_CTS_FLOW;
2543
2544         if (cflag & CLOCAL)
2545                 info->flags &= ~ASYNC_CHECK_CD;
2546         else
2547                 info->flags |= ASYNC_CHECK_CD;
2548
2549         /* process tty input control flags */
2550
2551         info->read_status_mask = IRQ_RXOVER;
2552         if (I_INPCK(info->tty))
2553                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2554         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2555                 info->read_status_mask |= MASK_BREAK;
2556         if (I_IGNPAR(info->tty))
2557                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2558         if (I_IGNBRK(info->tty)) {
2559                 info->ignore_status_mask |= MASK_BREAK;
2560                 /* If ignoring parity and break indicators, ignore
2561                  * overruns too.  (For real raw support).
2562                  */
2563                 if (I_IGNPAR(info->tty))
2564                         info->ignore_status_mask |= MASK_OVERRUN;
2565         }
2566
2567         program_hw(info);
2568 }
2569
2570 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2571 {
2572         DBGINFO(("%s get_stats\n",  info->device_name));
2573         if (!user_icount) {
2574                 memset(&info->icount, 0, sizeof(info->icount));
2575         } else {
2576                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2577                         return -EFAULT;
2578         }
2579         return 0;
2580 }
2581
2582 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2583 {
2584         DBGINFO(("%s get_params\n", info->device_name));
2585         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2586                 return -EFAULT;
2587         return 0;
2588 }
2589
2590 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2591 {
2592         unsigned long flags;
2593         MGSL_PARAMS tmp_params;
2594
2595         DBGINFO(("%s set_params\n", info->device_name));
2596         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2597                 return -EFAULT;
2598
2599         spin_lock_irqsave(&info->lock, flags);
2600         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2601         spin_unlock_irqrestore(&info->lock, flags);
2602
2603         change_params(info);
2604
2605         return 0;
2606 }
2607
2608 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2609 {
2610         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2611         if (put_user(info->idle_mode, idle_mode))
2612                 return -EFAULT;
2613         return 0;
2614 }
2615
2616 static int set_txidle(struct slgt_info *info, int idle_mode)
2617 {
2618         unsigned long flags;
2619         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2620         spin_lock_irqsave(&info->lock,flags);
2621         info->idle_mode = idle_mode;
2622         if (info->params.mode != MGSL_MODE_ASYNC)
2623                 tx_set_idle(info);
2624         spin_unlock_irqrestore(&info->lock,flags);
2625         return 0;
2626 }
2627
2628 static int tx_enable(struct slgt_info *info, int enable)
2629 {
2630         unsigned long flags;
2631         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2632         spin_lock_irqsave(&info->lock,flags);
2633         if (enable) {
2634                 if (!info->tx_enabled)
2635                         tx_start(info);
2636         } else {
2637                 if (info->tx_enabled)
2638                         tx_stop(info);
2639         }
2640         spin_unlock_irqrestore(&info->lock,flags);
2641         return 0;
2642 }
2643
2644 /*
2645  * abort transmit HDLC frame
2646  */
2647 static int tx_abort(struct slgt_info *info)
2648 {
2649         unsigned long flags;
2650         DBGINFO(("%s tx_abort\n", info->device_name));
2651         spin_lock_irqsave(&info->lock,flags);
2652         tdma_reset(info);
2653         spin_unlock_irqrestore(&info->lock,flags);
2654         return 0;
2655 }
2656
2657 static int rx_enable(struct slgt_info *info, int enable)
2658 {
2659         unsigned long flags;
2660         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2661         spin_lock_irqsave(&info->lock,flags);
2662         if (enable) {
2663                 if (!info->rx_enabled)
2664                         rx_start(info);
2665                 else if (enable == 2) {
2666                         /* force hunt mode (write 1 to RCR[3]) */
2667                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2668                 }
2669         } else {
2670                 if (info->rx_enabled)
2671                         rx_stop(info);
2672         }
2673         spin_unlock_irqrestore(&info->lock,flags);
2674         return 0;
2675 }
2676
2677 /*
2678  *  wait for specified event to occur
2679  */
2680 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2681 {
2682         unsigned long flags;
2683         int s;
2684         int rc=0;
2685         struct mgsl_icount cprev, cnow;
2686         int events;
2687         int mask;
2688         struct  _input_signal_events oldsigs, newsigs;
2689         DECLARE_WAITQUEUE(wait, current);
2690
2691         if (get_user(mask, mask_ptr))
2692                 return -EFAULT;
2693
2694         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2695
2696         spin_lock_irqsave(&info->lock,flags);
2697
2698         /* return immediately if state matches requested events */
2699         get_signals(info);
2700         s = info->signals;
2701
2702         events = mask &
2703                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2704                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2705                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2706                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2707         if (events) {
2708                 spin_unlock_irqrestore(&info->lock,flags);
2709                 goto exit;
2710         }
2711
2712         /* save current irq counts */
2713         cprev = info->icount;
2714         oldsigs = info->input_signal_events;
2715
2716         /* enable hunt and idle irqs if needed */
2717         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2718                 unsigned short val = rd_reg16(info, SCR);
2719                 if (!(val & IRQ_RXIDLE))
2720                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2721         }
2722
2723         set_current_state(TASK_INTERRUPTIBLE);
2724         add_wait_queue(&info->event_wait_q, &wait);
2725
2726         spin_unlock_irqrestore(&info->lock,flags);
2727
2728         for(;;) {
2729                 schedule();
2730                 if (signal_pending(current)) {
2731                         rc = -ERESTARTSYS;
2732                         break;
2733                 }
2734
2735                 /* get current irq counts */
2736                 spin_lock_irqsave(&info->lock,flags);
2737                 cnow = info->icount;
2738                 newsigs = info->input_signal_events;
2739                 set_current_state(TASK_INTERRUPTIBLE);
2740                 spin_unlock_irqrestore(&info->lock,flags);
2741
2742                 /* if no change, wait aborted for some reason */
2743                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2744                     newsigs.dsr_down == oldsigs.dsr_down &&
2745                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2746                     newsigs.dcd_down == oldsigs.dcd_down &&
2747                     newsigs.cts_up   == oldsigs.cts_up   &&
2748                     newsigs.cts_down == oldsigs.cts_down &&
2749                     newsigs.ri_up    == oldsigs.ri_up    &&
2750                     newsigs.ri_down  == oldsigs.ri_down  &&
2751                     cnow.exithunt    == cprev.exithunt   &&
2752                     cnow.rxidle      == cprev.rxidle) {
2753                         rc = -EIO;
2754                         break;
2755                 }
2756
2757                 events = mask &
2758                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2759                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2760                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2761                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2762                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2763                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2764                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2765                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2766                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2767                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2768                 if (events)
2769                         break;
2770
2771                 cprev = cnow;
2772                 oldsigs = newsigs;
2773         }
2774
2775         remove_wait_queue(&info->event_wait_q, &wait);
2776         set_current_state(TASK_RUNNING);
2777
2778
2779         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2780                 spin_lock_irqsave(&info->lock,flags);
2781                 if (!waitqueue_active(&info->event_wait_q)) {
2782                         /* disable enable exit hunt mode/idle rcvd IRQs */
2783                         wr_reg16(info, SCR,
2784                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2785                 }
2786                 spin_unlock_irqrestore(&info->lock,flags);
2787         }
2788 exit:
2789         if (rc == 0)
2790                 rc = put_user(events, mask_ptr);
2791         return rc;
2792 }
2793
2794 static int get_interface(struct slgt_info *info, int __user *if_mode)
2795 {
2796         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2797         if (put_user(info->if_mode, if_mode))
2798                 return -EFAULT;
2799         return 0;
2800 }
2801
2802 static int set_interface(struct slgt_info *info, int if_mode)
2803 {
2804         unsigned long flags;
2805         unsigned short val;
2806
2807         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2808         spin_lock_irqsave(&info->lock,flags);
2809         info->if_mode = if_mode;
2810
2811         msc_set_vcr(info);
2812
2813         /* TCR (tx control) 07  1=RTS driver control */
2814         val = rd_reg16(info, TCR);
2815         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2816                 val |= BIT7;
2817         else
2818                 val &= ~BIT7;
2819         wr_reg16(info, TCR, val);
2820
2821         spin_unlock_irqrestore(&info->lock,flags);
2822         return 0;
2823 }
2824
2825 /*
2826  * set general purpose IO pin state and direction
2827  *
2828  * user_gpio fields:
2829  * state   each bit indicates a pin state
2830  * smask   set bit indicates pin state to set
2831  * dir     each bit indicates a pin direction (0=input, 1=output)
2832  * dmask   set bit indicates pin direction to set
2833  */
2834 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2835 {
2836         unsigned long flags;
2837         struct gpio_desc gpio;
2838         __u32 data;
2839
2840         if (!info->gpio_present)
2841                 return -EINVAL;
2842         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2843                 return -EFAULT;
2844         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2845                  info->device_name, gpio.state, gpio.smask,
2846                  gpio.dir, gpio.dmask));
2847
2848         spin_lock_irqsave(&info->lock,flags);
2849         if (gpio.dmask) {
2850                 data = rd_reg32(info, IODR);
2851                 data |= gpio.dmask & gpio.dir;
2852                 data &= ~(gpio.dmask & ~gpio.dir);
2853                 wr_reg32(info, IODR, data);
2854         }
2855         if (gpio.smask) {
2856                 data = rd_reg32(info, IOVR);
2857                 data |= gpio.smask & gpio.state;
2858                 data &= ~(gpio.smask & ~gpio.state);
2859                 wr_reg32(info, IOVR, data);
2860         }
2861         spin_unlock_irqrestore(&info->lock,flags);
2862
2863         return 0;
2864 }
2865
2866 /*
2867  * get general purpose IO pin state and direction
2868  */
2869 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2870 {
2871         struct gpio_desc gpio;
2872         if (!info->gpio_present)
2873                 return -EINVAL;
2874         gpio.state = rd_reg32(info, IOVR);
2875         gpio.smask = 0xffffffff;
2876         gpio.dir   = rd_reg32(info, IODR);
2877         gpio.dmask = 0xffffffff;
2878         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2879                 return -EFAULT;
2880         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2881                  info->device_name, gpio.state, gpio.dir));
2882         return 0;
2883 }
2884
2885 /*
2886  * conditional wait facility
2887  */
2888 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2889 {
2890         init_waitqueue_head(&w->q);
2891         init_waitqueue_entry(&w->wait, current);
2892         w->data = data;
2893 }
2894
2895 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2896 {
2897         set_current_state(TASK_INTERRUPTIBLE);
2898         add_wait_queue(&w->q, &w->wait);
2899         w->next = *head;
2900         *head = w;
2901 }
2902
2903 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2904 {
2905         struct cond_wait *w, *prev;
2906         remove_wait_queue(&cw->q, &cw->wait);
2907         set_current_state(TASK_RUNNING);
2908         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2909                 if (w == cw) {
2910                         if (prev != NULL)
2911                                 prev->next = w->next;
2912                         else
2913                                 *head = w->next;
2914                         break;
2915                 }
2916         }
2917 }
2918
2919 static void flush_cond_wait(struct cond_wait **head)
2920 {
2921         while (*head != NULL) {
2922                 wake_up_interruptible(&(*head)->q);
2923                 *head = (*head)->next;
2924         }
2925 }
2926
2927 /*
2928  * wait for general purpose I/O pin(s) to enter specified state
2929  *
2930  * user_gpio fields:
2931  * state - bit indicates target pin state
2932  * smask - set bit indicates watched pin
2933  *
2934  * The wait ends when at least one watched pin enters the specified
2935  * state. When 0 (no error) is returned, user_gpio->state is set to the
2936  * state of all GPIO pins when the wait ends.
2937  *
2938  * Note: Each pin may be a dedicated input, dedicated output, or
2939  * configurable input/output. The number and configuration of pins
2940  * varies with the specific adapter model. Only input pins (dedicated
2941  * or configured) can be monitored with this function.
2942  */
2943 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2944 {
2945         unsigned long flags;
2946         int rc = 0;
2947         struct gpio_desc gpio;
2948         struct cond_wait wait;
2949         u32 state;
2950
2951         if (!info->gpio_present)
2952                 return -EINVAL;
2953         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2954                 return -EFAULT;
2955         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2956                  info->device_name, gpio.state, gpio.smask));
2957         /* ignore output pins identified by set IODR bit */
2958         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2959                 return -EINVAL;
2960         init_cond_wait(&wait, gpio.smask);
2961
2962         spin_lock_irqsave(&info->lock, flags);
2963         /* enable interrupts for watched pins */
2964         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2965         /* get current pin states */
2966         state = rd_reg32(info, IOVR);
2967
2968         if (gpio.smask & ~(state ^ gpio.state)) {
2969                 /* already in target state */
2970                 gpio.state = state;
2971         } else {
2972                 /* wait for target state */
2973                 add_cond_wait(&info->gpio_wait_q, &wait);
2974                 spin_unlock_irqrestore(&info->lock, flags);
2975                 schedule();
2976                 if (signal_pending(current))
2977                         rc = -ERESTARTSYS;
2978                 else
2979                         gpio.state = wait.data;
2980                 spin_lock_irqsave(&info->lock, flags);
2981                 remove_cond_wait(&info->gpio_wait_q, &wait);
2982         }
2983
2984         /* disable all GPIO interrupts if no waiting processes */
2985         if (info->gpio_wait_q == NULL)
2986                 wr_reg32(info, IOER, 0);
2987         spin_unlock_irqrestore(&info->lock,flags);
2988
2989         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2990                 rc = -EFAULT;
2991         return rc;
2992 }
2993
2994 static int modem_input_wait(struct slgt_info *info,int arg)
2995 {
2996         unsigned long flags;
2997         int rc;
2998         struct mgsl_icount cprev, cnow;
2999         DECLARE_WAITQUEUE(wait, current);
3000
3001         /* save current irq counts */
3002         spin_lock_irqsave(&info->lock,flags);
3003         cprev = info->icount;
3004         add_wait_queue(&info->status_event_wait_q, &wait);
3005         set_current_state(TASK_INTERRUPTIBLE);
3006         spin_unlock_irqrestore(&info->lock,flags);
3007
3008         for(;;) {
3009                 schedule();
3010                 if (signal_pending(current)) {
3011                         rc = -ERESTARTSYS;
3012                         break;
3013                 }
3014
3015                 /* get new irq counts */
3016                 spin_lock_irqsave(&info->lock,flags);
3017                 cnow = info->icount;
3018                 set_current_state(TASK_INTERRUPTIBLE);
3019                 spin_unlock_irqrestore(&info->lock,flags);
3020
3021                 /* if no change, wait aborted for some reason */
3022                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3023                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3024                         rc = -EIO;
3025                         break;
3026                 }
3027
3028                 /* check for change in caller specified modem input */
3029                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3030                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3031                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3032                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3033                         rc = 0;
3034                         break;
3035                 }
3036
3037                 cprev = cnow;
3038         }
3039         remove_wait_queue(&info->status_event_wait_q, &wait);
3040         set_current_state(TASK_RUNNING);
3041         return rc;
3042 }
3043
3044 /*
3045  *  return state of serial control and status signals
3046  */
3047 static int tiocmget(struct tty_struct *tty, struct file *file)
3048 {
3049         struct slgt_info *info = tty->driver_data;
3050         unsigned int result;
3051         unsigned long flags;
3052
3053         spin_lock_irqsave(&info->lock,flags);
3054         get_signals(info);
3055         spin_unlock_irqrestore(&info->lock,flags);
3056
3057         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3058                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3059                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3060                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3061                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3062                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3063
3064         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3065         return result;
3066 }
3067
3068 /*
3069  * set modem control signals (DTR/RTS)
3070  *
3071  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3072  *              TIOCMSET = set/clear signal values
3073  *      value   bit mask for command
3074  */
3075 static int tiocmset(struct tty_struct *tty, struct file *file,
3076                     unsigned int set, unsigned int clear)
3077 {
3078         struct slgt_info *info = tty->driver_data;
3079         unsigned long flags;
3080
3081         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3082
3083         if (set & TIOCM_RTS)
3084                 info->signals |= SerialSignal_RTS;
3085         if (set & TIOCM_DTR)
3086                 info->signals |= SerialSignal_DTR;
3087         if (clear & TIOCM_RTS)
3088                 info->signals &= ~SerialSignal_RTS;
3089         if (clear & TIOCM_DTR)
3090                 info->signals &= ~SerialSignal_DTR;
3091
3092         spin_lock_irqsave(&info->lock,flags);
3093         set_signals(info);
3094         spin_unlock_irqrestore(&info->lock,flags);
3095         return 0;
3096 }
3097
3098 /*
3099  *  block current process until the device is ready to open
3100  */
3101 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3102                            struct slgt_info *info)
3103 {
3104         DECLARE_WAITQUEUE(wait, current);
3105         int             retval;
3106         int             do_clocal = 0, extra_count = 0;
3107         unsigned long   flags;
3108
3109         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3110
3111         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3112                 /* nonblock mode is set or port is not enabled */
3113                 info->flags |= ASYNC_NORMAL_ACTIVE;
3114                 return 0;
3115         }
3116
3117         if (tty->termios->c_cflag & CLOCAL)
3118                 do_clocal = 1;
3119
3120         /* Wait for carrier detect and the line to become
3121          * free (i.e., not in use by the callout).  While we are in
3122          * this loop, info->count is dropped by one, so that
3123          * close() knows when to free things.  We restore it upon
3124          * exit, either normal or abnormal.
3125          */
3126
3127         retval = 0;
3128         add_wait_queue(&info->open_wait, &wait);
3129
3130         spin_lock_irqsave(&info->lock, flags);
3131         if (!tty_hung_up_p(filp)) {
3132                 extra_count = 1;
3133                 info->count--;
3134         }
3135         spin_unlock_irqrestore(&info->lock, flags);
3136         info->blocked_open++;
3137
3138         while (1) {
3139                 if ((tty->termios->c_cflag & CBAUD)) {
3140                         spin_lock_irqsave(&info->lock,flags);
3141                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3142                         set_signals(info);
3143                         spin_unlock_irqrestore(&info->lock,flags);
3144                 }
3145
3146                 set_current_state(TASK_INTERRUPTIBLE);
3147
3148                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3149                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3150                                         -EAGAIN : -ERESTARTSYS;
3151                         break;
3152                 }
3153
3154                 spin_lock_irqsave(&info->lock,flags);
3155                 get_signals(info);
3156                 spin_unlock_irqrestore(&info->lock,flags);
3157
3158                 if (!(info->flags & ASYNC_CLOSING) &&
3159                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3160                         break;
3161                 }
3162
3163                 if (signal_pending(current)) {
3164                         retval = -ERESTARTSYS;
3165                         break;
3166                 }
3167
3168                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3169                 schedule();
3170         }
3171
3172         set_current_state(TASK_RUNNING);
3173         remove_wait_queue(&info->open_wait, &wait);
3174
3175         if (extra_count)
3176                 info->count++;
3177         info->blocked_open--;
3178
3179         if (!retval)
3180                 info->flags |= ASYNC_NORMAL_ACTIVE;
3181
3182         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3183         return retval;
3184 }
3185
3186 static int alloc_tmp_rbuf(struct slgt_info *info)
3187 {
3188         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3189         if (info->tmp_rbuf == NULL)
3190                 return -ENOMEM;
3191         return 0;
3192 }
3193
3194 static void free_tmp_rbuf(struct slgt_info *info)
3195 {
3196         kfree(info->tmp_rbuf);
3197         info->tmp_rbuf = NULL;
3198 }
3199
3200 /*
3201  * allocate DMA descriptor lists.
3202  */
3203 static int alloc_desc(struct slgt_info *info)
3204 {
3205         unsigned int i;
3206         unsigned int pbufs;
3207
3208         /* allocate memory to hold descriptor lists */
3209         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3210         if (info->bufs == NULL)
3211                 return -ENOMEM;
3212
3213         memset(info->bufs, 0, DESC_LIST_SIZE);
3214
3215         info->rbufs = (struct slgt_desc*)info->bufs;
3216         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3217
3218         pbufs = (unsigned int)info->bufs_dma_addr;
3219
3220         /*
3221          * Build circular lists of descriptors
3222          */
3223
3224         for (i=0; i < info->rbuf_count; i++) {
3225                 /* physical address of this descriptor */
3226                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3227
3228                 /* physical address of next descriptor */
3229                 if (i == info->rbuf_count - 1)
3230                         info->rbufs[i].next = cpu_to_le32(pbufs);
3231                 else
3232                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3233                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3234         }
3235
3236         for (i=0; i < info->tbuf_count; i++) {
3237                 /* physical address of this descriptor */
3238                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3239
3240                 /* physical address of next descriptor */
3241                 if (i == info->tbuf_count - 1)
3242                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3243                 else
3244                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3245         }
3246
3247         return 0;
3248 }
3249
3250 static void free_desc(struct slgt_info *info)
3251 {
3252         if (info->bufs != NULL) {
3253                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3254                 info->bufs  = NULL;
3255                 info->rbufs = NULL;
3256                 info->tbufs = NULL;
3257         }
3258 }
3259
3260 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3261 {
3262         int i;
3263         for (i=0; i < count; i++) {
3264                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3265                         return -ENOMEM;
3266                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3267         }
3268         return 0;
3269 }
3270
3271 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3272 {
3273         int i;
3274         for (i=0; i < count; i++) {
3275                 if (bufs[i].buf == NULL)
3276                         continue;
3277                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3278                 bufs[i].buf = NULL;
3279         }
3280 }
3281
3282 static int alloc_dma_bufs(struct slgt_info *info)
3283 {
3284         info->rbuf_count = 32;
3285         info->tbuf_count = 32;
3286
3287         if (alloc_desc(info) < 0 ||
3288             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3289             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3290             alloc_tmp_rbuf(info) < 0) {
3291                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3292                 return -ENOMEM;
3293         }
3294         reset_rbufs(info);
3295         return 0;
3296 }
3297
3298 static void free_dma_bufs(struct slgt_info *info)
3299 {
3300         if (info->bufs) {
3301                 free_bufs(info, info->rbufs, info->rbuf_count);
3302                 free_bufs(info, info->tbufs, info->tbuf_count);
3303                 free_desc(info);
3304         }
3305         free_tmp_rbuf(info);
3306 }
3307
3308 static int claim_resources(struct slgt_info *info)
3309 {
3310         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3311                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3312                         info->device_name, info->phys_reg_addr));
3313                 info->init_error = DiagStatus_AddressConflict;
3314                 goto errout;
3315         }
3316         else
3317                 info->reg_addr_requested = 1;
3318
3319         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3320         if (!info->reg_addr) {
3321                 DBGERR(("%s cant map device registers, addr=%08X\n",
3322                         info->device_name, info->phys_reg_addr));
3323                 info->init_error = DiagStatus_CantAssignPciResources;
3324                 goto errout;
3325         }
3326         return 0;
3327
3328 errout:
3329         release_resources(info);
3330         return -ENODEV;
3331 }
3332
3333 static void release_resources(struct slgt_info *info)
3334 {
3335         if (info->irq_requested) {
3336                 free_irq(info->irq_level, info);
3337                 info->irq_requested = 0;
3338         }
3339
3340         if (info->reg_addr_requested) {
3341                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3342                 info->reg_addr_requested = 0;
3343         }
3344
3345         if (info->reg_addr) {
3346                 iounmap(info->reg_addr);
3347                 info->reg_addr = NULL;
3348         }
3349 }
3350
3351 /* Add the specified device instance data structure to the
3352  * global linked list of devices and increment the device count.
3353  */
3354 static void add_device(struct slgt_info *info)
3355 {
3356         char *devstr;
3357
3358         info->next_device = NULL;
3359         info->line = slgt_device_count;
3360         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3361
3362         if (info->line < MAX_DEVICES) {
3363                 if (maxframe[info->line])
3364                         info->max_frame_size = maxframe[info->line];
3365                 info->dosyncppp = dosyncppp[info->line];
3366         }
3367
3368         slgt_device_count++;
3369
3370         if (!slgt_device_list)
3371                 slgt_device_list = info;
3372         else {
3373                 struct slgt_info *current_dev = slgt_device_list;
3374                 while(current_dev->next_device)
3375                         current_dev = current_dev->next_device;
3376                 current_dev->next_device = info;
3377         }
3378
3379         if (info->max_frame_size < 4096)
3380                 info->max_frame_size = 4096;
3381         else if (info->max_frame_size > 65535)
3382                 info->max_frame_size = 65535;
3383
3384         switch(info->pdev->device) {
3385         case SYNCLINK_GT_DEVICE_ID:
3386                 devstr = "GT";
3387                 break;
3388         case SYNCLINK_GT2_DEVICE_ID:
3389                 devstr = "GT2";
3390                 break;
3391         case SYNCLINK_GT4_DEVICE_ID:
3392                 devstr = "GT4";
3393                 break;
3394         case SYNCLINK_AC_DEVICE_ID:
3395                 devstr = "AC";
3396                 info->params.mode = MGSL_MODE_ASYNC;
3397                 break;
3398         default:
3399                 devstr = "(unknown model)";
3400         }
3401         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3402                 devstr, info->device_name, info->phys_reg_addr,
3403                 info->irq_level, info->max_frame_size);
3404
3405 #if SYNCLINK_GENERIC_HDLC
3406         hdlcdev_init(info);
3407 #endif
3408 }
3409
3410 /*
3411  *  allocate device instance structure, return NULL on failure
3412  */
3413 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3414 {
3415         struct slgt_info *info;
3416
3417         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3418
3419         if (!info) {
3420                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3421                         driver_name, adapter_num, port_num));
3422         } else {
3423                 info->magic = MGSL_MAGIC;
3424                 INIT_WORK(&info->task, bh_handler);
3425                 info->max_frame_size = 4096;
3426                 info->raw_rx_size = DMABUFSIZE;
3427                 info->close_delay = 5*HZ/10;
3428                 info->closing_wait = 30*HZ;
3429                 init_waitqueue_head(&info->open_wait);
3430                 init_waitqueue_head(&info->close_wait);
3431                 init_waitqueue_head(&info->status_event_wait_q);
3432                 init_waitqueue_head(&info->event_wait_q);
3433                 spin_lock_init(&info->netlock);
3434                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3435                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3436                 info->adapter_num = adapter_num;
3437                 info->port_num = port_num;
3438
3439                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3440                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3441
3442                 /* Copy configuration info to device instance data */
3443                 info->pdev = pdev;
3444                 info->irq_level = pdev->irq;
3445                 info->phys_reg_addr = pci_resource_start(pdev,0);
3446
3447                 info->bus_type = MGSL_BUS_TYPE_PCI;
3448                 info->irq_flags = IRQF_SHARED;
3449
3450                 info->init_error = -1; /* assume error, set to 0 on successful init */
3451         }
3452
3453         return info;
3454 }
3455
3456 static void device_init(int adapter_num, struct pci_dev *pdev)
3457 {
3458         struct slgt_info *port_array[SLGT_MAX_PORTS];
3459         int i;
3460         int port_count = 1;
3461
3462         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3463                 port_count = 2;
3464         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3465                 port_count = 4;
3466
3467         /* allocate device instances for all ports */
3468         for (i=0; i < port_count; ++i) {
3469                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3470                 if (port_array[i] == NULL) {
3471                         for (--i; i >= 0; --i)
3472                                 kfree(port_array[i]);
3473                         return;
3474                 }
3475         }
3476
3477         /* give copy of port_array to all ports and add to device list  */
3478         for (i=0; i < port_count; ++i) {
3479                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3480                 add_device(port_array[i]);
3481                 port_array[i]->port_count = port_count;
3482                 spin_lock_init(&port_array[i]->lock);
3483         }
3484
3485         /* Allocate and claim adapter resources */
3486         if (!claim_resources(port_array[0])) {
3487
3488                 alloc_dma_bufs(port_array[0]);
3489
3490                 /* copy resource information from first port to others */
3491                 for (i = 1; i < port_count; ++i) {
3492                         port_array[i]->lock      = port_array[0]->lock;
3493                         port_array[i]->irq_level = port_array[0]->irq_level;
3494                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3495                         alloc_dma_bufs(port_array[i]);
3496                 }
3497
3498                 if (request_irq(port_array[0]->irq_level,
3499                                         slgt_interrupt,
3500                                         port_array[0]->irq_flags,
3501                                         port_array[0]->device_name,
3502                                         port_array[0]) < 0) {
3503                         DBGERR(("%s request_irq failed IRQ=%d\n",
3504                                 port_array[0]->device_name,
3505                                 port_array[0]->irq_level));
3506                 } else {
3507                         port_array[0]->irq_requested = 1;
3508                         adapter_test(port_array[0]);
3509                         for (i=1 ; i < port_count ; i++) {
3510                                 port_array[i]->init_error = port_array[0]->init_error;
3511                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3512                         }
3513                 }
3514         }
3515
3516         for (i=0; i < port_count; ++i)
3517                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3518 }
3519
3520 static int __devinit init_one(struct pci_dev *dev,
3521                               const struct pci_device_id *ent)
3522 {
3523         if (pci_enable_device(dev)) {
3524                 printk("error enabling pci device %p\n", dev);
3525                 return -EIO;
3526         }
3527         pci_set_master(dev);
3528         device_init(slgt_device_count, dev);
3529         return 0;
3530 }
3531
3532 static void __devexit remove_one(struct pci_dev *dev)
3533 {
3534 }
3535
3536 static const struct tty_operations ops = {
3537         .open = open,
3538         .close = close,
3539         .write = write,
3540         .put_char = put_char,
3541         .flush_chars = flush_chars,
3542         .write_room = write_room,
3543         .chars_in_buffer = chars_in_buffer,
3544         .flush_buffer = flush_buffer,
3545         .ioctl = ioctl,
3546         .compat_ioctl = slgt_compat_ioctl,
3547         .throttle = throttle,
3548         .unthrottle = unthrottle,
3549         .send_xchar = send_xchar,
3550         .break_ctl = set_break,
3551         .wait_until_sent = wait_until_sent,
3552         .read_proc = read_proc,
3553         .set_termios = set_termios,
3554         .stop = tx_hold,
3555         .start = tx_release,
3556         .hangup = hangup,
3557         .tiocmget = tiocmget,
3558         .tiocmset = tiocmset,
3559 };
3560
3561 static void slgt_cleanup(void)
3562 {
3563         int rc;
3564         struct slgt_info *info;
3565         struct slgt_info *tmp;
3566
3567         printk("unload %s %s\n", driver_name, driver_version);
3568
3569         if (serial_driver) {
3570                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3571                         tty_unregister_device(serial_driver, info->line);
3572                 if ((rc = tty_unregister_driver(serial_driver)))
3573                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3574                 put_tty_driver(serial_driver);
3575         }
3576
3577         /* reset devices */
3578         info = slgt_device_list;
3579         while(info) {
3580                 reset_port(info);
3581                 info = info->next_device;
3582         }
3583
3584         /* release devices */
3585         info = slgt_device_list;
3586         while(info) {
3587 #if SYNCLINK_GENERIC_HDLC
3588                 hdlcdev_exit(info);
3589 #endif
3590                 free_dma_bufs(info);
3591                 free_tmp_rbuf(info);
3592                 if (info->port_num == 0)
3593                         release_resources(info);
3594                 tmp = info;
3595                 info = info->next_device;
3596                 kfree(tmp);
3597         }
3598
3599         if (pci_registered)
3600                 pci_unregister_driver(&pci_driver);
3601 }
3602
3603 /*
3604  *  Driver initialization entry point.
3605  */
3606 static int __init slgt_init(void)
3607 {
3608         int rc;
3609
3610         printk("%s %s\n", driver_name, driver_version);
3611
3612         serial_driver = alloc_tty_driver(MAX_DEVICES);
3613         if (!serial_driver) {
3614                 printk("%s can't allocate tty driver\n", driver_name);
3615                 return -ENOMEM;
3616         }
3617
3618         /* Initialize the tty_driver structure */
3619
3620         serial_driver->owner = THIS_MODULE;
3621         serial_driver->driver_name = tty_driver_name;
3622         serial_driver->name = tty_dev_prefix;
3623         serial_driver->major = ttymajor;
3624         serial_driver->minor_start = 64;
3625         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3626         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3627         serial_driver->init_termios = tty_std_termios;
3628         serial_driver->init_termios.c_cflag =
3629                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3630         serial_driver->init_termios.c_ispeed = 9600;
3631         serial_driver->init_termios.c_ospeed = 9600;
3632         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3633         tty_set_operations(serial_driver, &ops);
3634         if ((rc = tty_register_driver(serial_driver)) < 0) {
3635                 DBGERR(("%s can't register serial driver\n", driver_name));
3636                 put_tty_driver(serial_driver);
3637                 serial_driver = NULL;
3638                 goto error;
3639         }
3640
3641         printk("%s %s, tty major#%d\n",
3642                 driver_name, driver_version,
3643                 serial_driver->major);
3644
3645         slgt_device_count = 0;
3646         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3647                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3648                 goto error;
3649         }
3650         pci_registered = 1;
3651
3652         if (!slgt_device_list)
3653                 printk("%s no devices found\n",driver_name);
3654
3655         return 0;
3656
3657 error:
3658         slgt_cleanup();
3659         return rc;
3660 }
3661
3662 static void __exit slgt_exit(void)
3663 {
3664         slgt_cleanup();
3665 }
3666
3667 module_init(slgt_init);
3668 module_exit(slgt_exit);
3669
3670 /*
3671  * register access routines
3672  */
3673
3674 #define CALC_REGADDR() \
3675         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3676         if (addr >= 0x80) \
3677                 reg_addr += (info->port_num) * 32;
3678
3679 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3680 {
3681         CALC_REGADDR();
3682         return readb((void __iomem *)reg_addr);
3683 }
3684
3685 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3686 {
3687         CALC_REGADDR();
3688         writeb(value, (void __iomem *)reg_addr);
3689 }
3690
3691 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3692 {
3693         CALC_REGADDR();
3694         return readw((void __iomem *)reg_addr);
3695 }
3696
3697 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3698 {
3699         CALC_REGADDR();
3700         writew(value, (void __iomem *)reg_addr);
3701 }
3702
3703 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3704 {
3705         CALC_REGADDR();
3706         return readl((void __iomem *)reg_addr);
3707 }
3708
3709 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3710 {
3711         CALC_REGADDR();
3712         writel(value, (void __iomem *)reg_addr);
3713 }
3714
3715 static void rdma_reset(struct slgt_info *info)
3716 {
3717         unsigned int i;
3718
3719         /* set reset bit */
3720         wr_reg32(info, RDCSR, BIT1);
3721
3722         /* wait for enable bit cleared */
3723         for(i=0 ; i < 1000 ; i++)
3724                 if (!(rd_reg32(info, RDCSR) & BIT0))
3725                         break;
3726 }
3727
3728 static void tdma_reset(struct slgt_info *info)
3729 {
3730         unsigned int i;
3731
3732         /* set reset bit */
3733         wr_reg32(info, TDCSR, BIT1);
3734
3735         /* wait for enable bit cleared */
3736         for(i=0 ; i < 1000 ; i++)
3737                 if (!(rd_reg32(info, TDCSR) & BIT0))
3738                         break;
3739 }
3740
3741 /*
3742  * enable internal loopback
3743  * TxCLK and RxCLK are generated from BRG
3744  * and TxD is looped back to RxD internally.
3745  */
3746 static void enable_loopback(struct slgt_info *info)
3747 {
3748         /* SCR (serial control) BIT2=looopback enable */
3749         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3750
3751         if (info->params.mode != MGSL_MODE_ASYNC) {
3752                 /* CCR (clock control)
3753                  * 07..05  tx clock source (010 = BRG)
3754                  * 04..02  rx clock source (010 = BRG)
3755                  * 01      auxclk enable   (0 = disable)
3756                  * 00      BRG enable      (1 = enable)
3757                  *
3758                  * 0100 1001
3759                  */
3760                 wr_reg8(info, CCR, 0x49);
3761
3762                 /* set speed if available, otherwise use default */
3763                 if (info->params.clock_speed)
3764                         set_rate(info, info->params.clock_speed);
3765                 else
3766                         set_rate(info, 3686400);
3767         }
3768 }
3769
3770 /*
3771  *  set baud rate generator to specified rate
3772  */
3773 static void set_rate(struct slgt_info *info, u32 rate)
3774 {
3775         unsigned int div;
3776         static unsigned int osc = 14745600;
3777
3778         /* div = osc/rate - 1
3779          *
3780          * Round div up if osc/rate is not integer to
3781          * force to next slowest rate.
3782          */
3783
3784         if (rate) {
3785                 div = osc/rate;
3786                 if (!(osc % rate) && div)
3787                         div--;
3788                 wr_reg16(info, BDR, (unsigned short)div);
3789         }
3790 }
3791
3792 static void rx_stop(struct slgt_info *info)
3793 {
3794         unsigned short val;
3795
3796         /* disable and reset receiver */
3797         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3798         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3799         wr_reg16(info, RCR, val);                  /* clear reset bit */
3800
3801         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3802
3803         /* clear pending rx interrupts */
3804         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3805
3806         rdma_reset(info);
3807
3808         info->rx_enabled = 0;
3809         info->rx_restart = 0;
3810 }
3811
3812 static void rx_start(struct slgt_info *info)
3813 {
3814         unsigned short val;
3815
3816         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3817
3818         /* clear pending rx overrun IRQ */
3819         wr_reg16(info, SSR, IRQ_RXOVER);
3820
3821         /* reset and disable receiver */
3822         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3823         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3824         wr_reg16(info, RCR, val);                  /* clear reset bit */
3825
3826         rdma_reset(info);
3827         reset_rbufs(info);
3828
3829         /* set 1st descriptor address */
3830         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3831
3832         if (info->params.mode != MGSL_MODE_ASYNC) {
3833                 /* enable rx DMA and DMA interrupt */
3834                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3835         } else {
3836                 /* enable saving of rx status, rx DMA and DMA interrupt */
3837                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3838         }
3839
3840         slgt_irq_on(info, IRQ_RXOVER);
3841
3842         /* enable receiver */
3843         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3844
3845         info->rx_restart = 0;
3846         info->rx_enabled = 1;
3847 }
3848
3849 static void tx_start(struct slgt_info *info)
3850 {
3851         if (!info->tx_enabled) {
3852                 wr_reg16(info, TCR,
3853                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3854                 info->tx_enabled = TRUE;
3855         }
3856
3857         if (info->tx_count) {
3858                 info->drop_rts_on_tx_done = 0;
3859
3860                 if (info->params.mode != MGSL_MODE_ASYNC) {
3861                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3862                                 get_signals(info);
3863                                 if (!(info->signals & SerialSignal_RTS)) {
3864                                         info->signals |= SerialSignal_RTS;
3865                                         set_signals(info);
3866                                         info->drop_rts_on_tx_done = 1;
3867                                 }
3868                         }
3869
3870                         slgt_irq_off(info, IRQ_TXDATA);
3871                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3872                         /* clear tx idle and underrun status bits */
3873                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3874
3875                         if (!(rd_reg32(info, TDCSR) & BIT0)) {
3876                                 /* tx DMA stopped, restart tx DMA */
3877                                 tdma_reset(info);
3878                                 /* set 1st descriptor address */
3879                                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3880                                 switch(info->params.mode) {
3881                                 case MGSL_MODE_RAW:
3882                                 case MGSL_MODE_MONOSYNC:
3883                                 case MGSL_MODE_BISYNC:
3884                                         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3885                                         break;
3886                                 default:
3887                                         wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3888                                 }
3889                         }
3890
3891                         if (info->params.mode == MGSL_MODE_HDLC)
3892                                 mod_timer(&info->tx_timer, jiffies +
3893                                                 msecs_to_jiffies(5000));
3894                 } else {
3895                         tdma_reset(info);
3896                         /* set 1st descriptor address */
3897                         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3898
3899                         slgt_irq_off(info, IRQ_TXDATA);
3900                         slgt_irq_on(info, IRQ_TXIDLE);
3901                         /* clear tx idle status bit */
3902                         wr_reg16(info, SSR, IRQ_TXIDLE);
3903
3904                         /* enable tx DMA */
3905                         wr_reg32(info, TDCSR, BIT0);
3906                 }
3907
3908                 info->tx_active = 1;
3909         }
3910 }
3911
3912 static void tx_stop(struct slgt_info *info)
3913 {
3914         unsigned short val;
3915
3916         del_timer(&info->tx_timer);
3917
3918         tdma_reset(info);
3919
3920         /* reset and disable transmitter */
3921         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3922         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3923
3924         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3925
3926         /* clear tx idle and underrun status bit */
3927         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3928
3929         reset_tbufs(info);
3930
3931         info->tx_enabled = 0;
3932         info->tx_active  = 0;
3933 }
3934
3935 static void reset_port(struct slgt_info *info)
3936 {
3937         if (!info->reg_addr)
3938                 return;
3939
3940         tx_stop(info);
3941         rx_stop(info);
3942
3943         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3944         set_signals(info);
3945
3946         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3947 }
3948
3949 static void reset_adapter(struct slgt_info *info)
3950 {
3951         int i;
3952         for (i=0; i < info->port_count; ++i) {
3953                 if (info->port_array[i])
3954                         reset_port(info->port_array[i]);
3955         }
3956 }
3957
3958 static void async_mode(struct slgt_info *info)
3959 {
3960         unsigned short val;
3961
3962         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3963         tx_stop(info);
3964         rx_stop(info);
3965
3966         /* TCR (tx control)
3967          *
3968          * 15..13  mode, 010=async
3969          * 12..10  encoding, 000=NRZ
3970          * 09      parity enable
3971          * 08      1=odd parity, 0=even parity
3972          * 07      1=RTS driver control
3973          * 06      1=break enable
3974          * 05..04  character length
3975          *         00=5 bits
3976          *         01=6 bits
3977          *         10=7 bits
3978          *         11=8 bits
3979          * 03      0=1 stop bit, 1=2 stop bits
3980          * 02      reset
3981          * 01      enable
3982          * 00      auto-CTS enable
3983          */
3984         val = 0x4000;
3985
3986         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3987                 val |= BIT7;
3988
3989         if (info->params.parity != ASYNC_PARITY_NONE) {
3990                 val |= BIT9;
3991                 if (info->params.parity == ASYNC_PARITY_ODD)
3992                         val |= BIT8;
3993         }
3994
3995         switch (info->params.data_bits)
3996         {
3997         case 6: val |= BIT4; break;
3998         case 7: val |= BIT5; break;
3999         case 8: val |= BIT5 + BIT4; break;
4000         }
4001
4002         if (info->params.stop_bits != 1)
4003                 val |= BIT3;
4004
4005         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4006                 val |= BIT0;
4007
4008         wr_reg16(info, TCR, val);
4009
4010         /* RCR (rx control)
4011          *
4012          * 15..13  mode, 010=async
4013          * 12..10  encoding, 000=NRZ
4014          * 09      parity enable
4015          * 08      1=odd parity, 0=even parity
4016          * 07..06  reserved, must be 0
4017          * 05..04  character length
4018          *         00=5 bits
4019          *         01=6 bits
4020          *         10=7 bits
4021          *         11=8 bits
4022          * 03      reserved, must be zero
4023          * 02      reset
4024          * 01      enable
4025          * 00      auto-DCD enable
4026          */
4027         val = 0x4000;
4028
4029         if (info->params.parity != ASYNC_PARITY_NONE) {
4030                 val |= BIT9;
4031                 if (info->params.parity == ASYNC_PARITY_ODD)
4032                         val |= BIT8;
4033         }
4034
4035         switch (info->params.data_bits)
4036         {
4037         case 6: val |= BIT4; break;
4038         case 7: val |= BIT5; break;
4039         case 8: val |= BIT5 + BIT4; break;
4040         }
4041
4042         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4043                 val |= BIT0;
4044
4045         wr_reg16(info, RCR, val);
4046
4047         /* CCR (clock control)
4048          *
4049          * 07..05  011 = tx clock source is BRG/16
4050          * 04..02  010 = rx clock source is BRG
4051          * 01      0 = auxclk disabled
4052          * 00      1 = BRG enabled
4053          *
4054          * 0110 1001
4055          */
4056         wr_reg8(info, CCR, 0x69);
4057
4058         msc_set_vcr(info);
4059
4060         /* SCR (serial control)
4061          *
4062          * 15  1=tx req on FIFO half empty
4063          * 14  1=rx req on FIFO half full
4064          * 13  tx data  IRQ enable
4065          * 12  tx idle  IRQ enable
4066          * 11  rx break on IRQ enable
4067          * 10  rx data  IRQ enable
4068          * 09  rx break off IRQ enable
4069          * 08  overrun  IRQ enable
4070          * 07  DSR      IRQ enable
4071          * 06  CTS      IRQ enable
4072          * 05  DCD      IRQ enable
4073          * 04  RI       IRQ enable
4074          * 03  reserved, must be zero
4075          * 02  1=txd->rxd internal loopback enable
4076          * 01  reserved, must be zero
4077          * 00  1=master IRQ enable
4078          */
4079         val = BIT15 + BIT14 + BIT0;
4080         wr_reg16(info, SCR, val);
4081
4082         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4083
4084         set_rate(info, info->params.data_rate * 16);
4085
4086         if (info->params.loopback)
4087                 enable_loopback(info);
4088 }
4089
4090 static void sync_mode(struct slgt_info *info)
4091 {
4092         unsigned short val;
4093
4094         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4095         tx_stop(info);
4096         rx_stop(info);
4097
4098         /* TCR (tx control)
4099          *
4100          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4101          * 12..10  encoding
4102          * 09      CRC enable
4103          * 08      CRC32
4104          * 07      1=RTS driver control
4105          * 06      preamble enable
4106          * 05..04  preamble length
4107          * 03      share open/close flag
4108          * 02      reset
4109          * 01      enable
4110          * 00      auto-CTS enable
4111          */
4112         val = 0;
4113
4114         switch(info->params.mode) {
4115         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4116         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4117         case MGSL_MODE_RAW:      val |= BIT13; break;
4118         }
4119         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4120                 val |= BIT7;
4121
4122         switch(info->params.encoding)
4123         {
4124         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4125         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4126         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4127         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4128         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4129         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4130         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4131         }
4132
4133         switch (info->params.crc_type & HDLC_CRC_MASK)
4134         {
4135         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4136         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4137         }
4138
4139         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4140                 val |= BIT6;
4141
4142         switch (info->params.preamble_length)
4143         {
4144         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4145         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4146         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4147         }
4148
4149         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4150                 val |= BIT0;
4151
4152         wr_reg16(info, TCR, val);
4153
4154         /* TPR (transmit preamble) */
4155
4156         switch (info->params.preamble)
4157         {
4158         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4159         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4160         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4161         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4162         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4163         default:                          val = 0x7e; break;
4164         }
4165         wr_reg8(info, TPR, (unsigned char)val);
4166
4167         /* RCR (rx control)
4168          *
4169          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4170          * 12..10  encoding
4171          * 09      CRC enable
4172          * 08      CRC32
4173          * 07..03  reserved, must be 0
4174          * 02      reset
4175          * 01      enable
4176          * 00      auto-DCD enable
4177          */
4178         val = 0;
4179
4180         switch(info->params.mode) {
4181         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4182         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4183         case MGSL_MODE_RAW:      val |= BIT13; break;
4184         }
4185
4186         switch(info->params.encoding)
4187         {
4188         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4189         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4190         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4191         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4192         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4193         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4194         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4195         }
4196
4197         switch (info->params.crc_type & HDLC_CRC_MASK)
4198         {
4199         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4200         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4201         }
4202
4203         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4204                 val |= BIT0;
4205
4206         wr_reg16(info, RCR, val);
4207
4208         /* CCR (clock control)
4209          *
4210          * 07..05  tx clock source
4211          * 04..02  rx clock source
4212          * 01      auxclk enable
4213          * 00      BRG enable
4214          */
4215         val = 0;
4216
4217         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4218         {
4219                 // when RxC source is DPLL, BRG generates 16X DPLL
4220                 // reference clock, so take TxC from BRG/16 to get
4221                 // transmit clock at actual data rate
4222                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4223                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4224                 else
4225                         val |= BIT6;    /* 010, txclk = BRG */
4226         }
4227         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4228                 val |= BIT7;    /* 100, txclk = DPLL Input */
4229         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4230                 val |= BIT5;    /* 001, txclk = RXC Input */
4231
4232         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4233                 val |= BIT3;    /* 010, rxclk = BRG */
4234         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4235                 val |= BIT4;    /* 100, rxclk = DPLL */
4236         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4237                 val |= BIT2;    /* 001, rxclk = TXC Input */
4238
4239         if (info->params.clock_speed)
4240                 val |= BIT1 + BIT0;
4241
4242         wr_reg8(info, CCR, (unsigned char)val);
4243
4244         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4245         {
4246                 // program DPLL mode
4247                 switch(info->params.encoding)
4248                 {
4249                 case HDLC_ENCODING_BIPHASE_MARK:
4250                 case HDLC_ENCODING_BIPHASE_SPACE:
4251                         val = BIT7; break;
4252                 case HDLC_ENCODING_BIPHASE_LEVEL:
4253                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4254                         val = BIT7 + BIT6; break;
4255                 default: val = BIT6;    // NRZ encodings
4256                 }
4257                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4258
4259                 // DPLL requires a 16X reference clock from BRG
4260                 set_rate(info, info->params.clock_speed * 16);
4261         }
4262         else
4263                 set_rate(info, info->params.clock_speed);
4264
4265         tx_set_idle(info);
4266
4267         msc_set_vcr(info);
4268
4269         /* SCR (serial control)
4270          *
4271          * 15  1=tx req on FIFO half empty
4272          * 14  1=rx req on FIFO half full
4273          * 13  tx data  IRQ enable
4274          * 12  tx idle  IRQ enable
4275          * 11  underrun IRQ enable
4276          * 10  rx data  IRQ enable
4277          * 09  rx idle  IRQ enable
4278          * 08  overrun  IRQ enable
4279          * 07  DSR      IRQ enable
4280          * 06  CTS      IRQ enable
4281          * 05  DCD      IRQ enable
4282          * 04  RI       IRQ enable
4283          * 03  reserved, must be zero
4284          * 02  1=txd->rxd internal loopback enable
4285          * 01  reserved, must be zero
4286          * 00  1=master IRQ enable
4287          */
4288         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4289
4290         if (info->params.loopback)
4291                 enable_loopback(info);
4292 }
4293
4294 /*
4295  *  set transmit idle mode
4296  */
4297 static void tx_set_idle(struct slgt_info *info)
4298 {
4299         unsigned char val;
4300         unsigned short tcr;
4301
4302         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4303          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4304          */
4305         tcr = rd_reg16(info, TCR);
4306         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4307                 /* disable preamble, set idle size to 16 bits */
4308                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4309                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4310                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4311         } else if (!(tcr & BIT6)) {
4312                 /* preamble is disabled, set idle size to 8 bits */
4313                 tcr &= ~(BIT5 + BIT4);
4314         }
4315         wr_reg16(info, TCR, tcr);
4316
4317         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4318                 /* LSB of custom tx idle specified in tx idle register */
4319                 val = (unsigned char)(info->idle_mode & 0xff);
4320         } else {
4321                 /* standard 8 bit idle patterns */
4322                 switch(info->idle_mode)
4323                 {
4324                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4325                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4326                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4327                 case HDLC_TXIDLE_ZEROS:
4328                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4329                 default:                         val = 0xff;
4330                 }
4331         }
4332
4333         wr_reg8(info, TIR, val);
4334 }
4335
4336 /*
4337  * get state of V24 status (input) signals
4338  */
4339 static void get_signals(struct slgt_info *info)
4340 {
4341         unsigned short status = rd_reg16(info, SSR);
4342
4343         /* clear all serial signals except DTR and RTS */
4344         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4345
4346         if (status & BIT3)
4347                 info->signals |= SerialSignal_DSR;
4348         if (status & BIT2)
4349                 info->signals |= SerialSignal_CTS;
4350         if (status & BIT1)
4351                 info->signals |= SerialSignal_DCD;
4352         if (status & BIT0)
4353                 info->signals |= SerialSignal_RI;
4354 }
4355
4356 /*
4357  * set V.24 Control Register based on current configuration
4358  */
4359 static void msc_set_vcr(struct slgt_info *info)
4360 {
4361         unsigned char val = 0;
4362
4363         /* VCR (V.24 control)
4364          *
4365          * 07..04  serial IF select
4366          * 03      DTR
4367          * 02      RTS
4368          * 01      LL
4369          * 00      RL
4370          */
4371
4372         switch(info->if_mode & MGSL_INTERFACE_MASK)
4373         {
4374         case MGSL_INTERFACE_RS232:
4375                 val |= BIT5; /* 0010 */
4376                 break;
4377         case MGSL_INTERFACE_V35:
4378                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4379                 break;
4380         case MGSL_INTERFACE_RS422:
4381                 val |= BIT6; /* 0100 */
4382                 break;
4383         }
4384
4385         if (info->signals & SerialSignal_DTR)
4386                 val |= BIT3;
4387         if (info->signals & SerialSignal_RTS)
4388                 val |= BIT2;
4389         if (info->if_mode & MGSL_INTERFACE_LL)
4390                 val |= BIT1;
4391         if (info->if_mode & MGSL_INTERFACE_RL)
4392                 val |= BIT0;
4393         wr_reg8(info, VCR, val);
4394 }
4395
4396 /*
4397  * set state of V24 control (output) signals
4398  */
4399 static void set_signals(struct slgt_info *info)
4400 {
4401         unsigned char val = rd_reg8(info, VCR);
4402         if (info->signals & SerialSignal_DTR)
4403                 val |= BIT3;
4404         else
4405                 val &= ~BIT3;
4406         if (info->signals & SerialSignal_RTS)
4407                 val |= BIT2;
4408         else
4409                 val &= ~BIT2;
4410         wr_reg8(info, VCR, val);
4411 }
4412
4413 /*
4414  * free range of receive DMA buffers (i to last)
4415  */
4416 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4417 {
4418         int done = 0;
4419
4420         while(!done) {
4421                 /* reset current buffer for reuse */
4422                 info->rbufs[i].status = 0;
4423                 switch(info->params.mode) {
4424                 case MGSL_MODE_RAW:
4425                 case MGSL_MODE_MONOSYNC:
4426                 case MGSL_MODE_BISYNC:
4427                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4428                         break;
4429                 default:
4430                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4431                 }
4432
4433                 if (i == last)
4434                         done = 1;
4435                 if (++i == info->rbuf_count)
4436                         i = 0;
4437         }
4438         info->rbuf_current = i;
4439 }
4440
4441 /*
4442  * mark all receive DMA buffers as free
4443  */
4444 static void reset_rbufs(struct slgt_info *info)
4445 {
4446         free_rbufs(info, 0, info->rbuf_count - 1);
4447 }
4448
4449 /*
4450  * pass receive HDLC frame to upper layer
4451  *
4452  * return 1 if frame available, otherwise 0
4453  */
4454 static int rx_get_frame(struct slgt_info *info)
4455 {
4456         unsigned int start, end;
4457         unsigned short status;
4458         unsigned int framesize = 0;
4459         int rc = 0;
4460         unsigned long flags;
4461         struct tty_struct *tty = info->tty;
4462         unsigned char addr_field = 0xff;
4463         unsigned int crc_size = 0;
4464
4465         switch (info->params.crc_type & HDLC_CRC_MASK) {
4466         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4467         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4468         }
4469
4470 check_again:
4471
4472         framesize = 0;
4473         addr_field = 0xff;
4474         start = end = info->rbuf_current;
4475
4476         for (;;) {
4477                 if (!desc_complete(info->rbufs[end]))
4478                         goto cleanup;
4479
4480                 if (framesize == 0 && info->params.addr_filter != 0xff)
4481                         addr_field = info->rbufs[end].buf[0];
4482
4483                 framesize += desc_count(info->rbufs[end]);
4484
4485                 if (desc_eof(info->rbufs[end]))
4486                         break;
4487
4488                 if (++end == info->rbuf_count)
4489                         end = 0;
4490
4491                 if (end == info->rbuf_current) {
4492                         if (info->rx_enabled){
4493                                 spin_lock_irqsave(&info->lock,flags);
4494                                 rx_start(info);
4495                                 spin_unlock_irqrestore(&info->lock,flags);
4496                         }
4497                         goto cleanup;
4498                 }
4499         }
4500
4501         /* status
4502          *
4503          * 15      buffer complete
4504          * 14..06  reserved
4505          * 05..04  residue
4506          * 02      eof (end of frame)
4507          * 01      CRC error
4508          * 00      abort
4509          */
4510         status = desc_status(info->rbufs[end]);
4511
4512         /* ignore CRC bit if not using CRC (bit is undefined) */
4513         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4514                 status &= ~BIT1;
4515
4516         if (framesize == 0 ||
4517                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4518                 free_rbufs(info, start, end);
4519                 goto check_again;
4520         }
4521
4522         if (framesize < (2 + crc_size) || status & BIT0) {
4523                 info->icount.rxshort++;
4524                 framesize = 0;
4525         } else if (status & BIT1) {
4526                 info->icount.rxcrc++;
4527                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4528                         framesize = 0;
4529         }
4530
4531 #if SYNCLINK_GENERIC_HDLC
4532         if (framesize == 0) {
4533                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4534                 stats->rx_errors++;
4535                 stats->rx_frame_errors++;
4536         }
4537 #endif
4538
4539         DBGBH(("%s rx frame status=%04X size=%d\n",
4540                 info->device_name, status, framesize));
4541         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4542
4543         if (framesize) {
4544                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4545                         framesize -= crc_size;
4546                         crc_size = 0;
4547                 }
4548
4549                 if (framesize > info->max_frame_size + crc_size)
4550                         info->icount.rxlong++;
4551                 else {
4552                         /* copy dma buffer(s) to contiguous temp buffer */
4553                         int copy_count = framesize;
4554                         int i = start;
4555                         unsigned char *p = info->tmp_rbuf;
4556                         info->tmp_rbuf_count = framesize;
4557
4558                         info->icount.rxok++;
4559
4560                         while(copy_count) {
4561                                 int partial_count = min(copy_count, DMABUFSIZE);
4562                                 memcpy(p, info->rbufs[i].buf, partial_count);
4563                                 p += partial_count;
4564                                 copy_count -= partial_count;
4565                                 if (++i == info->rbuf_count)
4566                                         i = 0;
4567                         }
4568
4569                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4570                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4571                                 framesize++;
4572                         }
4573
4574 #if SYNCLINK_GENERIC_HDLC
4575                         if (info->netcount)
4576                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4577                         else
4578 #endif
4579                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4580                 }
4581         }
4582         free_rbufs(info, start, end);
4583         rc = 1;
4584
4585 cleanup:
4586         return rc;
4587 }
4588
4589 /*
4590  * pass receive buffer (RAW synchronous mode) to tty layer
4591  * return 1 if buffer available, otherwise 0
4592  */
4593 static int rx_get_buf(struct slgt_info *info)
4594 {
4595         unsigned int i = info->rbuf_current;
4596         unsigned int count;
4597
4598         if (!desc_complete(info->rbufs[i]))
4599                 return 0;
4600         count = desc_count(info->rbufs[i]);
4601         switch(info->params.mode) {
4602         case MGSL_MODE_MONOSYNC:
4603         case MGSL_MODE_BISYNC:
4604                 /* ignore residue in byte synchronous modes */
4605                 if (desc_residue(info->rbufs[i]))
4606                         count--;
4607                 break;
4608         }
4609         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4610         DBGINFO(("rx_get_buf size=%d\n", count));
4611         if (count)
4612                 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4613                                   info->flag_buf, count);
4614         free_rbufs(info, i, i);
4615         return 1;
4616 }
4617
4618 static void reset_tbufs(struct slgt_info *info)
4619 {
4620         unsigned int i;
4621         info->tbuf_current = 0;
4622         for (i=0 ; i < info->tbuf_count ; i++) {
4623                 info->tbufs[i].status = 0;
4624                 info->tbufs[i].count  = 0;
4625         }
4626 }
4627
4628 /*
4629  * return number of free transmit DMA buffers
4630  */
4631 static unsigned int free_tbuf_count(struct slgt_info *info)
4632 {
4633         unsigned int count = 0;
4634         unsigned int i = info->tbuf_current;
4635
4636         do
4637         {
4638                 if (desc_count(info->tbufs[i]))
4639                         break; /* buffer in use */
4640                 ++count;
4641                 if (++i == info->tbuf_count)
4642                         i=0;
4643         } while (i != info->tbuf_current);
4644
4645         /* last buffer with zero count may be in use, assume it is */
4646         if (count)
4647                 --count;
4648
4649         return count;
4650 }
4651
4652 /*
4653  * load transmit DMA buffer(s) with data
4654  */
4655 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4656 {
4657         unsigned short count;
4658         unsigned int i;
4659         struct slgt_desc *d;
4660
4661         if (size == 0)
4662                 return;
4663
4664         DBGDATA(info, buf, size, "tx");
4665
4666         info->tbuf_start = i = info->tbuf_current;
4667
4668         while (size) {
4669                 d = &info->tbufs[i];
4670                 if (++i == info->tbuf_count)
4671                         i = 0;
4672
4673                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4674                 memcpy(d->buf, buf, count);
4675
4676                 size -= count;
4677                 buf  += count;
4678
4679                 /*
4680                  * set EOF bit for last buffer of HDLC frame or
4681                  * for every buffer in raw mode
4682                  */
4683                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4684                     info->params.mode == MGSL_MODE_RAW)
4685                         set_desc_eof(*d, 1);
4686                 else
4687                         set_desc_eof(*d, 0);
4688
4689                 set_desc_count(*d, count);
4690         }
4691
4692         info->tbuf_current = i;
4693 }
4694
4695 static int register_test(struct slgt_info *info)
4696 {
4697         static unsigned short patterns[] =
4698                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4699         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4700         unsigned int i;
4701         int rc = 0;
4702
4703         for (i=0 ; i < count ; i++) {
4704                 wr_reg16(info, TIR, patterns[i]);
4705                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4706                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4707                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4708                         rc = -ENODEV;
4709                         break;
4710                 }
4711         }
4712         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4713         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4714         return rc;
4715 }
4716
4717 static int irq_test(struct slgt_info *info)
4718 {
4719         unsigned long timeout;
4720         unsigned long flags;
4721         struct tty_struct *oldtty = info->tty;
4722         u32 speed = info->params.data_rate;
4723
4724         info->params.data_rate = 921600;
4725         info->tty = NULL;
4726
4727         spin_lock_irqsave(&info->lock, flags);
4728         async_mode(info);
4729         slgt_irq_on(info, IRQ_TXIDLE);
4730
4731         /* enable transmitter */
4732         wr_reg16(info, TCR,
4733                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4734
4735         /* write one byte and wait for tx idle */
4736         wr_reg16(info, TDR, 0);
4737
4738         /* assume failure */
4739         info->init_error = DiagStatus_IrqFailure;
4740         info->irq_occurred = FALSE;
4741
4742         spin_unlock_irqrestore(&info->lock, flags);
4743
4744         timeout=100;
4745         while(timeout-- && !info->irq_occurred)
4746                 msleep_interruptible(10);
4747
4748         spin_lock_irqsave(&info->lock,flags);
4749         reset_port(info);
4750         spin_unlock_irqrestore(&info->lock,flags);
4751
4752         info->params.data_rate = speed;
4753         info->tty = oldtty;
4754
4755         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4756         return info->irq_occurred ? 0 : -ENODEV;
4757 }
4758
4759 static int loopback_test_rx(struct slgt_info *info)
4760 {
4761         unsigned char *src, *dest;
4762         int count;
4763
4764         if (desc_complete(info->rbufs[0])) {
4765                 count = desc_count(info->rbufs[0]);
4766                 src   = info->rbufs[0].buf;
4767                 dest  = info->tmp_rbuf;
4768
4769                 for( ; count ; count-=2, src+=2) {
4770                         /* src=data byte (src+1)=status byte */
4771                         if (!(*(src+1) & (BIT9 + BIT8))) {
4772                                 *dest = *src;
4773                                 dest++;
4774                                 info->tmp_rbuf_count++;
4775                         }
4776                 }
4777                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4778                 return 1;
4779         }
4780         return 0;
4781 }
4782
4783 static int loopback_test(struct slgt_info *info)
4784 {
4785 #define TESTFRAMESIZE 20
4786
4787         unsigned long timeout;
4788         u16 count = TESTFRAMESIZE;
4789         unsigned char buf[TESTFRAMESIZE];
4790         int rc = -ENODEV;
4791         unsigned long flags;
4792
4793         struct tty_struct *oldtty = info->tty;
4794         MGSL_PARAMS params;
4795
4796         memcpy(&params, &info->params, sizeof(params));
4797
4798         info->params.mode = MGSL_MODE_ASYNC;
4799         info->params.data_rate = 921600;
4800         info->params.loopback = 1;
4801         info->tty = NULL;
4802
4803         /* build and send transmit frame */
4804         for (count = 0; count < TESTFRAMESIZE; ++count)
4805                 buf[count] = (unsigned char)count;
4806
4807         info->tmp_rbuf_count = 0;
4808         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4809
4810         /* program hardware for HDLC and enabled receiver */
4811         spin_lock_irqsave(&info->lock,flags);
4812         async_mode(info);
4813         rx_start(info);
4814         info->tx_count = count;
4815         tx_load(info, buf, count);
4816         tx_start(info);
4817         spin_unlock_irqrestore(&info->lock, flags);
4818
4819         /* wait for receive complete */
4820         for (timeout = 100; timeout; --timeout) {
4821                 msleep_interruptible(10);
4822                 if (loopback_test_rx(info)) {
4823                         rc = 0;
4824                         break;
4825                 }
4826         }
4827
4828         /* verify received frame length and contents */
4829         if (!rc && (info->tmp_rbuf_count != count ||
4830                   memcmp(buf, info->tmp_rbuf, count))) {
4831                 rc = -ENODEV;
4832         }
4833
4834         spin_lock_irqsave(&info->lock,flags);
4835         reset_adapter(info);
4836         spin_unlock_irqrestore(&info->lock,flags);
4837
4838         memcpy(&info->params, &params, sizeof(info->params));
4839         info->tty = oldtty;
4840
4841         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4842         return rc;
4843 }
4844
4845 static int adapter_test(struct slgt_info *info)
4846 {
4847         DBGINFO(("testing %s\n", info->device_name));
4848         if (register_test(info) < 0) {
4849                 printk("register test failure %s addr=%08X\n",
4850                         info->device_name, info->phys_reg_addr);
4851         } else if (irq_test(info) < 0) {
4852                 printk("IRQ test failure %s IRQ=%d\n",
4853                         info->device_name, info->irq_level);
4854         } else if (loopback_test(info) < 0) {
4855                 printk("loopback test failure %s\n", info->device_name);
4856         }
4857         return info->init_error;
4858 }
4859
4860 /*
4861  * transmit timeout handler
4862  */
4863 static void tx_timeout(unsigned long context)
4864 {
4865         struct slgt_info *info = (struct slgt_info*)context;
4866         unsigned long flags;
4867
4868         DBGINFO(("%s tx_timeout\n", info->device_name));
4869         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4870                 info->icount.txtimeout++;
4871         }
4872         spin_lock_irqsave(&info->lock,flags);
4873         info->tx_active = 0;
4874         info->tx_count = 0;
4875         spin_unlock_irqrestore(&info->lock,flags);
4876
4877 #if SYNCLINK_GENERIC_HDLC
4878         if (info->netcount)
4879                 hdlcdev_tx_done(info);
4880         else
4881 #endif
4882                 bh_transmit(info);
4883 }
4884
4885 /*
4886  * receive buffer polling timer
4887  */
4888 static void rx_timeout(unsigned long context)
4889 {
4890         struct slgt_info *info = (struct slgt_info*)context;
4891         unsigned long flags;
4892
4893         DBGINFO(("%s rx_timeout\n", info->device_name));
4894         spin_lock_irqsave(&info->lock, flags);
4895         info->pending_bh |= BH_RECEIVE;
4896         spin_unlock_irqrestore(&info->lock, flags);
4897         bh_handler(&info->task);
4898 }
4899