1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20050720"
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading)
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
91 #define DRIVER_MAJOR 1
92 #define DRIVER_MINOR 18
93 #define DRIVER_PATCHLEVEL 0
95 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
96 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
99 * Radeon chip families
120 enum radeon_cp_microcode_version {
129 enum radeon_chip_flags {
130 CHIP_FAMILY_MASK = 0x0000ffffUL,
131 CHIP_FLAGS_MASK = 0xffff0000UL,
132 CHIP_IS_MOBILITY = 0x00010000UL,
133 CHIP_IS_IGP = 0x00020000UL,
134 CHIP_SINGLE_CRTC = 0x00040000UL,
135 CHIP_IS_AGP = 0x00080000UL,
136 CHIP_HAS_HIERZ = 0x00100000UL,
139 typedef struct drm_radeon_freelist {
142 struct drm_radeon_freelist *next;
143 struct drm_radeon_freelist *prev;
144 } drm_radeon_freelist_t;
146 typedef struct drm_radeon_ring_buffer {
157 } drm_radeon_ring_buffer_t;
159 typedef struct drm_radeon_depth_clear_t {
161 u32 rb3d_zstencilcntl;
163 } drm_radeon_depth_clear_t;
165 struct drm_radeon_driver_file_fields {
166 int64_t radeon_fb_delta;
170 struct mem_block *next;
171 struct mem_block *prev;
174 DRMFILE filp; /* 0: free, -1: heap, other: real files */
177 struct radeon_surface {
184 struct radeon_virt_surface {
192 typedef struct drm_radeon_private {
193 drm_radeon_ring_buffer_t ring;
194 drm_radeon_sarea_t *sarea_priv;
200 unsigned long gart_buffers_offset;
205 drm_radeon_freelist_t *head;
206 drm_radeon_freelist_t *tail;
208 volatile u32 *scratch;
213 int microcode_version;
216 unsigned long phys_pci_gart;
217 dma_addr_t bus_pci_gart;
221 int freelist_timeouts;
224 int last_frame_reads;
225 int last_clear_reads;
235 unsigned int front_offset;
236 unsigned int front_pitch;
237 unsigned int back_offset;
238 unsigned int back_pitch;
241 unsigned int depth_offset;
242 unsigned int depth_pitch;
244 u32 front_pitch_offset;
245 u32 back_pitch_offset;
246 u32 depth_pitch_offset;
248 drm_radeon_depth_clear_t depth_clear;
250 unsigned long fb_offset;
251 unsigned long mmio_offset;
252 unsigned long ring_offset;
253 unsigned long ring_rptr_offset;
254 unsigned long buffers_offset;
255 unsigned long gart_textures_offset;
257 drm_local_map_t *sarea;
258 drm_local_map_t *mmio;
259 drm_local_map_t *cp_ring;
260 drm_local_map_t *ring_rptr;
261 drm_local_map_t *gart_textures;
263 struct mem_block *gart_heap;
264 struct mem_block *fb_heap;
267 wait_queue_head_t swi_queue;
268 atomic_t swi_emitted;
270 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
271 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
273 /* starting from here on, data is preserved accross an open */
274 uint32_t flags; /* see radeon_chip_flags */
275 } drm_radeon_private_t;
277 typedef struct drm_radeon_buf_priv {
279 } drm_radeon_buf_priv_t;
282 extern int radeon_cp_init( DRM_IOCTL_ARGS );
283 extern int radeon_cp_start( DRM_IOCTL_ARGS );
284 extern int radeon_cp_stop( DRM_IOCTL_ARGS );
285 extern int radeon_cp_reset( DRM_IOCTL_ARGS );
286 extern int radeon_cp_idle( DRM_IOCTL_ARGS );
287 extern int radeon_cp_resume( DRM_IOCTL_ARGS );
288 extern int radeon_engine_reset( DRM_IOCTL_ARGS );
289 extern int radeon_fullscreen( DRM_IOCTL_ARGS );
290 extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
292 extern void radeon_freelist_reset( drm_device_t *dev );
293 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
295 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
297 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
299 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
300 extern int radeon_presetup(struct drm_device *dev);
301 extern int radeon_driver_postcleanup(struct drm_device *dev);
303 extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
304 extern int radeon_mem_free( DRM_IOCTL_ARGS );
305 extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
306 extern void radeon_mem_takedown( struct mem_block **heap );
307 extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
310 extern int radeon_irq_emit( DRM_IOCTL_ARGS );
311 extern int radeon_irq_wait( DRM_IOCTL_ARGS );
313 extern void radeon_do_release(drm_device_t *dev);
314 extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
315 extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS );
316 extern void radeon_driver_irq_preinstall( drm_device_t *dev );
317 extern void radeon_driver_irq_postinstall( drm_device_t *dev );
318 extern void radeon_driver_irq_uninstall( drm_device_t *dev );
319 extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp);
320 extern void radeon_driver_pretakedown(drm_device_t *dev);
321 extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv);
322 extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv);
324 extern int radeon_preinit( struct drm_device *dev, unsigned long flags );
325 extern int radeon_postinit( struct drm_device *dev, unsigned long flags );
326 extern int radeon_postcleanup( struct drm_device *dev );
328 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
333 extern void r300_init_reg_flags(void);
335 extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
336 drm_file_t* filp_priv,
337 drm_radeon_cmd_buffer_t* cmdbuf);
339 /* Flags for stats.boxes
341 #define RADEON_BOX_DMA_IDLE 0x1
342 #define RADEON_BOX_RING_FULL 0x2
343 #define RADEON_BOX_FLIP 0x4
344 #define RADEON_BOX_WAIT_IDLE 0x8
345 #define RADEON_BOX_TEXTURE_LOAD 0x10
349 /* Register definitions, register access macros and drmAddMap constants
350 * for Radeon kernel driver.
353 #define RADEON_AGP_COMMAND 0x0f60
354 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
355 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
356 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
357 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
358 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
359 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
360 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
362 #define RADEON_BUS_CNTL 0x0030
363 # define RADEON_BUS_MASTER_DIS (1 << 6)
365 #define RADEON_CLOCK_CNTL_DATA 0x000c
366 # define RADEON_PLL_WR_EN (1 << 7)
367 #define RADEON_CLOCK_CNTL_INDEX 0x0008
368 #define RADEON_CONFIG_APER_SIZE 0x0108
369 #define RADEON_CRTC_OFFSET 0x0224
370 #define RADEON_CRTC_OFFSET_CNTL 0x0228
371 # define RADEON_CRTC_TILE_EN (1 << 15)
372 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
373 #define RADEON_CRTC2_OFFSET 0x0324
374 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
376 #define RADEON_MPP_TB_CONFIG 0x01c0
377 #define RADEON_MEM_CNTL 0x0140
378 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
379 #define RADEON_AGP_BASE 0x0170
381 #define RADEON_RB3D_COLOROFFSET 0x1c40
382 #define RADEON_RB3D_COLORPITCH 0x1c48
384 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
385 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
386 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
387 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
388 # define RADEON_GMC_BRUSH_NONE (15 << 4)
389 # define RADEON_GMC_DST_16BPP (4 << 8)
390 # define RADEON_GMC_DST_24BPP (5 << 8)
391 # define RADEON_GMC_DST_32BPP (6 << 8)
392 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
393 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
394 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
395 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
396 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
397 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
398 # define RADEON_ROP3_S 0x00cc0000
399 # define RADEON_ROP3_P 0x00f00000
400 #define RADEON_DP_WRITE_MASK 0x16cc
401 #define RADEON_DST_PITCH_OFFSET 0x142c
402 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
403 # define RADEON_DST_TILE_LINEAR (0 << 30)
404 # define RADEON_DST_TILE_MACRO (1 << 30)
405 # define RADEON_DST_TILE_MICRO (2 << 30)
406 # define RADEON_DST_TILE_BOTH (3 << 30)
408 #define RADEON_SCRATCH_REG0 0x15e0
409 #define RADEON_SCRATCH_REG1 0x15e4
410 #define RADEON_SCRATCH_REG2 0x15e8
411 #define RADEON_SCRATCH_REG3 0x15ec
412 #define RADEON_SCRATCH_REG4 0x15f0
413 #define RADEON_SCRATCH_REG5 0x15f4
414 #define RADEON_SCRATCH_UMSK 0x0770
415 #define RADEON_SCRATCH_ADDR 0x0774
417 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
419 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
420 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
421 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
424 #define RADEON_GEN_INT_CNTL 0x0040
425 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
426 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
427 # define RADEON_SW_INT_ENABLE (1 << 25)
429 #define RADEON_GEN_INT_STATUS 0x0044
430 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
431 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
432 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
433 # define RADEON_SW_INT_TEST (1 << 25)
434 # define RADEON_SW_INT_TEST_ACK (1 << 25)
435 # define RADEON_SW_INT_FIRE (1 << 26)
437 #define RADEON_HOST_PATH_CNTL 0x0130
438 # define RADEON_HDP_SOFT_RESET (1 << 26)
439 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
440 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
442 #define RADEON_ISYNC_CNTL 0x1724
443 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
444 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
445 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
446 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
447 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
448 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
450 #define RADEON_RBBM_GUICNTL 0x172c
451 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
452 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
453 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
454 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
456 #define RADEON_MC_AGP_LOCATION 0x014c
457 #define RADEON_MC_FB_LOCATION 0x0148
458 #define RADEON_MCLK_CNTL 0x0012
459 # define RADEON_FORCEON_MCLKA (1 << 16)
460 # define RADEON_FORCEON_MCLKB (1 << 17)
461 # define RADEON_FORCEON_YCLKA (1 << 18)
462 # define RADEON_FORCEON_YCLKB (1 << 19)
463 # define RADEON_FORCEON_MC (1 << 20)
464 # define RADEON_FORCEON_AIC (1 << 21)
466 #define RADEON_PP_BORDER_COLOR_0 0x1d40
467 #define RADEON_PP_BORDER_COLOR_1 0x1d44
468 #define RADEON_PP_BORDER_COLOR_2 0x1d48
469 #define RADEON_PP_CNTL 0x1c38
470 # define RADEON_SCISSOR_ENABLE (1 << 1)
471 #define RADEON_PP_LUM_MATRIX 0x1d00
472 #define RADEON_PP_MISC 0x1c14
473 #define RADEON_PP_ROT_MATRIX_0 0x1d58
474 #define RADEON_PP_TXFILTER_0 0x1c54
475 #define RADEON_PP_TXOFFSET_0 0x1c5c
476 #define RADEON_PP_TXFILTER_1 0x1c6c
477 #define RADEON_PP_TXFILTER_2 0x1c84
479 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
480 # define RADEON_RB2D_DC_FLUSH (3 << 0)
481 # define RADEON_RB2D_DC_FREE (3 << 2)
482 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
483 # define RADEON_RB2D_DC_BUSY (1 << 31)
484 #define RADEON_RB3D_CNTL 0x1c3c
485 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
486 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
487 # define RADEON_DITHER_ENABLE (1 << 2)
488 # define RADEON_ROUND_ENABLE (1 << 3)
489 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
490 # define RADEON_DITHER_INIT (1 << 5)
491 # define RADEON_ROP_ENABLE (1 << 6)
492 # define RADEON_STENCIL_ENABLE (1 << 7)
493 # define RADEON_Z_ENABLE (1 << 8)
494 # define RADEON_ZBLOCK16 (1 << 15)
495 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
496 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
497 #define RADEON_RB3D_DEPTHPITCH 0x1c28
498 #define RADEON_RB3D_PLANEMASK 0x1d84
499 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
500 #define RADEON_RB3D_ZCACHE_MODE 0x3250
501 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
502 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
503 # define RADEON_RB3D_ZC_FREE (1 << 2)
504 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
505 # define RADEON_RB3D_ZC_BUSY (1 << 31)
506 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
507 # define RADEON_Z_TEST_MASK (7 << 4)
508 # define RADEON_Z_TEST_ALWAYS (7 << 4)
509 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
510 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
511 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
512 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
513 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
514 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
515 # define RADEON_FORCE_Z_DIRTY (1 << 29)
516 # define RADEON_Z_WRITE_ENABLE (1 << 30)
517 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
518 #define RADEON_RBBM_SOFT_RESET 0x00f0
519 # define RADEON_SOFT_RESET_CP (1 << 0)
520 # define RADEON_SOFT_RESET_HI (1 << 1)
521 # define RADEON_SOFT_RESET_SE (1 << 2)
522 # define RADEON_SOFT_RESET_RE (1 << 3)
523 # define RADEON_SOFT_RESET_PP (1 << 4)
524 # define RADEON_SOFT_RESET_E2 (1 << 5)
525 # define RADEON_SOFT_RESET_RB (1 << 6)
526 # define RADEON_SOFT_RESET_HDP (1 << 7)
527 #define RADEON_RBBM_STATUS 0x0e40
528 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
529 # define RADEON_RBBM_ACTIVE (1 << 31)
530 #define RADEON_RE_LINE_PATTERN 0x1cd0
531 #define RADEON_RE_MISC 0x26c4
532 #define RADEON_RE_TOP_LEFT 0x26c0
533 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
534 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
535 #define RADEON_RE_STIPPLE_DATA 0x1ccc
537 #define RADEON_SCISSOR_TL_0 0x1cd8
538 #define RADEON_SCISSOR_BR_0 0x1cdc
539 #define RADEON_SCISSOR_TL_1 0x1ce0
540 #define RADEON_SCISSOR_BR_1 0x1ce4
541 #define RADEON_SCISSOR_TL_2 0x1ce8
542 #define RADEON_SCISSOR_BR_2 0x1cec
543 #define RADEON_SE_COORD_FMT 0x1c50
544 #define RADEON_SE_CNTL 0x1c4c
545 # define RADEON_FFACE_CULL_CW (0 << 0)
546 # define RADEON_BFACE_SOLID (3 << 1)
547 # define RADEON_FFACE_SOLID (3 << 3)
548 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
549 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
550 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
551 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
552 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
553 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
554 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
555 # define RADEON_FOG_SHADE_FLAT (1 << 14)
556 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
557 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
558 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
559 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
560 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
561 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
562 #define RADEON_SE_CNTL_STATUS 0x2140
563 #define RADEON_SE_LINE_WIDTH 0x1db8
564 #define RADEON_SE_VPORT_XSCALE 0x1d98
565 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
566 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
567 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
568 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
569 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
570 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
571 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
572 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
573 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
574 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
575 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
576 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
577 #define RADEON_SURFACE_CNTL 0x0b00
578 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
579 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
580 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
581 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
582 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
583 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
584 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
585 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
586 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
587 #define RADEON_SURFACE0_INFO 0x0b0c
588 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
589 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
590 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
591 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
592 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
593 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
594 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
595 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
596 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
597 #define RADEON_SURFACE1_INFO 0x0b1c
598 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
599 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
600 #define RADEON_SURFACE2_INFO 0x0b2c
601 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
602 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
603 #define RADEON_SURFACE3_INFO 0x0b3c
604 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
605 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
606 #define RADEON_SURFACE4_INFO 0x0b4c
607 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
608 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
609 #define RADEON_SURFACE5_INFO 0x0b5c
610 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
611 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
612 #define RADEON_SURFACE6_INFO 0x0b6c
613 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
614 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
615 #define RADEON_SURFACE7_INFO 0x0b7c
616 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
617 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
618 #define RADEON_SW_SEMAPHORE 0x013c
620 #define RADEON_WAIT_UNTIL 0x1720
621 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
622 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
623 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
624 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
626 #define RADEON_RB3D_ZMASKOFFSET 0x3234
627 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
628 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
629 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
633 #define RADEON_CP_ME_RAM_ADDR 0x07d4
634 #define RADEON_CP_ME_RAM_RADDR 0x07d8
635 #define RADEON_CP_ME_RAM_DATAH 0x07dc
636 #define RADEON_CP_ME_RAM_DATAL 0x07e0
638 #define RADEON_CP_RB_BASE 0x0700
639 #define RADEON_CP_RB_CNTL 0x0704
640 # define RADEON_BUF_SWAP_32BIT (2 << 16)
641 #define RADEON_CP_RB_RPTR_ADDR 0x070c
642 #define RADEON_CP_RB_RPTR 0x0710
643 #define RADEON_CP_RB_WPTR 0x0714
645 #define RADEON_CP_RB_WPTR_DELAY 0x0718
646 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
647 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
649 #define RADEON_CP_IB_BASE 0x0738
651 #define RADEON_CP_CSQ_CNTL 0x0740
652 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
653 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
654 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
655 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
656 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
657 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
658 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
660 #define RADEON_AIC_CNTL 0x01d0
661 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
662 #define RADEON_AIC_STAT 0x01d4
663 #define RADEON_AIC_PT_BASE 0x01d8
664 #define RADEON_AIC_LO_ADDR 0x01dc
665 #define RADEON_AIC_HI_ADDR 0x01e0
666 #define RADEON_AIC_TLB_ADDR 0x01e4
667 #define RADEON_AIC_TLB_DATA 0x01e8
669 /* CP command packets */
670 #define RADEON_CP_PACKET0 0x00000000
671 # define RADEON_ONE_REG_WR (1 << 15)
672 #define RADEON_CP_PACKET1 0x40000000
673 #define RADEON_CP_PACKET2 0x80000000
674 #define RADEON_CP_PACKET3 0xC0000000
675 # define RADEON_CP_NOP 0x00001000
676 # define RADEON_CP_NEXT_CHAR 0x00001900
677 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
678 # define RADEON_CP_SET_SCISSORS 0x00001E00
679 /* GEN_INDX_PRIM is unsupported starting with R300 */
680 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
681 # define RADEON_WAIT_FOR_IDLE 0x00002600
682 # define RADEON_3D_DRAW_VBUF 0x00002800
683 # define RADEON_3D_DRAW_IMMD 0x00002900
684 # define RADEON_3D_DRAW_INDX 0x00002A00
685 # define RADEON_CP_LOAD_PALETTE 0x00002C00
686 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
687 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
688 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
689 # define RADEON_3D_CLEAR_ZMASK 0x00003200
690 # define RADEON_CP_INDX_BUFFER 0x00003300
691 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
692 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
693 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
694 # define RADEON_3D_CLEAR_HIZ 0x00003700
695 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
696 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
697 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
698 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
699 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
701 #define RADEON_CP_PACKET_MASK 0xC0000000
702 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
703 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
704 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
705 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
707 #define RADEON_VTX_Z_PRESENT (1 << 31)
708 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
710 #define RADEON_PRIM_TYPE_NONE (0 << 0)
711 #define RADEON_PRIM_TYPE_POINT (1 << 0)
712 #define RADEON_PRIM_TYPE_LINE (2 << 0)
713 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
714 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
715 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
716 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
717 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
718 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
719 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
720 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
721 #define RADEON_PRIM_TYPE_MASK 0xf
722 #define RADEON_PRIM_WALK_IND (1 << 4)
723 #define RADEON_PRIM_WALK_LIST (2 << 4)
724 #define RADEON_PRIM_WALK_RING (3 << 4)
725 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
726 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
727 #define RADEON_MAOS_ENABLE (1 << 7)
728 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
729 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
730 #define RADEON_NUM_VERTICES_SHIFT 16
732 #define RADEON_COLOR_FORMAT_CI8 2
733 #define RADEON_COLOR_FORMAT_ARGB1555 3
734 #define RADEON_COLOR_FORMAT_RGB565 4
735 #define RADEON_COLOR_FORMAT_ARGB8888 6
736 #define RADEON_COLOR_FORMAT_RGB332 7
737 #define RADEON_COLOR_FORMAT_RGB8 9
738 #define RADEON_COLOR_FORMAT_ARGB4444 15
740 #define RADEON_TXFORMAT_I8 0
741 #define RADEON_TXFORMAT_AI88 1
742 #define RADEON_TXFORMAT_RGB332 2
743 #define RADEON_TXFORMAT_ARGB1555 3
744 #define RADEON_TXFORMAT_RGB565 4
745 #define RADEON_TXFORMAT_ARGB4444 5
746 #define RADEON_TXFORMAT_ARGB8888 6
747 #define RADEON_TXFORMAT_RGBA8888 7
748 #define RADEON_TXFORMAT_Y8 8
749 #define RADEON_TXFORMAT_VYUY422 10
750 #define RADEON_TXFORMAT_YVYU422 11
751 #define RADEON_TXFORMAT_DXT1 12
752 #define RADEON_TXFORMAT_DXT23 14
753 #define RADEON_TXFORMAT_DXT45 15
755 #define R200_PP_TXCBLEND_0 0x2f00
756 #define R200_PP_TXCBLEND_1 0x2f10
757 #define R200_PP_TXCBLEND_2 0x2f20
758 #define R200_PP_TXCBLEND_3 0x2f30
759 #define R200_PP_TXCBLEND_4 0x2f40
760 #define R200_PP_TXCBLEND_5 0x2f50
761 #define R200_PP_TXCBLEND_6 0x2f60
762 #define R200_PP_TXCBLEND_7 0x2f70
763 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
764 #define R200_PP_TFACTOR_0 0x2ee0
765 #define R200_SE_VTX_FMT_0 0x2088
766 #define R200_SE_VAP_CNTL 0x2080
767 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
768 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
769 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
770 #define R200_PP_TXFILTER_5 0x2ca0
771 #define R200_PP_TXFILTER_4 0x2c80
772 #define R200_PP_TXFILTER_3 0x2c60
773 #define R200_PP_TXFILTER_2 0x2c40
774 #define R200_PP_TXFILTER_1 0x2c20
775 #define R200_PP_TXFILTER_0 0x2c00
776 #define R200_PP_TXOFFSET_5 0x2d78
777 #define R200_PP_TXOFFSET_4 0x2d60
778 #define R200_PP_TXOFFSET_3 0x2d48
779 #define R200_PP_TXOFFSET_2 0x2d30
780 #define R200_PP_TXOFFSET_1 0x2d18
781 #define R200_PP_TXOFFSET_0 0x2d00
783 #define R200_PP_CUBIC_FACES_0 0x2c18
784 #define R200_PP_CUBIC_FACES_1 0x2c38
785 #define R200_PP_CUBIC_FACES_2 0x2c58
786 #define R200_PP_CUBIC_FACES_3 0x2c78
787 #define R200_PP_CUBIC_FACES_4 0x2c98
788 #define R200_PP_CUBIC_FACES_5 0x2cb8
789 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
790 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
791 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
792 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
793 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
794 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
795 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
796 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
797 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
798 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
799 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
800 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
801 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
802 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
803 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
804 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
805 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
806 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
807 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
808 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
809 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
810 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
811 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
812 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
813 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
814 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
815 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
816 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
817 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
818 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
820 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
821 #define R200_SE_VTE_CNTL 0x20b0
822 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
823 #define R200_PP_TAM_DEBUG3 0x2d9c
824 #define R200_PP_CNTL_X 0x2cc4
825 #define R200_SE_VAP_CNTL_STATUS 0x2140
826 #define R200_RE_SCISSOR_TL_0 0x1cd8
827 #define R200_RE_SCISSOR_TL_1 0x1ce0
828 #define R200_RE_SCISSOR_TL_2 0x1ce8
829 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
830 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
831 #define R200_SE_VTX_STATE_CNTL 0x2180
832 #define R200_RE_POINTSIZE 0x2648
833 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
835 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
836 #define RADEON_PP_TEX_SIZE_1 0x1d0c
837 #define RADEON_PP_TEX_SIZE_2 0x1d14
839 #define RADEON_PP_CUBIC_FACES_0 0x1d24
840 #define RADEON_PP_CUBIC_FACES_1 0x1d28
841 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
842 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
843 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
844 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
846 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
847 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
848 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
849 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
850 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
851 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
852 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
853 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
854 #define R200_3D_DRAW_IMMD_2 0xC0003500
855 #define R200_SE_VTX_FMT_1 0x208c
856 #define R200_RE_CNTL 0x1c50
858 #define R200_RB3D_BLENDCOLOR 0x3218
860 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
862 #define R200_PP_TRI_PERF 0x2cf8
864 #define R200_PP_AFS_0 0x2f80
865 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
868 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
870 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
871 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
872 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
873 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
874 #define RADEON_LAST_DISPATCH 1
876 #define RADEON_MAX_VB_AGE 0x7fffffff
877 #define RADEON_MAX_VB_VERTS (0xffff)
879 #define RADEON_RING_HIGH_MARK 128
881 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
882 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
883 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
884 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
886 #define RADEON_WRITE_PLL( addr, val ) \
888 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
889 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
890 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
893 #define CP_PACKET0( reg, n ) \
894 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
895 #define CP_PACKET0_TABLE( reg, n ) \
896 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
897 #define CP_PACKET1( reg0, reg1 ) \
898 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
899 #define CP_PACKET2() \
901 #define CP_PACKET3( pkt, n ) \
902 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
905 /* ================================================================
906 * Engine control helper macros
909 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
910 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
911 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
912 RADEON_WAIT_HOST_IDLECLEAN) ); \
915 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
916 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
917 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
918 RADEON_WAIT_HOST_IDLECLEAN) ); \
921 #define RADEON_WAIT_UNTIL_IDLE() do { \
922 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
923 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
924 RADEON_WAIT_3D_IDLECLEAN | \
925 RADEON_WAIT_HOST_IDLECLEAN) ); \
928 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
929 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
930 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
933 #define RADEON_FLUSH_CACHE() do { \
934 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
935 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
938 #define RADEON_PURGE_CACHE() do { \
939 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
940 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
943 #define RADEON_FLUSH_ZCACHE() do { \
944 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
945 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
948 #define RADEON_PURGE_ZCACHE() do { \
949 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
950 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
954 /* ================================================================
958 /* Perfbox functionality only.
960 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
962 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
963 u32 head = GET_RING_HEAD( dev_priv ); \
964 if (head == dev_priv->ring.tail) \
965 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
969 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
971 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
972 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
973 int __ret = radeon_do_cp_idle( dev_priv ); \
974 if ( __ret ) return __ret; \
975 sarea_priv->last_dispatch = 0; \
976 radeon_freelist_reset( dev ); \
980 #define RADEON_DISPATCH_AGE( age ) do { \
981 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
985 #define RADEON_FRAME_AGE( age ) do { \
986 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
990 #define RADEON_CLEAR_AGE( age ) do { \
991 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
996 /* ================================================================
1000 #define RADEON_VERBOSE 0
1002 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1004 #define BEGIN_RING( n ) do { \
1005 if ( RADEON_VERBOSE ) { \
1006 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1007 n, __FUNCTION__ ); \
1009 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1011 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1013 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1014 ring = dev_priv->ring.start; \
1015 write = dev_priv->ring.tail; \
1016 mask = dev_priv->ring.tail_mask; \
1019 #define ADVANCE_RING() do { \
1020 if ( RADEON_VERBOSE ) { \
1021 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1022 write, dev_priv->ring.tail ); \
1024 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1026 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1027 ((dev_priv->ring.tail + _nr) & mask), \
1030 dev_priv->ring.tail = write; \
1033 #define COMMIT_RING() do { \
1034 /* Flush writes to ring */ \
1035 DRM_MEMORYBARRIER(); \
1036 GET_RING_HEAD( dev_priv ); \
1037 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1038 /* read from PCI bus to ensure correct posting */ \
1039 RADEON_READ( RADEON_CP_RB_RPTR ); \
1042 #define OUT_RING( x ) do { \
1043 if ( RADEON_VERBOSE ) { \
1044 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1045 (unsigned int)(x), write ); \
1047 ring[write++] = (x); \
1051 #define OUT_RING_REG( reg, val ) do { \
1052 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1057 #define OUT_RING_TABLE( tab, sz ) do { \
1059 int *_tab = (int *)(tab); \
1061 if (write + _size > mask) { \
1062 int _i = (mask+1) - write; \
1065 *(int *)(ring + write) = *_tab++; \
1073 while (_size > 0) { \
1074 *(ring + write) = *_tab++; \
1082 #endif /* __RADEON_DRV_H__ */