drivers/char/agp/uninorth-agp.c

   1 /*
   2  * UniNorth AGPGART routines.
   3  */
   4 #include <linux/module.h>
   5 #include <linux/pci.h>
   6 #include <linux/init.h>
   7 #include <linux/pagemap.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/delay.h>
  10 #include <asm/uninorth.h>
  11 #include <asm/pci-bridge.h>
  12 #include <asm/prom.h>
  13 #include <asm/pmac_feature.h>
  14 #include "agp.h"
  15
  16 /*
  17  * NOTES for uninorth3 (G5 AGP) supports :
  18  *
  19  * There maybe also possibility to have bigger cache line size for
  20  * agp (see pmac_pci.c and look for cache line). Need to be investigated
  21  * by someone.
  22  *
  23  * PAGE size are hardcoded but this may change, see asm/page.h.
  24  *
  25  * Jerome Glisse <j.glisse@gmail.com>
  26  */
  27 static int uninorth_rev;
  28 static int is_u3;
  29
  30 static char *aperture = NULL;
  31
  32 static int uninorth_fetch_size(void)
  33 {
  34         int i, size = 0;
  35         struct aper_size_info_32 *values =
  36             A_SIZE_32(agp_bridge->driver->aperture_sizes);
  37
  38         if (aperture) {
  39                 char *save = aperture;
  40
  41                 size = memparse(aperture, &aperture) >> 20;
  42                 aperture = save;
  43
  44                 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
  45                         if (size == values[i].size)
  46                                 break;
  47
  48                 if (i == agp_bridge->driver->num_aperture_sizes) {
  49                         dev_err(&agp_bridge->dev->dev, "invalid aperture size, "
  50                                 "using default\n");
  51                         size = 0;
  52                         aperture = NULL;
  53                 }
  54         }
  55
  56         if (!size) {
  57                 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
  58                         if (values[i].size == 32)
  59                                 break;
  60         }
  61
  62         agp_bridge->previous_size =
  63             agp_bridge->current_size = (void *)(values + i);
  64         agp_bridge->aperture_size_idx = i;
  65         return values[i].size;
  66 }
  67
  68 static void uninorth_tlbflush(struct agp_memory *mem)
  69 {
  70         u32 ctrl = UNI_N_CFG_GART_ENABLE;
  71
  72         if (is_u3)
  73                 ctrl |= U3_N_CFG_GART_PERFRD;
  74         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  75                                ctrl | UNI_N_CFG_GART_INVAL);
  76         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
  77
  78         if (uninorth_rev <= 0x30) {
  79                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  80                                        ctrl | UNI_N_CFG_GART_2xRESET);
  81                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  82                                        ctrl);
  83         }
  84 }
  85
  86 static void uninorth_cleanup(void)
  87 {
  88         u32 tmp;
  89
  90         pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp);
  91         if (!(tmp & UNI_N_CFG_GART_ENABLE))
  92                 return;
  93         tmp |= UNI_N_CFG_GART_INVAL;
  94         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp);
  95         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0);
  96
  97         if (uninorth_rev <= 0x30) {
  98                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  99                                        UNI_N_CFG_GART_2xRESET);
 100                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
 101                                        0);
 102         }
 103 }
 104
 105 static int uninorth_configure(void)
 106 {
 107         struct aper_size_info_32 *current_size;
 108
 109         current_size = A_SIZE_32(agp_bridge->current_size);
 110
 111         dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n",
 112                  current_size->size_value);
 113
 114         /* aperture size and gatt addr */
 115         pci_write_config_dword(agp_bridge->dev,
 116                 UNI_N_CFG_GART_BASE,
 117                 (agp_bridge->gatt_bus_addr & 0xfffff000)
 118                         | current_size->size_value);
 119
 120         /* HACK ALERT
 121          * UniNorth seem to be buggy enough not to handle properly when
 122          * the AGP aperture isn't mapped at bus physical address 0
 123          */
 124         agp_bridge->gart_bus_addr = 0;
 125 #ifdef CONFIG_PPC64
 126         /* Assume U3 or later on PPC64 systems */
 127         /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */
 128         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE,
 129                                (agp_bridge->gatt_bus_addr >> 32) & 0xf);
 130 #else
 131         pci_write_config_dword(agp_bridge->dev,
 132                 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr);
 133 #endif
 134
 135         if (is_u3) {
 136                 pci_write_config_dword(agp_bridge->dev,
 137                                        UNI_N_CFG_GART_DUMMY_PAGE,
 138                                        agp_bridge->scratch_page_real >> 12);
 139         }
 140
 141         return 0;
 142 }
 143
 144 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start,
 145                                 int type)
 146 {
 147         int i, j, num_entries;
 148         void *temp;
 149         int mask_type;
 150
 151         temp = agp_bridge->current_size;
 152         num_entries = A_SIZE_32(temp)->num_entries;
 153
 154         if (type != mem->type)
 155                 return -EINVAL;
 156
 157         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 158         if (mask_type != 0) {
 159                 /* We know nothing of memory types */
 160                 return -EINVAL;
 161         }
 162
 163         if ((pg_start + mem->page_count) > num_entries)
 164                 return -EINVAL;
 165
 166         j = pg_start;
 167
 168         while (j < (pg_start + mem->page_count)) {
 169                 if (agp_bridge->gatt_table[j])
 170                         return -EBUSY;
 171                 j++;
 172         }
 173
 174         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 175                 agp_bridge->gatt_table[j] =
 176                         cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 0x1UL);
 177                 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
 178                                    (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
 179         }
 180         (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
 181         mb();
 182         flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
 183                 (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]);
 184
 185         uninorth_tlbflush(mem);
 186         return 0;
 187 }
 188
 189 static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 190 {
 191         int i, num_entries;
 192         void *temp;
 193         u32 *gp;
 194         int mask_type;
 195
 196         temp = agp_bridge->current_size;
 197         num_entries = A_SIZE_32(temp)->num_entries;
 198
 199         if (type != mem->type)
 200                 return -EINVAL;
 201
 202         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 203         if (mask_type != 0) {
 204                 /* We know nothing of memory types */
 205                 return -EINVAL;
 206         }
 207
 208         if ((pg_start + mem->page_count) > num_entries)
 209                 return -EINVAL;
 210
 211         gp = (u32 *) &agp_bridge->gatt_table[pg_start];
 212         for (i = 0; i < mem->page_count; ++i) {
 213                 if (gp[i]) {
 214                         dev_info(&agp_bridge->dev->dev,
 215                                  "u3_insert_memory: entry 0x%x occupied (%x)\n",
 216                                  i, gp[i]);
 217                         return -EBUSY;
 218                 }
 219         }
 220
 221         for (i = 0; i < mem->page_count; i++) {
 222                 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
 223                 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
 224                                    (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
 225         }
 226         mb();
 227         flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]);
 228         uninorth_tlbflush(mem);
 229
 230         return 0;
 231 }
 232
 233 int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 234 {
 235         size_t i;
 236         u32 *gp;
 237
 238         if (type != 0 || mem->type != 0)
 239                 /* We know nothing of memory types */
 240                 return -EINVAL;
 241
 242         gp = (u32 *) &agp_bridge->gatt_table[pg_start];
 243         for (i = 0; i < mem->page_count; ++i)
 244                 gp[i] = 0;
 245         mb();
 246         flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]);
 247         uninorth_tlbflush(mem);
 248
 249         return 0;
 250 }
 251
 252 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 253 {
 254         u32 command, scratch, status;
 255         int timeout;
 256
 257         pci_read_config_dword(bridge->dev,
 258                               bridge->capndx + PCI_AGP_STATUS,
 259                               &status);
 260
 261         command = agp_collect_device_status(bridge, mode, status);
 262         command |= PCI_AGP_COMMAND_AGP;
 263
 264         if (uninorth_rev == 0x21) {
 265                 /*
 266                  * Darwin disable AGP 4x on this revision, thus we
 267                  * may assume it's broken. This is an AGP2 controller.
 268                  */
 269                 command &= ~AGPSTAT2_4X;
 270         }
 271
 272         if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
 273                 /*
 274                  * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
 275                  * 2.2 and 2.3, Darwin do so.
 276                  */
 277                 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7)
 278                         command = (command & ~AGPSTAT_RQ_DEPTH)
 279                                 | (7 << AGPSTAT_RQ_DEPTH_SHIFT);
 280         }
 281
 282         uninorth_tlbflush(NULL);
 283
 284         timeout = 0;
 285         do {
 286                 pci_write_config_dword(bridge->dev,
 287                                        bridge->capndx + PCI_AGP_COMMAND,
 288                                        command);
 289                 pci_read_config_dword(bridge->dev,
 290                                       bridge->capndx + PCI_AGP_COMMAND,
 291                                        &scratch);
 292         } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);
 293         if ((scratch & PCI_AGP_COMMAND_AGP) == 0)
 294                 dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
 295                         "command register\n");
 296
 297         if (uninorth_rev >= 0x30) {
 298                 /* This is an AGP V3 */
 299                 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
 300         } else {
 301                 /* AGP V2 */
 302                 agp_device_command(command, false);
 303         }
 304
 305         uninorth_tlbflush(NULL);
 306 }
 307
 308 #ifdef CONFIG_PM
 309 /*
 310  * These Power Management routines are _not_ called by the normal PCI PM layer,
 311  * but directly by the video driver through function pointers in the device
 312  * tree.
 313  */
 314 static int agp_uninorth_suspend(struct pci_dev *pdev)
 315 {
 316         struct agp_bridge_data *bridge;
 317         u32 cmd;
 318         u8 agp;
 319         struct pci_dev *device = NULL;
 320
 321         bridge = agp_find_bridge(pdev);
 322         if (bridge == NULL)
 323                 return -ENODEV;
 324
 325         /* Only one suspend supported */
 326         if (bridge->dev_private_data)
 327                 return 0;
 328
 329         /* turn off AGP on the video chip, if it was enabled */
 330         for_each_pci_dev(device) {
 331                 /* Don't touch the bridge yet, device first */
 332                 if (device == pdev)
 333                         continue;
 334                 /* Only deal with devices on the same bus here, no Mac has a P2P
 335                  * bridge on the AGP port, and mucking around the entire PCI
 336                  * tree is source of problems on some machines because of a bug
 337                  * in some versions of pci_find_capability() when hitting a dead
 338                  * device
 339                  */
 340                 if (device->bus != pdev->bus)
 341                         continue;
 342                 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
 343                 if (!agp)
 344                         continue;
 345                 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd);
 346                 if (!(cmd & PCI_AGP_COMMAND_AGP))
 347                         continue;
 348                 dev_info(&pdev->dev, "disabling AGP on device %s\n",
 349                          pci_name(device));
 350                 cmd &= ~PCI_AGP_COMMAND_AGP;
 351                 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd);
 352         }
 353
 354         /* turn off AGP on the bridge */
 355         agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 356         pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
 357         bridge->dev_private_data = (void *)(long)cmd;
 358         if (cmd & PCI_AGP_COMMAND_AGP) {
 359                 dev_info(&pdev->dev, "disabling AGP on bridge\n");
 360                 cmd &= ~PCI_AGP_COMMAND_AGP;
 361                 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd);
 362         }
 363         /* turn off the GART */
 364         uninorth_cleanup();
 365
 366         return 0;
 367 }
 368
 369 static int agp_uninorth_resume(struct pci_dev *pdev)
 370 {
 371         struct agp_bridge_data *bridge;
 372         u32 command;
 373
 374         bridge = agp_find_bridge(pdev);
 375         if (bridge == NULL)
 376                 return -ENODEV;
 377
 378         command = (long)bridge->dev_private_data;
 379         bridge->dev_private_data = NULL;
 380         if (!(command & PCI_AGP_COMMAND_AGP))
 381                 return 0;
 382
 383         uninorth_agp_enable(bridge, command);
 384
 385         return 0;
 386 }
 387 #endif /* CONFIG_PM */
 388
 389 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
 390 {
 391         char *table;
 392         char *table_end;
 393         int size;
 394         int page_order;
 395         int num_entries;
 396         int i;
 397         void *temp;
 398         struct page *page;
 399
 400         /* We can't handle 2 level gatt's */
 401         if (bridge->driver->size_type == LVL2_APER_SIZE)
 402                 return -EINVAL;
 403
 404         table = NULL;
 405         i = bridge->aperture_size_idx;
 406         temp = bridge->current_size;
 407         size = page_order = num_entries = 0;
 408
 409         do {
 410                 size = A_SIZE_32(temp)->size;
 411                 page_order = A_SIZE_32(temp)->page_order;
 412                 num_entries = A_SIZE_32(temp)->num_entries;
 413
 414                 table = (char *) __get_free_pages(GFP_KERNEL, page_order);
 415
 416                 if (table == NULL) {
 417                         i++;
 418                         bridge->current_size = A_IDX32(bridge);
 419                 } else {
 420                         bridge->aperture_size_idx = i;
 421                 }
 422         } while (!table && (i < bridge->driver->num_aperture_sizes));
 423
 424         if (table == NULL)
 425                 return -ENOMEM;
 426
 427         table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
 428
 429         for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
 430                 SetPageReserved(page);
 431
 432         bridge->gatt_table_real = (u32 *) table;
 433         bridge->gatt_table = (u32 *)table;
 434         bridge->gatt_bus_addr = virt_to_gart(table);
 435
 436         for (i = 0; i < num_entries; i++)
 437                 bridge->gatt_table[i] = 0;
 438
 439         flush_dcache_range((unsigned long)table, (unsigned long)table_end);
 440
 441         return 0;
 442 }
 443
 444 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
 445 {
 446         int page_order;
 447         char *table, *table_end;
 448         void *temp;
 449         struct page *page;
 450
 451         temp = bridge->current_size;
 452         page_order = A_SIZE_32(temp)->page_order;
 453
 454         /* Do not worry about freeing memory, because if this is
 455          * called, then all agp memory is deallocated and removed
 456          * from the table.
 457          */
 458
 459         table = (char *) bridge->gatt_table_real;
 460         table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
 461
 462         for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
 463                 ClearPageReserved(page);
 464
 465         free_pages((unsigned long) bridge->gatt_table_real, page_order);
 466
 467         return 0;
 468 }
 469
 470 void null_cache_flush(void)
 471 {
 472         mb();
 473 }
 474
 475 /* Setup function */
 476
 477 static const struct aper_size_info_32 uninorth_sizes[7] =
 478 {
 479 #if 0 /* Not sure uninorth supports that high aperture sizes */
 480         {256, 65536, 6, 64},
 481         {128, 32768, 5, 32},
 482         {64, 16384, 4, 16},
 483 #endif
 484         {32, 8192, 3, 8},
 485         {16, 4096, 2, 4},
 486         {8, 2048, 1, 2},
 487         {4, 1024, 0, 1}
 488 };
 489
 490 /*
 491  * Not sure that u3 supports that high aperture sizes but it
 492  * would strange if it did not :)
 493  */
 494 static const struct aper_size_info_32 u3_sizes[8] =
 495 {
 496         {512, 131072, 7, 128},
 497         {256, 65536, 6, 64},
 498         {128, 32768, 5, 32},
 499         {64, 16384, 4, 16},
 500         {32, 8192, 3, 8},
 501         {16, 4096, 2, 4},
 502         {8, 2048, 1, 2},
 503         {4, 1024, 0, 1}
 504 };
 505
 506 const struct agp_bridge_driver uninorth_agp_driver = {
 507         .owner                  = THIS_MODULE,
 508         .aperture_sizes         = (void *)uninorth_sizes,
 509         .size_type              = U32_APER_SIZE,
 510         .num_aperture_sizes     = 4,
 511         .configure              = uninorth_configure,
 512         .fetch_size             = uninorth_fetch_size,
 513         .cleanup                = uninorth_cleanup,
 514         .tlb_flush              = uninorth_tlbflush,
 515         .mask_memory            = agp_generic_mask_memory,
 516         .masks                  = NULL,
 517         .cache_flush            = null_cache_flush,
 518         .agp_enable             = uninorth_agp_enable,
 519         .create_gatt_table      = uninorth_create_gatt_table,
 520         .free_gatt_table        = uninorth_free_gatt_table,
 521         .insert_memory          = uninorth_insert_memory,
 522         .remove_memory          = agp_generic_remove_memory,
 523         .alloc_by_type          = agp_generic_alloc_by_type,
 524         .free_by_type           = agp_generic_free_by_type,
 525         .agp_alloc_page         = agp_generic_alloc_page,
 526         .agp_alloc_pages        = agp_generic_alloc_pages,
 527         .agp_destroy_page       = agp_generic_destroy_page,
 528         .agp_destroy_pages      = agp_generic_destroy_pages,
 529         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 530         .cant_use_aperture      = true,
 531 };
 532
 533 const struct agp_bridge_driver u3_agp_driver = {
 534         .owner                  = THIS_MODULE,
 535         .aperture_sizes         = (void *)u3_sizes,
 536         .size_type              = U32_APER_SIZE,
 537         .num_aperture_sizes     = 8,
 538         .configure              = uninorth_configure,
 539         .fetch_size             = uninorth_fetch_size,
 540         .cleanup                = uninorth_cleanup,
 541         .tlb_flush              = uninorth_tlbflush,
 542         .mask_memory            = agp_generic_mask_memory,
 543         .masks                  = NULL,
 544         .cache_flush            = null_cache_flush,
 545         .agp_enable             = uninorth_agp_enable,
 546         .create_gatt_table      = uninorth_create_gatt_table,
 547         .free_gatt_table        = uninorth_free_gatt_table,
 548         .insert_memory          = u3_insert_memory,
 549         .remove_memory          = u3_remove_memory,
 550         .alloc_by_type          = agp_generic_alloc_by_type,
 551         .free_by_type           = agp_generic_free_by_type,
 552         .agp_alloc_page         = agp_generic_alloc_page,
 553         .agp_alloc_pages        = agp_generic_alloc_pages,
 554         .agp_destroy_page       = agp_generic_destroy_page,
 555         .agp_destroy_pages      = agp_generic_destroy_pages,
 556         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 557         .cant_use_aperture      = true,
 558         .needs_scratch_page     = true,
 559 };
 560
 561 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
 562         {
 563                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
 564                 .chipset_name   = "UniNorth",
 565         },
 566         {
 567                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
 568                 .chipset_name   = "UniNorth/Pangea",
 569         },
 570         {
 571                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
 572                 .chipset_name   = "UniNorth 1.5",
 573         },
 574         {
 575                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
 576                 .chipset_name   = "UniNorth 2",
 577         },
 578         {
 579                 .device_id      = PCI_DEVICE_ID_APPLE_U3_AGP,
 580                 .chipset_name   = "U3",
 581         },
 582         {
 583                 .device_id      = PCI_DEVICE_ID_APPLE_U3L_AGP,
 584                 .chipset_name   = "U3L",
 585         },
 586         {
 587                 .device_id      = PCI_DEVICE_ID_APPLE_U3H_AGP,
 588                 .chipset_name   = "U3H",
 589         },
 590         {
 591                 .device_id      = PCI_DEVICE_ID_APPLE_IPID2_AGP,
 592                 .chipset_name   = "UniNorth/Intrepid2",
 593         },
 594 };
 595
 596 static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
 597                                         const struct pci_device_id *ent)
 598 {
 599         struct agp_device_ids *devs = uninorth_agp_device_ids;
 600         struct agp_bridge_data *bridge;
 601         struct device_node *uninorth_node;
 602         u8 cap_ptr;
 603         int j;
 604
 605         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 606         if (cap_ptr == 0)
 607                 return -ENODEV;
 608
 609         /* probe for known chipsets */
 610         for (j = 0; devs[j].chipset_name != NULL; ++j) {
 611                 if (pdev->device == devs[j].device_id) {
 612                         dev_info(&pdev->dev, "Apple %s chipset\n",
 613                                  devs[j].chipset_name);
 614                         goto found;
 615                 }
 616         }
 617
 618         dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n",
 619                 pdev->vendor, pdev->device);
 620         return -ENODEV;
 621
 622  found:
 623         /* Set revision to 0 if we could not read it. */
 624         uninorth_rev = 0;
 625         is_u3 = 0;
 626         /* Locate core99 Uni-N */
 627         uninorth_node = of_find_node_by_name(NULL, "uni-n");
 628         /* Locate G5 u3 */
 629         if (uninorth_node == NULL) {
 630                 is_u3 = 1;
 631                 uninorth_node = of_find_node_by_name(NULL, "u3");
 632         }
 633         if (uninorth_node) {
 634                 const int *revprop = of_get_property(uninorth_node,
 635                                 "device-rev", NULL);
 636                 if (revprop != NULL)
 637                         uninorth_rev = *revprop & 0x3f;
 638                 of_node_put(uninorth_node);
 639         }
 640
 641 #ifdef CONFIG_PM
 642         /* Inform platform of our suspend/resume caps */
 643         pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume);
 644 #endif
 645
 646         /* Allocate & setup our driver */
 647         bridge = agp_alloc_bridge();
 648         if (!bridge)
 649                 return -ENOMEM;
 650
 651         if (is_u3)
 652                 bridge->driver = &u3_agp_driver;
 653         else
 654                 bridge->driver = &uninorth_agp_driver;
 655
 656         bridge->dev = pdev;
 657         bridge->capndx = cap_ptr;
 658         bridge->flags = AGP_ERRATA_FASTWRITES;
 659
 660         /* Fill in the mode register */
 661         pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode);
 662
 663         pci_set_drvdata(pdev, bridge);
 664         return agp_add_bridge(bridge);
 665 }
 666
 667 static void __devexit agp_uninorth_remove(struct pci_dev *pdev)
 668 {
 669         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 670
 671 #ifdef CONFIG_PM
 672         /* Inform platform of our suspend/resume caps */
 673         pmac_register_agp_pm(pdev, NULL, NULL);
 674 #endif
 675
 676         agp_remove_bridge(bridge);
 677         agp_put_bridge(bridge);
 678 }
 679
 680 static struct pci_device_id agp_uninorth_pci_table[] = {
 681         {
 682         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 683         .class_mask     = ~0,
 684         .vendor         = PCI_VENDOR_ID_APPLE,
 685         .device         = PCI_ANY_ID,
 686         .subvendor      = PCI_ANY_ID,
 687         .subdevice      = PCI_ANY_ID,
 688         },
 689         { }
 690 };
 691
 692 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table);
 693
 694 static struct pci_driver agp_uninorth_pci_driver = {
 695         .name           = "agpgart-uninorth",
 696         .id_table       = agp_uninorth_pci_table,
 697         .probe          = agp_uninorth_probe,
 698         .remove         = agp_uninorth_remove,
 699 };
 700
 701 static int __init agp_uninorth_init(void)
 702 {
 703         if (agp_off)
 704                 return -EINVAL;
 705         return pci_register_driver(&agp_uninorth_pci_driver);
 706 }
 707
 708 static void __exit agp_uninorth_cleanup(void)
 709 {
 710         pci_unregister_driver(&agp_uninorth_pci_driver);
 711 }
 712
 713 module_init(agp_uninorth_init);
 714 module_exit(agp_uninorth_cleanup);
 715
 716 module_param(aperture, charp, 0);
 717 MODULE_PARM_DESC(aperture,
 718                  "Aperture size, must be power of two between 4MB and an\n"
 719                  "\t\tupper limit specific to the UniNorth revision.\n"
 720                  "\t\tDefault: 32M");
 721
 722 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras");
 723 MODULE_LICENSE("GPL");