2 * Marvell BT-over-SDIO driver: SDIO interface related definitions
4 * Copyright (C) 2009, Marvell International Ltd.
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
15 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
17 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
18 * this warranty disclaimer.
22 #ifndef _BTMRVL_SDIO_H_
23 #define _BTMRVL_SDIO_H_
25 #define SDIO_HEADER_LEN 4
27 /* SD block size can not bigger than 64 due to buf size limit in firmware */
28 /* define SD block size for data Tx/Rx */
29 #define SDIO_BLOCK_SIZE 64
31 /* Number of blocks for firmware transfer */
32 #define FIRMWARE_TRANSFER_NBLOCK 2
34 /* This is for firmware specific length */
35 #define FW_EXTRA_LEN 36
37 #define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
39 #define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
40 (HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
42 #define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
43 MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
44 + SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
47 /* The number of times to try when polling for status */
48 #define MAX_POLL_TRIES 100
50 /* Max retry number of CMD53 write */
51 #define MAX_WRITE_IOMEM_RETRY 2
53 /* Host Control Registers */
54 #define IO_PORT_0_REG 0x00
55 #define IO_PORT_1_REG 0x01
56 #define IO_PORT_2_REG 0x02
58 #define CONFIG_REG 0x03
59 #define HOST_POWER_UP BIT(1)
60 #define HOST_CMD53_FIN BIT(2)
62 #define HOST_INT_MASK_REG 0x04
63 #define HIM_DISABLE 0xff
64 #define HIM_ENABLE (BIT(0) | BIT(1))
66 #define HOST_INTSTATUS_REG 0x05
67 #define UP_LD_HOST_INT_STATUS BIT(0)
68 #define DN_LD_HOST_INT_STATUS BIT(1)
70 /* Card Control Registers */
71 #define SQ_READ_BASE_ADDRESS_A0_REG 0x10
72 #define SQ_READ_BASE_ADDRESS_A1_REG 0x11
74 #define CARD_STATUS_REG 0x20
75 #define DN_LD_CARD_RDY BIT(0)
76 #define CARD_IO_READY BIT(3)
78 #define CARD_FW_STATUS0_REG 0x40
79 #define CARD_FW_STATUS1_REG 0x41
80 #define FIRMWARE_READY 0xfedc
82 #define CARD_RX_LEN_REG 0x42
83 #define CARD_RX_UNIT_REG 0x43
86 struct btmrvl_sdio_card {
87 struct sdio_func *func;
92 struct btmrvl_private *priv;
95 struct btmrvl_sdio_device {
96 unsigned short dev_id;
102 /* Platform specific DMA alignment */
103 #define BTSDIO_DMA_ALIGN 8
105 /* Macros for Data Alignment : size */
106 #define ALIGN_SZ(p, a) \
107 (((p) + ((a) - 1)) & ~((a) - 1))
109 /* Macros for Data Alignment : address */
110 #define ALIGN_ADDR(p, a) \
111 ((((u32)(p)) + (((u32)(a)) - 1)) & ~(((u32)(a)) - 1))
113 #endif /* _BTMRVL_SDIO_H_ */