2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
41 #define DRV_NAME "sata_qstor"
42 #define DRV_VERSION "0.09"
48 QS_MAX_PRD = LIBATA_MAX_PRD,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
103 QS_DMA_BOUNDARY = ~0UL
106 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
108 struct qs_port_priv {
114 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
115 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
117 static int qs_port_start(struct ata_port *ap);
118 static void qs_host_stop(struct ata_host *host);
119 static void qs_phy_reset(struct ata_port *ap);
120 static void qs_qc_prep(struct ata_queued_cmd *qc);
121 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
122 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
123 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
124 static u8 qs_bmdma_status(struct ata_port *ap);
125 static void qs_irq_clear(struct ata_port *ap);
126 static void qs_eng_timeout(struct ata_port *ap);
128 static struct scsi_host_template qs_ata_sht = {
129 .module = THIS_MODULE,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = QS_MAX_PRD,
136 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
137 .emulated = ATA_SHT_EMULATED,
138 .use_clustering = ENABLE_CLUSTERING,
139 .proc_name = DRV_NAME,
140 .dma_boundary = QS_DMA_BOUNDARY,
141 .slave_configure = ata_scsi_slave_config,
142 .slave_destroy = ata_scsi_slave_destroy,
143 .bios_param = ata_std_bios_param,
146 static const struct ata_port_operations qs_ata_ops = {
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .check_atapi_dma = qs_check_atapi_dma,
151 .exec_command = ata_exec_command,
152 .dev_select = ata_std_dev_select,
153 .phy_reset = qs_phy_reset,
154 .qc_prep = qs_qc_prep,
155 .qc_issue = qs_qc_issue,
156 .data_xfer = ata_data_xfer,
157 .eng_timeout = qs_eng_timeout,
158 .irq_clear = qs_irq_clear,
159 .irq_on = ata_irq_on,
160 .scr_read = qs_scr_read,
161 .scr_write = qs_scr_write,
162 .port_start = qs_port_start,
163 .host_stop = qs_host_stop,
164 .bmdma_stop = qs_bmdma_stop,
165 .bmdma_status = qs_bmdma_status,
168 static const struct ata_port_info qs_port_info[] = {
171 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
172 ATA_FLAG_SATA_RESET |
173 //FIXME ATA_FLAG_SRST |
174 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
175 .pio_mask = 0x10, /* pio4 */
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &qs_ata_ops,
181 static const struct pci_device_id qs_ata_pci_tbl[] = {
182 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
184 { } /* terminate list */
187 static struct pci_driver qs_ata_pci_driver = {
189 .id_table = qs_ata_pci_tbl,
190 .probe = qs_ata_init_one,
191 .remove = ata_pci_remove_one,
194 static void __iomem *qs_mmio_base(struct ata_host *host)
196 return host->iomap[QS_MMIO_BAR];
199 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
201 return 1; /* ATAPI DMA not supported */
204 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
209 static u8 qs_bmdma_status(struct ata_port *ap)
214 static void qs_irq_clear(struct ata_port *ap)
219 static inline void qs_enter_reg_mode(struct ata_port *ap)
221 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
222 struct qs_port_priv *pp = ap->private_data;
224 pp->state = qs_state_mmio;
225 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
226 readb(chan + QS_CCT_CTR0); /* flush */
229 static inline void qs_reset_channel_logic(struct ata_port *ap)
231 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
233 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
234 readb(chan + QS_CCT_CTR0); /* flush */
235 qs_enter_reg_mode(ap);
238 static void qs_phy_reset(struct ata_port *ap)
240 qs_reset_channel_logic(ap);
244 static void qs_eng_timeout(struct ata_port *ap)
246 qs_reset_channel_logic(ap);
250 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
252 if (sc_reg > SCR_CONTROL)
254 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
258 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
260 if (sc_reg > SCR_CONTROL)
262 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
266 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
268 struct scatterlist *sg;
269 struct ata_port *ap = qc->ap;
270 struct qs_port_priv *pp = ap->private_data;
272 u8 *prd = pp->pkt + QS_CPB_BYTES;
274 WARN_ON(qc->__sg == NULL);
275 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
278 ata_for_each_sg(sg, qc) {
282 addr = sg_dma_address(sg);
283 *(__le64 *)prd = cpu_to_le64(addr);
286 len = sg_dma_len(sg);
287 *(__le32 *)prd = cpu_to_le32(len);
290 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
291 (unsigned long long)addr, len);
298 static void qs_qc_prep(struct ata_queued_cmd *qc)
300 struct qs_port_priv *pp = qc->ap->private_data;
301 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
302 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
308 qs_enter_reg_mode(qc->ap);
309 if (qc->tf.protocol != ATA_PROT_DMA) {
314 nelem = qs_fill_sg(qc);
316 if ((qc->tf.flags & ATA_TFLAG_WRITE))
317 hflags |= QS_HF_DIRO;
318 if ((qc->tf.flags & ATA_TFLAG_LBA48))
319 dflags |= QS_DF_ELBA;
321 /* host control block (HCB) */
322 buf[ 0] = QS_HCB_HDR;
324 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
325 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
326 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
327 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
329 /* device control block (DCB) */
330 buf[24] = QS_DCB_HDR;
333 /* frame information structure (FIS) */
334 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
337 static inline void qs_packet_start(struct ata_queued_cmd *qc)
339 struct ata_port *ap = qc->ap;
340 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
342 VPRINTK("ENTER, ap %p\n", ap);
344 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
345 wmb(); /* flush PRDs and pkt to memory */
346 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
347 readl(chan + QS_CCT_CFF); /* flush */
350 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
352 struct qs_port_priv *pp = qc->ap->private_data;
354 switch (qc->tf.protocol) {
357 pp->state = qs_state_pkt;
361 case ATA_PROT_ATAPI_DMA:
369 pp->state = qs_state_mmio;
370 return ata_qc_issue_prot(qc);
373 static inline unsigned int qs_intr_pkt(struct ata_host *host)
375 unsigned int handled = 0;
377 u8 __iomem *mmio_base = qs_mmio_base(host);
380 u32 sff0 = readl(mmio_base + QS_HST_SFF);
381 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
382 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
383 sFFE = sff1 >> 31; /* empty flag */
386 u8 sDST = sff0 >> 16; /* dev status */
387 u8 sHST = sff1 & 0x3f; /* host status */
388 unsigned int port_no = (sff1 >> 8) & 0x03;
389 struct ata_port *ap = host->ports[port_no];
391 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
392 sff1, sff0, port_no, sHST, sDST);
394 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
395 struct ata_queued_cmd *qc;
396 struct qs_port_priv *pp = ap->private_data;
397 if (!pp || pp->state != qs_state_pkt)
399 qc = ata_qc_from_tag(ap, ap->link.active_tag);
400 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
402 case 0: /* successful CPB */
403 case 3: /* device error */
404 qs_enter_reg_mode(qc->ap);
405 qc->err_mask |= ac_err_mask(sDST);
418 static inline unsigned int qs_intr_mmio(struct ata_host *host)
420 unsigned int handled = 0, port_no;
422 for (port_no = 0; port_no < host->n_ports; ++port_no) {
424 ap = host->ports[port_no];
426 !(ap->flags & ATA_FLAG_DISABLED)) {
427 struct ata_queued_cmd *qc;
428 struct qs_port_priv *pp;
429 qc = ata_qc_from_tag(ap, ap->link.active_tag);
430 if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
432 * The qstor hardware generates spurious
433 * interrupts from time to time when switching
434 * in and out of packet mode.
435 * There's no obvious way to know if we're
436 * here now due to that, so just ack the irq
437 * and pretend we knew it was ours.. (ugh).
438 * This does not affect packet mode.
440 ata_check_status(ap);
444 pp = ap->private_data;
445 if (!pp || pp->state != qs_state_mmio)
447 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
448 handled |= ata_host_intr(ap, qc);
454 static irqreturn_t qs_intr(int irq, void *dev_instance)
456 struct ata_host *host = dev_instance;
457 unsigned int handled = 0;
462 spin_lock_irqsave(&host->lock, flags);
463 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
464 spin_unlock_irqrestore(&host->lock, flags);
468 return IRQ_RETVAL(handled);
471 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
474 port->data_addr = base + 0x400;
476 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
477 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
478 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
479 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
480 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
481 port->device_addr = base + 0x430;
483 port->command_addr = base + 0x438;
484 port->altstatus_addr =
485 port->ctl_addr = base + 0x440;
486 port->scr_addr = base + 0xc00;
489 static int qs_port_start(struct ata_port *ap)
491 struct device *dev = ap->host->dev;
492 struct qs_port_priv *pp;
493 void __iomem *mmio_base = qs_mmio_base(ap->host);
494 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
498 rc = ata_port_start(ap);
501 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
504 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
508 memset(pp->pkt, 0, QS_PKT_BYTES);
509 ap->private_data = pp;
511 qs_enter_reg_mode(ap);
512 addr = (u64)pp->pkt_dma;
513 writel((u32) addr, chan + QS_CCF_CPBA);
514 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
518 static void qs_host_stop(struct ata_host *host)
520 void __iomem *mmio_base = qs_mmio_base(host);
522 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
523 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
526 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
528 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
529 unsigned int port_no;
531 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
532 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
534 /* reset each channel in turn */
535 for (port_no = 0; port_no < host->n_ports; ++port_no) {
536 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
537 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
538 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
539 readb(chan + QS_CCT_CTR0); /* flush */
541 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
543 for (port_no = 0; port_no < host->n_ports; ++port_no) {
544 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
545 /* set FIFO depths to same settings as Windows driver */
546 writew(32, chan + QS_CFC_HUFT);
547 writew(32, chan + QS_CFC_HDFT);
548 writew(10, chan + QS_CFC_DUFT);
549 writew( 8, chan + QS_CFC_DDFT);
550 /* set CPB size in bytes, as a power of two */
551 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
553 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
557 * The QStor understands 64-bit buses, and uses 64-bit fields
558 * for DMA pointers regardless of bus width. We just have to
559 * make sure our DMA masks are set appropriately for whatever
560 * bridge lies between us and the QStor, and then the DMA mapping
561 * code will ensure we only ever "see" appropriate buffer addresses.
562 * If we're 32-bit limited somewhere, then our 64-bit fields will
563 * just end up with zeros in the upper 32-bits, without any special
564 * logic required outside of this routine (below).
566 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
568 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
569 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
571 if (have_64bit_bus &&
572 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
573 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
575 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
577 dev_printk(KERN_ERR, &pdev->dev,
578 "64-bit DMA enable failed\n");
583 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
585 dev_printk(KERN_ERR, &pdev->dev,
586 "32-bit DMA enable failed\n");
589 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
591 dev_printk(KERN_ERR, &pdev->dev,
592 "32-bit consistent DMA enable failed\n");
599 static int qs_ata_init_one(struct pci_dev *pdev,
600 const struct pci_device_id *ent)
602 static int printed_version;
603 unsigned int board_idx = (unsigned int) ent->driver_data;
604 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
605 struct ata_host *host;
608 if (!printed_version++)
609 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
612 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
616 /* acquire resources and fill host */
617 rc = pcim_enable_device(pdev);
621 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
624 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
627 host->iomap = pcim_iomap_table(pdev);
629 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
633 for (port_no = 0; port_no < host->n_ports; ++port_no) {
634 struct ata_port *ap = host->ports[port_no];
635 unsigned int offset = port_no * 0x4000;
636 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
638 qs_ata_setup_port(&ap->ioaddr, chan);
640 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
641 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
644 /* initialize adapter */
645 qs_host_init(host, board_idx);
647 pci_set_master(pdev);
648 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
652 static int __init qs_ata_init(void)
654 return pci_register_driver(&qs_ata_pci_driver);
657 static void __exit qs_ata_exit(void)
659 pci_unregister_driver(&qs_ata_pci_driver);
662 MODULE_AUTHOR("Mark Lord");
663 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
664 MODULE_LICENSE("GPL");
665 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
666 MODULE_VERSION(DRV_VERSION);
668 module_init(qs_ata_init);
669 module_exit(qs_ata_exit);