2 * libata-bmdma.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
42 * ata_irq_on - Enable interrupts on a port.
43 * @ap: Port on which interrupts are enabled.
45 * Enable interrupts on a legacy IDE device using MMIO or PIO,
46 * wait for idle, clear any pending interrupts.
49 * Inherited from caller.
51 u8 ata_irq_on(struct ata_port *ap)
53 struct ata_ioports *ioaddr = &ap->ioaddr;
57 ap->last_ctl = ap->ctl;
59 iowrite8(ap->ctl, ioaddr->ctl_addr);
60 tmp = ata_wait_idle(ap);
62 ap->ops->irq_clear(ap);
68 * ata_tf_load - send taskfile registers to host controller
69 * @ap: Port to which output is sent
70 * @tf: ATA taskfile register set
72 * Outputs ATA taskfile to standard ATA host controller.
75 * Inherited from caller.
78 void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
80 struct ata_ioports *ioaddr = &ap->ioaddr;
81 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
83 if (tf->ctl != ap->last_ctl) {
84 iowrite8(tf->ctl, ioaddr->ctl_addr);
85 ap->last_ctl = tf->ctl;
89 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
90 iowrite8(tf->hob_feature, ioaddr->feature_addr);
91 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
92 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
93 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
94 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
95 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
104 iowrite8(tf->feature, ioaddr->feature_addr);
105 iowrite8(tf->nsect, ioaddr->nsect_addr);
106 iowrite8(tf->lbal, ioaddr->lbal_addr);
107 iowrite8(tf->lbam, ioaddr->lbam_addr);
108 iowrite8(tf->lbah, ioaddr->lbah_addr);
109 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
117 if (tf->flags & ATA_TFLAG_DEVICE) {
118 iowrite8(tf->device, ioaddr->device_addr);
119 VPRINTK("device 0x%X\n", tf->device);
126 * ata_exec_command - issue ATA command to host controller
127 * @ap: port to which command is being issued
128 * @tf: ATA taskfile register set
130 * Issues ATA command, with proper synchronization with interrupt
131 * handler / other threads.
134 * spin_lock_irqsave(host lock)
136 void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
138 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
140 iowrite8(tf->command, ap->ioaddr.command_addr);
145 * ata_tf_read - input device's ATA taskfile shadow registers
146 * @ap: Port from which input is read
147 * @tf: ATA taskfile register set for storing input
149 * Reads ATA taskfile registers for currently-selected device
153 * Inherited from caller.
155 void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
157 struct ata_ioports *ioaddr = &ap->ioaddr;
159 tf->command = ata_check_status(ap);
160 tf->feature = ioread8(ioaddr->error_addr);
161 tf->nsect = ioread8(ioaddr->nsect_addr);
162 tf->lbal = ioread8(ioaddr->lbal_addr);
163 tf->lbam = ioread8(ioaddr->lbam_addr);
164 tf->lbah = ioread8(ioaddr->lbah_addr);
165 tf->device = ioread8(ioaddr->device_addr);
167 if (tf->flags & ATA_TFLAG_LBA48) {
168 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
169 tf->hob_feature = ioread8(ioaddr->error_addr);
170 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
171 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
172 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
173 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
178 * ata_check_status - Read device status reg & clear interrupt
179 * @ap: port where the device is
181 * Reads ATA taskfile status register for currently-selected device
182 * and return its value. This also clears pending interrupts
186 * Inherited from caller.
188 u8 ata_check_status(struct ata_port *ap)
190 return ioread8(ap->ioaddr.status_addr);
194 * ata_altstatus - Read device alternate status reg
195 * @ap: port where the device is
197 * Reads ATA taskfile alternate status register for
198 * currently-selected device and return its value.
200 * Note: may NOT be used as the check_altstatus() entry in
201 * ata_port_operations.
204 * Inherited from caller.
206 u8 ata_altstatus(struct ata_port *ap)
208 if (ap->ops->check_altstatus)
209 return ap->ops->check_altstatus(ap);
211 return ioread8(ap->ioaddr.altstatus_addr);
215 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
216 * @qc: Info associated with this ATA transaction.
219 * spin_lock_irqsave(host lock)
221 void ata_bmdma_setup(struct ata_queued_cmd *qc)
223 struct ata_port *ap = qc->ap;
224 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
227 /* load PRD table addr. */
228 mb(); /* make sure PRD table writes are visible to controller */
229 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
231 /* specify data direction, triple-check start bit is clear */
232 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
233 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
235 dmactl |= ATA_DMA_WR;
236 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
238 /* issue r/w command */
239 ap->ops->exec_command(ap, &qc->tf);
243 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
244 * @qc: Info associated with this ATA transaction.
247 * spin_lock_irqsave(host lock)
249 void ata_bmdma_start (struct ata_queued_cmd *qc)
251 struct ata_port *ap = qc->ap;
254 /* start host DMA transaction */
255 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
256 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
258 /* Strictly, one may wish to issue a readb() here, to
259 * flush the mmio write. However, control also passes
260 * to the hardware at this point, and it will interrupt
261 * us when we are to resume control. So, in effect,
262 * we don't care when the mmio write flushes.
263 * Further, a read of the DMA status register _immediately_
264 * following the write may not be what certain flaky hardware
265 * is expected, so I think it is best to not add a readb()
266 * without first all the MMIO ATA cards/mobos.
267 * Or maybe I'm just being paranoid.
272 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
273 * @ap: Port associated with this ATA transaction.
275 * Clear interrupt and error flags in DMA status register.
277 * May be used as the irq_clear() entry in ata_port_operations.
280 * spin_lock_irqsave(host lock)
282 void ata_bmdma_irq_clear(struct ata_port *ap)
284 void __iomem *mmio = ap->ioaddr.bmdma_addr;
289 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
293 * ata_bmdma_status - Read PCI IDE BMDMA status
294 * @ap: Port associated with this ATA transaction.
296 * Read and return BMDMA status register.
298 * May be used as the bmdma_status() entry in ata_port_operations.
301 * spin_lock_irqsave(host lock)
303 u8 ata_bmdma_status(struct ata_port *ap)
305 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
309 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
310 * @qc: Command we are ending DMA for
312 * Clears the ATA_DMA_START flag in the dma control register
314 * May be used as the bmdma_stop() entry in ata_port_operations.
317 * spin_lock_irqsave(host lock)
319 void ata_bmdma_stop(struct ata_queued_cmd *qc)
321 struct ata_port *ap = qc->ap;
322 void __iomem *mmio = ap->ioaddr.bmdma_addr;
324 /* clear start/stop bit */
325 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
328 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
329 ata_altstatus(ap); /* dummy read */
333 * ata_bmdma_freeze - Freeze BMDMA controller port
334 * @ap: port to freeze
336 * Freeze BMDMA controller port.
339 * Inherited from caller.
341 void ata_bmdma_freeze(struct ata_port *ap)
343 struct ata_ioports *ioaddr = &ap->ioaddr;
346 ap->last_ctl = ap->ctl;
348 iowrite8(ap->ctl, ioaddr->ctl_addr);
350 /* Under certain circumstances, some controllers raise IRQ on
351 * ATA_NIEN manipulation. Also, many controllers fail to mask
352 * previously pending IRQ on ATA_NIEN assertion. Clear it.
356 ap->ops->irq_clear(ap);
360 * ata_bmdma_thaw - Thaw BMDMA controller port
363 * Thaw BMDMA controller port.
366 * Inherited from caller.
368 void ata_bmdma_thaw(struct ata_port *ap)
370 /* clear & re-enable interrupts */
372 ap->ops->irq_clear(ap);
373 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
378 * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller
379 * @ap: port to handle error for
380 * @prereset: prereset method (can be NULL)
381 * @softreset: softreset method (can be NULL)
382 * @hardreset: hardreset method (can be NULL)
383 * @postreset: postreset method (can be NULL)
385 * Handle error for ATA BMDMA controller. It can handle both
386 * PATA and SATA controllers. Many controllers should be able to
387 * use this EH as-is or with some added handling before and
390 * This function is intended to be used for constructing
391 * ->error_handler callback by low level drivers.
394 * Kernel thread context (may sleep)
396 void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
397 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
398 ata_postreset_fn_t postreset)
400 struct ata_queued_cmd *qc;
404 qc = __ata_qc_from_tag(ap, ap->active_tag);
405 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
408 /* reset PIO HSM and stop DMA engine */
409 spin_lock_irqsave(ap->lock, flags);
411 ap->hsm_task_state = HSM_ST_IDLE;
413 if (qc && (qc->tf.protocol == ATA_PROT_DMA ||
414 qc->tf.protocol == ATA_PROT_ATAPI_DMA)) {
417 host_stat = ap->ops->bmdma_status(ap);
419 /* BMDMA controllers indicate host bus error by
420 * setting DMA_ERR bit and timing out. As it wasn't
421 * really a timeout event, adjust error mask and
422 * cancel frozen state.
424 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
425 qc->err_mask = AC_ERR_HOST_BUS;
429 ap->ops->bmdma_stop(qc);
434 ap->ops->irq_clear(ap);
436 spin_unlock_irqrestore(ap->lock, flags);
439 ata_eh_thaw_port(ap);
441 /* PIO and DMA engines have been stopped, perform recovery */
442 ata_do_eh(ap, prereset, softreset, hardreset, postreset);
446 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
447 * @ap: port to handle error for
449 * Stock error handler for BMDMA controller.
452 * Kernel thread context (may sleep)
454 void ata_bmdma_error_handler(struct ata_port *ap)
456 ata_reset_fn_t hardreset;
459 if (sata_scr_valid(ap))
460 hardreset = sata_std_hardreset;
462 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
467 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for
469 * @qc: internal command to clean up
472 * Kernel thread context (may sleep)
474 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
476 if (qc->ap->ioaddr.bmdma_addr)
482 static int ata_resources_present(struct pci_dev *pdev, int port)
486 /* Check the PCI resources for this channel are enabled */
488 for (i = 0; i < 2; i ++) {
489 if (pci_resource_start(pdev, port + i) == 0 ||
490 pci_resource_len(pdev, port + i) == 0)
497 * ata_pci_init_native_mode - Initialize native-mode driver
498 * @pdev: pci device to be initialized
499 * @port: array[2] of pointers to port info structures.
500 * @ports: bitmap of ports present
502 * Utility function which allocates and initializes an
503 * ata_probe_ent structure for a standard dual-port
504 * PIO-based IDE controller. The returned ata_probe_ent
505 * structure can be passed to ata_device_add(). The returned
506 * ata_probe_ent structure should then be freed with kfree().
508 * The caller need only pass the address of the primary port, the
509 * secondary will be deduced automatically. If the device has non
510 * standard secondary port mappings this function can be called twice,
511 * once for each interface.
514 struct ata_probe_ent *
515 ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
517 struct ata_probe_ent *probe_ent;
519 void __iomem * const *iomap;
522 for (i = 0; i < 4; i++) {
523 if (pcim_iomap(pdev, i, 0) == NULL) {
524 dev_printk(KERN_ERR, &pdev->dev,
525 "failed to iomap PCI BAR %d\n", i);
530 pcim_iomap(pdev, 4, 0); /* may fail */
531 iomap = pcim_iomap_table(pdev);
533 /* alloc and init probe_ent */
534 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
538 probe_ent->irq = pdev->irq;
539 probe_ent->irq_flags = IRQF_SHARED;
541 /* Discard disabled ports. Some controllers show their
542 unused channels this way */
543 if (ata_resources_present(pdev, 0) == 0)
544 ports &= ~ATA_PORT_PRIMARY;
545 if (ata_resources_present(pdev, 1) == 0)
546 ports &= ~ATA_PORT_SECONDARY;
548 if (ports & ATA_PORT_PRIMARY) {
549 probe_ent->port[p].cmd_addr = iomap[0];
550 probe_ent->port[p].altstatus_addr =
551 probe_ent->port[p].ctl_addr = (void __iomem *)
552 ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS);
554 if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) &&
555 (ioread8(iomap[4] + 2) & 0x80))
556 probe_ent->_host_flags |= ATA_HOST_SIMPLEX;
557 probe_ent->port[p].bmdma_addr = iomap[4];
559 ata_std_ports(&probe_ent->port[p]);
563 if (ports & ATA_PORT_SECONDARY) {
564 probe_ent->port[p].cmd_addr = iomap[2];
565 probe_ent->port[p].altstatus_addr =
566 probe_ent->port[p].ctl_addr = (void __iomem *)
567 ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS);
569 if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) &&
570 (ioread8(iomap[4] + 10) & 0x80))
571 probe_ent->_host_flags |= ATA_HOST_SIMPLEX;
572 probe_ent->port[p].bmdma_addr = iomap[4] + 8;
574 ata_std_ports(&probe_ent->port[p]);
575 probe_ent->pinfo2 = port[1];
579 probe_ent->n_ports = p;
583 static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev,
584 struct ata_port_info **port, int port_mask)
586 struct ata_probe_ent *probe_ent;
587 void __iomem *iomap[5] = { }, *bmdma;
589 if (port_mask & ATA_PORT_PRIMARY) {
590 iomap[0] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CMD, 8);
591 iomap[1] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CTL, 1);
592 if (!iomap[0] || !iomap[1])
596 if (port_mask & ATA_PORT_SECONDARY) {
597 iomap[2] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CMD, 8);
598 iomap[3] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CTL, 1);
599 if (!iomap[2] || !iomap[3])
603 bmdma = pcim_iomap(pdev, 4, 16); /* may fail */
605 /* alloc and init probe_ent */
606 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
610 probe_ent->n_ports = 2;
611 probe_ent->irq_flags = IRQF_SHARED;
613 if (port_mask & ATA_PORT_PRIMARY) {
614 probe_ent->irq = ATA_PRIMARY_IRQ(pdev);
615 probe_ent->port[0].cmd_addr = iomap[0];
616 probe_ent->port[0].altstatus_addr =
617 probe_ent->port[0].ctl_addr = iomap[1];
619 probe_ent->port[0].bmdma_addr = bmdma;
620 if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) &&
621 (ioread8(bmdma + 2) & 0x80))
622 probe_ent->_host_flags |= ATA_HOST_SIMPLEX;
624 ata_std_ports(&probe_ent->port[0]);
626 probe_ent->dummy_port_mask |= ATA_PORT_PRIMARY;
628 if (port_mask & ATA_PORT_SECONDARY) {
630 probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev);
632 probe_ent->irq = ATA_SECONDARY_IRQ(pdev);
633 probe_ent->port[1].cmd_addr = iomap[2];
634 probe_ent->port[1].altstatus_addr =
635 probe_ent->port[1].ctl_addr = iomap[3];
637 probe_ent->port[1].bmdma_addr = bmdma + 8;
638 if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) &&
639 (ioread8(bmdma + 10) & 0x80))
640 probe_ent->_host_flags |= ATA_HOST_SIMPLEX;
642 ata_std_ports(&probe_ent->port[1]);
644 /* FIXME: could be pointing to stack area; must copy */
645 probe_ent->pinfo2 = port[1];
647 probe_ent->dummy_port_mask |= ATA_PORT_SECONDARY;
654 * ata_pci_init_one - Initialize/register PCI IDE host controller
655 * @pdev: Controller to be initialized
656 * @port_info: Information from low-level host driver
657 * @n_ports: Number of ports attached to host controller
659 * This is a helper function which can be called from a driver's
660 * xxx_init_one() probe function if the hardware uses traditional
661 * IDE taskfile registers.
663 * This function calls pci_enable_device(), reserves its register
664 * regions, sets the dma mask, enables bus master mode, and calls
668 * Nobody makes a single channel controller that appears solely as
669 * the secondary legacy port on PCI.
672 * Inherited from PCI layer (may sleep).
675 * Zero on success, negative on errno-based value on error.
678 int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
679 unsigned int n_ports)
681 struct device *dev = &pdev->dev;
682 struct ata_probe_ent *probe_ent = NULL;
683 struct ata_port_info *port[2];
685 unsigned int legacy_mode = 0;
690 if (!devres_open_group(dev, NULL, GFP_KERNEL))
693 BUG_ON(n_ports < 1 || n_ports > 2);
695 port[0] = port_info[0];
697 port[1] = port_info[1];
701 /* FIXME: Really for ATA it isn't safe because the device may be
702 multi-purpose and we want to leave it alone if it was already
703 enabled. Secondly for shared use as Arjan says we want refcounting
705 Checking dev->is_enabled is insufficient as this is not set at
706 boot for the primary video which is BIOS enabled
709 rc = pcim_enable_device(pdev);
713 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
716 /* TODO: What if one channel is in native mode ... */
717 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
718 mask = (1 << 2) | (1 << 0);
719 if ((tmp8 & mask) != mask)
720 legacy_mode = (1 << 3);
721 #if defined(CONFIG_NO_ATA_LEGACY)
722 /* Some platforms with PCI limits cannot address compat
723 port space. In that case we punt if their firmware has
724 left a device in compatibility mode */
726 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
734 rc = pci_request_regions(pdev, DRV_NAME);
736 pcim_pin_device(pdev);
740 /* Deal with combined mode hack. This side of the logic all
741 goes away once the combined mode hack is killed in 2.6.21 */
742 if (!devm_request_region(dev, ATA_PRIMARY_CMD, 8, "libata")) {
743 struct resource *conflict, res;
744 res.start = ATA_PRIMARY_CMD;
745 res.end = ATA_PRIMARY_CMD + 8 - 1;
746 conflict = ____request_resource(&ioport_resource, &res);
747 while (conflict->child)
748 conflict = ____request_resource(conflict, &res);
749 if (!strcmp(conflict->name, "libata"))
750 legacy_mode |= ATA_PORT_PRIMARY;
752 pcim_pin_device(pdev);
753 printk(KERN_WARNING "ata: 0x%0X IDE port busy\n" \
754 "ata: conflict with %s\n",
759 legacy_mode |= ATA_PORT_PRIMARY;
761 if (!devm_request_region(dev, ATA_SECONDARY_CMD, 8, "libata")) {
762 struct resource *conflict, res;
763 res.start = ATA_SECONDARY_CMD;
764 res.end = ATA_SECONDARY_CMD + 8 - 1;
765 conflict = ____request_resource(&ioport_resource, &res);
766 while (conflict->child)
767 conflict = ____request_resource(conflict, &res);
768 if (!strcmp(conflict->name, "libata"))
769 legacy_mode |= ATA_PORT_SECONDARY;
771 pcim_pin_device(pdev);
772 printk(KERN_WARNING "ata: 0x%X IDE port busy\n" \
773 "ata: conflict with %s\n",
778 legacy_mode |= ATA_PORT_SECONDARY;
780 if (legacy_mode & ATA_PORT_PRIMARY)
781 pci_request_region(pdev, 1, DRV_NAME);
782 if (legacy_mode & ATA_PORT_SECONDARY)
783 pci_request_region(pdev, 3, DRV_NAME);
784 /* If there is a DMA resource, allocate it */
785 pci_request_region(pdev, 4, DRV_NAME);
788 /* we have legacy mode, but all ports are unavailable */
789 if (legacy_mode == (1 << 3)) {
794 /* TODO: If we get no DMA mask we should fall back to PIO */
795 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
798 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
803 probe_ent = ata_pci_init_legacy_port(pdev, port, legacy_mode);
806 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
808 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
815 pci_set_master(pdev);
817 if (!ata_device_add(probe_ent)) {
822 devm_kfree(dev, probe_ent);
823 devres_remove_group(dev, NULL);
827 devres_release_group(dev, NULL);
832 * ata_pci_clear_simplex - attempt to kick device out of simplex
835 * Some PCI ATA devices report simplex mode but in fact can be told to
836 * enter non simplex mode. This implements the neccessary logic to
837 * perform the task on such devices. Calling it on other devices will
838 * have -undefined- behaviour.
841 int ata_pci_clear_simplex(struct pci_dev *pdev)
843 unsigned long bmdma = pci_resource_start(pdev, 4);
849 simplex = inb(bmdma + 0x02);
850 outb(simplex & 0x60, bmdma + 0x02);
851 simplex = inb(bmdma + 0x02);
857 unsigned long ata_pci_default_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long xfer_mask)
859 /* Filter out DMA modes if the device has been configured by
860 the BIOS as PIO only */
862 if (ap->ioaddr.bmdma_addr == 0)
863 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
867 #endif /* CONFIG_PCI */