2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_sb700, /* for SB700 and SB800 */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
95 static struct scsi_host_template ahci_sht = {
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
109 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
111 static const struct ata_port_info ahci_port_info[] = {
115 .flags = AHCI_FLAG_COMMON,
116 .pio_mask = ATA_PIO4,
117 .udma_mask = ATA_UDMA6,
118 .port_ops = &ahci_ops,
120 [board_ahci_ign_iferr] =
122 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_nomsi] = {
129 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
135 [board_ahci_noncq] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
142 [board_ahci_nosntf] =
144 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_yes_fbs] =
152 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
163 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
178 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
186 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
187 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
188 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
196 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
197 AHCI_HFLAG_32BIT_ONLY),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_pmp_retry_srst_ops,
203 [board_ahci_sb700] = /* for SB700 and SB800 */
205 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
206 .flags = AHCI_FLAG_COMMON,
207 .pio_mask = ATA_PIO4,
208 .udma_mask = ATA_UDMA6,
209 .port_ops = &ahci_pmp_retry_srst_ops,
211 [board_ahci_vt8251] =
213 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
214 .flags = AHCI_FLAG_COMMON,
215 .pio_mask = ATA_PIO4,
216 .udma_mask = ATA_UDMA6,
217 .port_ops = &ahci_vt8251_ops,
221 static const struct pci_device_id ahci_pci_tbl[] = {
223 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
224 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
225 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
226 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
227 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
228 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
229 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
230 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
231 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
232 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
233 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
234 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
235 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
236 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
237 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
238 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
240 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
241 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
242 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
244 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
245 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
246 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
247 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
249 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
251 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
252 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
253 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
254 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
255 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
256 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
257 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
258 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
259 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
261 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
263 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
264 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
265 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
266 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
267 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
268 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
269 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
270 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
271 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
272 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
273 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
274 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
275 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
276 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
277 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
278 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
279 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
280 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
281 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
282 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
283 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
284 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
285 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
286 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
287 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
288 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
289 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
290 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
291 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
292 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
293 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
294 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
295 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
296 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
297 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
298 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
299 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
302 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
303 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
306 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
307 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
308 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
309 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
310 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
311 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
312 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
313 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
314 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
315 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
316 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
317 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
318 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
319 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
320 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
321 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
322 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
323 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
327 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
328 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
329 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
330 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
331 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
332 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
333 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
335 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
336 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
337 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
340 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
341 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
346 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
349 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
350 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
351 /* AMD is using RAID class only for ahci controllers */
352 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
353 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
356 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
357 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
360 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
368 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
380 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
432 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
443 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
446 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
447 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
448 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
450 /* ST Microelectronics */
451 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
454 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
455 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
457 .class = PCI_CLASS_STORAGE_SATA_AHCI,
458 .class_mask = 0xffffff,
459 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
461 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
462 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
463 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
464 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
465 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
466 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
467 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
468 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
469 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
470 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
472 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
474 .driver_data = board_ahci_yes_fbs },
475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
476 .driver_data = board_ahci_yes_fbs },
477 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
478 .driver_data = board_ahci_yes_fbs },
479 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
480 .driver_data = board_ahci_yes_fbs },
483 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
484 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
487 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
488 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
489 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
490 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
493 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
494 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
496 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
499 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
501 /* Generic, PCI class code for AHCI */
502 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
503 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
505 { } /* terminate list */
509 static struct pci_driver ahci_pci_driver = {
511 .id_table = ahci_pci_tbl,
512 .probe = ahci_init_one,
513 .remove = ata_pci_remove_one,
515 .suspend = ahci_pci_device_suspend,
516 .resume = ahci_pci_device_resume,
520 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
521 static int marvell_enable;
523 static int marvell_enable = 1;
525 module_param(marvell_enable, int, 0644);
526 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
529 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
530 struct ahci_host_priv *hpriv)
532 unsigned int force_port_map = 0;
533 unsigned int mask_port_map = 0;
535 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
536 dev_info(&pdev->dev, "JMB361 has only one port\n");
541 * Temporary Marvell 6145 hack: PATA port presence
542 * is asserted through the standard AHCI port
543 * presence register, as bit 4 (counting from 0)
545 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
546 if (pdev->device == 0x6121)
551 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
554 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
558 static int ahci_pci_reset_controller(struct ata_host *host)
560 struct pci_dev *pdev = to_pci_dev(host->dev);
562 ahci_reset_controller(host);
564 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
565 struct ahci_host_priv *hpriv = host->private_data;
569 pci_read_config_word(pdev, 0x92, &tmp16);
570 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
571 tmp16 |= hpriv->port_map;
572 pci_write_config_word(pdev, 0x92, tmp16);
579 static void ahci_pci_init_controller(struct ata_host *host)
581 struct ahci_host_priv *hpriv = host->private_data;
582 struct pci_dev *pdev = to_pci_dev(host->dev);
583 void __iomem *port_mmio;
587 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
588 if (pdev->device == 0x6121)
592 port_mmio = __ahci_port_base(host, mv);
594 writel(0, port_mmio + PORT_IRQ_MASK);
597 tmp = readl(port_mmio + PORT_IRQ_STAT);
598 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
600 writel(tmp, port_mmio + PORT_IRQ_STAT);
603 ahci_init_controller(host);
606 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
607 unsigned long deadline)
609 struct ata_port *ap = link->ap;
615 ahci_stop_engine(ap);
617 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
618 deadline, &online, NULL);
620 ahci_start_engine(ap);
622 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
624 /* vt8251 doesn't clear BSY on signature FIS reception,
625 * request follow-up softreset.
627 return online ? -EAGAIN : rc;
630 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
631 unsigned long deadline)
633 struct ata_port *ap = link->ap;
634 struct ahci_port_priv *pp = ap->private_data;
635 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
636 struct ata_taskfile tf;
640 ahci_stop_engine(ap);
642 /* clear D2H reception area to properly wait for D2H FIS */
643 ata_tf_init(link->device, &tf);
645 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
647 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
648 deadline, &online, NULL);
650 ahci_start_engine(ap);
652 /* The pseudo configuration device on SIMG4726 attached to
653 * ASUS P5W-DH Deluxe doesn't send signature FIS after
654 * hardreset if no device is attached to the first downstream
655 * port && the pseudo device locks up on SRST w/ PMP==0. To
656 * work around this, wait for !BSY only briefly. If BSY isn't
657 * cleared, perform CLO and proceed to IDENTIFY (achieved by
658 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
660 * Wait for two seconds. Devices attached to downstream port
661 * which can't process the following IDENTIFY after this will
662 * have to be reset again. For most cases, this should
663 * suffice while making probing snappish enough.
666 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
669 ahci_kick_engine(ap);
675 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
677 struct ata_host *host = dev_get_drvdata(&pdev->dev);
678 struct ahci_host_priv *hpriv = host->private_data;
679 void __iomem *mmio = hpriv->mmio;
682 if (mesg.event & PM_EVENT_SUSPEND &&
683 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
685 "BIOS update required for suspend/resume\n");
689 if (mesg.event & PM_EVENT_SLEEP) {
690 /* AHCI spec rev1.1 section 8.3.3:
691 * Software must disable interrupts prior to requesting a
692 * transition of the HBA to D3 state.
694 ctl = readl(mmio + HOST_CTL);
696 writel(ctl, mmio + HOST_CTL);
697 readl(mmio + HOST_CTL); /* flush */
700 return ata_pci_device_suspend(pdev, mesg);
703 static int ahci_pci_device_resume(struct pci_dev *pdev)
705 struct ata_host *host = dev_get_drvdata(&pdev->dev);
708 rc = ata_pci_device_do_resume(pdev);
712 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
713 rc = ahci_pci_reset_controller(host);
717 ahci_pci_init_controller(host);
720 ata_host_resume(host);
726 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
731 * If the device fixup already set the dma_mask to some non-standard
732 * value, don't extend it here. This happens on STA2X11, for example.
734 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
738 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
739 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
741 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
744 "64-bit DMA enable failed\n");
749 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
751 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
754 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
757 "32-bit consistent DMA enable failed\n");
764 static void ahci_pci_print_info(struct ata_host *host)
766 struct pci_dev *pdev = to_pci_dev(host->dev);
770 pci_read_config_word(pdev, 0x0a, &cc);
771 if (cc == PCI_CLASS_STORAGE_IDE)
773 else if (cc == PCI_CLASS_STORAGE_SATA)
775 else if (cc == PCI_CLASS_STORAGE_RAID)
780 ahci_print_info(host, scc_s);
783 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
784 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
785 * support PMP and the 4726 either directly exports the device
786 * attached to the first downstream port or acts as a hardware storage
787 * controller and emulate a single ATA device (can be RAID 0/1 or some
788 * other configuration).
790 * When there's no device attached to the first downstream port of the
791 * 4726, "Config Disk" appears, which is a pseudo ATA device to
792 * configure the 4726. However, ATA emulation of the device is very
793 * lame. It doesn't send signature D2H Reg FIS after the initial
794 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
796 * The following function works around the problem by always using
797 * hardreset on the port and not depending on receiving signature FIS
798 * afterward. If signature FIS isn't received soon, ATA class is
799 * assumed without follow-up softreset.
801 static void ahci_p5wdh_workaround(struct ata_host *host)
803 static struct dmi_system_id sysids[] = {
805 .ident = "P5W DH Deluxe",
807 DMI_MATCH(DMI_SYS_VENDOR,
808 "ASUSTEK COMPUTER INC"),
809 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
814 struct pci_dev *pdev = to_pci_dev(host->dev);
816 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
817 dmi_check_system(sysids)) {
818 struct ata_port *ap = host->ports[1];
821 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
823 ap->ops = &ahci_p5wdh_ops;
824 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
828 /* only some SB600 ahci controllers can do 64bit DMA */
829 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
831 static const struct dmi_system_id sysids[] = {
833 * The oldest version known to be broken is 0901 and
834 * working is 1501 which was released on 2007-10-26.
835 * Enable 64bit DMA on 1501 and anything newer.
837 * Please read bko#9412 for more info.
840 .ident = "ASUS M2A-VM",
842 DMI_MATCH(DMI_BOARD_VENDOR,
843 "ASUSTeK Computer INC."),
844 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
846 .driver_data = "20071026", /* yyyymmdd */
849 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
852 * BIOS versions earlier than 1.5 had the Manufacturer DMI
853 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
854 * This spelling mistake was fixed in BIOS version 1.5, so
855 * 1.5 and later have the Manufacturer as
856 * "MICRO-STAR INTERNATIONAL CO.,LTD".
857 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
859 * BIOS versions earlier than 1.9 had a Board Product Name
860 * DMI field of "MS-7376". This was changed to be
861 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
862 * match on DMI_BOARD_NAME of "MS-7376".
865 .ident = "MSI K9A2 Platinum",
867 DMI_MATCH(DMI_BOARD_VENDOR,
869 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
873 * All BIOS versions for the Asus M3A support 64bit DMA.
874 * (all release versions from 0301 to 1206 were tested)
879 DMI_MATCH(DMI_BOARD_VENDOR,
880 "ASUSTeK Computer INC."),
881 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
886 const struct dmi_system_id *match;
887 int year, month, date;
890 match = dmi_first_match(sysids);
891 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
895 if (!match->driver_data)
898 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
899 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
901 if (strcmp(buf, match->driver_data) >= 0)
905 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
911 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
915 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
917 static const struct dmi_system_id broken_systems[] = {
919 .ident = "HP Compaq nx6310",
921 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
922 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
924 /* PCI slot number of the controller */
925 .driver_data = (void *)0x1FUL,
928 .ident = "HP Compaq 6720s",
930 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
931 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
933 /* PCI slot number of the controller */
934 .driver_data = (void *)0x1FUL,
937 { } /* terminate list */
939 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
942 unsigned long slot = (unsigned long)dmi->driver_data;
943 /* apply the quirk only to on-board controllers */
944 return slot == PCI_SLOT(pdev->devfn);
950 static bool ahci_broken_suspend(struct pci_dev *pdev)
952 static const struct dmi_system_id sysids[] = {
954 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
955 * to the harddisk doesn't become online after
956 * resuming from STR. Warn and fail suspend.
958 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
960 * Use dates instead of versions to match as HP is
961 * apparently recycling both product and version
964 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
969 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
970 DMI_MATCH(DMI_PRODUCT_NAME,
971 "HP Pavilion dv4 Notebook PC"),
973 .driver_data = "20090105", /* F.30 */
978 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
979 DMI_MATCH(DMI_PRODUCT_NAME,
980 "HP Pavilion dv5 Notebook PC"),
982 .driver_data = "20090506", /* F.16 */
987 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
988 DMI_MATCH(DMI_PRODUCT_NAME,
989 "HP Pavilion dv6 Notebook PC"),
991 .driver_data = "20090423", /* F.21 */
996 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
997 DMI_MATCH(DMI_PRODUCT_NAME,
998 "HP HDX18 Notebook PC"),
1000 .driver_data = "20090430", /* F.23 */
1003 * Acer eMachines G725 has the same problem. BIOS
1004 * V1.03 is known to be broken. V3.04 is known to
1005 * work. Between, there are V1.06, V2.06 and V3.03
1006 * that we don't have much idea about. For now,
1007 * blacklist anything older than V3.04.
1009 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1014 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1017 .driver_data = "20091216", /* V3.04 */
1019 { } /* terminate list */
1021 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1022 int year, month, date;
1025 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1028 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1029 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1031 return strcmp(buf, dmi->driver_data) < 0;
1034 static bool ahci_broken_online(struct pci_dev *pdev)
1036 #define ENCODE_BUSDEVFN(bus, slot, func) \
1037 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1038 static const struct dmi_system_id sysids[] = {
1040 * There are several gigabyte boards which use
1041 * SIMG5723s configured as hardware RAID. Certain
1042 * 5723 firmware revisions shipped there keep the link
1043 * online but fail to answer properly to SRST or
1044 * IDENTIFY when no device is attached downstream
1045 * causing libata to retry quite a few times leading
1046 * to excessive detection delay.
1048 * As these firmwares respond to the second reset try
1049 * with invalid device signature, considering unknown
1050 * sig as offline works around the problem acceptably.
1053 .ident = "EP45-DQ6",
1055 DMI_MATCH(DMI_BOARD_VENDOR,
1056 "Gigabyte Technology Co., Ltd."),
1057 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1059 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1062 .ident = "EP45-DS5",
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "Gigabyte Technology Co., Ltd."),
1066 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1068 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1070 { } /* terminate list */
1072 #undef ENCODE_BUSDEVFN
1073 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1079 val = (unsigned long)dmi->driver_data;
1081 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1084 #ifdef CONFIG_ATA_ACPI
1085 static void ahci_gtf_filter_workaround(struct ata_host *host)
1087 static const struct dmi_system_id sysids[] = {
1089 * Aspire 3810T issues a bunch of SATA enable commands
1090 * via _GTF including an invalid one and one which is
1091 * rejected by the device. Among the successful ones
1092 * is FPDMA non-zero offset enable which when enabled
1093 * only on the drive side leads to NCQ command
1094 * failures. Filter it out.
1097 .ident = "Aspire 3810T",
1099 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1100 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1102 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1106 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1107 unsigned int filter;
1113 filter = (unsigned long)dmi->driver_data;
1114 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1115 filter, dmi->ident);
1117 for (i = 0; i < host->n_ports; i++) {
1118 struct ata_port *ap = host->ports[i];
1119 struct ata_link *link;
1120 struct ata_device *dev;
1122 ata_for_each_link(link, ap, EDGE)
1123 ata_for_each_dev(dev, link, ALL)
1124 dev->gtf_filter |= filter;
1128 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1132 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1134 unsigned int board_id = ent->driver_data;
1135 struct ata_port_info pi = ahci_port_info[board_id];
1136 const struct ata_port_info *ppi[] = { &pi, NULL };
1137 struct device *dev = &pdev->dev;
1138 struct ahci_host_priv *hpriv;
1139 struct ata_host *host;
1141 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1145 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1147 ata_print_version_once(&pdev->dev, DRV_VERSION);
1149 /* The AHCI driver can only drive the SATA ports, the PATA driver
1150 can drive them all so if both drivers are selected make sure
1151 AHCI stays out of the way */
1152 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1156 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1157 * ahci, use ata_generic instead.
1159 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1160 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1161 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1162 pdev->subsystem_device == 0xcb89)
1165 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1166 * At the moment, we can only use the AHCI mode. Let the users know
1167 * that for SAS drives they're out of luck.
1169 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1170 dev_info(&pdev->dev,
1171 "PDC42819 can only drive SATA devices with this driver\n");
1173 /* Both Connext and Enmotus devices use non-standard BARs */
1174 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1175 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1176 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1177 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1179 /* acquire resources */
1180 rc = pcim_enable_device(pdev);
1184 /* AHCI controllers often implement SFF compatible interface.
1185 * Grab all PCI BARs just in case.
1187 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1189 pcim_pin_device(pdev);
1193 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1194 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1197 /* ICH6s share the same PCI ID for both piix and ahci
1198 * modes. Enabling ahci mode while MAP indicates
1199 * combined mode is a bad idea. Yield to ata_piix.
1201 pci_read_config_byte(pdev, ICH_MAP, &map);
1203 dev_info(&pdev->dev,
1204 "controller is in combined mode, can't enable AHCI mode\n");
1209 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1212 hpriv->flags |= (unsigned long)pi.private_data;
1214 /* MCP65 revision A1 and A2 can't do MSI */
1215 if (board_id == board_ahci_mcp65 &&
1216 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1217 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1219 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1220 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1221 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1223 /* only some SB600s can do 64bit DMA */
1224 if (ahci_sb600_enable_64bit(pdev))
1225 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1227 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1230 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1232 /* save initial config */
1233 ahci_pci_save_initial_config(pdev, hpriv);
1236 if (hpriv->cap & HOST_CAP_NCQ) {
1237 pi.flags |= ATA_FLAG_NCQ;
1239 * Auto-activate optimization is supposed to be
1240 * supported on all AHCI controllers indicating NCQ
1241 * capability, but it seems to be broken on some
1242 * chipsets including NVIDIAs.
1244 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1245 pi.flags |= ATA_FLAG_FPDMA_AA;
1248 if (hpriv->cap & HOST_CAP_PMP)
1249 pi.flags |= ATA_FLAG_PMP;
1251 ahci_set_em_messages(hpriv, &pi);
1253 if (ahci_broken_system_poweroff(pdev)) {
1254 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1255 dev_info(&pdev->dev,
1256 "quirky BIOS, skipping spindown on poweroff\n");
1259 if (ahci_broken_suspend(pdev)) {
1260 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1261 dev_warn(&pdev->dev,
1262 "BIOS update required for suspend/resume\n");
1265 if (ahci_broken_online(pdev)) {
1266 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1267 dev_info(&pdev->dev,
1268 "online status unreliable, applying workaround\n");
1271 /* CAP.NP sometimes indicate the index of the last enabled
1272 * port, at other times, that of the last possible port, so
1273 * determining the maximum port number requires looking at
1274 * both CAP.NP and port_map.
1276 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1278 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1281 host->private_data = hpriv;
1283 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1284 host->flags |= ATA_HOST_PARALLEL_SCAN;
1286 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1288 if (pi.flags & ATA_FLAG_EM)
1289 ahci_reset_em(host);
1291 for (i = 0; i < host->n_ports; i++) {
1292 struct ata_port *ap = host->ports[i];
1294 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1295 ata_port_pbar_desc(ap, ahci_pci_bar,
1296 0x100 + ap->port_no * 0x80, "port");
1298 /* set enclosure management message type */
1299 if (ap->flags & ATA_FLAG_EM)
1300 ap->em_message_type = hpriv->em_msg_type;
1303 /* disabled/not-implemented port */
1304 if (!(hpriv->port_map & (1 << i)))
1305 ap->ops = &ata_dummy_port_ops;
1308 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1309 ahci_p5wdh_workaround(host);
1311 /* apply gtf filter quirk */
1312 ahci_gtf_filter_workaround(host);
1314 /* initialize adapter */
1315 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1319 rc = ahci_pci_reset_controller(host);
1323 ahci_pci_init_controller(host);
1324 ahci_pci_print_info(host);
1326 pci_set_master(pdev);
1327 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1331 static int __init ahci_init(void)
1333 return pci_register_driver(&ahci_pci_driver);
1336 static void __exit ahci_exit(void)
1338 pci_unregister_driver(&ahci_pci_driver);
1342 MODULE_AUTHOR("Jeff Garzik");
1343 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1344 MODULE_LICENSE("GPL");
1345 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1346 MODULE_VERSION(DRV_VERSION);
1348 module_init(ahci_init);
1349 module_exit(ahci_exit);