2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
76 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
86 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
95 static int ahci_pci_device_resume(struct pci_dev *pdev);
98 static struct scsi_host_template ahci_sht = {
102 static struct ata_port_operations ahci_vt8251_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_vt8251_hardreset,
107 static struct ata_port_operations ahci_p5wdh_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_p5wdh_hardreset,
112 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114 static struct ata_port_operations ahci_avn_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_avn_hardreset,
119 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] =
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_nomsi] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_noncq] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_nosntf] =
152 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
158 [board_ahci_yes_fbs] =
160 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_avn_ops,
175 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_ops,
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = /* for SB700 and SB800 */
219 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
225 [board_ahci_vt8251] =
227 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_vt8251_ops,
235 static const struct pci_device_id ahci_pci_tbl[] = {
237 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
238 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
239 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
240 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
241 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
242 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
243 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
245 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
246 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
247 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
249 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
250 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
251 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
252 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
256 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
265 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
266 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
268 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
269 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
270 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
275 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
276 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
298 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
299 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
301 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
302 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
303 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
304 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
305 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
306 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
307 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
308 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
309 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
310 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
312 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
314 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
316 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
321 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
322 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
323 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
324 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
325 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
331 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
332 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
333 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
340 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
341 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
346 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
350 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
354 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
356 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
357 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
358 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
363 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
364 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
368 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
369 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
370 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
371 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
372 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
373 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
374 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
375 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
376 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
377 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
378 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
379 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
381 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
386 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
389 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
390 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
391 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
392 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
393 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
394 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
399 /* JMicron 362B and 362C have an AHCI function with IDE class code */
400 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
401 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
404 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
405 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
406 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
408 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
409 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
410 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
413 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
414 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
415 /* AMD is using RAID class only for ahci controllers */
416 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
417 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
420 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
421 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
424 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
455 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
456 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
457 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
458 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
459 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
460 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
502 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
503 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
505 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
506 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
507 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
510 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
511 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
512 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
514 /* ST Microelectronics */
515 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
518 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
519 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
521 .class = PCI_CLASS_STORAGE_SATA_AHCI,
522 .class_mask = 0xffffff,
523 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
526 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
527 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
532 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
534 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
536 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
542 .driver_data = board_ahci_yes_fbs },
543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
544 .driver_data = board_ahci_yes_fbs },
545 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
546 .driver_data = board_ahci_yes_fbs },
547 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
548 .driver_data = board_ahci_yes_fbs },
551 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
552 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
555 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
556 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
557 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
558 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
561 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
562 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
564 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
565 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
568 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
570 /* Generic, PCI class code for AHCI */
571 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
572 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
574 { } /* terminate list */
578 static struct pci_driver ahci_pci_driver = {
580 .id_table = ahci_pci_tbl,
581 .probe = ahci_init_one,
582 .remove = ata_pci_remove_one,
584 .suspend = ahci_pci_device_suspend,
585 .resume = ahci_pci_device_resume,
589 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
590 static int marvell_enable;
592 static int marvell_enable = 1;
594 module_param(marvell_enable, int, 0644);
595 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
598 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
599 struct ahci_host_priv *hpriv)
601 unsigned int force_port_map = 0;
602 unsigned int mask_port_map = 0;
604 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
605 dev_info(&pdev->dev, "JMB361 has only one port\n");
610 * Temporary Marvell 6145 hack: PATA port presence
611 * is asserted through the standard AHCI port
612 * presence register, as bit 4 (counting from 0)
614 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
615 if (pdev->device == 0x6121)
620 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
623 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
627 static int ahci_pci_reset_controller(struct ata_host *host)
629 struct pci_dev *pdev = to_pci_dev(host->dev);
631 ahci_reset_controller(host);
633 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
634 struct ahci_host_priv *hpriv = host->private_data;
638 pci_read_config_word(pdev, 0x92, &tmp16);
639 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
640 tmp16 |= hpriv->port_map;
641 pci_write_config_word(pdev, 0x92, tmp16);
648 static void ahci_pci_init_controller(struct ata_host *host)
650 struct ahci_host_priv *hpriv = host->private_data;
651 struct pci_dev *pdev = to_pci_dev(host->dev);
652 void __iomem *port_mmio;
656 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
657 if (pdev->device == 0x6121)
661 port_mmio = __ahci_port_base(host, mv);
663 writel(0, port_mmio + PORT_IRQ_MASK);
666 tmp = readl(port_mmio + PORT_IRQ_STAT);
667 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
669 writel(tmp, port_mmio + PORT_IRQ_STAT);
672 ahci_init_controller(host);
675 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
676 unsigned long deadline)
678 struct ata_port *ap = link->ap;
684 ahci_stop_engine(ap);
686 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
687 deadline, &online, NULL);
689 ahci_start_engine(ap);
691 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
693 /* vt8251 doesn't clear BSY on signature FIS reception,
694 * request follow-up softreset.
696 return online ? -EAGAIN : rc;
699 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
700 unsigned long deadline)
702 struct ata_port *ap = link->ap;
703 struct ahci_port_priv *pp = ap->private_data;
704 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
705 struct ata_taskfile tf;
709 ahci_stop_engine(ap);
711 /* clear D2H reception area to properly wait for D2H FIS */
712 ata_tf_init(link->device, &tf);
714 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
716 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
717 deadline, &online, NULL);
719 ahci_start_engine(ap);
721 /* The pseudo configuration device on SIMG4726 attached to
722 * ASUS P5W-DH Deluxe doesn't send signature FIS after
723 * hardreset if no device is attached to the first downstream
724 * port && the pseudo device locks up on SRST w/ PMP==0. To
725 * work around this, wait for !BSY only briefly. If BSY isn't
726 * cleared, perform CLO and proceed to IDENTIFY (achieved by
727 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
729 * Wait for two seconds. Devices attached to downstream port
730 * which can't process the following IDENTIFY after this will
731 * have to be reset again. For most cases, this should
732 * suffice while making probing snappish enough.
735 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
738 ahci_kick_engine(ap);
744 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
746 * It has been observed with some SSDs that the timing of events in the
747 * link synchronization phase can leave the port in a state that can not
748 * be recovered by a SATA-hard-reset alone. The failing signature is
749 * SStatus.DET stuck at 1 ("Device presence detected but Phy
750 * communication not established"). It was found that unloading and
751 * reloading the driver when this problem occurs allows the drive
752 * connection to be recovered (DET advanced to 0x3). The critical
753 * component of reloading the driver is that the port state machines are
754 * reset by bouncing "port enable" in the AHCI PCS configuration
755 * register. So, reproduce that effect by bouncing a port whenever we
756 * see DET==1 after a reset.
758 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
759 unsigned long deadline)
761 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
762 struct ata_port *ap = link->ap;
763 struct ahci_port_priv *pp = ap->private_data;
764 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
765 unsigned long tmo = deadline - jiffies;
766 struct ata_taskfile tf;
772 ahci_stop_engine(ap);
774 for (i = 0; i < 2; i++) {
777 int port = ap->port_no;
778 struct ata_host *host = ap->host;
779 struct pci_dev *pdev = to_pci_dev(host->dev);
781 /* clear D2H reception area to properly wait for D2H FIS */
782 ata_tf_init(link->device, &tf);
783 tf.command = ATA_BUSY;
784 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
786 rc = sata_link_hardreset(link, timing, deadline, &online,
789 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
790 (sstatus & 0xf) != 1)
793 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
796 pci_read_config_word(pdev, 0x92, &val);
798 pci_write_config_word(pdev, 0x92, val);
799 ata_msleep(ap, 1000);
801 pci_write_config_word(pdev, 0x92, val);
805 ahci_start_engine(ap);
808 *class = ahci_dev_classify(ap);
810 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
816 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
818 struct ata_host *host = dev_get_drvdata(&pdev->dev);
819 struct ahci_host_priv *hpriv = host->private_data;
820 void __iomem *mmio = hpriv->mmio;
823 if (mesg.event & PM_EVENT_SUSPEND &&
824 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
826 "BIOS update required for suspend/resume\n");
830 if (mesg.event & PM_EVENT_SLEEP) {
831 /* AHCI spec rev1.1 section 8.3.3:
832 * Software must disable interrupts prior to requesting a
833 * transition of the HBA to D3 state.
835 ctl = readl(mmio + HOST_CTL);
837 writel(ctl, mmio + HOST_CTL);
838 readl(mmio + HOST_CTL); /* flush */
841 return ata_pci_device_suspend(pdev, mesg);
844 static int ahci_pci_device_resume(struct pci_dev *pdev)
846 struct ata_host *host = dev_get_drvdata(&pdev->dev);
849 rc = ata_pci_device_do_resume(pdev);
853 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
854 rc = ahci_pci_reset_controller(host);
858 ahci_pci_init_controller(host);
861 ata_host_resume(host);
867 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
872 * If the device fixup already set the dma_mask to some non-standard
873 * value, don't extend it here. This happens on STA2X11, for example.
875 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
879 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
880 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
882 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
885 "64-bit DMA enable failed\n");
890 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
892 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
895 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
898 "32-bit consistent DMA enable failed\n");
905 static void ahci_pci_print_info(struct ata_host *host)
907 struct pci_dev *pdev = to_pci_dev(host->dev);
911 pci_read_config_word(pdev, 0x0a, &cc);
912 if (cc == PCI_CLASS_STORAGE_IDE)
914 else if (cc == PCI_CLASS_STORAGE_SATA)
916 else if (cc == PCI_CLASS_STORAGE_RAID)
921 ahci_print_info(host, scc_s);
924 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
925 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
926 * support PMP and the 4726 either directly exports the device
927 * attached to the first downstream port or acts as a hardware storage
928 * controller and emulate a single ATA device (can be RAID 0/1 or some
929 * other configuration).
931 * When there's no device attached to the first downstream port of the
932 * 4726, "Config Disk" appears, which is a pseudo ATA device to
933 * configure the 4726. However, ATA emulation of the device is very
934 * lame. It doesn't send signature D2H Reg FIS after the initial
935 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
937 * The following function works around the problem by always using
938 * hardreset on the port and not depending on receiving signature FIS
939 * afterward. If signature FIS isn't received soon, ATA class is
940 * assumed without follow-up softreset.
942 static void ahci_p5wdh_workaround(struct ata_host *host)
944 static struct dmi_system_id sysids[] = {
946 .ident = "P5W DH Deluxe",
948 DMI_MATCH(DMI_SYS_VENDOR,
949 "ASUSTEK COMPUTER INC"),
950 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
955 struct pci_dev *pdev = to_pci_dev(host->dev);
957 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
958 dmi_check_system(sysids)) {
959 struct ata_port *ap = host->ports[1];
962 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
964 ap->ops = &ahci_p5wdh_ops;
965 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
969 /* only some SB600 ahci controllers can do 64bit DMA */
970 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
972 static const struct dmi_system_id sysids[] = {
974 * The oldest version known to be broken is 0901 and
975 * working is 1501 which was released on 2007-10-26.
976 * Enable 64bit DMA on 1501 and anything newer.
978 * Please read bko#9412 for more info.
981 .ident = "ASUS M2A-VM",
983 DMI_MATCH(DMI_BOARD_VENDOR,
984 "ASUSTeK Computer INC."),
985 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
987 .driver_data = "20071026", /* yyyymmdd */
990 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
993 * BIOS versions earlier than 1.5 had the Manufacturer DMI
994 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
995 * This spelling mistake was fixed in BIOS version 1.5, so
996 * 1.5 and later have the Manufacturer as
997 * "MICRO-STAR INTERNATIONAL CO.,LTD".
998 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1000 * BIOS versions earlier than 1.9 had a Board Product Name
1001 * DMI field of "MS-7376". This was changed to be
1002 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1003 * match on DMI_BOARD_NAME of "MS-7376".
1006 .ident = "MSI K9A2 Platinum",
1008 DMI_MATCH(DMI_BOARD_VENDOR,
1009 "MICRO-STAR INTER"),
1010 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1014 * All BIOS versions for the Asus M3A support 64bit DMA.
1015 * (all release versions from 0301 to 1206 were tested)
1018 .ident = "ASUS M3A",
1020 DMI_MATCH(DMI_BOARD_VENDOR,
1021 "ASUSTeK Computer INC."),
1022 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1027 const struct dmi_system_id *match;
1028 int year, month, date;
1031 match = dmi_first_match(sysids);
1032 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1036 if (!match->driver_data)
1039 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1040 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1042 if (strcmp(buf, match->driver_data) >= 0)
1045 dev_warn(&pdev->dev,
1046 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1052 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1056 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1058 static const struct dmi_system_id broken_systems[] = {
1060 .ident = "HP Compaq nx6310",
1062 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1065 /* PCI slot number of the controller */
1066 .driver_data = (void *)0x1FUL,
1069 .ident = "HP Compaq 6720s",
1071 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1072 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1074 /* PCI slot number of the controller */
1075 .driver_data = (void *)0x1FUL,
1078 { } /* terminate list */
1080 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1083 unsigned long slot = (unsigned long)dmi->driver_data;
1084 /* apply the quirk only to on-board controllers */
1085 return slot == PCI_SLOT(pdev->devfn);
1091 static bool ahci_broken_suspend(struct pci_dev *pdev)
1093 static const struct dmi_system_id sysids[] = {
1095 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1096 * to the harddisk doesn't become online after
1097 * resuming from STR. Warn and fail suspend.
1099 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1101 * Use dates instead of versions to match as HP is
1102 * apparently recycling both product and version
1105 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1110 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1111 DMI_MATCH(DMI_PRODUCT_NAME,
1112 "HP Pavilion dv4 Notebook PC"),
1114 .driver_data = "20090105", /* F.30 */
1119 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1120 DMI_MATCH(DMI_PRODUCT_NAME,
1121 "HP Pavilion dv5 Notebook PC"),
1123 .driver_data = "20090506", /* F.16 */
1128 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1129 DMI_MATCH(DMI_PRODUCT_NAME,
1130 "HP Pavilion dv6 Notebook PC"),
1132 .driver_data = "20090423", /* F.21 */
1137 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1138 DMI_MATCH(DMI_PRODUCT_NAME,
1139 "HP HDX18 Notebook PC"),
1141 .driver_data = "20090430", /* F.23 */
1144 * Acer eMachines G725 has the same problem. BIOS
1145 * V1.03 is known to be broken. V3.04 is known to
1146 * work. Between, there are V1.06, V2.06 and V3.03
1147 * that we don't have much idea about. For now,
1148 * blacklist anything older than V3.04.
1150 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1155 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1156 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1158 .driver_data = "20091216", /* V3.04 */
1160 { } /* terminate list */
1162 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1163 int year, month, date;
1166 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1169 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1170 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1172 return strcmp(buf, dmi->driver_data) < 0;
1175 static bool ahci_broken_online(struct pci_dev *pdev)
1177 #define ENCODE_BUSDEVFN(bus, slot, func) \
1178 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1179 static const struct dmi_system_id sysids[] = {
1181 * There are several gigabyte boards which use
1182 * SIMG5723s configured as hardware RAID. Certain
1183 * 5723 firmware revisions shipped there keep the link
1184 * online but fail to answer properly to SRST or
1185 * IDENTIFY when no device is attached downstream
1186 * causing libata to retry quite a few times leading
1187 * to excessive detection delay.
1189 * As these firmwares respond to the second reset try
1190 * with invalid device signature, considering unknown
1191 * sig as offline works around the problem acceptably.
1194 .ident = "EP45-DQ6",
1196 DMI_MATCH(DMI_BOARD_VENDOR,
1197 "Gigabyte Technology Co., Ltd."),
1198 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1200 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1203 .ident = "EP45-DS5",
1205 DMI_MATCH(DMI_BOARD_VENDOR,
1206 "Gigabyte Technology Co., Ltd."),
1207 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1209 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1211 { } /* terminate list */
1213 #undef ENCODE_BUSDEVFN
1214 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1220 val = (unsigned long)dmi->driver_data;
1222 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1225 #ifdef CONFIG_ATA_ACPI
1226 static void ahci_gtf_filter_workaround(struct ata_host *host)
1228 static const struct dmi_system_id sysids[] = {
1230 * Aspire 3810T issues a bunch of SATA enable commands
1231 * via _GTF including an invalid one and one which is
1232 * rejected by the device. Among the successful ones
1233 * is FPDMA non-zero offset enable which when enabled
1234 * only on the drive side leads to NCQ command
1235 * failures. Filter it out.
1238 .ident = "Aspire 3810T",
1240 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1241 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1243 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1247 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1248 unsigned int filter;
1254 filter = (unsigned long)dmi->driver_data;
1255 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1256 filter, dmi->ident);
1258 for (i = 0; i < host->n_ports; i++) {
1259 struct ata_port *ap = host->ports[i];
1260 struct ata_link *link;
1261 struct ata_device *dev;
1263 ata_for_each_link(link, ap, EDGE)
1264 ata_for_each_dev(dev, link, ALL)
1265 dev->gtf_filter |= filter;
1269 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1274 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1275 * as DUMMY, or detected but eventually get a "link down" and never get up
1276 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1277 * port_map may hold a value of 0x00.
1279 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1280 * and can significantly reduce the occurrence of the problem.
1282 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1284 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1285 struct pci_dev *pdev)
1287 static const struct dmi_system_id sysids[] = {
1289 .ident = "Acer Switch Alpha 12",
1291 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1292 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1298 if (dmi_check_system(sysids)) {
1299 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1300 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1301 hpriv->port_map = 0x7;
1302 hpriv->cap = 0xC734FF02;
1307 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1309 unsigned int board_id = ent->driver_data;
1310 struct ata_port_info pi = ahci_port_info[board_id];
1311 const struct ata_port_info *ppi[] = { &pi, NULL };
1312 struct device *dev = &pdev->dev;
1313 struct ahci_host_priv *hpriv;
1314 struct ata_host *host;
1316 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1320 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1322 ata_print_version_once(&pdev->dev, DRV_VERSION);
1324 /* The AHCI driver can only drive the SATA ports, the PATA driver
1325 can drive them all so if both drivers are selected make sure
1326 AHCI stays out of the way */
1327 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1331 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1332 * ahci, use ata_generic instead.
1334 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1335 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1336 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1337 pdev->subsystem_device == 0xcb89)
1340 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1341 * At the moment, we can only use the AHCI mode. Let the users know
1342 * that for SAS drives they're out of luck.
1344 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1345 dev_info(&pdev->dev,
1346 "PDC42819 can only drive SATA devices with this driver\n");
1348 /* Both Connext and Enmotus devices use non-standard BARs */
1349 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1350 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1351 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1352 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1354 /* acquire resources */
1355 rc = pcim_enable_device(pdev);
1359 /* AHCI controllers often implement SFF compatible interface.
1360 * Grab all PCI BARs just in case.
1362 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1364 pcim_pin_device(pdev);
1368 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1369 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1372 /* ICH6s share the same PCI ID for both piix and ahci
1373 * modes. Enabling ahci mode while MAP indicates
1374 * combined mode is a bad idea. Yield to ata_piix.
1376 pci_read_config_byte(pdev, ICH_MAP, &map);
1378 dev_info(&pdev->dev,
1379 "controller is in combined mode, can't enable AHCI mode\n");
1384 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1387 hpriv->flags |= (unsigned long)pi.private_data;
1389 /* MCP65 revision A1 and A2 can't do MSI */
1390 if (board_id == board_ahci_mcp65 &&
1391 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1392 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1394 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1395 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1396 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1398 /* only some SB600s can do 64bit DMA */
1399 if (ahci_sb600_enable_64bit(pdev))
1400 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1402 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1405 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1407 /* save initial config */
1408 ahci_pci_save_initial_config(pdev, hpriv);
1411 if (hpriv->cap & HOST_CAP_NCQ) {
1412 pi.flags |= ATA_FLAG_NCQ;
1414 * Auto-activate optimization is supposed to be
1415 * supported on all AHCI controllers indicating NCQ
1416 * capability, but it seems to be broken on some
1417 * chipsets including NVIDIAs.
1419 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1420 pi.flags |= ATA_FLAG_FPDMA_AA;
1423 if (hpriv->cap & HOST_CAP_PMP)
1424 pi.flags |= ATA_FLAG_PMP;
1426 ahci_set_em_messages(hpriv, &pi);
1428 if (ahci_broken_system_poweroff(pdev)) {
1429 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1430 dev_info(&pdev->dev,
1431 "quirky BIOS, skipping spindown on poweroff\n");
1434 if (ahci_broken_suspend(pdev)) {
1435 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1436 dev_warn(&pdev->dev,
1437 "BIOS update required for suspend/resume\n");
1440 if (ahci_broken_online(pdev)) {
1441 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1442 dev_info(&pdev->dev,
1443 "online status unreliable, applying workaround\n");
1447 /* Acer SA5-271 workaround modifies private_data */
1448 acer_sa5_271_workaround(hpriv, pdev);
1450 /* CAP.NP sometimes indicate the index of the last enabled
1451 * port, at other times, that of the last possible port, so
1452 * determining the maximum port number requires looking at
1453 * both CAP.NP and port_map.
1455 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1457 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1460 host->private_data = hpriv;
1462 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1463 host->flags |= ATA_HOST_PARALLEL_SCAN;
1465 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1467 if (pi.flags & ATA_FLAG_EM)
1468 ahci_reset_em(host);
1470 for (i = 0; i < host->n_ports; i++) {
1471 struct ata_port *ap = host->ports[i];
1473 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1474 ata_port_pbar_desc(ap, ahci_pci_bar,
1475 0x100 + ap->port_no * 0x80, "port");
1477 /* set enclosure management message type */
1478 if (ap->flags & ATA_FLAG_EM)
1479 ap->em_message_type = hpriv->em_msg_type;
1482 /* disabled/not-implemented port */
1483 if (!(hpriv->port_map & (1 << i)))
1484 ap->ops = &ata_dummy_port_ops;
1487 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1488 ahci_p5wdh_workaround(host);
1490 /* apply gtf filter quirk */
1491 ahci_gtf_filter_workaround(host);
1493 /* initialize adapter */
1494 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1498 rc = ahci_pci_reset_controller(host);
1502 ahci_pci_init_controller(host);
1503 ahci_pci_print_info(host);
1505 pci_set_master(pdev);
1506 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1510 static int __init ahci_init(void)
1512 return pci_register_driver(&ahci_pci_driver);
1515 static void __exit ahci_exit(void)
1517 pci_unregister_driver(&ahci_pci_driver);
1521 MODULE_AUTHOR("Jeff Garzik");
1522 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1523 MODULE_LICENSE("GPL");
1524 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1525 MODULE_VERSION(DRV_VERSION);
1527 module_init(ahci_init);
1528 module_exit(ahci_exit);