2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 static struct scsi_host_template ahci_sht = {
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
108 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
110 static const struct ata_port_info ahci_port_info[] = {
114 .flags = AHCI_FLAG_COMMON,
115 .pio_mask = ATA_PIO4,
116 .udma_mask = ATA_UDMA6,
117 .port_ops = &ahci_ops,
119 [board_ahci_ign_iferr] =
121 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
122 .flags = AHCI_FLAG_COMMON,
123 .pio_mask = ATA_PIO4,
124 .udma_mask = ATA_UDMA6,
125 .port_ops = &ahci_ops,
127 [board_ahci_noncq] = {
128 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_nosntf] =
136 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
142 [board_ahci_yes_fbs] =
144 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
155 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
178 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
179 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
180 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
188 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
189 AHCI_HFLAG_32BIT_ONLY),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_sb700] = /* for SB700 and SB800 */
197 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_pmp_retry_srst_ops,
203 [board_ahci_vt8251] =
205 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
206 .flags = AHCI_FLAG_COMMON,
207 .pio_mask = ATA_PIO4,
208 .udma_mask = ATA_UDMA6,
209 .port_ops = &ahci_vt8251_ops,
213 static const struct pci_device_id ahci_pci_tbl[] = {
215 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
216 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
217 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
218 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
219 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
220 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
221 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
223 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
224 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
225 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
227 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
228 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
229 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
230 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
234 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
235 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
239 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
241 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
242 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
243 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
244 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
246 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
247 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
249 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
252 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
253 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
254 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
256 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
257 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
260 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
261 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
262 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
264 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
265 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
266 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
268 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
270 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
271 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
272 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
274 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
275 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
277 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
278 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
279 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
280 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
281 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
282 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
283 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
285 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
286 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
287 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
288 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
289 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
290 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
291 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
298 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
299 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
302 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
303 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
306 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
308 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
310 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
311 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
312 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
313 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
319 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
320 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
321 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
324 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
325 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
326 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
333 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
334 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
335 /* AMD is using RAID class only for ahci controllers */
336 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
337 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
340 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
341 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
344 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
430 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
431 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
432 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
434 /* ST Microelectronics */
435 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
438 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
439 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
441 .class = PCI_CLASS_STORAGE_SATA_AHCI,
442 .class_mask = 0xffffff,
443 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
446 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
447 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
448 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
450 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
452 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
454 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
455 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
456 .driver_data = board_ahci_yes_fbs },
457 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
458 .driver_data = board_ahci_yes_fbs },
461 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
464 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
465 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
466 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
467 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
470 * Samsung SSDs found on some macbooks. NCQ times out.
471 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
473 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
476 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
478 /* Generic, PCI class code for AHCI */
479 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
480 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
482 { } /* terminate list */
486 static struct pci_driver ahci_pci_driver = {
488 .id_table = ahci_pci_tbl,
489 .probe = ahci_init_one,
490 .remove = ata_pci_remove_one,
492 .suspend = ahci_pci_device_suspend,
493 .resume = ahci_pci_device_resume,
497 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
498 static int marvell_enable;
500 static int marvell_enable = 1;
502 module_param(marvell_enable, int, 0644);
503 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
506 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
507 struct ahci_host_priv *hpriv)
509 unsigned int force_port_map = 0;
510 unsigned int mask_port_map = 0;
512 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
513 dev_info(&pdev->dev, "JMB361 has only one port\n");
518 * Temporary Marvell 6145 hack: PATA port presence
519 * is asserted through the standard AHCI port
520 * presence register, as bit 4 (counting from 0)
522 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
523 if (pdev->device == 0x6121)
528 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
531 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
535 static int ahci_pci_reset_controller(struct ata_host *host)
537 struct pci_dev *pdev = to_pci_dev(host->dev);
539 ahci_reset_controller(host);
541 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
542 struct ahci_host_priv *hpriv = host->private_data;
546 pci_read_config_word(pdev, 0x92, &tmp16);
547 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
548 tmp16 |= hpriv->port_map;
549 pci_write_config_word(pdev, 0x92, tmp16);
556 static void ahci_pci_init_controller(struct ata_host *host)
558 struct ahci_host_priv *hpriv = host->private_data;
559 struct pci_dev *pdev = to_pci_dev(host->dev);
560 void __iomem *port_mmio;
564 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
565 if (pdev->device == 0x6121)
569 port_mmio = __ahci_port_base(host, mv);
571 writel(0, port_mmio + PORT_IRQ_MASK);
574 tmp = readl(port_mmio + PORT_IRQ_STAT);
575 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
577 writel(tmp, port_mmio + PORT_IRQ_STAT);
580 ahci_init_controller(host);
583 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
584 unsigned long deadline)
586 struct ata_port *ap = link->ap;
592 ahci_stop_engine(ap);
594 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
595 deadline, &online, NULL);
597 ahci_start_engine(ap);
599 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
601 /* vt8251 doesn't clear BSY on signature FIS reception,
602 * request follow-up softreset.
604 return online ? -EAGAIN : rc;
607 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
608 unsigned long deadline)
610 struct ata_port *ap = link->ap;
611 struct ahci_port_priv *pp = ap->private_data;
612 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
613 struct ata_taskfile tf;
617 ahci_stop_engine(ap);
619 /* clear D2H reception area to properly wait for D2H FIS */
620 ata_tf_init(link->device, &tf);
622 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
624 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
625 deadline, &online, NULL);
627 ahci_start_engine(ap);
629 /* The pseudo configuration device on SIMG4726 attached to
630 * ASUS P5W-DH Deluxe doesn't send signature FIS after
631 * hardreset if no device is attached to the first downstream
632 * port && the pseudo device locks up on SRST w/ PMP==0. To
633 * work around this, wait for !BSY only briefly. If BSY isn't
634 * cleared, perform CLO and proceed to IDENTIFY (achieved by
635 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
637 * Wait for two seconds. Devices attached to downstream port
638 * which can't process the following IDENTIFY after this will
639 * have to be reset again. For most cases, this should
640 * suffice while making probing snappish enough.
643 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
646 ahci_kick_engine(ap);
652 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
654 struct ata_host *host = dev_get_drvdata(&pdev->dev);
655 struct ahci_host_priv *hpriv = host->private_data;
656 void __iomem *mmio = hpriv->mmio;
659 if (mesg.event & PM_EVENT_SUSPEND &&
660 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
662 "BIOS update required for suspend/resume\n");
666 if (mesg.event & PM_EVENT_SLEEP) {
667 /* AHCI spec rev1.1 section 8.3.3:
668 * Software must disable interrupts prior to requesting a
669 * transition of the HBA to D3 state.
671 ctl = readl(mmio + HOST_CTL);
673 writel(ctl, mmio + HOST_CTL);
674 readl(mmio + HOST_CTL); /* flush */
677 return ata_pci_device_suspend(pdev, mesg);
680 static int ahci_pci_device_resume(struct pci_dev *pdev)
682 struct ata_host *host = dev_get_drvdata(&pdev->dev);
685 rc = ata_pci_device_do_resume(pdev);
689 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
690 rc = ahci_pci_reset_controller(host);
694 ahci_pci_init_controller(host);
697 ata_host_resume(host);
703 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
708 * If the device fixup already set the dma_mask to some non-standard
709 * value, don't extend it here. This happens on STA2X11, for example.
711 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
715 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
716 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
718 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
721 "64-bit DMA enable failed\n");
726 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
728 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
731 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
734 "32-bit consistent DMA enable failed\n");
741 static void ahci_pci_print_info(struct ata_host *host)
743 struct pci_dev *pdev = to_pci_dev(host->dev);
747 pci_read_config_word(pdev, 0x0a, &cc);
748 if (cc == PCI_CLASS_STORAGE_IDE)
750 else if (cc == PCI_CLASS_STORAGE_SATA)
752 else if (cc == PCI_CLASS_STORAGE_RAID)
757 ahci_print_info(host, scc_s);
760 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
761 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
762 * support PMP and the 4726 either directly exports the device
763 * attached to the first downstream port or acts as a hardware storage
764 * controller and emulate a single ATA device (can be RAID 0/1 or some
765 * other configuration).
767 * When there's no device attached to the first downstream port of the
768 * 4726, "Config Disk" appears, which is a pseudo ATA device to
769 * configure the 4726. However, ATA emulation of the device is very
770 * lame. It doesn't send signature D2H Reg FIS after the initial
771 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
773 * The following function works around the problem by always using
774 * hardreset on the port and not depending on receiving signature FIS
775 * afterward. If signature FIS isn't received soon, ATA class is
776 * assumed without follow-up softreset.
778 static void ahci_p5wdh_workaround(struct ata_host *host)
780 static struct dmi_system_id sysids[] = {
782 .ident = "P5W DH Deluxe",
784 DMI_MATCH(DMI_SYS_VENDOR,
785 "ASUSTEK COMPUTER INC"),
786 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
791 struct pci_dev *pdev = to_pci_dev(host->dev);
793 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
794 dmi_check_system(sysids)) {
795 struct ata_port *ap = host->ports[1];
798 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
800 ap->ops = &ahci_p5wdh_ops;
801 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
805 /* only some SB600 ahci controllers can do 64bit DMA */
806 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
808 static const struct dmi_system_id sysids[] = {
810 * The oldest version known to be broken is 0901 and
811 * working is 1501 which was released on 2007-10-26.
812 * Enable 64bit DMA on 1501 and anything newer.
814 * Please read bko#9412 for more info.
817 .ident = "ASUS M2A-VM",
819 DMI_MATCH(DMI_BOARD_VENDOR,
820 "ASUSTeK Computer INC."),
821 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
823 .driver_data = "20071026", /* yyyymmdd */
826 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
829 * BIOS versions earlier than 1.5 had the Manufacturer DMI
830 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
831 * This spelling mistake was fixed in BIOS version 1.5, so
832 * 1.5 and later have the Manufacturer as
833 * "MICRO-STAR INTERNATIONAL CO.,LTD".
834 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
836 * BIOS versions earlier than 1.9 had a Board Product Name
837 * DMI field of "MS-7376". This was changed to be
838 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
839 * match on DMI_BOARD_NAME of "MS-7376".
842 .ident = "MSI K9A2 Platinum",
844 DMI_MATCH(DMI_BOARD_VENDOR,
846 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
850 * All BIOS versions for the Asus M3A support 64bit DMA.
851 * (all release versions from 0301 to 1206 were tested)
856 DMI_MATCH(DMI_BOARD_VENDOR,
857 "ASUSTeK Computer INC."),
858 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
863 const struct dmi_system_id *match;
864 int year, month, date;
867 match = dmi_first_match(sysids);
868 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
872 if (!match->driver_data)
875 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
876 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
878 if (strcmp(buf, match->driver_data) >= 0)
882 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
888 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
892 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
894 static const struct dmi_system_id broken_systems[] = {
896 .ident = "HP Compaq nx6310",
898 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
901 /* PCI slot number of the controller */
902 .driver_data = (void *)0x1FUL,
905 .ident = "HP Compaq 6720s",
907 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
908 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
910 /* PCI slot number of the controller */
911 .driver_data = (void *)0x1FUL,
914 { } /* terminate list */
916 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
919 unsigned long slot = (unsigned long)dmi->driver_data;
920 /* apply the quirk only to on-board controllers */
921 return slot == PCI_SLOT(pdev->devfn);
927 static bool ahci_broken_suspend(struct pci_dev *pdev)
929 static const struct dmi_system_id sysids[] = {
931 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
932 * to the harddisk doesn't become online after
933 * resuming from STR. Warn and fail suspend.
935 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
937 * Use dates instead of versions to match as HP is
938 * apparently recycling both product and version
941 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
946 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
947 DMI_MATCH(DMI_PRODUCT_NAME,
948 "HP Pavilion dv4 Notebook PC"),
950 .driver_data = "20090105", /* F.30 */
955 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
956 DMI_MATCH(DMI_PRODUCT_NAME,
957 "HP Pavilion dv5 Notebook PC"),
959 .driver_data = "20090506", /* F.16 */
964 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
965 DMI_MATCH(DMI_PRODUCT_NAME,
966 "HP Pavilion dv6 Notebook PC"),
968 .driver_data = "20090423", /* F.21 */
973 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
974 DMI_MATCH(DMI_PRODUCT_NAME,
975 "HP HDX18 Notebook PC"),
977 .driver_data = "20090430", /* F.23 */
980 * Acer eMachines G725 has the same problem. BIOS
981 * V1.03 is known to be broken. V3.04 is known to
982 * work. Between, there are V1.06, V2.06 and V3.03
983 * that we don't have much idea about. For now,
984 * blacklist anything older than V3.04.
986 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
991 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
994 .driver_data = "20091216", /* V3.04 */
996 { } /* terminate list */
998 const struct dmi_system_id *dmi = dmi_first_match(sysids);
999 int year, month, date;
1002 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1005 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1006 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1008 return strcmp(buf, dmi->driver_data) < 0;
1011 static bool ahci_broken_online(struct pci_dev *pdev)
1013 #define ENCODE_BUSDEVFN(bus, slot, func) \
1014 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1015 static const struct dmi_system_id sysids[] = {
1017 * There are several gigabyte boards which use
1018 * SIMG5723s configured as hardware RAID. Certain
1019 * 5723 firmware revisions shipped there keep the link
1020 * online but fail to answer properly to SRST or
1021 * IDENTIFY when no device is attached downstream
1022 * causing libata to retry quite a few times leading
1023 * to excessive detection delay.
1025 * As these firmwares respond to the second reset try
1026 * with invalid device signature, considering unknown
1027 * sig as offline works around the problem acceptably.
1030 .ident = "EP45-DQ6",
1032 DMI_MATCH(DMI_BOARD_VENDOR,
1033 "Gigabyte Technology Co., Ltd."),
1034 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1036 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1039 .ident = "EP45-DS5",
1041 DMI_MATCH(DMI_BOARD_VENDOR,
1042 "Gigabyte Technology Co., Ltd."),
1043 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1045 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1047 { } /* terminate list */
1049 #undef ENCODE_BUSDEVFN
1050 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1056 val = (unsigned long)dmi->driver_data;
1058 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1061 #ifdef CONFIG_ATA_ACPI
1062 static void ahci_gtf_filter_workaround(struct ata_host *host)
1064 static const struct dmi_system_id sysids[] = {
1066 * Aspire 3810T issues a bunch of SATA enable commands
1067 * via _GTF including an invalid one and one which is
1068 * rejected by the device. Among the successful ones
1069 * is FPDMA non-zero offset enable which when enabled
1070 * only on the drive side leads to NCQ command
1071 * failures. Filter it out.
1074 .ident = "Aspire 3810T",
1076 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1077 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1079 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1083 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1084 unsigned int filter;
1090 filter = (unsigned long)dmi->driver_data;
1091 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1092 filter, dmi->ident);
1094 for (i = 0; i < host->n_ports; i++) {
1095 struct ata_port *ap = host->ports[i];
1096 struct ata_link *link;
1097 struct ata_device *dev;
1099 ata_for_each_link(link, ap, EDGE)
1100 ata_for_each_dev(dev, link, ALL)
1101 dev->gtf_filter |= filter;
1105 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1109 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1111 unsigned int board_id = ent->driver_data;
1112 struct ata_port_info pi = ahci_port_info[board_id];
1113 const struct ata_port_info *ppi[] = { &pi, NULL };
1114 struct device *dev = &pdev->dev;
1115 struct ahci_host_priv *hpriv;
1116 struct ata_host *host;
1118 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1122 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1124 ata_print_version_once(&pdev->dev, DRV_VERSION);
1126 /* The AHCI driver can only drive the SATA ports, the PATA driver
1127 can drive them all so if both drivers are selected make sure
1128 AHCI stays out of the way */
1129 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1133 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1134 * ahci, use ata_generic instead.
1136 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1137 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1138 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1139 pdev->subsystem_device == 0xcb89)
1142 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1143 * At the moment, we can only use the AHCI mode. Let the users know
1144 * that for SAS drives they're out of luck.
1146 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1147 dev_info(&pdev->dev,
1148 "PDC42819 can only drive SATA devices with this driver\n");
1150 /* Both Connext and Enmotus devices use non-standard BARs */
1151 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1152 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1153 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1154 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1156 /* acquire resources */
1157 rc = pcim_enable_device(pdev);
1161 /* AHCI controllers often implement SFF compatible interface.
1162 * Grab all PCI BARs just in case.
1164 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1166 pcim_pin_device(pdev);
1170 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1171 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1174 /* ICH6s share the same PCI ID for both piix and ahci
1175 * modes. Enabling ahci mode while MAP indicates
1176 * combined mode is a bad idea. Yield to ata_piix.
1178 pci_read_config_byte(pdev, ICH_MAP, &map);
1180 dev_info(&pdev->dev,
1181 "controller is in combined mode, can't enable AHCI mode\n");
1186 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1189 hpriv->flags |= (unsigned long)pi.private_data;
1191 /* MCP65 revision A1 and A2 can't do MSI */
1192 if (board_id == board_ahci_mcp65 &&
1193 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1194 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1196 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1197 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1198 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1200 /* only some SB600s can do 64bit DMA */
1201 if (ahci_sb600_enable_64bit(pdev))
1202 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1204 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1207 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1209 /* save initial config */
1210 ahci_pci_save_initial_config(pdev, hpriv);
1213 if (hpriv->cap & HOST_CAP_NCQ) {
1214 pi.flags |= ATA_FLAG_NCQ;
1216 * Auto-activate optimization is supposed to be
1217 * supported on all AHCI controllers indicating NCQ
1218 * capability, but it seems to be broken on some
1219 * chipsets including NVIDIAs.
1221 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1222 pi.flags |= ATA_FLAG_FPDMA_AA;
1225 if (hpriv->cap & HOST_CAP_PMP)
1226 pi.flags |= ATA_FLAG_PMP;
1228 ahci_set_em_messages(hpriv, &pi);
1230 if (ahci_broken_system_poweroff(pdev)) {
1231 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1232 dev_info(&pdev->dev,
1233 "quirky BIOS, skipping spindown on poweroff\n");
1236 if (ahci_broken_suspend(pdev)) {
1237 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1238 dev_warn(&pdev->dev,
1239 "BIOS update required for suspend/resume\n");
1242 if (ahci_broken_online(pdev)) {
1243 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1244 dev_info(&pdev->dev,
1245 "online status unreliable, applying workaround\n");
1248 /* CAP.NP sometimes indicate the index of the last enabled
1249 * port, at other times, that of the last possible port, so
1250 * determining the maximum port number requires looking at
1251 * both CAP.NP and port_map.
1253 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1255 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1258 host->private_data = hpriv;
1260 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1261 host->flags |= ATA_HOST_PARALLEL_SCAN;
1263 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1265 if (pi.flags & ATA_FLAG_EM)
1266 ahci_reset_em(host);
1268 for (i = 0; i < host->n_ports; i++) {
1269 struct ata_port *ap = host->ports[i];
1271 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1272 ata_port_pbar_desc(ap, ahci_pci_bar,
1273 0x100 + ap->port_no * 0x80, "port");
1275 /* set enclosure management message type */
1276 if (ap->flags & ATA_FLAG_EM)
1277 ap->em_message_type = hpriv->em_msg_type;
1280 /* disabled/not-implemented port */
1281 if (!(hpriv->port_map & (1 << i)))
1282 ap->ops = &ata_dummy_port_ops;
1285 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1286 ahci_p5wdh_workaround(host);
1288 /* apply gtf filter quirk */
1289 ahci_gtf_filter_workaround(host);
1291 /* initialize adapter */
1292 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1296 rc = ahci_pci_reset_controller(host);
1300 ahci_pci_init_controller(host);
1301 ahci_pci_print_info(host);
1303 pci_set_master(pdev);
1304 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1308 static int __init ahci_init(void)
1310 return pci_register_driver(&ahci_pci_driver);
1313 static void __exit ahci_exit(void)
1315 pci_unregister_driver(&ahci_pci_driver);
1319 MODULE_AUTHOR("Jeff Garzik");
1320 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1321 MODULE_LICENSE("GPL");
1322 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1323 MODULE_VERSION(DRV_VERSION);
1325 module_init(ahci_init);
1326 module_exit(ahci_exit);