2 /*******************************************************************************
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
7 ******************************************************************************/
10 * Copyright (C) 2000 - 2012, Intel Corp.
11 * All rights reserved.
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14 * modification, are permitted provided that the following conditions
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22 * including a substantially similar Disclaimer requirement for further
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25 * of any contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
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46 #include <acpi/acpi.h>
51 #define _COMPONENT ACPI_HARDWARE
52 ACPI_MODULE_NAME("hwregs")
54 #if (!ACPI_REDUCED_HARDWARE)
55 /* Local Prototypes */
57 acpi_hw_read_multiple(u32 *value,
58 struct acpi_generic_address *register_a,
59 struct acpi_generic_address *register_b);
62 acpi_hw_write_multiple(u32 value,
63 struct acpi_generic_address *register_a,
64 struct acpi_generic_address *register_b);
66 #endif /* !ACPI_REDUCED_HARDWARE */
68 /******************************************************************************
70 * FUNCTION: acpi_hw_validate_register
72 * PARAMETERS: Reg - GAS register structure
73 * max_bit_width - Max bit_width supported (32 or 64)
74 * Address - Pointer to where the gas->address
79 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
80 * pointer, Address, space_id, bit_width, and bit_offset.
82 ******************************************************************************/
85 acpi_hw_validate_register(struct acpi_generic_address *reg,
86 u8 max_bit_width, u64 *address)
89 /* Must have a valid pointer to a GAS structure */
92 return (AE_BAD_PARAMETER);
96 * Copy the target address. This handles possible alignment issues.
97 * Address must not be null. A null address also indicates an optional
98 * ACPI register that is not supported, so no error message.
100 ACPI_MOVE_64_TO_64(address, ®->address);
102 return (AE_BAD_ADDRESS);
105 /* Validate the space_iD */
107 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
108 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
110 "Unsupported address space: 0x%X", reg->space_id));
114 /* Validate the bit_width */
116 if ((reg->bit_width != 8) &&
117 (reg->bit_width != 16) &&
118 (reg->bit_width != 32) && (reg->bit_width != max_bit_width)) {
120 "Unsupported register bit width: 0x%X",
125 /* Validate the bit_offset. Just a warning for now. */
127 if (reg->bit_offset != 0) {
128 ACPI_WARNING((AE_INFO,
129 "Unsupported register bit offset: 0x%X",
136 /******************************************************************************
138 * FUNCTION: acpi_hw_read
140 * PARAMETERS: Value - Where the value is returned
141 * Reg - GAS register structure
145 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max
146 * version of acpi_read, used internally since the overhead of
147 * 64-bit values is not needed.
149 * LIMITATIONS: <These limitations also apply to acpi_hw_write>
150 * bit_width must be exactly 8, 16, or 32.
151 * space_iD must be system_memory or system_iO.
152 * bit_offset and access_width are currently ignored, as there has
153 * not been a need to implement these.
155 ******************************************************************************/
157 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg)
162 ACPI_FUNCTION_NAME(hw_read);
164 /* Validate contents of the GAS register */
166 status = acpi_hw_validate_register(reg, 32, &address);
167 if (ACPI_FAILURE(status)) {
171 /* Initialize entire 32-bit return value to zero */
176 * Two address spaces supported: Memory or IO. PCI_Config is
177 * not supported here because the GAS structure is insufficient
179 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
180 status = acpi_os_read_memory((acpi_physical_address)
181 address, value, reg->bit_width);
182 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
184 status = acpi_hw_read_port((acpi_io_address)
185 address, value, reg->bit_width);
188 ACPI_DEBUG_PRINT((ACPI_DB_IO,
189 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n",
190 *value, reg->bit_width, ACPI_FORMAT_UINT64(address),
191 acpi_ut_get_region_name(reg->space_id)));
196 /******************************************************************************
198 * FUNCTION: acpi_hw_write
200 * PARAMETERS: Value - Value to be written
201 * Reg - GAS register structure
205 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max
206 * version of acpi_write, used internally since the overhead of
207 * 64-bit values is not needed.
209 ******************************************************************************/
211 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg)
216 ACPI_FUNCTION_NAME(hw_write);
218 /* Validate contents of the GAS register */
220 status = acpi_hw_validate_register(reg, 32, &address);
221 if (ACPI_FAILURE(status)) {
226 * Two address spaces supported: Memory or IO. PCI_Config is
227 * not supported here because the GAS structure is insufficient
229 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
230 status = acpi_os_write_memory((acpi_physical_address)
231 address, value, reg->bit_width);
232 } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
234 status = acpi_hw_write_port((acpi_io_address)
235 address, value, reg->bit_width);
238 ACPI_DEBUG_PRINT((ACPI_DB_IO,
239 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n",
240 value, reg->bit_width, ACPI_FORMAT_UINT64(address),
241 acpi_ut_get_region_name(reg->space_id)));
246 #if (!ACPI_REDUCED_HARDWARE)
247 /*******************************************************************************
249 * FUNCTION: acpi_hw_clear_acpi_status
255 * DESCRIPTION: Clears all fixed and general purpose status bits
257 ******************************************************************************/
259 acpi_status acpi_hw_clear_acpi_status(void)
262 acpi_cpu_flags lock_flags = 0;
264 ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
266 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
267 ACPI_BITMASK_ALL_FIXED_STATUS,
268 ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address)));
270 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
272 /* Clear the fixed events in PM1 A/B */
274 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
275 ACPI_BITMASK_ALL_FIXED_STATUS);
277 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
279 if (ACPI_FAILURE(status))
282 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
284 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
287 return_ACPI_STATUS(status);
290 /*******************************************************************************
292 * FUNCTION: acpi_hw_get_bit_register_info
294 * PARAMETERS: register_id - Index of ACPI Register to access
296 * RETURN: The bitmask to be used when accessing the register
298 * DESCRIPTION: Map register_id into a register bitmask.
300 ******************************************************************************/
302 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
304 ACPI_FUNCTION_ENTRY();
306 if (register_id > ACPI_BITREG_MAX) {
307 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X",
312 return (&acpi_gbl_bit_register_info[register_id]);
315 /******************************************************************************
317 * FUNCTION: acpi_hw_write_pm1_control
319 * PARAMETERS: pm1a_control - Value to be written to PM1A control
320 * pm1b_control - Value to be written to PM1B control
324 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
325 * different than than the PM1 A/B status and enable registers
326 * in that different values can be written to the A/B registers.
327 * Most notably, the SLP_TYP bits can be different, as per the
328 * values returned from the _Sx predefined methods.
330 ******************************************************************************/
332 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
336 ACPI_FUNCTION_TRACE(hw_write_pm1_control);
339 acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
340 if (ACPI_FAILURE(status)) {
341 return_ACPI_STATUS(status);
344 if (acpi_gbl_FADT.xpm1b_control_block.address) {
346 acpi_hw_write(pm1b_control,
347 &acpi_gbl_FADT.xpm1b_control_block);
349 return_ACPI_STATUS(status);
352 /******************************************************************************
354 * FUNCTION: acpi_hw_register_read
356 * PARAMETERS: register_id - ACPI Register ID
357 * return_value - Where the register value is returned
359 * RETURN: Status and the value read.
361 * DESCRIPTION: Read from the specified ACPI register
363 ******************************************************************************/
365 acpi_hw_register_read(u32 register_id, u32 * return_value)
370 ACPI_FUNCTION_TRACE(hw_register_read);
372 switch (register_id) {
373 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
375 status = acpi_hw_read_multiple(&value,
376 &acpi_gbl_xpm1a_status,
377 &acpi_gbl_xpm1b_status);
380 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
382 status = acpi_hw_read_multiple(&value,
383 &acpi_gbl_xpm1a_enable,
384 &acpi_gbl_xpm1b_enable);
387 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
389 status = acpi_hw_read_multiple(&value,
393 xpm1b_control_block);
396 * Zero the write-only bits. From the ACPI specification, "Hardware
397 * Write-Only Bits": "Upon reads to registers with write-only bits,
398 * software masks out all write-only bits."
400 value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
403 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
406 acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block);
409 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
411 status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block);
414 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
417 acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
421 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
422 status = AE_BAD_PARAMETER;
426 if (ACPI_SUCCESS(status)) {
427 *return_value = value;
430 return_ACPI_STATUS(status);
433 /******************************************************************************
435 * FUNCTION: acpi_hw_register_write
437 * PARAMETERS: register_id - ACPI Register ID
438 * Value - The value to write
442 * DESCRIPTION: Write to the specified ACPI register
444 * NOTE: In accordance with the ACPI specification, this function automatically
445 * preserves the value of the following bits, meaning that these bits cannot be
446 * changed via this interface:
448 * PM1_CONTROL[0] = SCI_EN
453 * 1) Hardware Ignored Bits: When software writes to a register with ignored
454 * bit fields, it preserves the ignored bit fields
455 * 2) SCI_EN: OSPM always preserves this bit position
457 ******************************************************************************/
459 acpi_status acpi_hw_register_write(u32 register_id, u32 value)
464 ACPI_FUNCTION_TRACE(hw_register_write);
466 switch (register_id) {
467 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
469 * Handle the "ignored" bit in PM1 Status. According to the ACPI
470 * specification, ignored bits are to be preserved when writing.
471 * Normally, this would mean a read/modify/write sequence. However,
472 * preserving a bit in the status register is different. Writing a
473 * one clears the status, and writing a zero preserves the status.
474 * Therefore, we must always write zero to the ignored bit.
476 * This behavior is clarified in the ACPI 4.0 specification.
478 value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
480 status = acpi_hw_write_multiple(value,
481 &acpi_gbl_xpm1a_status,
482 &acpi_gbl_xpm1b_status);
485 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */
487 status = acpi_hw_write_multiple(value,
488 &acpi_gbl_xpm1a_enable,
489 &acpi_gbl_xpm1b_enable);
492 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
495 * Perform a read first to preserve certain bits (per ACPI spec)
496 * Note: This includes SCI_EN, we never want to change this bit
498 status = acpi_hw_read_multiple(&read_value,
502 xpm1b_control_block);
503 if (ACPI_FAILURE(status)) {
507 /* Insert the bits to be preserved */
509 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
512 /* Now we can write the data */
514 status = acpi_hw_write_multiple(value,
518 xpm1b_control_block);
521 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
524 * For control registers, all reserved bits must be preserved,
525 * as per the ACPI spec.
528 acpi_hw_read(&read_value,
529 &acpi_gbl_FADT.xpm2_control_block);
530 if (ACPI_FAILURE(status)) {
534 /* Insert the bits to be preserved */
536 ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
540 acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block);
543 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
545 status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block);
548 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
550 /* SMI_CMD is currently always in IO space */
553 acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
557 ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
558 status = AE_BAD_PARAMETER;
563 return_ACPI_STATUS(status);
566 /******************************************************************************
568 * FUNCTION: acpi_hw_read_multiple
570 * PARAMETERS: Value - Where the register value is returned
571 * register_a - First ACPI register (required)
572 * register_b - Second ACPI register (optional)
576 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
578 ******************************************************************************/
581 acpi_hw_read_multiple(u32 *value,
582 struct acpi_generic_address *register_a,
583 struct acpi_generic_address *register_b)
589 /* The first register is always required */
591 status = acpi_hw_read(&value_a, register_a);
592 if (ACPI_FAILURE(status)) {
596 /* Second register is optional */
598 if (register_b->address) {
599 status = acpi_hw_read(&value_b, register_b);
600 if (ACPI_FAILURE(status)) {
606 * OR the two return values together. No shifting or masking is necessary,
607 * because of how the PM1 registers are defined in the ACPI specification:
609 * "Although the bits can be split between the two register blocks (each
610 * register block has a unique pointer within the FADT), the bit positions
611 * are maintained. The register block with unimplemented bits (that is,
612 * those implemented in the other register block) always returns zeros,
613 * and writes have no side effects"
615 *value = (value_a | value_b);
619 /******************************************************************************
621 * FUNCTION: acpi_hw_write_multiple
623 * PARAMETERS: Value - The value to write
624 * register_a - First ACPI register (required)
625 * register_b - Second ACPI register (optional)
629 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
631 ******************************************************************************/
634 acpi_hw_write_multiple(u32 value,
635 struct acpi_generic_address *register_a,
636 struct acpi_generic_address *register_b)
640 /* The first register is always required */
642 status = acpi_hw_write(value, register_a);
643 if (ACPI_FAILURE(status)) {
648 * Second register is optional
650 * No bit shifting or clearing is necessary, because of how the PM1
651 * registers are defined in the ACPI specification:
653 * "Although the bits can be split between the two register blocks (each
654 * register block has a unique pointer within the FADT), the bit positions
655 * are maintained. The register block with unimplemented bits (that is,
656 * those implemented in the other register block) always returns zeros,
657 * and writes have no side effects"
659 if (register_b->address) {
660 status = acpi_hw_write(value, register_b);
666 #endif /* !ACPI_REDUCED_HARDWARE */