drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, 2014, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/delay.h>
  23
  24 #include "internal.h"
  25
  26 ACPI_MODULE_NAME("acpi_lpss");
  27
  28 #ifdef CONFIG_X86_INTEL_LPSS
  29
  30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  31
  32 #define LPSS_CLK_SIZE   0x04
  33 #define LPSS_LTR_SIZE   0x18
  34
  35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  36 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  37 #define LPSS_RESETS                     0x04
  38 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  39 #define LPSS_RESETS_RESET_APB           BIT(1)
  40 #define LPSS_GENERAL                    0x08
  41 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  42 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  43 #define LPSS_SW_LTR                     0x10
  44 #define LPSS_AUTO_LTR                   0x14
  45 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  46 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  47 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  48 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  49 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  50 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  51 #define LPSS_LTR_MAX_VAL                0x3FF
  52 #define LPSS_TX_INT                     0x20
  53 #define LPSS_TX_INT_MASK                BIT(1)
  54
  55 #define LPSS_PRV_REG_COUNT              9
  56
  57 /* LPSS Flags */
  58 #define LPSS_CLK                        BIT(0)
  59 #define LPSS_CLK_GATE                   BIT(1)
  60 #define LPSS_CLK_DIVIDER                BIT(2)
  61 #define LPSS_LTR                        BIT(3)
  62 #define LPSS_SAVE_CTX                   BIT(4)
  63 #define LPSS_DEV_PROXY                  BIT(5)
  64 #define LPSS_PROXY_REQ                  BIT(6)
  65
  66 struct lpss_private_data;
  67
  68 struct lpss_device_desc {
  69         unsigned int flags;
  70         unsigned int prv_offset;
  71         size_t prv_size_override;
  72         void (*setup)(struct lpss_private_data *pdata);
  73 };
  74
  75 static struct device *proxy_device;
  76
  77 static struct lpss_device_desc lpss_dma_desc = {
  78         .flags = LPSS_CLK | LPSS_PROXY_REQ,
  79 };
  80
  81 struct lpss_private_data {
  82         void __iomem *mmio_base;
  83         resource_size_t mmio_size;
  84         unsigned int fixed_clk_rate;
  85         struct clk *clk;
  86         const struct lpss_device_desc *dev_desc;
  87         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  88 };
  89
  90 /* UART Component Parameter Register */
  91 #define LPSS_UART_CPR                   0xF4
  92 #define LPSS_UART_CPR_AFCE              BIT(4)
  93
  94 static void lpss_uart_setup(struct lpss_private_data *pdata)
  95 {
  96         unsigned int offset;
  97         u32 val;
  98
  99         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 100         val = readl(pdata->mmio_base + offset);
 101         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 102
 103         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 104         if (!(val & LPSS_UART_CPR_AFCE)) {
 105                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 106                 val = readl(pdata->mmio_base + offset);
 107                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 108                 writel(val, pdata->mmio_base + offset);
 109         }
 110 }
 111
 112 static void byt_i2c_setup(struct lpss_private_data *pdata)
 113 {
 114         unsigned int offset;
 115         u32 val;
 116
 117         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 118         val = readl(pdata->mmio_base + offset);
 119         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 120         writel(val, pdata->mmio_base + offset);
 121
 122         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 123                 pdata->fixed_clk_rate = 133000000;
 124 }
 125
 126 static struct lpss_device_desc lpt_dev_desc = {
 127         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 128         .prv_offset = 0x800,
 129 };
 130
 131 static struct lpss_device_desc lpt_i2c_dev_desc = {
 132         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 133         .prv_offset = 0x800,
 134 };
 135
 136 static struct lpss_device_desc lpt_uart_dev_desc = {
 137         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 138         .prv_offset = 0x800,
 139         .setup = lpss_uart_setup,
 140 };
 141
 142 static struct lpss_device_desc lpt_sdio_dev_desc = {
 143         .flags = LPSS_LTR,
 144         .prv_offset = 0x1000,
 145         .prv_size_override = 0x1018,
 146 };
 147
 148 static struct lpss_device_desc byt_pwm_dev_desc = {
 149         .flags = LPSS_SAVE_CTX,
 150 };
 151
 152 static struct lpss_device_desc byt_uart_dev_desc = {
 153         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
 154                  LPSS_DEV_PROXY,
 155         .prv_offset = 0x800,
 156         .setup = lpss_uart_setup,
 157 };
 158
 159 static struct lpss_device_desc byt_spi_dev_desc = {
 160         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
 161                  LPSS_DEV_PROXY,
 162         .prv_offset = 0x400,
 163 };
 164
 165 static struct lpss_device_desc byt_sdio_dev_desc = {
 166         .flags = LPSS_CLK | LPSS_DEV_PROXY,
 167 };
 168
 169 static struct lpss_device_desc byt_i2c_dev_desc = {
 170         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_DEV_PROXY,
 171         .prv_offset = 0x800,
 172         .setup = byt_i2c_setup,
 173 };
 174
 175 #else
 176
 177 #define LPSS_ADDR(desc) (0UL)
 178
 179 #endif /* CONFIG_X86_INTEL_LPSS */
 180
 181 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 182         /* Generic LPSS devices */
 183         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 184
 185         /* Lynxpoint LPSS devices */
 186         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 187         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 188         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 189         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 190         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 191         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 192         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 193         { "INT33C7", },
 194
 195         /* BayTrail LPSS devices */
 196         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 197         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 198         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 199         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 200         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 201         { "INT33B2", },
 202         { "INT33FC", },
 203
 204         /* Braswell LPSS devices */
 205         { "80862288", LPSS_ADDR(byt_pwm_dev_desc) },
 206         { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
 207         { "8086228E", LPSS_ADDR(byt_spi_dev_desc) },
 208         { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
 209
 210         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 211         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 212         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 213         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 214         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 215         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 216         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 217         { "INT3437", },
 218
 219         /* Wildcat Point LPSS devices */
 220         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 221
 222         { }
 223 };
 224
 225 #ifdef CONFIG_X86_INTEL_LPSS
 226
 227 static int is_memory(struct acpi_resource *res, void *not_used)
 228 {
 229         struct resource r;
 230         return !acpi_dev_resource_memory(res, &r);
 231 }
 232
 233 /* LPSS main clock device. */
 234 static struct platform_device *lpss_clk_dev;
 235
 236 static inline void lpt_register_clock_device(void)
 237 {
 238         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 239 }
 240
 241 static int register_device_clock(struct acpi_device *adev,
 242                                  struct lpss_private_data *pdata)
 243 {
 244         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 245         const char *devname = dev_name(&adev->dev);
 246         struct clk *clk = ERR_PTR(-ENODEV);
 247         struct lpss_clk_data *clk_data;
 248         const char *parent, *clk_name;
 249         void __iomem *prv_base;
 250
 251         if (!lpss_clk_dev)
 252                 lpt_register_clock_device();
 253
 254         clk_data = platform_get_drvdata(lpss_clk_dev);
 255         if (!clk_data)
 256                 return -ENODEV;
 257         clk = clk_data->clk;
 258
 259         if (!pdata->mmio_base
 260             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 261                 return -ENODATA;
 262
 263         parent = clk_data->name;
 264         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 265
 266         if (pdata->fixed_clk_rate) {
 267                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 268                                               pdata->fixed_clk_rate);
 269                 goto out;
 270         }
 271
 272         if (dev_desc->flags & LPSS_CLK_GATE) {
 273                 clk = clk_register_gate(NULL, devname, parent, 0,
 274                                         prv_base, 0, 0, NULL);
 275                 parent = devname;
 276         }
 277
 278         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 279                 /* Prevent division by zero */
 280                 if (!readl(prv_base))
 281                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 282
 283                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 284                 if (!clk_name)
 285                         return -ENOMEM;
 286                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 287                                                       0, prv_base,
 288                                                       1, 15, 16, 15, 0, NULL);
 289                 parent = clk_name;
 290
 291                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 292                 if (!clk_name) {
 293                         kfree(parent);
 294                         return -ENOMEM;
 295                 }
 296                 clk = clk_register_gate(NULL, clk_name, parent,
 297                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 298                                         prv_base, 31, 0, NULL);
 299                 kfree(parent);
 300                 kfree(clk_name);
 301         }
 302 out:
 303         if (IS_ERR(clk))
 304                 return PTR_ERR(clk);
 305
 306         pdata->clk = clk;
 307         clk_register_clkdev(clk, NULL, devname);
 308         return 0;
 309 }
 310
 311 static int acpi_lpss_create_device(struct acpi_device *adev,
 312                                    const struct acpi_device_id *id)
 313 {
 314         struct lpss_device_desc *dev_desc;
 315         struct lpss_private_data *pdata;
 316         struct resource_list_entry *rentry;
 317         struct list_head resource_list;
 318         struct platform_device *pdev;
 319         int ret;
 320
 321         dev_desc = (struct lpss_device_desc *)id->driver_data;
 322         if (!dev_desc) {
 323                 pdev = acpi_create_platform_device(adev);
 324                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 325         }
 326         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 327         if (!pdata)
 328                 return -ENOMEM;
 329
 330         INIT_LIST_HEAD(&resource_list);
 331         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 332         if (ret < 0)
 333                 goto err_out;
 334
 335         list_for_each_entry(rentry, &resource_list, node)
 336                 if (resource_type(&rentry->res) == IORESOURCE_MEM) {
 337                         if (dev_desc->prv_size_override)
 338                                 pdata->mmio_size = dev_desc->prv_size_override;
 339                         else
 340                                 pdata->mmio_size = resource_size(&rentry->res);
 341                         pdata->mmio_base = ioremap(rentry->res.start,
 342                                                    pdata->mmio_size);
 343                         break;
 344                 }
 345
 346         acpi_dev_free_resource_list(&resource_list);
 347
 348         pdata->dev_desc = dev_desc;
 349
 350         if (dev_desc->setup)
 351                 dev_desc->setup(pdata);
 352
 353         if (dev_desc->flags & LPSS_CLK) {
 354                 ret = register_device_clock(adev, pdata);
 355                 if (ret) {
 356                         /* Skip the device, but continue the namespace scan. */
 357                         ret = 0;
 358                         goto err_out;
 359                 }
 360         }
 361
 362         /*
 363          * This works around a known issue in ACPI tables where LPSS devices
 364          * have _PS0 and _PS3 without _PSC (and no power resources), so
 365          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 366          */
 367         ret = acpi_device_fix_up_power(adev);
 368         if (ret) {
 369                 /* Skip the device, but continue the namespace scan. */
 370                 ret = 0;
 371                 goto err_out;
 372         }
 373
 374         adev->driver_data = pdata;
 375         pdev = acpi_create_platform_device(adev);
 376         if (!IS_ERR_OR_NULL(pdev)) {
 377                 if (!proxy_device && dev_desc->flags & LPSS_DEV_PROXY)
 378                         proxy_device = &pdev->dev;
 379                 return 1;
 380         }
 381
 382         ret = PTR_ERR(pdev);
 383         adev->driver_data = NULL;
 384
 385  err_out:
 386         kfree(pdata);
 387         return ret;
 388 }
 389
 390 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 391 {
 392         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 393 }
 394
 395 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 396                              unsigned int reg)
 397 {
 398         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 399 }
 400
 401 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 402 {
 403         struct acpi_device *adev;
 404         struct lpss_private_data *pdata;
 405         unsigned long flags;
 406         int ret;
 407
 408         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 409         if (WARN_ON(ret))
 410                 return ret;
 411
 412         spin_lock_irqsave(&dev->power.lock, flags);
 413         if (pm_runtime_suspended(dev)) {
 414                 ret = -EAGAIN;
 415                 goto out;
 416         }
 417         pdata = acpi_driver_data(adev);
 418         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 419                 ret = -ENODEV;
 420                 goto out;
 421         }
 422         *val = __lpss_reg_read(pdata, reg);
 423
 424  out:
 425         spin_unlock_irqrestore(&dev->power.lock, flags);
 426         return ret;
 427 }
 428
 429 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 430                              char *buf)
 431 {
 432         u32 ltr_value = 0;
 433         unsigned int reg;
 434         int ret;
 435
 436         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 437         ret = lpss_reg_read(dev, reg, &ltr_value);
 438         if (ret)
 439                 return ret;
 440
 441         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 442 }
 443
 444 static ssize_t lpss_ltr_mode_show(struct device *dev,
 445                                   struct device_attribute *attr, char *buf)
 446 {
 447         u32 ltr_mode = 0;
 448         char *outstr;
 449         int ret;
 450
 451         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 452         if (ret)
 453                 return ret;
 454
 455         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 456         return sprintf(buf, "%s\n", outstr);
 457 }
 458
 459 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 460 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 461 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 462
 463 static struct attribute *lpss_attrs[] = {
 464         &dev_attr_auto_ltr.attr,
 465         &dev_attr_sw_ltr.attr,
 466         &dev_attr_ltr_mode.attr,
 467         NULL,
 468 };
 469
 470 static struct attribute_group lpss_attr_group = {
 471         .attrs = lpss_attrs,
 472         .name = "lpss_ltr",
 473 };
 474
 475 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 476 {
 477         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 478         u32 ltr_mode, ltr_val;
 479
 480         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 481         if (val < 0) {
 482                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 483                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 484                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 485                 }
 486                 return;
 487         }
 488         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 489         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 490                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 491                 val = LPSS_LTR_MAX_VAL;
 492         } else if (val > LPSS_LTR_MAX_VAL) {
 493                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 494                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 495         } else {
 496                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 497         }
 498         ltr_val |= val;
 499         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 500         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 501                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 502                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 503         }
 504 }
 505
 506 #ifdef CONFIG_PM
 507 /**
 508  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 509  * @dev: LPSS device
 510  * @pdata: pointer to the private data of the LPSS device
 511  *
 512  * Most LPSS devices have private registers which may loose their context when
 513  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 514  * prv_reg_ctx array.
 515  */
 516 static void acpi_lpss_save_ctx(struct device *dev,
 517                                struct lpss_private_data *pdata)
 518 {
 519         unsigned int i;
 520
 521         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 522                 unsigned long offset = i * sizeof(u32);
 523
 524                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 525                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 526                         pdata->prv_reg_ctx[i], offset);
 527         }
 528 }
 529
 530 /**
 531  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 532  * @dev: LPSS device
 533  * @pdata: pointer to the private data of the LPSS device
 534  *
 535  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 536  */
 537 static void acpi_lpss_restore_ctx(struct device *dev,
 538                                   struct lpss_private_data *pdata)
 539 {
 540         unsigned int i;
 541
 542         /*
 543          * The following delay is needed or the subsequent write operations may
 544          * fail. The LPSS devices are actually PCI devices and the PCI spec
 545          * expects 10ms delay before the device can be accessed after D3 to D0
 546          * transition.
 547          */
 548         msleep(10);
 549
 550         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 551                 unsigned long offset = i * sizeof(u32);
 552
 553                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 554                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 555                         pdata->prv_reg_ctx[i], offset);
 556         }
 557 }
 558
 559 #ifdef CONFIG_PM_SLEEP
 560 static int acpi_lpss_suspend_late(struct device *dev)
 561 {
 562         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 563         int ret;
 564
 565         ret = pm_generic_suspend_late(dev);
 566         if (ret)
 567                 return ret;
 568
 569         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 570                 acpi_lpss_save_ctx(dev, pdata);
 571
 572         return acpi_dev_suspend_late(dev);
 573 }
 574
 575 static int acpi_lpss_resume_early(struct device *dev)
 576 {
 577         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 578         int ret;
 579
 580         ret = acpi_dev_resume_early(dev);
 581         if (ret)
 582                 return ret;
 583
 584         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 585                 acpi_lpss_restore_ctx(dev, pdata);
 586
 587         return pm_generic_resume_early(dev);
 588 }
 589 #endif /* CONFIG_PM_SLEEP */
 590
 591 static int acpi_lpss_runtime_suspend(struct device *dev)
 592 {
 593         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 594         int ret;
 595
 596         ret = pm_generic_runtime_suspend(dev);
 597         if (ret)
 598                 return ret;
 599
 600         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 601                 acpi_lpss_save_ctx(dev, pdata);
 602
 603         ret = acpi_dev_runtime_suspend(dev);
 604         if (ret)
 605                 return ret;
 606
 607         if (pdata->dev_desc->flags & LPSS_PROXY_REQ && proxy_device)
 608                 return pm_runtime_put_sync_suspend(proxy_device);
 609
 610         return 0;
 611 }
 612
 613 static int acpi_lpss_runtime_resume(struct device *dev)
 614 {
 615         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 616         int ret;
 617
 618         if (pdata->dev_desc->flags & LPSS_PROXY_REQ && proxy_device) {
 619                 ret = pm_runtime_get_sync(proxy_device);
 620                 if (ret)
 621                         return ret;
 622         }
 623
 624         ret = acpi_dev_runtime_resume(dev);
 625         if (ret)
 626                 return ret;
 627
 628         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 629                 acpi_lpss_restore_ctx(dev, pdata);
 630
 631         return pm_generic_runtime_resume(dev);
 632 }
 633 #endif /* CONFIG_PM */
 634
 635 static struct dev_pm_domain acpi_lpss_pm_domain = {
 636         .ops = {
 637 #ifdef CONFIG_PM
 638 #ifdef CONFIG_PM_SLEEP
 639                 .prepare = acpi_subsys_prepare,
 640                 .complete = acpi_subsys_complete,
 641                 .suspend = acpi_subsys_suspend,
 642                 .suspend_late = acpi_lpss_suspend_late,
 643                 .resume_early = acpi_lpss_resume_early,
 644                 .freeze = acpi_subsys_freeze,
 645                 .poweroff = acpi_subsys_suspend,
 646                 .poweroff_late = acpi_lpss_suspend_late,
 647                 .restore_early = acpi_lpss_resume_early,
 648 #endif
 649                 .runtime_suspend = acpi_lpss_runtime_suspend,
 650                 .runtime_resume = acpi_lpss_runtime_resume,
 651 #endif
 652         },
 653 };
 654
 655 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 656                                      unsigned long action, void *data)
 657 {
 658         struct platform_device *pdev = to_platform_device(data);
 659         struct lpss_private_data *pdata;
 660         struct acpi_device *adev;
 661         const struct acpi_device_id *id;
 662
 663         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 664         if (!id || !id->driver_data)
 665                 return 0;
 666
 667         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 668                 return 0;
 669
 670         pdata = acpi_driver_data(adev);
 671         if (!pdata)
 672                 return 0;
 673
 674         if (pdata->mmio_base &&
 675             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 676                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 677                 return 0;
 678         }
 679
 680         switch (action) {
 681         case BUS_NOTIFY_ADD_DEVICE:
 682                 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
 683                 if (pdata->dev_desc->flags & LPSS_LTR)
 684                         return sysfs_create_group(&pdev->dev.kobj,
 685                                                   &lpss_attr_group);
 686                 break;
 687         case BUS_NOTIFY_DEL_DEVICE:
 688                 if (pdata->dev_desc->flags & LPSS_LTR)
 689                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 690                 pdev->dev.pm_domain = NULL;
 691                 break;
 692         default:
 693                 break;
 694         }
 695
 696         return 0;
 697 }
 698
 699 static struct notifier_block acpi_lpss_nb = {
 700         .notifier_call = acpi_lpss_platform_notify,
 701 };
 702
 703 static void acpi_lpss_bind(struct device *dev)
 704 {
 705         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 706
 707         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 708                 return;
 709
 710         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 711                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 712         else
 713                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 714 }
 715
 716 static void acpi_lpss_unbind(struct device *dev)
 717 {
 718         dev->power.set_latency_tolerance = NULL;
 719 }
 720
 721 static struct acpi_scan_handler lpss_handler = {
 722         .ids = acpi_lpss_device_ids,
 723         .attach = acpi_lpss_create_device,
 724         .bind = acpi_lpss_bind,
 725         .unbind = acpi_lpss_unbind,
 726 };
 727
 728 void __init acpi_lpss_init(void)
 729 {
 730         if (!lpt_clk_init()) {
 731                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 732                 acpi_scan_add_handler(&lpss_handler);
 733         }
 734 }
 735
 736 #else
 737
 738 static struct acpi_scan_handler lpss_handler = {
 739         .ids = acpi_lpss_device_ids,
 740 };
 741
 742 void __init acpi_lpss_init(void)
 743 {
 744         acpi_scan_add_handler(&lpss_handler);
 745 }
 746
 747 #endif /* CONFIG_X86_INTEL_LPSS */