arch/x86_64/kernel/pci-calgary.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  47 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  48         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  49
  50 /* we need these for register space address calculation */
  51 #define START_ADDRESS           0xfe000000
  52 #define CHASSIS_BASE            0
  53 #define ONE_BASED_CHASSIS_NUM   1
  54
  55 /* register offsets inside the host bridge space */
  56 #define CALGARY_CONFIG_REG      0x0108
  57 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  58 #define PHB_PLSSR_OFFSET        0x0120
  59 #define PHB_CONFIG_RW_OFFSET    0x0160
  60 #define PHB_IOBASE_BAR_LOW      0x0170
  61 #define PHB_IOBASE_BAR_HIGH     0x0180
  62 #define PHB_MEM_1_LOW           0x0190
  63 #define PHB_MEM_1_HIGH          0x01A0
  64 #define PHB_IO_ADDR_SIZE        0x01B0
  65 #define PHB_MEM_1_SIZE          0x01C0
  66 #define PHB_MEM_ST_OFFSET       0x01D0
  67 #define PHB_AER_OFFSET          0x0200
  68 #define PHB_CONFIG_0_HIGH       0x0220
  69 #define PHB_CONFIG_0_LOW        0x0230
  70 #define PHB_CONFIG_0_END        0x0240
  71 #define PHB_MEM_2_LOW           0x02B0
  72 #define PHB_MEM_2_HIGH          0x02C0
  73 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  74 #define PHB_MEM_2_SIZE_LOW      0x02E0
  75 #define PHB_DOSHOLE_OFFSET      0x08E0
  76
  77 /* PHB_CONFIG_RW */
  78 #define PHB_TCE_ENABLE          0x20000000
  79 #define PHB_SLOT_DISABLE        0x1C000000
  80 #define PHB_DAC_DISABLE         0x01000000
  81 #define PHB_MEM2_ENABLE         0x00400000
  82 #define PHB_MCSR_ENABLE         0x00100000
  83 /* TAR (Table Address Register) */
  84 #define TAR_SW_BITS             0x0000ffffffff800fUL
  85 #define TAR_VALID               0x0000000000000008UL
  86 /* CSR (Channel/DMA Status Register) */
  87 #define CSR_AGENT_MASK          0xffe0ffff
  88 /* CCR (Calgary Configuration Register) */
  89 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  90
  91 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  92 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
  93 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
  94 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
  95 #define PHBS_PER_CALGARY        4
  96
  97 /* register offsets in Calgary's internal register space */
  98 static const unsigned long tar_offsets[] = {
  99         0x0580 /* TAR0 */,
 100         0x0588 /* TAR1 */,
 101         0x0590 /* TAR2 */,
 102         0x0598 /* TAR3 */
 103 };
 104
 105 static const unsigned long split_queue_offsets[] = {
 106         0x4870 /* SPLIT QUEUE 0 */,
 107         0x5870 /* SPLIT QUEUE 1 */,
 108         0x6870 /* SPLIT QUEUE 2 */,
 109         0x7870 /* SPLIT QUEUE 3 */
 110 };
 111
 112 static const unsigned long phb_offsets[] = {
 113         0x8000 /* PHB0 */,
 114         0x9000 /* PHB1 */,
 115         0xA000 /* PHB2 */,
 116         0xB000 /* PHB3 */
 117 };
 118
 119 /* PHB debug registers */
 120
 121 static const unsigned long phb_debug_offsets[] = {
 122         0x4000  /* PHB 0 DEBUG */,
 123         0x5000  /* PHB 1 DEBUG */,
 124         0x6000  /* PHB 2 DEBUG */,
 125         0x7000  /* PHB 3 DEBUG */
 126 };
 127
 128 /*
 129  * STUFF register for each debug PHB,
 130  * byte 1 = start bus number, byte 2 = end bus number
 131  */
 132
 133 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 134
 135 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 136 static int translate_empty_slots __read_mostly = 0;
 137 static int calgary_detected __read_mostly = 0;
 138
 139 static struct rio_table_hdr     *rio_table_hdr __initdata;
 140 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 141 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 142
 143 struct calgary_bus_info {
 144         void *tce_space;
 145         unsigned char translation_disabled;
 146         signed char phbid;
 147         void __iomem *bbar;
 148 };
 149
 150 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 151
 152 static void tce_cache_blast(struct iommu_table *tbl);
 153
 154 /* enable this to stress test the chip's TCE cache */
 155 #ifdef CONFIG_IOMMU_DEBUG
 156 int debugging __read_mostly = 1;
 157
 158 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 159         int expected, unsigned long start, unsigned long end)
 160 {
 161         unsigned long idx = start;
 162
 163         BUG_ON(start >= end);
 164
 165         while (idx < end) {
 166                 if (!!test_bit(idx, bitmap) != expected)
 167                         return idx;
 168                 ++idx;
 169         }
 170
 171         /* all bits have the expected value */
 172         return ~0UL;
 173 }
 174 #else /* debugging is disabled */
 175 int debugging __read_mostly = 0;
 176
 177 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 178         int expected, unsigned long start, unsigned long end)
 179 {
 180         return ~0UL;
 181 }
 182 #endif /* CONFIG_IOMMU_DEBUG */
 183
 184 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 185 {
 186         unsigned int npages;
 187
 188         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 189         npages >>= PAGE_SHIFT;
 190
 191         return npages;
 192 }
 193
 194 static inline int translate_phb(struct pci_dev* dev)
 195 {
 196         int disabled = bus_info[dev->bus->number].translation_disabled;
 197         return !disabled;
 198 }
 199
 200 static void iommu_range_reserve(struct iommu_table *tbl,
 201         unsigned long start_addr, unsigned int npages)
 202 {
 203         unsigned long index;
 204         unsigned long end;
 205         unsigned long badbit;
 206
 207         index = start_addr >> PAGE_SHIFT;
 208
 209         /* bail out if we're asked to reserve a region we don't cover */
 210         if (index >= tbl->it_size)
 211                 return;
 212
 213         end = index + npages;
 214         if (end > tbl->it_size) /* don't go off the table */
 215                 end = tbl->it_size;
 216
 217         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 218         if (badbit != ~0UL) {
 219                 if (printk_ratelimit())
 220                         printk(KERN_ERR "Calgary: entry already allocated at "
 221                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 222                                badbit, tbl, start_addr, npages);
 223         }
 224
 225         set_bit_string(tbl->it_map, index, npages);
 226 }
 227
 228 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 229         unsigned int npages)
 230 {
 231         unsigned long offset;
 232
 233         BUG_ON(npages == 0);
 234
 235         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 236                                        tbl->it_size, npages);
 237         if (offset == ~0UL) {
 238                 tce_cache_blast(tbl);
 239                 offset = find_next_zero_string(tbl->it_map, 0,
 240                                                tbl->it_size, npages);
 241                 if (offset == ~0UL) {
 242                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 243                         if (panic_on_overflow)
 244                                 panic("Calgary: fix the allocator.\n");
 245                         else
 246                                 return bad_dma_address;
 247                 }
 248         }
 249
 250         set_bit_string(tbl->it_map, offset, npages);
 251         tbl->it_hint = offset + npages;
 252         BUG_ON(tbl->it_hint > tbl->it_size);
 253
 254         return offset;
 255 }
 256
 257 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 258         unsigned int npages, int direction)
 259 {
 260         unsigned long entry, flags;
 261         dma_addr_t ret = bad_dma_address;
 262
 263         spin_lock_irqsave(&tbl->it_lock, flags);
 264
 265         entry = iommu_range_alloc(tbl, npages);
 266
 267         if (unlikely(entry == bad_dma_address))
 268                 goto error;
 269
 270         /* set the return dma address */
 271         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 272
 273         /* put the TCEs in the HW table */
 274         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 275                   direction);
 276
 277         spin_unlock_irqrestore(&tbl->it_lock, flags);
 278
 279         return ret;
 280
 281 error:
 282         spin_unlock_irqrestore(&tbl->it_lock, flags);
 283         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 284                "iommu %p\n", npages, tbl);
 285         return bad_dma_address;
 286 }
 287
 288 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 289         unsigned int npages)
 290 {
 291         unsigned long entry;
 292         unsigned long badbit;
 293
 294         entry = dma_addr >> PAGE_SHIFT;
 295
 296         BUG_ON(entry + npages > tbl->it_size);
 297
 298         tce_free(tbl, entry, npages);
 299
 300         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 301         if (badbit != ~0UL) {
 302                 if (printk_ratelimit())
 303                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 304                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 305                                badbit, tbl, dma_addr, entry, npages);
 306         }
 307
 308         __clear_bit_string(tbl->it_map, entry, npages);
 309 }
 310
 311 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 312         unsigned int npages)
 313 {
 314         unsigned long flags;
 315
 316         spin_lock_irqsave(&tbl->it_lock, flags);
 317
 318         __iommu_free(tbl, dma_addr, npages);
 319
 320         spin_unlock_irqrestore(&tbl->it_lock, flags);
 321 }
 322
 323 static void __calgary_unmap_sg(struct iommu_table *tbl,
 324         struct scatterlist *sglist, int nelems, int direction)
 325 {
 326         while (nelems--) {
 327                 unsigned int npages;
 328                 dma_addr_t dma = sglist->dma_address;
 329                 unsigned int dmalen = sglist->dma_length;
 330
 331                 if (dmalen == 0)
 332                         break;
 333
 334                 npages = num_dma_pages(dma, dmalen);
 335                 __iommu_free(tbl, dma, npages);
 336                 sglist++;
 337         }
 338 }
 339
 340 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 341                       int nelems, int direction)
 342 {
 343         unsigned long flags;
 344         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 345
 346         if (!translate_phb(to_pci_dev(dev)))
 347                 return;
 348
 349         spin_lock_irqsave(&tbl->it_lock, flags);
 350
 351         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 352
 353         spin_unlock_irqrestore(&tbl->it_lock, flags);
 354 }
 355
 356 static int calgary_nontranslate_map_sg(struct device* dev,
 357         struct scatterlist *sg, int nelems, int direction)
 358 {
 359         int i;
 360
 361         for (i = 0; i < nelems; i++ ) {
 362                 struct scatterlist *s = &sg[i];
 363                 BUG_ON(!s->page);
 364                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 365                 s->dma_length = s->length;
 366         }
 367         return nelems;
 368 }
 369
 370 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 371         int nelems, int direction)
 372 {
 373         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 374         unsigned long flags;
 375         unsigned long vaddr;
 376         unsigned int npages;
 377         unsigned long entry;
 378         int i;
 379
 380         if (!translate_phb(to_pci_dev(dev)))
 381                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 382
 383         spin_lock_irqsave(&tbl->it_lock, flags);
 384
 385         for (i = 0; i < nelems; i++ ) {
 386                 struct scatterlist *s = &sg[i];
 387                 BUG_ON(!s->page);
 388
 389                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 390                 npages = num_dma_pages(vaddr, s->length);
 391
 392                 entry = iommu_range_alloc(tbl, npages);
 393                 if (entry == bad_dma_address) {
 394                         /* makes sure unmap knows to stop */
 395                         s->dma_length = 0;
 396                         goto error;
 397                 }
 398
 399                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 400
 401                 /* insert into HW table */
 402                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 403                           direction);
 404
 405                 s->dma_length = s->length;
 406         }
 407
 408         spin_unlock_irqrestore(&tbl->it_lock, flags);
 409
 410         return nelems;
 411 error:
 412         __calgary_unmap_sg(tbl, sg, nelems, direction);
 413         for (i = 0; i < nelems; i++) {
 414                 sg[i].dma_address = bad_dma_address;
 415                 sg[i].dma_length = 0;
 416         }
 417         spin_unlock_irqrestore(&tbl->it_lock, flags);
 418         return 0;
 419 }
 420
 421 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 422         size_t size, int direction)
 423 {
 424         dma_addr_t dma_handle = bad_dma_address;
 425         unsigned long uaddr;
 426         unsigned int npages;
 427         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 428
 429         uaddr = (unsigned long)vaddr;
 430         npages = num_dma_pages(uaddr, size);
 431
 432         if (translate_phb(to_pci_dev(dev)))
 433                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 434         else
 435                 dma_handle = virt_to_bus(vaddr);
 436
 437         return dma_handle;
 438 }
 439
 440 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 441         size_t size, int direction)
 442 {
 443         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 444         unsigned int npages;
 445
 446         if (!translate_phb(to_pci_dev(dev)))
 447                 return;
 448
 449         npages = num_dma_pages(dma_handle, size);
 450         iommu_free(tbl, dma_handle, npages);
 451 }
 452
 453 void* calgary_alloc_coherent(struct device *dev, size_t size,
 454         dma_addr_t *dma_handle, gfp_t flag)
 455 {
 456         void *ret = NULL;
 457         dma_addr_t mapping;
 458         unsigned int npages, order;
 459         struct iommu_table *tbl;
 460
 461         tbl = to_pci_dev(dev)->bus->self->sysdata;
 462
 463         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 464         npages = size >> PAGE_SHIFT;
 465         order = get_order(size);
 466
 467         /* alloc enough pages (and possibly more) */
 468         ret = (void *)__get_free_pages(flag, order);
 469         if (!ret)
 470                 goto error;
 471         memset(ret, 0, size);
 472
 473         if (translate_phb(to_pci_dev(dev))) {
 474                 /* set up tces to cover the allocated range */
 475                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 476                 if (mapping == bad_dma_address)
 477                         goto free;
 478
 479                 *dma_handle = mapping;
 480         } else /* non translated slot */
 481                 *dma_handle = virt_to_bus(ret);
 482
 483         return ret;
 484
 485 free:
 486         free_pages((unsigned long)ret, get_order(size));
 487         ret = NULL;
 488 error:
 489         return ret;
 490 }
 491
 492 static struct dma_mapping_ops calgary_dma_ops = {
 493         .alloc_coherent = calgary_alloc_coherent,
 494         .map_single = calgary_map_single,
 495         .unmap_single = calgary_unmap_single,
 496         .map_sg = calgary_map_sg,
 497         .unmap_sg = calgary_unmap_sg,
 498 };
 499
 500 static inline void __iomem * busno_to_bbar(unsigned char num)
 501 {
 502         return bus_info[num].bbar;
 503 }
 504
 505 static inline int busno_to_phbid(unsigned char num)
 506 {
 507         return bus_info[num].phbid;
 508 }
 509
 510 static inline unsigned long split_queue_offset(unsigned char num)
 511 {
 512         size_t idx = busno_to_phbid(num);
 513
 514         return split_queue_offsets[idx];
 515 }
 516
 517 static inline unsigned long tar_offset(unsigned char num)
 518 {
 519         size_t idx = busno_to_phbid(num);
 520
 521         return tar_offsets[idx];
 522 }
 523
 524 static inline unsigned long phb_offset(unsigned char num)
 525 {
 526         size_t idx = busno_to_phbid(num);
 527
 528         return phb_offsets[idx];
 529 }
 530
 531 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 532 {
 533         unsigned long target = ((unsigned long)bar) | offset;
 534         return (void __iomem*)target;
 535 }
 536
 537 static void tce_cache_blast(struct iommu_table *tbl)
 538 {
 539         u64 val;
 540         u32 aer;
 541         int i = 0;
 542         void __iomem *bbar = tbl->bbar;
 543         void __iomem *target;
 544
 545         /* disable arbitration on the bus */
 546         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 547         aer = readl(target);
 548         writel(0, target);
 549
 550         /* read plssr to ensure it got there */
 551         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 552         val = readl(target);
 553
 554         /* poll split queues until all DMA activity is done */
 555         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 556         do {
 557                 val = readq(target);
 558                 i++;
 559         } while ((val & 0xff) != 0xff && i < 100);
 560         if (i == 100)
 561                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 562                        "continuing anyway\n");
 563
 564         /* invalidate TCE cache */
 565         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 566         writeq(tbl->tar_val, target);
 567
 568         /* enable arbitration */
 569         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 570         writel(aer, target);
 571         (void)readl(target); /* flush */
 572 }
 573
 574 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 575         u64 limit)
 576 {
 577         unsigned int numpages;
 578
 579         limit = limit | 0xfffff;
 580         limit++;
 581
 582         numpages = ((limit - start) >> PAGE_SHIFT);
 583         iommu_range_reserve(dev->sysdata, start, numpages);
 584 }
 585
 586 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 587 {
 588         void __iomem *target;
 589         u64 low, high, sizelow;
 590         u64 start, limit;
 591         struct iommu_table *tbl = dev->sysdata;
 592         unsigned char busnum = dev->bus->number;
 593         void __iomem *bbar = tbl->bbar;
 594
 595         /* peripheral MEM_1 region */
 596         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 597         low = be32_to_cpu(readl(target));
 598         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 599         high = be32_to_cpu(readl(target));
 600         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 601         sizelow = be32_to_cpu(readl(target));
 602
 603         start = (high << 32) | low;
 604         limit = sizelow;
 605
 606         calgary_reserve_mem_region(dev, start, limit);
 607 }
 608
 609 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 610 {
 611         void __iomem *target;
 612         u32 val32;
 613         u64 low, high, sizelow, sizehigh;
 614         u64 start, limit;
 615         struct iommu_table *tbl = dev->sysdata;
 616         unsigned char busnum = dev->bus->number;
 617         void __iomem *bbar = tbl->bbar;
 618
 619         /* is it enabled? */
 620         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 621         val32 = be32_to_cpu(readl(target));
 622         if (!(val32 & PHB_MEM2_ENABLE))
 623                 return;
 624
 625         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 626         low = be32_to_cpu(readl(target));
 627         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 628         high = be32_to_cpu(readl(target));
 629         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 630         sizelow = be32_to_cpu(readl(target));
 631         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 632         sizehigh = be32_to_cpu(readl(target));
 633
 634         start = (high << 32) | low;
 635         limit = (sizehigh << 32) | sizelow;
 636
 637         calgary_reserve_mem_region(dev, start, limit);
 638 }
 639
 640 /*
 641  * some regions of the IO address space do not get translated, so we
 642  * must not give devices IO addresses in those regions. The regions
 643  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 644  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 645  * later.
 646  */
 647 static void __init calgary_reserve_regions(struct pci_dev *dev)
 648 {
 649         unsigned int npages;
 650         void __iomem *bbar;
 651         unsigned char busnum;
 652         u64 start;
 653         struct iommu_table *tbl = dev->sysdata;
 654
 655         bbar = tbl->bbar;
 656         busnum = dev->bus->number;
 657
 658         /* reserve bad_dma_address in case it's a legal address */
 659         iommu_range_reserve(tbl, bad_dma_address, 1);
 660
 661         /* avoid the BIOS/VGA first 640KB-1MB region */
 662         start = (640 * 1024);
 663         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 664         iommu_range_reserve(tbl, start, npages);
 665
 666         /* reserve the two PCI peripheral memory regions in IO space */
 667         calgary_reserve_peripheral_mem_1(dev);
 668         calgary_reserve_peripheral_mem_2(dev);
 669 }
 670
 671 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 672 {
 673         u64 val64;
 674         u64 table_phys;
 675         void __iomem *target;
 676         int ret;
 677         struct iommu_table *tbl;
 678
 679         /* build TCE tables for each PHB */
 680         ret = build_tce_table(dev, bbar);
 681         if (ret)
 682                 return ret;
 683
 684         tbl = dev->sysdata;
 685         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 686         tce_free(tbl, 0, tbl->it_size);
 687
 688         calgary_reserve_regions(dev);
 689
 690         /* set TARs for each PHB */
 691         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 692         val64 = be64_to_cpu(readq(target));
 693
 694         /* zero out all TAR bits under sw control */
 695         val64 &= ~TAR_SW_BITS;
 696
 697         tbl = dev->sysdata;
 698         table_phys = (u64)__pa(tbl->it_base);
 699         val64 |= table_phys;
 700
 701         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 702         val64 |= (u64) specified_table_size;
 703
 704         tbl->tar_val = cpu_to_be64(val64);
 705         writeq(tbl->tar_val, target);
 706         readq(target); /* flush */
 707
 708         return 0;
 709 }
 710
 711 static void __init calgary_free_bus(struct pci_dev *dev)
 712 {
 713         u64 val64;
 714         struct iommu_table *tbl = dev->sysdata;
 715         void __iomem *target;
 716         unsigned int bitmapsz;
 717
 718         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 719         val64 = be64_to_cpu(readq(target));
 720         val64 &= ~TAR_SW_BITS;
 721         writeq(cpu_to_be64(val64), target);
 722         readq(target); /* flush */
 723
 724         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 725         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 726         tbl->it_map = NULL;
 727
 728         kfree(tbl);
 729         dev->sysdata = NULL;
 730
 731         /* Can't free bootmem allocated memory after system is up :-( */
 732         bus_info[dev->bus->number].tce_space = NULL;
 733 }
 734
 735 static void calgary_watchdog(unsigned long data)
 736 {
 737         struct pci_dev *dev = (struct pci_dev *)data;
 738         struct iommu_table *tbl = dev->sysdata;
 739         void __iomem *bbar = tbl->bbar;
 740         u32 val32;
 741         void __iomem *target;
 742
 743         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 744         val32 = be32_to_cpu(readl(target));
 745
 746         /* If no error, the agent ID in the CSR is not valid */
 747         if (val32 & CSR_AGENT_MASK) {
 748                 printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
 749                                   "CSR = %#x\n", dev->bus->number, val32);
 750                 writel(0, target);
 751
 752                 /* Disable bus that caused the error */
 753                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 754                                            PHB_CONFIG_RW_OFFSET);
 755                 val32 = be32_to_cpu(readl(target));
 756                 val32 |= PHB_SLOT_DISABLE;
 757                 writel(cpu_to_be32(val32), target);
 758                 readl(target); /* flush */
 759         } else {
 760                 /* Reset the timer */
 761                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 762         }
 763 }
 764
 765 static void __init calgary_increase_split_completion_timeout(void __iomem *bbar,
 766         unsigned char busnum)
 767 {
 768         u64 val64;
 769         void __iomem *target;
 770         unsigned int phb_shift = ~0; /* silence gcc */
 771         u64 mask;
 772
 773         switch (busno_to_phbid(busnum)) {
 774         case 0: phb_shift = (63 - 19);
 775                 break;
 776         case 1: phb_shift = (63 - 23);
 777                 break;
 778         case 2: phb_shift = (63 - 27);
 779                 break;
 780         case 3: phb_shift = (63 - 35);
 781                 break;
 782         default:
 783                 BUG_ON(busno_to_phbid(busnum));
 784         }
 785
 786         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 787         val64 = be64_to_cpu(readq(target));
 788
 789         /* zero out this PHB's timer bits */
 790         mask = ~(0xFUL << phb_shift);
 791         val64 &= mask;
 792         val64 |= (CCR_2SEC_TIMEOUT << phb_shift);
 793         writeq(cpu_to_be64(val64), target);
 794         readq(target); /* flush */
 795 }
 796
 797 static void __init calgary_enable_translation(struct pci_dev *dev)
 798 {
 799         u32 val32;
 800         unsigned char busnum;
 801         void __iomem *target;
 802         void __iomem *bbar;
 803         struct iommu_table *tbl;
 804
 805         busnum = dev->bus->number;
 806         tbl = dev->sysdata;
 807         bbar = tbl->bbar;
 808
 809         /* enable TCE in PHB Config Register */
 810         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 811         val32 = be32_to_cpu(readl(target));
 812         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 813
 814         printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
 815         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 816                "bus.\n");
 817
 818         writel(cpu_to_be32(val32), target);
 819         readl(target); /* flush */
 820
 821         /*
 822          * Give split completion a longer timeout on bus 1 for aic94xx
 823          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 824          */
 825         if (busnum == 1)
 826                 calgary_increase_split_completion_timeout(bbar, busnum);
 827
 828         init_timer(&tbl->watchdog_timer);
 829         tbl->watchdog_timer.function = &calgary_watchdog;
 830         tbl->watchdog_timer.data = (unsigned long)dev;
 831         mod_timer(&tbl->watchdog_timer, jiffies);
 832 }
 833
 834 static void __init calgary_disable_translation(struct pci_dev *dev)
 835 {
 836         u32 val32;
 837         unsigned char busnum;
 838         void __iomem *target;
 839         void __iomem *bbar;
 840         struct iommu_table *tbl;
 841
 842         busnum = dev->bus->number;
 843         tbl = dev->sysdata;
 844         bbar = tbl->bbar;
 845
 846         /* disable TCE in PHB Config Register */
 847         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 848         val32 = be32_to_cpu(readl(target));
 849         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 850
 851         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
 852         writel(cpu_to_be32(val32), target);
 853         readl(target); /* flush */
 854
 855         del_timer_sync(&tbl->watchdog_timer);
 856 }
 857
 858 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
 859 {
 860         pci_dev_get(dev);
 861         dev->sysdata = NULL;
 862         dev->bus->self = dev;
 863 }
 864
 865 static int __init calgary_init_one(struct pci_dev *dev)
 866 {
 867         void __iomem *bbar;
 868         int ret;
 869
 870         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
 871
 872         bbar = busno_to_bbar(dev->bus->number);
 873         ret = calgary_setup_tar(dev, bbar);
 874         if (ret)
 875                 goto done;
 876
 877         pci_dev_get(dev);
 878         dev->bus->self = dev;
 879         calgary_enable_translation(dev);
 880
 881         return 0;
 882
 883 done:
 884         return ret;
 885 }
 886
 887 static int __init calgary_locate_bbars(void)
 888 {
 889         int ret;
 890         int rioidx, phb, bus;
 891         void __iomem *bbar;
 892         void __iomem *target;
 893         unsigned long offset;
 894         u8 start_bus, end_bus;
 895         u32 val;
 896
 897         ret = -ENODATA;
 898         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
 899                 struct rio_detail *rio = rio_devs[rioidx];
 900
 901                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
 902                         continue;
 903
 904                 /* map entire 1MB of Calgary config space */
 905                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
 906                 if (!bbar)
 907                         goto error;
 908
 909                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
 910                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
 911                         target = calgary_reg(bbar, offset);
 912
 913                         val = be32_to_cpu(readl(target));
 914                         start_bus = (u8)((val & 0x00FF0000) >> 16);
 915                         end_bus = (u8)((val & 0x0000FF00) >> 8);
 916                         for (bus = start_bus; bus <= end_bus; bus++) {
 917                                 bus_info[bus].bbar = bbar;
 918                                 bus_info[bus].phbid = phb;
 919                         }
 920                 }
 921         }
 922
 923         return 0;
 924
 925 error:
 926         /* scan bus_info and iounmap any bbars we previously ioremap'd */
 927         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
 928                 if (bus_info[bus].bbar)
 929                         iounmap(bus_info[bus].bbar);
 930
 931         return ret;
 932 }
 933
 934 static int __init calgary_init(void)
 935 {
 936         int ret;
 937         struct pci_dev *dev = NULL;
 938
 939         ret = calgary_locate_bbars();
 940         if (ret)
 941                 return ret;
 942
 943         do {
 944                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 945                                      PCI_DEVICE_ID_IBM_CALGARY,
 946                                      dev);
 947                 if (!dev)
 948                         break;
 949                 if (!translate_phb(dev)) {
 950                         calgary_init_one_nontraslated(dev);
 951                         continue;
 952                 }
 953                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 954                         continue;
 955
 956                 ret = calgary_init_one(dev);
 957                 if (ret)
 958                         goto error;
 959         } while (1);
 960
 961         return ret;
 962
 963 error:
 964         do {
 965                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
 966                                               PCI_DEVICE_ID_IBM_CALGARY,
 967                                               dev);
 968                 if (!dev)
 969                         break;
 970                 if (!translate_phb(dev)) {
 971                         pci_dev_put(dev);
 972                         continue;
 973                 }
 974                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 975                         continue;
 976
 977                 calgary_disable_translation(dev);
 978                 calgary_free_bus(dev);
 979                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
 980         } while (1);
 981
 982         return ret;
 983 }
 984
 985 static inline int __init determine_tce_table_size(u64 ram)
 986 {
 987         int ret;
 988
 989         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
 990                 return specified_table_size;
 991
 992         /*
 993          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
 994          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
 995          * larger table size has twice as many entries, so shift the
 996          * max ram address by 13 to divide by 8K and then look at the
 997          * order of the result to choose between 0-7.
 998          */
 999         ret = get_order(ram >> 13);
1000         if (ret > TCE_TABLE_SIZE_8M)
1001                 ret = TCE_TABLE_SIZE_8M;
1002
1003         return ret;
1004 }
1005
1006 static int __init build_detail_arrays(void)
1007 {
1008         unsigned long ptr;
1009         int i, scal_detail_size, rio_detail_size;
1010
1011         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1012                 printk(KERN_WARNING
1013                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1014                         "but system has %d nodes.\n",
1015                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1016                 return -ENODEV;
1017         }
1018
1019         switch (rio_table_hdr->version){
1020         case 2:
1021                 scal_detail_size = 11;
1022                 rio_detail_size = 13;
1023                 break;
1024         case 3:
1025                 scal_detail_size = 12;
1026                 rio_detail_size = 15;
1027                 break;
1028         default:
1029                 printk(KERN_WARNING
1030                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1031                        rio_table_hdr->version);
1032                 return -EPROTO;
1033         }
1034
1035         ptr = ((unsigned long)rio_table_hdr) + 3;
1036         for (i = 0; i < rio_table_hdr->num_scal_dev;
1037                     i++, ptr += scal_detail_size)
1038                 scal_devs[i] = (struct scal_detail *)ptr;
1039
1040         for (i = 0; i < rio_table_hdr->num_rio_dev;
1041                     i++, ptr += rio_detail_size)
1042                 rio_devs[i] = (struct rio_detail *)ptr;
1043
1044         return 0;
1045 }
1046
1047 void __init detect_calgary(void)
1048 {
1049         u32 val;
1050         int bus;
1051         void *tbl;
1052         int calgary_found = 0;
1053         unsigned long ptr;
1054         int offset;
1055         int ret;
1056
1057         /*
1058          * if the user specified iommu=off or iommu=soft or we found
1059          * another HW IOMMU already, bail out.
1060          */
1061         if (swiotlb || no_iommu || iommu_detected)
1062                 return;
1063
1064         if (!early_pci_allowed())
1065                 return;
1066
1067         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1068
1069         rio_table_hdr = NULL;
1070         offset = 0x180;
1071         while (offset) {
1072                 /* The block id is stored in the 2nd word */
1073                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1074                         /* set the pointer past the offset & block id */
1075                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1076                         break;
1077                 }
1078                 /* The next offset is stored in the 1st word. 0 means no more */
1079                 offset = *((unsigned short *)(ptr + offset));
1080         }
1081         if (!rio_table_hdr) {
1082                 printk(KERN_ERR "Calgary: Unable to locate "
1083                                 "Rio Grande Table in EBDA - bailing!\n");
1084                 return;
1085         }
1086
1087         ret = build_detail_arrays();
1088         if (ret) {
1089                 printk(KERN_ERR "Calgary: build_detail_arrays ret %d\n", ret);
1090                 return;
1091         }
1092
1093         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1094
1095         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1096                 int dev;
1097                 struct calgary_bus_info *info = &bus_info[bus];
1098
1099                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
1100                         continue;
1101
1102                 if (info->translation_disabled)
1103                         continue;
1104
1105                 /*
1106                  * Scan the slots of the PCI bus to see if there is a device present.
1107                  * The parent bus will be the zero-ith device, so start at 1.
1108                  */
1109                 for (dev = 1; dev < 8; dev++) {
1110                         val = read_pci_config(bus, dev, 0, 0);
1111                         if (val != 0xffffffff || translate_empty_slots) {
1112                                 tbl = alloc_tce_table();
1113                                 if (!tbl)
1114                                         goto cleanup;
1115                                 info->tce_space = tbl;
1116                                 calgary_found = 1;
1117                                 break;
1118                         }
1119                 }
1120         }
1121
1122         if (calgary_found) {
1123                 iommu_detected = 1;
1124                 calgary_detected = 1;
1125                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1126                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1127                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1128                        debugging ? "enabled" : "disabled");
1129         }
1130         return;
1131
1132 cleanup:
1133         for (--bus; bus >= 0; --bus) {
1134                 struct calgary_bus_info *info = &bus_info[bus];
1135
1136                 if (info->tce_space)
1137                         free_tce_table(info->tce_space);
1138         }
1139 }
1140
1141 int __init calgary_iommu_init(void)
1142 {
1143         int ret;
1144
1145         if (no_iommu || swiotlb)
1146                 return -ENODEV;
1147
1148         if (!calgary_detected)
1149                 return -ENODEV;
1150
1151         /* ok, we're trying to use Calgary - let's roll */
1152         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1153
1154         ret = calgary_init();
1155         if (ret) {
1156                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1157                        "falling back to no_iommu\n", ret);
1158                 if (end_pfn > MAX_DMA32_PFN)
1159                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1160                                         "32bit PCI may malfunction.\n");
1161                 return ret;
1162         }
1163
1164         force_iommu = 1;
1165         dma_ops = &calgary_dma_ops;
1166
1167         return 0;
1168 }
1169
1170 static int __init calgary_parse_options(char *p)
1171 {
1172         unsigned int bridge;
1173         size_t len;
1174         char* endp;
1175
1176         while (*p) {
1177                 if (!strncmp(p, "64k", 3))
1178                         specified_table_size = TCE_TABLE_SIZE_64K;
1179                 else if (!strncmp(p, "128k", 4))
1180                         specified_table_size = TCE_TABLE_SIZE_128K;
1181                 else if (!strncmp(p, "256k", 4))
1182                         specified_table_size = TCE_TABLE_SIZE_256K;
1183                 else if (!strncmp(p, "512k", 4))
1184                         specified_table_size = TCE_TABLE_SIZE_512K;
1185                 else if (!strncmp(p, "1M", 2))
1186                         specified_table_size = TCE_TABLE_SIZE_1M;
1187                 else if (!strncmp(p, "2M", 2))
1188                         specified_table_size = TCE_TABLE_SIZE_2M;
1189                 else if (!strncmp(p, "4M", 2))
1190                         specified_table_size = TCE_TABLE_SIZE_4M;
1191                 else if (!strncmp(p, "8M", 2))
1192                         specified_table_size = TCE_TABLE_SIZE_8M;
1193
1194                 len = strlen("translate_empty_slots");
1195                 if (!strncmp(p, "translate_empty_slots", len))
1196                         translate_empty_slots = 1;
1197
1198                 len = strlen("disable");
1199                 if (!strncmp(p, "disable", len)) {
1200                         p += len;
1201                         if (*p == '=')
1202                                 ++p;
1203                         if (*p == '\0')
1204                                 break;
1205                         bridge = simple_strtol(p, &endp, 0);
1206                         if (p == endp)
1207                                 break;
1208
1209                         if (bridge < MAX_PHB_BUS_NUM) {
1210                                 printk(KERN_INFO "Calgary: disabling "
1211                                        "translation for PHB %#x\n", bridge);
1212                                 bus_info[bridge].translation_disabled = 1;
1213                         }
1214                 }
1215
1216                 p = strpbrk(p, ",");
1217                 if (!p)
1218                         break;
1219
1220                 p++; /* skip ',' */
1221         }
1222         return 1;
1223 }
1224 __setup("calgary=", calgary_parse_options);