arch/x86_64/kernel/pci-calgary.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  47 int use_calgary __read_mostly = 1;
  48 #else
  49 int use_calgary __read_mostly = 0;
  50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  51
  52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  53 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  54         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  55
  56 /* we need these for register space address calculation */
  57 #define START_ADDRESS           0xfe000000
  58 #define CHASSIS_BASE            0
  59 #define ONE_BASED_CHASSIS_NUM   1
  60
  61 /* register offsets inside the host bridge space */
  62 #define CALGARY_CONFIG_REG      0x0108
  63 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  64 #define PHB_PLSSR_OFFSET        0x0120
  65 #define PHB_CONFIG_RW_OFFSET    0x0160
  66 #define PHB_IOBASE_BAR_LOW      0x0170
  67 #define PHB_IOBASE_BAR_HIGH     0x0180
  68 #define PHB_MEM_1_LOW           0x0190
  69 #define PHB_MEM_1_HIGH          0x01A0
  70 #define PHB_IO_ADDR_SIZE        0x01B0
  71 #define PHB_MEM_1_SIZE          0x01C0
  72 #define PHB_MEM_ST_OFFSET       0x01D0
  73 #define PHB_AER_OFFSET          0x0200
  74 #define PHB_CONFIG_0_HIGH       0x0220
  75 #define PHB_CONFIG_0_LOW        0x0230
  76 #define PHB_CONFIG_0_END        0x0240
  77 #define PHB_MEM_2_LOW           0x02B0
  78 #define PHB_MEM_2_HIGH          0x02C0
  79 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  80 #define PHB_MEM_2_SIZE_LOW      0x02E0
  81 #define PHB_DOSHOLE_OFFSET      0x08E0
  82
  83 /* PHB_CONFIG_RW */
  84 #define PHB_TCE_ENABLE          0x20000000
  85 #define PHB_SLOT_DISABLE        0x1C000000
  86 #define PHB_DAC_DISABLE         0x01000000
  87 #define PHB_MEM2_ENABLE         0x00400000
  88 #define PHB_MCSR_ENABLE         0x00100000
  89 /* TAR (Table Address Register) */
  90 #define TAR_SW_BITS             0x0000ffffffff800fUL
  91 #define TAR_VALID               0x0000000000000008UL
  92 /* CSR (Channel/DMA Status Register) */
  93 #define CSR_AGENT_MASK          0xffe0ffff
  94 /* CCR (Calgary Configuration Register) */
  95 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  96
  97 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  98 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
  99 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 100 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 101 #define PHBS_PER_CALGARY        4
 102
 103 /* register offsets in Calgary's internal register space */
 104 static const unsigned long tar_offsets[] = {
 105         0x0580 /* TAR0 */,
 106         0x0588 /* TAR1 */,
 107         0x0590 /* TAR2 */,
 108         0x0598 /* TAR3 */
 109 };
 110
 111 static const unsigned long split_queue_offsets[] = {
 112         0x4870 /* SPLIT QUEUE 0 */,
 113         0x5870 /* SPLIT QUEUE 1 */,
 114         0x6870 /* SPLIT QUEUE 2 */,
 115         0x7870 /* SPLIT QUEUE 3 */
 116 };
 117
 118 static const unsigned long phb_offsets[] = {
 119         0x8000 /* PHB0 */,
 120         0x9000 /* PHB1 */,
 121         0xA000 /* PHB2 */,
 122         0xB000 /* PHB3 */
 123 };
 124
 125 /* PHB debug registers */
 126
 127 static const unsigned long phb_debug_offsets[] = {
 128         0x4000  /* PHB 0 DEBUG */,
 129         0x5000  /* PHB 1 DEBUG */,
 130         0x6000  /* PHB 2 DEBUG */,
 131         0x7000  /* PHB 3 DEBUG */
 132 };
 133
 134 /*
 135  * STUFF register for each debug PHB,
 136  * byte 1 = start bus number, byte 2 = end bus number
 137  */
 138
 139 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 140
 141 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 142 static int translate_empty_slots __read_mostly = 0;
 143 static int calgary_detected __read_mostly = 0;
 144
 145 static struct rio_table_hdr     *rio_table_hdr __initdata;
 146 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 147 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 148
 149 struct calgary_bus_info {
 150         void *tce_space;
 151         unsigned char translation_disabled;
 152         signed char phbid;
 153         void __iomem *bbar;
 154 };
 155
 156 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 157
 158 static void tce_cache_blast(struct iommu_table *tbl);
 159
 160 /* enable this to stress test the chip's TCE cache */
 161 #ifdef CONFIG_IOMMU_DEBUG
 162 int debugging __read_mostly = 1;
 163
 164 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 165         int expected, unsigned long start, unsigned long end)
 166 {
 167         unsigned long idx = start;
 168
 169         BUG_ON(start >= end);
 170
 171         while (idx < end) {
 172                 if (!!test_bit(idx, bitmap) != expected)
 173                         return idx;
 174                 ++idx;
 175         }
 176
 177         /* all bits have the expected value */
 178         return ~0UL;
 179 }
 180 #else /* debugging is disabled */
 181 int debugging __read_mostly = 0;
 182
 183 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 184         int expected, unsigned long start, unsigned long end)
 185 {
 186         return ~0UL;
 187 }
 188 #endif /* CONFIG_IOMMU_DEBUG */
 189
 190 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 191 {
 192         unsigned int npages;
 193
 194         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 195         npages >>= PAGE_SHIFT;
 196
 197         return npages;
 198 }
 199
 200 static inline int translate_phb(struct pci_dev* dev)
 201 {
 202         int disabled = bus_info[dev->bus->number].translation_disabled;
 203         return !disabled;
 204 }
 205
 206 static void iommu_range_reserve(struct iommu_table *tbl,
 207         unsigned long start_addr, unsigned int npages)
 208 {
 209         unsigned long index;
 210         unsigned long end;
 211         unsigned long badbit;
 212
 213         index = start_addr >> PAGE_SHIFT;
 214
 215         /* bail out if we're asked to reserve a region we don't cover */
 216         if (index >= tbl->it_size)
 217                 return;
 218
 219         end = index + npages;
 220         if (end > tbl->it_size) /* don't go off the table */
 221                 end = tbl->it_size;
 222
 223         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 224         if (badbit != ~0UL) {
 225                 if (printk_ratelimit())
 226                         printk(KERN_ERR "Calgary: entry already allocated at "
 227                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 228                                badbit, tbl, start_addr, npages);
 229         }
 230
 231         set_bit_string(tbl->it_map, index, npages);
 232 }
 233
 234 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 235         unsigned int npages)
 236 {
 237         unsigned long offset;
 238
 239         BUG_ON(npages == 0);
 240
 241         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 242                                        tbl->it_size, npages);
 243         if (offset == ~0UL) {
 244                 tce_cache_blast(tbl);
 245                 offset = find_next_zero_string(tbl->it_map, 0,
 246                                                tbl->it_size, npages);
 247                 if (offset == ~0UL) {
 248                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 249                         if (panic_on_overflow)
 250                                 panic("Calgary: fix the allocator.\n");
 251                         else
 252                                 return bad_dma_address;
 253                 }
 254         }
 255
 256         set_bit_string(tbl->it_map, offset, npages);
 257         tbl->it_hint = offset + npages;
 258         BUG_ON(tbl->it_hint > tbl->it_size);
 259
 260         return offset;
 261 }
 262
 263 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 264         unsigned int npages, int direction)
 265 {
 266         unsigned long entry, flags;
 267         dma_addr_t ret = bad_dma_address;
 268
 269         spin_lock_irqsave(&tbl->it_lock, flags);
 270
 271         entry = iommu_range_alloc(tbl, npages);
 272
 273         if (unlikely(entry == bad_dma_address))
 274                 goto error;
 275
 276         /* set the return dma address */
 277         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 278
 279         /* put the TCEs in the HW table */
 280         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 281                   direction);
 282
 283         spin_unlock_irqrestore(&tbl->it_lock, flags);
 284
 285         return ret;
 286
 287 error:
 288         spin_unlock_irqrestore(&tbl->it_lock, flags);
 289         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 290                "iommu %p\n", npages, tbl);
 291         return bad_dma_address;
 292 }
 293
 294 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 295         unsigned int npages)
 296 {
 297         unsigned long entry;
 298         unsigned long badbit;
 299
 300         entry = dma_addr >> PAGE_SHIFT;
 301
 302         BUG_ON(entry + npages > tbl->it_size);
 303
 304         tce_free(tbl, entry, npages);
 305
 306         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 307         if (badbit != ~0UL) {
 308                 if (printk_ratelimit())
 309                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 310                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 311                                badbit, tbl, dma_addr, entry, npages);
 312         }
 313
 314         __clear_bit_string(tbl->it_map, entry, npages);
 315 }
 316
 317 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 318         unsigned int npages)
 319 {
 320         unsigned long flags;
 321
 322         spin_lock_irqsave(&tbl->it_lock, flags);
 323
 324         __iommu_free(tbl, dma_addr, npages);
 325
 326         spin_unlock_irqrestore(&tbl->it_lock, flags);
 327 }
 328
 329 static void __calgary_unmap_sg(struct iommu_table *tbl,
 330         struct scatterlist *sglist, int nelems, int direction)
 331 {
 332         while (nelems--) {
 333                 unsigned int npages;
 334                 dma_addr_t dma = sglist->dma_address;
 335                 unsigned int dmalen = sglist->dma_length;
 336
 337                 if (dmalen == 0)
 338                         break;
 339
 340                 npages = num_dma_pages(dma, dmalen);
 341                 __iommu_free(tbl, dma, npages);
 342                 sglist++;
 343         }
 344 }
 345
 346 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 347                       int nelems, int direction)
 348 {
 349         unsigned long flags;
 350         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 351
 352         if (!translate_phb(to_pci_dev(dev)))
 353                 return;
 354
 355         spin_lock_irqsave(&tbl->it_lock, flags);
 356
 357         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 358
 359         spin_unlock_irqrestore(&tbl->it_lock, flags);
 360 }
 361
 362 static int calgary_nontranslate_map_sg(struct device* dev,
 363         struct scatterlist *sg, int nelems, int direction)
 364 {
 365         int i;
 366
 367         for (i = 0; i < nelems; i++ ) {
 368                 struct scatterlist *s = &sg[i];
 369                 BUG_ON(!s->page);
 370                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 371                 s->dma_length = s->length;
 372         }
 373         return nelems;
 374 }
 375
 376 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 377         int nelems, int direction)
 378 {
 379         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 380         unsigned long flags;
 381         unsigned long vaddr;
 382         unsigned int npages;
 383         unsigned long entry;
 384         int i;
 385
 386         if (!translate_phb(to_pci_dev(dev)))
 387                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 388
 389         spin_lock_irqsave(&tbl->it_lock, flags);
 390
 391         for (i = 0; i < nelems; i++ ) {
 392                 struct scatterlist *s = &sg[i];
 393                 BUG_ON(!s->page);
 394
 395                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 396                 npages = num_dma_pages(vaddr, s->length);
 397
 398                 entry = iommu_range_alloc(tbl, npages);
 399                 if (entry == bad_dma_address) {
 400                         /* makes sure unmap knows to stop */
 401                         s->dma_length = 0;
 402                         goto error;
 403                 }
 404
 405                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 406
 407                 /* insert into HW table */
 408                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 409                           direction);
 410
 411                 s->dma_length = s->length;
 412         }
 413
 414         spin_unlock_irqrestore(&tbl->it_lock, flags);
 415
 416         return nelems;
 417 error:
 418         __calgary_unmap_sg(tbl, sg, nelems, direction);
 419         for (i = 0; i < nelems; i++) {
 420                 sg[i].dma_address = bad_dma_address;
 421                 sg[i].dma_length = 0;
 422         }
 423         spin_unlock_irqrestore(&tbl->it_lock, flags);
 424         return 0;
 425 }
 426
 427 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 428         size_t size, int direction)
 429 {
 430         dma_addr_t dma_handle = bad_dma_address;
 431         unsigned long uaddr;
 432         unsigned int npages;
 433         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 434
 435         uaddr = (unsigned long)vaddr;
 436         npages = num_dma_pages(uaddr, size);
 437
 438         if (translate_phb(to_pci_dev(dev)))
 439                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 440         else
 441                 dma_handle = virt_to_bus(vaddr);
 442
 443         return dma_handle;
 444 }
 445
 446 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 447         size_t size, int direction)
 448 {
 449         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 450         unsigned int npages;
 451
 452         if (!translate_phb(to_pci_dev(dev)))
 453                 return;
 454
 455         npages = num_dma_pages(dma_handle, size);
 456         iommu_free(tbl, dma_handle, npages);
 457 }
 458
 459 void* calgary_alloc_coherent(struct device *dev, size_t size,
 460         dma_addr_t *dma_handle, gfp_t flag)
 461 {
 462         void *ret = NULL;
 463         dma_addr_t mapping;
 464         unsigned int npages, order;
 465         struct iommu_table *tbl;
 466
 467         tbl = to_pci_dev(dev)->bus->self->sysdata;
 468
 469         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 470         npages = size >> PAGE_SHIFT;
 471         order = get_order(size);
 472
 473         /* alloc enough pages (and possibly more) */
 474         ret = (void *)__get_free_pages(flag, order);
 475         if (!ret)
 476                 goto error;
 477         memset(ret, 0, size);
 478
 479         if (translate_phb(to_pci_dev(dev))) {
 480                 /* set up tces to cover the allocated range */
 481                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 482                 if (mapping == bad_dma_address)
 483                         goto free;
 484
 485                 *dma_handle = mapping;
 486         } else /* non translated slot */
 487                 *dma_handle = virt_to_bus(ret);
 488
 489         return ret;
 490
 491 free:
 492         free_pages((unsigned long)ret, get_order(size));
 493         ret = NULL;
 494 error:
 495         return ret;
 496 }
 497
 498 static struct dma_mapping_ops calgary_dma_ops = {
 499         .alloc_coherent = calgary_alloc_coherent,
 500         .map_single = calgary_map_single,
 501         .unmap_single = calgary_unmap_single,
 502         .map_sg = calgary_map_sg,
 503         .unmap_sg = calgary_unmap_sg,
 504 };
 505
 506 static inline void __iomem * busno_to_bbar(unsigned char num)
 507 {
 508         return bus_info[num].bbar;
 509 }
 510
 511 static inline int busno_to_phbid(unsigned char num)
 512 {
 513         return bus_info[num].phbid;
 514 }
 515
 516 static inline unsigned long split_queue_offset(unsigned char num)
 517 {
 518         size_t idx = busno_to_phbid(num);
 519
 520         return split_queue_offsets[idx];
 521 }
 522
 523 static inline unsigned long tar_offset(unsigned char num)
 524 {
 525         size_t idx = busno_to_phbid(num);
 526
 527         return tar_offsets[idx];
 528 }
 529
 530 static inline unsigned long phb_offset(unsigned char num)
 531 {
 532         size_t idx = busno_to_phbid(num);
 533
 534         return phb_offsets[idx];
 535 }
 536
 537 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 538 {
 539         unsigned long target = ((unsigned long)bar) | offset;
 540         return (void __iomem*)target;
 541 }
 542
 543 static void tce_cache_blast(struct iommu_table *tbl)
 544 {
 545         u64 val;
 546         u32 aer;
 547         int i = 0;
 548         void __iomem *bbar = tbl->bbar;
 549         void __iomem *target;
 550
 551         /* disable arbitration on the bus */
 552         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 553         aer = readl(target);
 554         writel(0, target);
 555
 556         /* read plssr to ensure it got there */
 557         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 558         val = readl(target);
 559
 560         /* poll split queues until all DMA activity is done */
 561         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 562         do {
 563                 val = readq(target);
 564                 i++;
 565         } while ((val & 0xff) != 0xff && i < 100);
 566         if (i == 100)
 567                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 568                        "continuing anyway\n");
 569
 570         /* invalidate TCE cache */
 571         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 572         writeq(tbl->tar_val, target);
 573
 574         /* enable arbitration */
 575         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 576         writel(aer, target);
 577         (void)readl(target); /* flush */
 578 }
 579
 580 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 581         u64 limit)
 582 {
 583         unsigned int numpages;
 584
 585         limit = limit | 0xfffff;
 586         limit++;
 587
 588         numpages = ((limit - start) >> PAGE_SHIFT);
 589         iommu_range_reserve(dev->sysdata, start, numpages);
 590 }
 591
 592 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 593 {
 594         void __iomem *target;
 595         u64 low, high, sizelow;
 596         u64 start, limit;
 597         struct iommu_table *tbl = dev->sysdata;
 598         unsigned char busnum = dev->bus->number;
 599         void __iomem *bbar = tbl->bbar;
 600
 601         /* peripheral MEM_1 region */
 602         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 603         low = be32_to_cpu(readl(target));
 604         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 605         high = be32_to_cpu(readl(target));
 606         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 607         sizelow = be32_to_cpu(readl(target));
 608
 609         start = (high << 32) | low;
 610         limit = sizelow;
 611
 612         calgary_reserve_mem_region(dev, start, limit);
 613 }
 614
 615 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 616 {
 617         void __iomem *target;
 618         u32 val32;
 619         u64 low, high, sizelow, sizehigh;
 620         u64 start, limit;
 621         struct iommu_table *tbl = dev->sysdata;
 622         unsigned char busnum = dev->bus->number;
 623         void __iomem *bbar = tbl->bbar;
 624
 625         /* is it enabled? */
 626         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 627         val32 = be32_to_cpu(readl(target));
 628         if (!(val32 & PHB_MEM2_ENABLE))
 629                 return;
 630
 631         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 632         low = be32_to_cpu(readl(target));
 633         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 634         high = be32_to_cpu(readl(target));
 635         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 636         sizelow = be32_to_cpu(readl(target));
 637         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 638         sizehigh = be32_to_cpu(readl(target));
 639
 640         start = (high << 32) | low;
 641         limit = (sizehigh << 32) | sizelow;
 642
 643         calgary_reserve_mem_region(dev, start, limit);
 644 }
 645
 646 /*
 647  * some regions of the IO address space do not get translated, so we
 648  * must not give devices IO addresses in those regions. The regions
 649  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 650  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 651  * later.
 652  */
 653 static void __init calgary_reserve_regions(struct pci_dev *dev)
 654 {
 655         unsigned int npages;
 656         void __iomem *bbar;
 657         unsigned char busnum;
 658         u64 start;
 659         struct iommu_table *tbl = dev->sysdata;
 660
 661         bbar = tbl->bbar;
 662         busnum = dev->bus->number;
 663
 664         /* reserve bad_dma_address in case it's a legal address */
 665         iommu_range_reserve(tbl, bad_dma_address, 1);
 666
 667         /* avoid the BIOS/VGA first 640KB-1MB region */
 668         start = (640 * 1024);
 669         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 670         iommu_range_reserve(tbl, start, npages);
 671
 672         /* reserve the two PCI peripheral memory regions in IO space */
 673         calgary_reserve_peripheral_mem_1(dev);
 674         calgary_reserve_peripheral_mem_2(dev);
 675 }
 676
 677 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 678 {
 679         u64 val64;
 680         u64 table_phys;
 681         void __iomem *target;
 682         int ret;
 683         struct iommu_table *tbl;
 684
 685         /* build TCE tables for each PHB */
 686         ret = build_tce_table(dev, bbar);
 687         if (ret)
 688                 return ret;
 689
 690         tbl = dev->sysdata;
 691         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 692         tce_free(tbl, 0, tbl->it_size);
 693
 694         calgary_reserve_regions(dev);
 695
 696         /* set TARs for each PHB */
 697         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 698         val64 = be64_to_cpu(readq(target));
 699
 700         /* zero out all TAR bits under sw control */
 701         val64 &= ~TAR_SW_BITS;
 702
 703         tbl = dev->sysdata;
 704         table_phys = (u64)__pa(tbl->it_base);
 705         val64 |= table_phys;
 706
 707         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 708         val64 |= (u64) specified_table_size;
 709
 710         tbl->tar_val = cpu_to_be64(val64);
 711         writeq(tbl->tar_val, target);
 712         readq(target); /* flush */
 713
 714         return 0;
 715 }
 716
 717 static void __init calgary_free_bus(struct pci_dev *dev)
 718 {
 719         u64 val64;
 720         struct iommu_table *tbl = dev->sysdata;
 721         void __iomem *target;
 722         unsigned int bitmapsz;
 723
 724         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 725         val64 = be64_to_cpu(readq(target));
 726         val64 &= ~TAR_SW_BITS;
 727         writeq(cpu_to_be64(val64), target);
 728         readq(target); /* flush */
 729
 730         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 731         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 732         tbl->it_map = NULL;
 733
 734         kfree(tbl);
 735         dev->sysdata = NULL;
 736
 737         /* Can't free bootmem allocated memory after system is up :-( */
 738         bus_info[dev->bus->number].tce_space = NULL;
 739 }
 740
 741 static void calgary_watchdog(unsigned long data)
 742 {
 743         struct pci_dev *dev = (struct pci_dev *)data;
 744         struct iommu_table *tbl = dev->sysdata;
 745         void __iomem *bbar = tbl->bbar;
 746         u32 val32;
 747         void __iomem *target;
 748
 749         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 750         val32 = be32_to_cpu(readl(target));
 751
 752         /* If no error, the agent ID in the CSR is not valid */
 753         if (val32 & CSR_AGENT_MASK) {
 754                 printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
 755                                   "CSR = %#x\n", dev->bus->number, val32);
 756                 writel(0, target);
 757
 758                 /* Disable bus that caused the error */
 759                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 760                                            PHB_CONFIG_RW_OFFSET);
 761                 val32 = be32_to_cpu(readl(target));
 762                 val32 |= PHB_SLOT_DISABLE;
 763                 writel(cpu_to_be32(val32), target);
 764                 readl(target); /* flush */
 765         } else {
 766                 /* Reset the timer */
 767                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 768         }
 769 }
 770
 771 static void __init calgary_increase_split_completion_timeout(void __iomem *bbar,
 772         unsigned char busnum)
 773 {
 774         u64 val64;
 775         void __iomem *target;
 776         unsigned int phb_shift = ~0; /* silence gcc */
 777         u64 mask;
 778
 779         switch (busno_to_phbid(busnum)) {
 780         case 0: phb_shift = (63 - 19);
 781                 break;
 782         case 1: phb_shift = (63 - 23);
 783                 break;
 784         case 2: phb_shift = (63 - 27);
 785                 break;
 786         case 3: phb_shift = (63 - 35);
 787                 break;
 788         default:
 789                 BUG_ON(busno_to_phbid(busnum));
 790         }
 791
 792         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 793         val64 = be64_to_cpu(readq(target));
 794
 795         /* zero out this PHB's timer bits */
 796         mask = ~(0xFUL << phb_shift);
 797         val64 &= mask;
 798         val64 |= (CCR_2SEC_TIMEOUT << phb_shift);
 799         writeq(cpu_to_be64(val64), target);
 800         readq(target); /* flush */
 801 }
 802
 803 static void __init calgary_enable_translation(struct pci_dev *dev)
 804 {
 805         u32 val32;
 806         unsigned char busnum;
 807         void __iomem *target;
 808         void __iomem *bbar;
 809         struct iommu_table *tbl;
 810
 811         busnum = dev->bus->number;
 812         tbl = dev->sysdata;
 813         bbar = tbl->bbar;
 814
 815         /* enable TCE in PHB Config Register */
 816         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 817         val32 = be32_to_cpu(readl(target));
 818         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 819
 820         printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
 821         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 822                "bus.\n");
 823
 824         writel(cpu_to_be32(val32), target);
 825         readl(target); /* flush */
 826
 827         /*
 828          * Give split completion a longer timeout on bus 1 for aic94xx
 829          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 830          */
 831         if (busnum == 1)
 832                 calgary_increase_split_completion_timeout(bbar, busnum);
 833
 834         init_timer(&tbl->watchdog_timer);
 835         tbl->watchdog_timer.function = &calgary_watchdog;
 836         tbl->watchdog_timer.data = (unsigned long)dev;
 837         mod_timer(&tbl->watchdog_timer, jiffies);
 838 }
 839
 840 static void __init calgary_disable_translation(struct pci_dev *dev)
 841 {
 842         u32 val32;
 843         unsigned char busnum;
 844         void __iomem *target;
 845         void __iomem *bbar;
 846         struct iommu_table *tbl;
 847
 848         busnum = dev->bus->number;
 849         tbl = dev->sysdata;
 850         bbar = tbl->bbar;
 851
 852         /* disable TCE in PHB Config Register */
 853         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 854         val32 = be32_to_cpu(readl(target));
 855         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 856
 857         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
 858         writel(cpu_to_be32(val32), target);
 859         readl(target); /* flush */
 860
 861         del_timer_sync(&tbl->watchdog_timer);
 862 }
 863
 864 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
 865 {
 866         pci_dev_get(dev);
 867         dev->sysdata = NULL;
 868         dev->bus->self = dev;
 869 }
 870
 871 static int __init calgary_init_one(struct pci_dev *dev)
 872 {
 873         void __iomem *bbar;
 874         int ret;
 875
 876         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
 877
 878         bbar = busno_to_bbar(dev->bus->number);
 879         ret = calgary_setup_tar(dev, bbar);
 880         if (ret)
 881                 goto done;
 882
 883         pci_dev_get(dev);
 884         dev->bus->self = dev;
 885         calgary_enable_translation(dev);
 886
 887         return 0;
 888
 889 done:
 890         return ret;
 891 }
 892
 893 static int __init calgary_locate_bbars(void)
 894 {
 895         int ret;
 896         int rioidx, phb, bus;
 897         void __iomem *bbar;
 898         void __iomem *target;
 899         unsigned long offset;
 900         u8 start_bus, end_bus;
 901         u32 val;
 902
 903         ret = -ENODATA;
 904         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
 905                 struct rio_detail *rio = rio_devs[rioidx];
 906
 907                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
 908                         continue;
 909
 910                 /* map entire 1MB of Calgary config space */
 911                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
 912                 if (!bbar)
 913                         goto error;
 914
 915                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
 916                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
 917                         target = calgary_reg(bbar, offset);
 918
 919                         val = be32_to_cpu(readl(target));
 920                         start_bus = (u8)((val & 0x00FF0000) >> 16);
 921                         end_bus = (u8)((val & 0x0000FF00) >> 8);
 922                         for (bus = start_bus; bus <= end_bus; bus++) {
 923                                 bus_info[bus].bbar = bbar;
 924                                 bus_info[bus].phbid = phb;
 925                         }
 926                 }
 927         }
 928
 929         return 0;
 930
 931 error:
 932         /* scan bus_info and iounmap any bbars we previously ioremap'd */
 933         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
 934                 if (bus_info[bus].bbar)
 935                         iounmap(bus_info[bus].bbar);
 936
 937         return ret;
 938 }
 939
 940 static int __init calgary_init(void)
 941 {
 942         int ret;
 943         struct pci_dev *dev = NULL;
 944
 945         ret = calgary_locate_bbars();
 946         if (ret)
 947                 return ret;
 948
 949         do {
 950                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 951                                      PCI_DEVICE_ID_IBM_CALGARY,
 952                                      dev);
 953                 if (!dev)
 954                         break;
 955                 if (!translate_phb(dev)) {
 956                         calgary_init_one_nontraslated(dev);
 957                         continue;
 958                 }
 959                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 960                         continue;
 961
 962                 ret = calgary_init_one(dev);
 963                 if (ret)
 964                         goto error;
 965         } while (1);
 966
 967         return ret;
 968
 969 error:
 970         do {
 971                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
 972                                               PCI_DEVICE_ID_IBM_CALGARY,
 973                                               dev);
 974                 if (!dev)
 975                         break;
 976                 if (!translate_phb(dev)) {
 977                         pci_dev_put(dev);
 978                         continue;
 979                 }
 980                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 981                         continue;
 982
 983                 calgary_disable_translation(dev);
 984                 calgary_free_bus(dev);
 985                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
 986         } while (1);
 987
 988         return ret;
 989 }
 990
 991 static inline int __init determine_tce_table_size(u64 ram)
 992 {
 993         int ret;
 994
 995         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
 996                 return specified_table_size;
 997
 998         /*
 999          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1000          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1001          * larger table size has twice as many entries, so shift the
1002          * max ram address by 13 to divide by 8K and then look at the
1003          * order of the result to choose between 0-7.
1004          */
1005         ret = get_order(ram >> 13);
1006         if (ret > TCE_TABLE_SIZE_8M)
1007                 ret = TCE_TABLE_SIZE_8M;
1008
1009         return ret;
1010 }
1011
1012 static int __init build_detail_arrays(void)
1013 {
1014         unsigned long ptr;
1015         int i, scal_detail_size, rio_detail_size;
1016
1017         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1018                 printk(KERN_WARNING
1019                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1020                         "but system has %d nodes.\n",
1021                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1022                 return -ENODEV;
1023         }
1024
1025         switch (rio_table_hdr->version){
1026         case 2:
1027                 scal_detail_size = 11;
1028                 rio_detail_size = 13;
1029                 break;
1030         case 3:
1031                 scal_detail_size = 12;
1032                 rio_detail_size = 15;
1033                 break;
1034         default:
1035                 printk(KERN_WARNING
1036                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1037                        rio_table_hdr->version);
1038                 return -EPROTO;
1039         }
1040
1041         ptr = ((unsigned long)rio_table_hdr) + 3;
1042         for (i = 0; i < rio_table_hdr->num_scal_dev;
1043                     i++, ptr += scal_detail_size)
1044                 scal_devs[i] = (struct scal_detail *)ptr;
1045
1046         for (i = 0; i < rio_table_hdr->num_rio_dev;
1047                     i++, ptr += rio_detail_size)
1048                 rio_devs[i] = (struct rio_detail *)ptr;
1049
1050         return 0;
1051 }
1052
1053 void __init detect_calgary(void)
1054 {
1055         u32 val;
1056         int bus;
1057         void *tbl;
1058         int calgary_found = 0;
1059         unsigned long ptr;
1060         int offset;
1061         int ret;
1062
1063         /*
1064          * if the user specified iommu=off or iommu=soft or we found
1065          * another HW IOMMU already, bail out.
1066          */
1067         if (swiotlb || no_iommu || iommu_detected)
1068                 return;
1069
1070         if (!use_calgary)
1071                 return;
1072
1073         if (!early_pci_allowed())
1074                 return;
1075
1076         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1077
1078         rio_table_hdr = NULL;
1079         offset = 0x180;
1080         while (offset) {
1081                 /* The block id is stored in the 2nd word */
1082                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1083                         /* set the pointer past the offset & block id */
1084                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1085                         break;
1086                 }
1087                 /* The next offset is stored in the 1st word. 0 means no more */
1088                 offset = *((unsigned short *)(ptr + offset));
1089         }
1090         if (!rio_table_hdr) {
1091                 printk(KERN_ERR "Calgary: Unable to locate "
1092                                 "Rio Grande Table in EBDA - bailing!\n");
1093                 return;
1094         }
1095
1096         ret = build_detail_arrays();
1097         if (ret) {
1098                 printk(KERN_ERR "Calgary: build_detail_arrays ret %d\n", ret);
1099                 return;
1100         }
1101
1102         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1103
1104         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1105                 int dev;
1106                 struct calgary_bus_info *info = &bus_info[bus];
1107
1108                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
1109                         continue;
1110
1111                 if (info->translation_disabled)
1112                         continue;
1113
1114                 /*
1115                  * Scan the slots of the PCI bus to see if there is a device present.
1116                  * The parent bus will be the zero-ith device, so start at 1.
1117                  */
1118                 for (dev = 1; dev < 8; dev++) {
1119                         val = read_pci_config(bus, dev, 0, 0);
1120                         if (val != 0xffffffff || translate_empty_slots) {
1121                                 tbl = alloc_tce_table();
1122                                 if (!tbl)
1123                                         goto cleanup;
1124                                 info->tce_space = tbl;
1125                                 calgary_found = 1;
1126                                 break;
1127                         }
1128                 }
1129         }
1130
1131         if (calgary_found) {
1132                 iommu_detected = 1;
1133                 calgary_detected = 1;
1134                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1135                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1136                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1137                        debugging ? "enabled" : "disabled");
1138         }
1139         return;
1140
1141 cleanup:
1142         for (--bus; bus >= 0; --bus) {
1143                 struct calgary_bus_info *info = &bus_info[bus];
1144
1145                 if (info->tce_space)
1146                         free_tce_table(info->tce_space);
1147         }
1148 }
1149
1150 int __init calgary_iommu_init(void)
1151 {
1152         int ret;
1153
1154         if (no_iommu || swiotlb)
1155                 return -ENODEV;
1156
1157         if (!calgary_detected)
1158                 return -ENODEV;
1159
1160         /* ok, we're trying to use Calgary - let's roll */
1161         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1162
1163         ret = calgary_init();
1164         if (ret) {
1165                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1166                        "falling back to no_iommu\n", ret);
1167                 if (end_pfn > MAX_DMA32_PFN)
1168                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1169                                         "32bit PCI may malfunction.\n");
1170                 return ret;
1171         }
1172
1173         force_iommu = 1;
1174         dma_ops = &calgary_dma_ops;
1175
1176         return 0;
1177 }
1178
1179 static int __init calgary_parse_options(char *p)
1180 {
1181         unsigned int bridge;
1182         size_t len;
1183         char* endp;
1184
1185         while (*p) {
1186                 if (!strncmp(p, "64k", 3))
1187                         specified_table_size = TCE_TABLE_SIZE_64K;
1188                 else if (!strncmp(p, "128k", 4))
1189                         specified_table_size = TCE_TABLE_SIZE_128K;
1190                 else if (!strncmp(p, "256k", 4))
1191                         specified_table_size = TCE_TABLE_SIZE_256K;
1192                 else if (!strncmp(p, "512k", 4))
1193                         specified_table_size = TCE_TABLE_SIZE_512K;
1194                 else if (!strncmp(p, "1M", 2))
1195                         specified_table_size = TCE_TABLE_SIZE_1M;
1196                 else if (!strncmp(p, "2M", 2))
1197                         specified_table_size = TCE_TABLE_SIZE_2M;
1198                 else if (!strncmp(p, "4M", 2))
1199                         specified_table_size = TCE_TABLE_SIZE_4M;
1200                 else if (!strncmp(p, "8M", 2))
1201                         specified_table_size = TCE_TABLE_SIZE_8M;
1202
1203                 len = strlen("translate_empty_slots");
1204                 if (!strncmp(p, "translate_empty_slots", len))
1205                         translate_empty_slots = 1;
1206
1207                 len = strlen("disable");
1208                 if (!strncmp(p, "disable", len)) {
1209                         p += len;
1210                         if (*p == '=')
1211                                 ++p;
1212                         if (*p == '\0')
1213                                 break;
1214                         bridge = simple_strtol(p, &endp, 0);
1215                         if (p == endp)
1216                                 break;
1217
1218                         if (bridge < MAX_PHB_BUS_NUM) {
1219                                 printk(KERN_INFO "Calgary: disabling "
1220                                        "translation for PHB %#x\n", bridge);
1221                                 bus_info[bridge].translation_disabled = 1;
1222                         }
1223                 }
1224
1225                 p = strpbrk(p, ",");
1226                 if (!p)
1227                         break;
1228
1229                 p++; /* skip ',' */
1230         }
1231         return 1;
1232 }
1233 __setup("calgary=", calgary_parse_options);