arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/nmi.h>
  22 #include <linux/sysctl.h>
  23 #include <linux/kprobes.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30 #include <asm/intel_arch_perfmon.h>
  31
  32 /*
  33  * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  34  * - it may be reserved by some other driver, or not
  35  * - when not reserved by some other driver, it may be used for
  36  *   the NMI watchdog, or not
  37  *
  38  * This is maintained separately from nmi_active because the NMI
  39  * watchdog may also be driven from the I/O APIC timer.
  40  */
  41 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
  42 static unsigned int lapic_nmi_owner;
  43 #define LAPIC_NMI_WATCHDOG      (1<<0)
  44 #define LAPIC_NMI_RESERVED      (1<<1)
  45
  46 /* nmi_active:
  47  * +1: the lapic NMI watchdog is active, but can be disabled
  48  *  0: the lapic NMI watchdog has not been set up, and cannot
  49  *     be enabled
  50  * -1: the lapic NMI watchdog is disabled, but can be enabled
  51  */
  52 int nmi_active;         /* oprofile uses this */
  53 int panic_on_timeout;
  54
  55 unsigned int nmi_watchdog = NMI_DEFAULT;
  56 static unsigned int nmi_hz = HZ;
  57 static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
  58 static unsigned int nmi_p4_cccr_val;
  59
  60 /* Note that these events don't tick when the CPU idles. This means
  61    the frequency varies with CPU load. */
  62
  63 #define K7_EVNTSEL_ENABLE       (1 << 22)
  64 #define K7_EVNTSEL_INT          (1 << 20)
  65 #define K7_EVNTSEL_OS           (1 << 17)
  66 #define K7_EVNTSEL_USR          (1 << 16)
  67 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
  68 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  69
  70 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
  71 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
  72
  73 #define MSR_P4_MISC_ENABLE      0x1A0
  74 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
  75 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
  76 #define MSR_P4_PERFCTR0         0x300
  77 #define MSR_P4_CCCR0            0x360
  78 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  79 #define P4_ESCR_OS              (1<<3)
  80 #define P4_ESCR_USR             (1<<2)
  81 #define P4_CCCR_OVF_PMI0        (1<<26)
  82 #define P4_CCCR_OVF_PMI1        (1<<27)
  83 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
  84 #define P4_CCCR_COMPLEMENT      (1<<19)
  85 #define P4_CCCR_COMPARE         (1<<18)
  86 #define P4_CCCR_REQUIRED        (3<<16)
  87 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
  88 #define P4_CCCR_ENABLE          (1<<12)
  89 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  90    CRU_ESCR0 (with any non-null event selector) through a complemented
  91    max threshold. [IA32-Vol3, Section 14.9.9] */
  92 #define MSR_P4_IQ_COUNTER0      0x30C
  93 #define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
  94 #define P4_NMI_IQ_CCCR0 \
  95         (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
  96          P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
  97
  98 static __cpuinit inline int nmi_known_cpu(void)
  99 {
 100         switch (boot_cpu_data.x86_vendor) {
 101         case X86_VENDOR_AMD:
 102                 return boot_cpu_data.x86 == 15;
 103         case X86_VENDOR_INTEL:
 104                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 105                         return 1;
 106                 else
 107                         return (boot_cpu_data.x86 == 15);
 108         }
 109         return 0;
 110 }
 111
 112 /* Run after command line and cpu_init init, but before all other checks */
 113 void __cpuinit nmi_watchdog_default(void)
 114 {
 115         if (nmi_watchdog != NMI_DEFAULT)
 116                 return;
 117         if (nmi_known_cpu())
 118                 nmi_watchdog = NMI_LOCAL_APIC;
 119         else
 120                 nmi_watchdog = NMI_IO_APIC;
 121 }
 122
 123 #ifdef CONFIG_SMP
 124 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 125  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 126  * CPUs during the test make them busy.
 127  */
 128 static __init void nmi_cpu_busy(void *data)
 129 {
 130         volatile int *endflag = data;
 131         local_irq_enable();
 132         /* Intentionally don't use cpu_relax here. This is
 133            to make sure that the performance counter really ticks,
 134            even if there is a simulator or similar that catches the
 135            pause instruction. On a real HT machine this is fine because
 136            all other CPUs are busy with "useless" delay loops and don't
 137            care if they get somewhat less cycles. */
 138         while (*endflag == 0)
 139                 barrier();
 140 }
 141 #endif
 142
 143 int __init check_nmi_watchdog (void)
 144 {
 145         volatile int endflag = 0;
 146         int *counts;
 147         int cpu;
 148
 149         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 150         if (!counts)
 151                 return -1;
 152
 153         printk(KERN_INFO "testing NMI watchdog ... ");
 154
 155 #ifdef CONFIG_SMP
 156         if (nmi_watchdog == NMI_LOCAL_APIC)
 157                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 158 #endif
 159
 160         for (cpu = 0; cpu < NR_CPUS; cpu++)
 161                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 162         local_irq_enable();
 163         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 164
 165         for_each_online_cpu(cpu) {
 166                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 167                         endflag = 1;
 168                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 169                                cpu,
 170                                counts[cpu],
 171                                cpu_pda(cpu)->__nmi_count);
 172                         nmi_active = 0;
 173                         lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
 174                         nmi_perfctr_msr = 0;
 175                         kfree(counts);
 176                         return -1;
 177                 }
 178         }
 179         endflag = 1;
 180         printk("OK.\n");
 181
 182         /* now that we know it works we can reduce NMI frequency to
 183            something more reasonable; makes a difference in some configs */
 184         if (nmi_watchdog == NMI_LOCAL_APIC)
 185                 nmi_hz = 1;
 186
 187         kfree(counts);
 188         return 0;
 189 }
 190
 191 int __init setup_nmi_watchdog(char *str)
 192 {
 193         int nmi;
 194
 195         if (!strncmp(str,"panic",5)) {
 196                 panic_on_timeout = 1;
 197                 str = strchr(str, ',');
 198                 if (!str)
 199                         return 1;
 200                 ++str;
 201         }
 202
 203         get_option(&str, &nmi);
 204
 205         if (nmi >= NMI_INVALID)
 206                 return 0;
 207         nmi_watchdog = nmi;
 208         return 1;
 209 }
 210
 211 __setup("nmi_watchdog=", setup_nmi_watchdog);
 212
 213 static void disable_intel_arch_watchdog(void);
 214
 215 static void disable_lapic_nmi_watchdog(void)
 216 {
 217         if (nmi_active <= 0)
 218                 return;
 219         switch (boot_cpu_data.x86_vendor) {
 220         case X86_VENDOR_AMD:
 221                 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 222                 break;
 223         case X86_VENDOR_INTEL:
 224                 if (boot_cpu_data.x86 == 15) {
 225                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
 226                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
 227                 } else if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 228                         disable_intel_arch_watchdog();
 229                 }
 230                 break;
 231         }
 232         nmi_active = -1;
 233         /* tell do_nmi() and others that we're not active any more */
 234         nmi_watchdog = 0;
 235 }
 236
 237 static void enable_lapic_nmi_watchdog(void)
 238 {
 239         if (nmi_active < 0) {
 240                 nmi_watchdog = NMI_LOCAL_APIC;
 241                 touch_nmi_watchdog();
 242                 setup_apic_nmi_watchdog();
 243         }
 244 }
 245
 246 int reserve_lapic_nmi(void)
 247 {
 248         unsigned int old_owner;
 249
 250         spin_lock(&lapic_nmi_owner_lock);
 251         old_owner = lapic_nmi_owner;
 252         lapic_nmi_owner |= LAPIC_NMI_RESERVED;
 253         spin_unlock(&lapic_nmi_owner_lock);
 254         if (old_owner & LAPIC_NMI_RESERVED)
 255                 return -EBUSY;
 256         if (old_owner & LAPIC_NMI_WATCHDOG)
 257                 disable_lapic_nmi_watchdog();
 258         return 0;
 259 }
 260
 261 void release_lapic_nmi(void)
 262 {
 263         unsigned int new_owner;
 264
 265         spin_lock(&lapic_nmi_owner_lock);
 266         new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
 267         lapic_nmi_owner = new_owner;
 268         spin_unlock(&lapic_nmi_owner_lock);
 269         if (new_owner & LAPIC_NMI_WATCHDOG)
 270                 enable_lapic_nmi_watchdog();
 271 }
 272
 273 void disable_timer_nmi_watchdog(void)
 274 {
 275         if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
 276                 return;
 277
 278         disable_irq(0);
 279         unset_nmi_callback();
 280         nmi_active = -1;
 281         nmi_watchdog = NMI_NONE;
 282 }
 283
 284 void enable_timer_nmi_watchdog(void)
 285 {
 286         if (nmi_active < 0) {
 287                 nmi_watchdog = NMI_IO_APIC;
 288                 touch_nmi_watchdog();
 289                 nmi_active = 1;
 290                 enable_irq(0);
 291         }
 292 }
 293
 294 #ifdef CONFIG_PM
 295
 296 static int nmi_pm_active; /* nmi_active before suspend */
 297
 298 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 299 {
 300         nmi_pm_active = nmi_active;
 301         disable_lapic_nmi_watchdog();
 302         return 0;
 303 }
 304
 305 static int lapic_nmi_resume(struct sys_device *dev)
 306 {
 307         if (nmi_pm_active > 0)
 308         enable_lapic_nmi_watchdog();
 309         return 0;
 310 }
 311
 312 static struct sysdev_class nmi_sysclass = {
 313         set_kset_name("lapic_nmi"),
 314         .resume         = lapic_nmi_resume,
 315         .suspend        = lapic_nmi_suspend,
 316 };
 317
 318 static struct sys_device device_lapic_nmi = {
 319         .id             = 0,
 320         .cls    = &nmi_sysclass,
 321 };
 322
 323 static int __init init_lapic_nmi_sysfs(void)
 324 {
 325         int error;
 326
 327         if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
 328                 return 0;
 329
 330         error = sysdev_class_register(&nmi_sysclass);
 331         if (!error)
 332                 error = sysdev_register(&device_lapic_nmi);
 333         return error;
 334 }
 335 /* must come after the local APIC's device_initcall() */
 336 late_initcall(init_lapic_nmi_sysfs);
 337
 338 #endif  /* CONFIG_PM */
 339
 340 /*
 341  * Activate the NMI watchdog via the local APIC.
 342  * Original code written by Keith Owens.
 343  */
 344
 345 static void clear_msr_range(unsigned int base, unsigned int n)
 346 {
 347         unsigned int i;
 348
 349         for(i = 0; i < n; ++i)
 350                 wrmsr(base+i, 0, 0);
 351 }
 352
 353 static void setup_k7_watchdog(void)
 354 {
 355         int i;
 356         unsigned int evntsel;
 357
 358         nmi_perfctr_msr = MSR_K7_PERFCTR0;
 359
 360         for(i = 0; i < 4; ++i) {
 361                 /* Simulator may not support it */
 362                 if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
 363                         nmi_perfctr_msr = 0;
 364                         return;
 365                 }
 366                 wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
 367         }
 368
 369         evntsel = K7_EVNTSEL_INT
 370                 | K7_EVNTSEL_OS
 371                 | K7_EVNTSEL_USR
 372                 | K7_NMI_EVENT;
 373
 374         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 375         wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
 376         apic_write(APIC_LVTPC, APIC_DM_NMI);
 377         evntsel |= K7_EVNTSEL_ENABLE;
 378         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 379 }
 380
 381 static void disable_intel_arch_watchdog(void)
 382 {
 383         unsigned ebx;
 384
 385         /*
 386          * Check whether the Architectural PerfMon supports
 387          * Unhalted Core Cycles Event or not.
 388          * NOTE: Corresponding bit = 0 in ebp indicates event present.
 389          */
 390         ebx = cpuid_ebx(10);
 391         if (!(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 392                 wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, 0, 0);
 393 }
 394
 395 static int setup_intel_arch_watchdog(void)
 396 {
 397         unsigned int evntsel;
 398         unsigned ebx;
 399
 400         /*
 401          * Check whether the Architectural PerfMon supports
 402          * Unhalted Core Cycles Event or not.
 403          * NOTE: Corresponding bit = 0 in ebp indicates event present.
 404          */
 405         ebx = cpuid_ebx(10);
 406         if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 407                 return 0;
 408
 409         nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 410
 411         clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);
 412         clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);
 413
 414         evntsel = ARCH_PERFMON_EVENTSEL_INT
 415                 | ARCH_PERFMON_EVENTSEL_OS
 416                 | ARCH_PERFMON_EVENTSEL_USR
 417                 | ARCH_PERFMON_NMI_EVENT_SEL
 418                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 419
 420         wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
 421         wrmsrl(MSR_ARCH_PERFMON_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
 422         apic_write(APIC_LVTPC, APIC_DM_NMI);
 423         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 424         wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
 425         return 1;
 426 }
 427
 428
 429 static int setup_p4_watchdog(void)
 430 {
 431         unsigned int misc_enable, dummy;
 432
 433         rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
 434         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 435                 return 0;
 436
 437         nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 438         nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
 439 #ifdef CONFIG_SMP
 440         if (smp_num_siblings == 2)
 441                 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
 442 #endif
 443
 444         if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
 445                 clear_msr_range(0x3F1, 2);
 446         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
 447            docs doesn't fully define it, so leave it alone for now. */
 448         if (boot_cpu_data.x86_model >= 0x3) {
 449                 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
 450                 clear_msr_range(0x3A0, 26);
 451                 clear_msr_range(0x3BC, 3);
 452         } else {
 453                 clear_msr_range(0x3A0, 31);
 454         }
 455         clear_msr_range(0x3C0, 6);
 456         clear_msr_range(0x3C8, 6);
 457         clear_msr_range(0x3E0, 2);
 458         clear_msr_range(MSR_P4_CCCR0, 18);
 459         clear_msr_range(MSR_P4_PERFCTR0, 18);
 460
 461         wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
 462         wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
 463         Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
 464         wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
 465         apic_write(APIC_LVTPC, APIC_DM_NMI);
 466         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 467         return 1;
 468 }
 469
 470 void setup_apic_nmi_watchdog(void)
 471 {
 472         switch (boot_cpu_data.x86_vendor) {
 473         case X86_VENDOR_AMD:
 474                 if (boot_cpu_data.x86 != 15)
 475                         return;
 476                 if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 477                         return;
 478                 setup_k7_watchdog();
 479                 break;
 480         case X86_VENDOR_INTEL:
 481                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 482                         if (!setup_intel_arch_watchdog())
 483                                 return;
 484                 } else if (boot_cpu_data.x86 == 15) {
 485                         if (!setup_p4_watchdog())
 486                                 return;
 487                 } else {
 488                         return;
 489                 }
 490
 491                 break;
 492
 493         default:
 494                 return;
 495         }
 496         lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
 497         nmi_active = 1;
 498 }
 499
 500 /*
 501  * the best way to detect whether a CPU has a 'hard lockup' problem
 502  * is to check it's local APIC timer IRQ counts. If they are not
 503  * changing then that CPU has some problem.
 504  *
 505  * as these watchdog NMI IRQs are generated on every CPU, we only
 506  * have to check the current processor.
 507  */
 508
 509 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 510 static DEFINE_PER_CPU(local_t, alert_counter);
 511 static DEFINE_PER_CPU(int, nmi_touch);
 512
 513 void touch_nmi_watchdog (void)
 514 {
 515         if (nmi_watchdog > 0) {
 516                 unsigned cpu;
 517
 518                 /*
 519                  * Tell other CPUs to reset their alert counters. We cannot
 520                  * do it ourselves because the alert count increase is not
 521                  * atomic.
 522                  */
 523                 for_each_present_cpu (cpu)
 524                         per_cpu(nmi_touch, cpu) = 1;
 525         }
 526
 527         touch_softlockup_watchdog();
 528 }
 529
 530 void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 531 {
 532         int sum;
 533         int touched = 0;
 534
 535         sum = read_pda(apic_timer_irqs);
 536         if (__get_cpu_var(nmi_touch)) {
 537                 __get_cpu_var(nmi_touch) = 0;
 538                 touched = 1;
 539         }
 540 #ifdef CONFIG_X86_MCE
 541         /* Could check oops_in_progress here too, but it's safer
 542            not too */
 543         if (atomic_read(&mce_entry) > 0)
 544                 touched = 1;
 545 #endif
 546         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 547                 /*
 548                  * Ayiee, looks like this CPU is stuck ...
 549                  * wait a few IRQs (5 seconds) before doing the oops ...
 550                  */
 551                 local_inc(&__get_cpu_var(alert_counter));
 552                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
 553                         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 554                                                         == NOTIFY_STOP) {
 555                                 local_set(&__get_cpu_var(alert_counter), 0);
 556                                 return;
 557                         }
 558                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
 559                 }
 560         } else {
 561                 __get_cpu_var(last_irq_sum) = sum;
 562                 local_set(&__get_cpu_var(alert_counter), 0);
 563         }
 564         if (nmi_perfctr_msr) {
 565                 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 566                         /*
 567                          * P4 quirks:
 568                          * - An overflown perfctr will assert its interrupt
 569                          *   until the OVF flag in its CCCR is cleared.
 570                          * - LVTPC is masked on interrupt and must be
 571                          *   unmasked by the LVTPC handler.
 572                          */
 573                         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 574                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 575                 } else if (nmi_perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 576                         /*
 577                          * For Intel based architectural perfmon
 578                          * - LVTPC is masked on interrupt and must be
 579                          *   unmasked by the LVTPC handler.
 580                          */
 581                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 582                 }
 583                 wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 584         }
 585 }
 586
 587 static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
 588 {
 589         return 0;
 590 }
 591
 592 static nmi_callback_t nmi_callback = dummy_nmi_callback;
 593
 594 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 595 {
 596         int cpu = safe_smp_processor_id();
 597
 598         nmi_enter();
 599         add_pda(__nmi_count,1);
 600         if (!rcu_dereference(nmi_callback)(regs, cpu))
 601                 default_do_nmi(regs);
 602         nmi_exit();
 603 }
 604
 605 void set_nmi_callback(nmi_callback_t callback)
 606 {
 607         vmalloc_sync_all();
 608         rcu_assign_pointer(nmi_callback, callback);
 609 }
 610
 611 void unset_nmi_callback(void)
 612 {
 613         nmi_callback = dummy_nmi_callback;
 614 }
 615
 616 #ifdef CONFIG_SYSCTL
 617
 618 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 619 {
 620         unsigned char reason = get_nmi_reason();
 621         char buf[64];
 622
 623         if (!(reason & 0xc0)) {
 624                 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 625                 die_nmi(buf,regs);
 626         }
 627         return 0;
 628 }
 629
 630 /*
 631  * proc handler for /proc/sys/kernel/unknown_nmi_panic
 632  */
 633 int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
 634                         void __user *buffer, size_t *length, loff_t *ppos)
 635 {
 636         int old_state;
 637
 638         old_state = unknown_nmi_panic;
 639         proc_dointvec(table, write, file, buffer, length, ppos);
 640         if (!!old_state == !!unknown_nmi_panic)
 641                 return 0;
 642
 643         if (unknown_nmi_panic) {
 644                 if (reserve_lapic_nmi() < 0) {
 645                         unknown_nmi_panic = 0;
 646                         return -EBUSY;
 647                 } else {
 648                         set_nmi_callback(unknown_nmi_panic_callback);
 649                 }
 650         } else {
 651                 release_lapic_nmi();
 652                 unset_nmi_callback();
 653         }
 654         return 0;
 655 }
 656
 657 #endif
 658
 659 EXPORT_SYMBOL(nmi_active);
 660 EXPORT_SYMBOL(nmi_watchdog);
 661 EXPORT_SYMBOL(reserve_lapic_nmi);
 662 EXPORT_SYMBOL(release_lapic_nmi);
 663 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 664 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
 665 EXPORT_SYMBOL(touch_nmi_watchdog);