arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #ifdef CONFIG_ACPI
  34 #include <acpi/acpi_bus.h>
  35 #endif
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/proto.h>
  41 #include <asm/mach_apic.h>
  42 #include <asm/acpi.h>
  43 #include <asm/dma.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 /* Where if anywhere is the i8259 connect in external int mode */
  54 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  55
  56 static DEFINE_SPINLOCK(ioapic_lock);
  57
  58 /*
  59  * # of IRQ routing registers
  60  */
  61 int nr_ioapic_registers[MAX_IO_APICS];
  62
  63 /*
  64  * Rough estimation of how many shared IRQs there are, can
  65  * be changed anytime.
  66  */
  67 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  68 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  69
  70 /*
  71  * This is performance-critical, we want to do it O(1)
  72  *
  73  * the indexing order of this array favors 1:1 mappings
  74  * between pins and IRQs.
  75  */
  76
  77 static struct irq_pin_list {
  78         short apic, pin, next;
  79 } irq_2_pin[PIN_MAP_SIZE];
  80
  81 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  82 #ifdef CONFIG_PCI_MSI
  83 #define vector_to_irq(vector)   \
  84         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  85 #else
  86 #define vector_to_irq(vector)   (vector)
  87 #endif
  88
  89 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  90                                                                         \
  91 {                                                                       \
  92         int pin;                                                        \
  93         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  94                                                                         \
  95         BUG_ON(irq >= NR_IRQS);                                         \
  96         for (;;) {                                                      \
  97                 unsigned int reg;                                       \
  98                 pin = entry->pin;                                       \
  99                 if (pin == -1)                                          \
 100                         break;                                          \
 101                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 102                 reg ACTION;                                             \
 103                 io_apic_modify(entry->apic, reg);                       \
 104                 if (!entry->next)                                       \
 105                         break;                                          \
 106                 entry = irq_2_pin + entry->next;                        \
 107         }                                                               \
 108         FINAL;                                                          \
 109 }
 110
 111 #ifdef CONFIG_SMP
 112 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 113 {
 114         unsigned long flags;
 115         unsigned int dest;
 116         cpumask_t tmp;
 117
 118         cpus_and(tmp, mask, cpu_online_map);
 119         if (cpus_empty(tmp))
 120                 tmp = TARGET_CPUS;
 121
 122         cpus_and(mask, tmp, CPU_MASK_ALL);
 123
 124         dest = cpu_mask_to_apicid(mask);
 125
 126         /*
 127          * Only the high 8 bits are valid.
 128          */
 129         dest = SET_APIC_LOGICAL_ID(dest);
 130
 131         spin_lock_irqsave(&ioapic_lock, flags);
 132         __DO_ACTION(1, = dest, )
 133         set_irq_info(irq, mask);
 134         spin_unlock_irqrestore(&ioapic_lock, flags);
 135 }
 136 #endif
 137
 138 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 139
 140 /*
 141  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 142  * shared ISA-space IRQs, so we have to support them. We are super
 143  * fast in the common case, and fast for shared ISA-space IRQs.
 144  */
 145 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 146 {
 147         static int first_free_entry = NR_IRQS;
 148         struct irq_pin_list *entry = irq_2_pin + irq;
 149
 150         BUG_ON(irq >= NR_IRQS);
 151         while (entry->next)
 152                 entry = irq_2_pin + entry->next;
 153
 154         if (entry->pin != -1) {
 155                 entry->next = first_free_entry;
 156                 entry = irq_2_pin + entry->next;
 157                 if (++first_free_entry >= PIN_MAP_SIZE)
 158                         panic("io_apic.c: ran out of irq_2_pin entries!");
 159         }
 160         entry->apic = apic;
 161         entry->pin = pin;
 162 }
 163
 164
 165 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 166                                                                         \
 167         static void name##_IO_APIC_irq (unsigned int irq)               \
 168         __DO_ACTION(R, ACTION, FINAL)
 169
 170 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 171                                                 /* mask = 1 */
 172 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 173                                                 /* mask = 0 */
 174
 175 static void mask_IO_APIC_irq (unsigned int irq)
 176 {
 177         unsigned long flags;
 178
 179         spin_lock_irqsave(&ioapic_lock, flags);
 180         __mask_IO_APIC_irq(irq);
 181         spin_unlock_irqrestore(&ioapic_lock, flags);
 182 }
 183
 184 static void unmask_IO_APIC_irq (unsigned int irq)
 185 {
 186         unsigned long flags;
 187
 188         spin_lock_irqsave(&ioapic_lock, flags);
 189         __unmask_IO_APIC_irq(irq);
 190         spin_unlock_irqrestore(&ioapic_lock, flags);
 191 }
 192
 193 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 194 {
 195         struct IO_APIC_route_entry entry;
 196         unsigned long flags;
 197
 198         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 199         spin_lock_irqsave(&ioapic_lock, flags);
 200         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 201         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 202         spin_unlock_irqrestore(&ioapic_lock, flags);
 203         if (entry.delivery_mode == dest_SMI)
 204                 return;
 205         /*
 206          * Disable it in the IO-APIC irq-routing table:
 207          */
 208         memset(&entry, 0, sizeof(entry));
 209         entry.mask = 1;
 210         spin_lock_irqsave(&ioapic_lock, flags);
 211         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 212         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 213         spin_unlock_irqrestore(&ioapic_lock, flags);
 214 }
 215
 216 static void clear_IO_APIC (void)
 217 {
 218         int apic, pin;
 219
 220         for (apic = 0; apic < nr_ioapics; apic++)
 221                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 222                         clear_IO_APIC_pin(apic, pin);
 223 }
 224
 225 /*
 226  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 227  * specific CPU-side IRQs.
 228  */
 229
 230 #define MAX_PIRQS 8
 231 static int pirq_entries [MAX_PIRQS];
 232 static int pirqs_enabled;
 233 int skip_ioapic_setup;
 234 int ioapic_force;
 235
 236 /* dummy parsing: see setup.c */
 237
 238 static int __init disable_ioapic_setup(char *str)
 239 {
 240         skip_ioapic_setup = 1;
 241         return 1;
 242 }
 243
 244 static int __init enable_ioapic_setup(char *str)
 245 {
 246         ioapic_force = 1;
 247         skip_ioapic_setup = 0;
 248         return 1;
 249 }
 250
 251 __setup("noapic", disable_ioapic_setup);
 252 __setup("apic", enable_ioapic_setup);
 253
 254 #include <asm/pci-direct.h>
 255 #include <linux/pci_ids.h>
 256 #include <linux/pci.h>
 257
 258 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 259    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 260    Use pci direct infrastructure because this runs before the PCI subsystem.
 261
 262    Can be overwritten with "apic"
 263
 264    And another hack to disable the IOMMU on VIA chipsets.
 265
 266    ... and others. Really should move this somewhere else.
 267
 268    Kludge-O-Rama. */
 269 void __init check_ioapic(void)
 270 {
 271         int num,slot,func;
 272         /* Poor man's PCI discovery */
 273         for (num = 0; num < 32; num++) {
 274                 for (slot = 0; slot < 32; slot++) {
 275                         for (func = 0; func < 8; func++) {
 276                                 u32 class;
 277                                 u32 vendor;
 278                                 u8 type;
 279                                 class = read_pci_config(num,slot,func,
 280                                                         PCI_CLASS_REVISION);
 281                                 if (class == 0xffffffff)
 282                                         break;
 283
 284                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 285                                         continue;
 286
 287                                 vendor = read_pci_config(num, slot, func,
 288                                                          PCI_VENDOR_ID);
 289                                 vendor &= 0xffff;
 290                                 switch (vendor) {
 291                                 case PCI_VENDOR_ID_VIA:
 292 #ifdef CONFIG_GART_IOMMU
 293                                         if ((end_pfn > MAX_DMA32_PFN ||
 294                                              force_iommu) &&
 295                                             !iommu_aperture_allowed) {
 296                                                 printk(KERN_INFO
 297     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 298                                                 iommu_aperture_disabled = 1;
 299                                         }
 300 #endif
 301                                         return;
 302                                 case PCI_VENDOR_ID_NVIDIA:
 303 #ifdef CONFIG_ACPI
 304                                         /* All timer overrides on Nvidia
 305                                            seem to be wrong. Skip them. */
 306                                         acpi_skip_timer_override = 1;
 307                                         printk(KERN_INFO
 308              "Nvidia board detected. Ignoring ACPI timer override.\n");
 309 #endif
 310                                         /* RED-PEN skip them on mptables too? */
 311                                         return;
 312                                 case PCI_VENDOR_ID_ATI:
 313                                         if (apic_runs_main_timer != 0)
 314                                                 break;
 315 #ifdef CONFIG_ACPI
 316                                         /* Don't do this for laptops right
 317                                            right now because their timer
 318                                            doesn't necessarily tick in C2/3 */
 319                                         if (acpi_fadt.revision >= 3 &&
 320                         (acpi_fadt.plvl2_lat + acpi_fadt.plvl3_lat) < 1100) {
 321                                                 printk(KERN_INFO
 322 "ATI board detected, but seems to be a laptop. Timer might be shakey, sorry\n");
 323                                                 break;
 324                                         }
 325 #endif
 326                                         printk(KERN_INFO
 327              "ATI board detected. Using APIC/PM timer.\n");
 328                                         apic_runs_main_timer = 1;
 329                                         nohpet = 1;
 330                                         return;
 331                                 }
 332
 333                                 /* No multi-function device? */
 334                                 type = read_pci_config_byte(num,slot,func,
 335                                                             PCI_HEADER_TYPE);
 336                                 if (!(type & 0x80))
 337                                         break;
 338                         }
 339                 }
 340         }
 341 }
 342
 343 static int __init ioapic_pirq_setup(char *str)
 344 {
 345         int i, max;
 346         int ints[MAX_PIRQS+1];
 347
 348         get_options(str, ARRAY_SIZE(ints), ints);
 349
 350         for (i = 0; i < MAX_PIRQS; i++)
 351                 pirq_entries[i] = -1;
 352
 353         pirqs_enabled = 1;
 354         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 355         max = MAX_PIRQS;
 356         if (ints[0] < MAX_PIRQS)
 357                 max = ints[0];
 358
 359         for (i = 0; i < max; i++) {
 360                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 361                 /*
 362                  * PIRQs are mapped upside down, usually.
 363                  */
 364                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 365         }
 366         return 1;
 367 }
 368
 369 __setup("pirq=", ioapic_pirq_setup);
 370
 371 /*
 372  * Find the IRQ entry number of a certain pin.
 373  */
 374 static int find_irq_entry(int apic, int pin, int type)
 375 {
 376         int i;
 377
 378         for (i = 0; i < mp_irq_entries; i++)
 379                 if (mp_irqs[i].mpc_irqtype == type &&
 380                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 381                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 382                     mp_irqs[i].mpc_dstirq == pin)
 383                         return i;
 384
 385         return -1;
 386 }
 387
 388 /*
 389  * Find the pin to which IRQ[irq] (ISA) is connected
 390  */
 391 static int __init find_isa_irq_pin(int irq, int type)
 392 {
 393         int i;
 394
 395         for (i = 0; i < mp_irq_entries; i++) {
 396                 int lbus = mp_irqs[i].mpc_srcbus;
 397
 398                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 399                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 400                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 401                     (mp_irqs[i].mpc_irqtype == type) &&
 402                     (mp_irqs[i].mpc_srcbusirq == irq))
 403
 404                         return mp_irqs[i].mpc_dstirq;
 405         }
 406         return -1;
 407 }
 408
 409 static int __init find_isa_irq_apic(int irq, int type)
 410 {
 411         int i;
 412
 413         for (i = 0; i < mp_irq_entries; i++) {
 414                 int lbus = mp_irqs[i].mpc_srcbus;
 415
 416                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 417                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 418                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 419                     (mp_irqs[i].mpc_irqtype == type) &&
 420                     (mp_irqs[i].mpc_srcbusirq == irq))
 421                         break;
 422         }
 423         if (i < mp_irq_entries) {
 424                 int apic;
 425                 for(apic = 0; apic < nr_ioapics; apic++) {
 426                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 427                                 return apic;
 428                 }
 429         }
 430
 431         return -1;
 432 }
 433
 434 /*
 435  * Find a specific PCI IRQ entry.
 436  * Not an __init, possibly needed by modules
 437  */
 438 static int pin_2_irq(int idx, int apic, int pin);
 439
 440 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 441 {
 442         int apic, i, best_guess = -1;
 443
 444         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 445                 bus, slot, pin);
 446         if (mp_bus_id_to_pci_bus[bus] == -1) {
 447                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 448                 return -1;
 449         }
 450         for (i = 0; i < mp_irq_entries; i++) {
 451                 int lbus = mp_irqs[i].mpc_srcbus;
 452
 453                 for (apic = 0; apic < nr_ioapics; apic++)
 454                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 455                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 456                                 break;
 457
 458                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 459                     !mp_irqs[i].mpc_irqtype &&
 460                     (bus == lbus) &&
 461                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 462                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 463
 464                         if (!(apic || IO_APIC_IRQ(irq)))
 465                                 continue;
 466
 467                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 468                                 return irq;
 469                         /*
 470                          * Use the first all-but-pin matching entry as a
 471                          * best-guess fuzzy result for broken mptables.
 472                          */
 473                         if (best_guess < 0)
 474                                 best_guess = irq;
 475                 }
 476         }
 477         BUG_ON(best_guess >= NR_IRQS);
 478         return best_guess;
 479 }
 480
 481 /*
 482  * EISA Edge/Level control register, ELCR
 483  */
 484 static int EISA_ELCR(unsigned int irq)
 485 {
 486         if (irq < 16) {
 487                 unsigned int port = 0x4d0 + (irq >> 3);
 488                 return (inb(port) >> (irq & 7)) & 1;
 489         }
 490         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 491         return 0;
 492 }
 493
 494 /* EISA interrupts are always polarity zero and can be edge or level
 495  * trigger depending on the ELCR value.  If an interrupt is listed as
 496  * EISA conforming in the MP table, that means its trigger type must
 497  * be read in from the ELCR */
 498
 499 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 500 #define default_EISA_polarity(idx)      (0)
 501
 502 /* ISA interrupts are always polarity zero edge triggered,
 503  * when listed as conforming in the MP table. */
 504
 505 #define default_ISA_trigger(idx)        (0)
 506 #define default_ISA_polarity(idx)       (0)
 507
 508 /* PCI interrupts are always polarity one level triggered,
 509  * when listed as conforming in the MP table. */
 510
 511 #define default_PCI_trigger(idx)        (1)
 512 #define default_PCI_polarity(idx)       (1)
 513
 514 /* MCA interrupts are always polarity zero level triggered,
 515  * when listed as conforming in the MP table. */
 516
 517 #define default_MCA_trigger(idx)        (1)
 518 #define default_MCA_polarity(idx)       (0)
 519
 520 static int __init MPBIOS_polarity(int idx)
 521 {
 522         int bus = mp_irqs[idx].mpc_srcbus;
 523         int polarity;
 524
 525         /*
 526          * Determine IRQ line polarity (high active or low active):
 527          */
 528         switch (mp_irqs[idx].mpc_irqflag & 3)
 529         {
 530                 case 0: /* conforms, ie. bus-type dependent polarity */
 531                 {
 532                         switch (mp_bus_id_to_type[bus])
 533                         {
 534                                 case MP_BUS_ISA: /* ISA pin */
 535                                 {
 536                                         polarity = default_ISA_polarity(idx);
 537                                         break;
 538                                 }
 539                                 case MP_BUS_EISA: /* EISA pin */
 540                                 {
 541                                         polarity = default_EISA_polarity(idx);
 542                                         break;
 543                                 }
 544                                 case MP_BUS_PCI: /* PCI pin */
 545                                 {
 546                                         polarity = default_PCI_polarity(idx);
 547                                         break;
 548                                 }
 549                                 case MP_BUS_MCA: /* MCA pin */
 550                                 {
 551                                         polarity = default_MCA_polarity(idx);
 552                                         break;
 553                                 }
 554                                 default:
 555                                 {
 556                                         printk(KERN_WARNING "broken BIOS!!\n");
 557                                         polarity = 1;
 558                                         break;
 559                                 }
 560                         }
 561                         break;
 562                 }
 563                 case 1: /* high active */
 564                 {
 565                         polarity = 0;
 566                         break;
 567                 }
 568                 case 2: /* reserved */
 569                 {
 570                         printk(KERN_WARNING "broken BIOS!!\n");
 571                         polarity = 1;
 572                         break;
 573                 }
 574                 case 3: /* low active */
 575                 {
 576                         polarity = 1;
 577                         break;
 578                 }
 579                 default: /* invalid */
 580                 {
 581                         printk(KERN_WARNING "broken BIOS!!\n");
 582                         polarity = 1;
 583                         break;
 584                 }
 585         }
 586         return polarity;
 587 }
 588
 589 static int MPBIOS_trigger(int idx)
 590 {
 591         int bus = mp_irqs[idx].mpc_srcbus;
 592         int trigger;
 593
 594         /*
 595          * Determine IRQ trigger mode (edge or level sensitive):
 596          */
 597         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 598         {
 599                 case 0: /* conforms, ie. bus-type dependent */
 600                 {
 601                         switch (mp_bus_id_to_type[bus])
 602                         {
 603                                 case MP_BUS_ISA: /* ISA pin */
 604                                 {
 605                                         trigger = default_ISA_trigger(idx);
 606                                         break;
 607                                 }
 608                                 case MP_BUS_EISA: /* EISA pin */
 609                                 {
 610                                         trigger = default_EISA_trigger(idx);
 611                                         break;
 612                                 }
 613                                 case MP_BUS_PCI: /* PCI pin */
 614                                 {
 615                                         trigger = default_PCI_trigger(idx);
 616                                         break;
 617                                 }
 618                                 case MP_BUS_MCA: /* MCA pin */
 619                                 {
 620                                         trigger = default_MCA_trigger(idx);
 621                                         break;
 622                                 }
 623                                 default:
 624                                 {
 625                                         printk(KERN_WARNING "broken BIOS!!\n");
 626                                         trigger = 1;
 627                                         break;
 628                                 }
 629                         }
 630                         break;
 631                 }
 632                 case 1: /* edge */
 633                 {
 634                         trigger = 0;
 635                         break;
 636                 }
 637                 case 2: /* reserved */
 638                 {
 639                         printk(KERN_WARNING "broken BIOS!!\n");
 640                         trigger = 1;
 641                         break;
 642                 }
 643                 case 3: /* level */
 644                 {
 645                         trigger = 1;
 646                         break;
 647                 }
 648                 default: /* invalid */
 649                 {
 650                         printk(KERN_WARNING "broken BIOS!!\n");
 651                         trigger = 0;
 652                         break;
 653                 }
 654         }
 655         return trigger;
 656 }
 657
 658 static inline int irq_polarity(int idx)
 659 {
 660         return MPBIOS_polarity(idx);
 661 }
 662
 663 static inline int irq_trigger(int idx)
 664 {
 665         return MPBIOS_trigger(idx);
 666 }
 667
 668 static int next_irq = 16;
 669
 670 /*
 671  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 672  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 673  * from ACPI, which can reach 800 in large boxen.
 674  *
 675  * Compact the sparse GSI space into a sequential IRQ series and reuse
 676  * vectors if possible.
 677  */
 678 int gsi_irq_sharing(int gsi)
 679 {
 680         int i, tries, vector;
 681
 682         BUG_ON(gsi >= NR_IRQ_VECTORS);
 683
 684         if (platform_legacy_irq(gsi))
 685                 return gsi;
 686
 687         if (gsi_2_irq[gsi] != 0xFF)
 688                 return (int)gsi_2_irq[gsi];
 689
 690         tries = NR_IRQS;
 691   try_again:
 692         vector = assign_irq_vector(gsi);
 693
 694         /*
 695          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 696          * use of vector and if found, return that IRQ.  However, we never want
 697          * to share legacy IRQs, which usually have a different trigger mode
 698          * than PCI.
 699          */
 700         for (i = 0; i < NR_IRQS; i++)
 701                 if (IO_APIC_VECTOR(i) == vector)
 702                         break;
 703         if (platform_legacy_irq(i)) {
 704                 if (--tries >= 0) {
 705                         IO_APIC_VECTOR(i) = 0;
 706                         goto try_again;
 707                 }
 708                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 709         }
 710         if (i < NR_IRQS) {
 711                 gsi_2_irq[gsi] = i;
 712                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 713                                 gsi, vector, i);
 714                 return i;
 715         }
 716
 717         i = next_irq++;
 718         BUG_ON(i >= NR_IRQS);
 719         gsi_2_irq[gsi] = i;
 720         IO_APIC_VECTOR(i) = vector;
 721         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 722                         gsi, vector, i);
 723         return i;
 724 }
 725
 726 static int pin_2_irq(int idx, int apic, int pin)
 727 {
 728         int irq, i;
 729         int bus = mp_irqs[idx].mpc_srcbus;
 730
 731         /*
 732          * Debugging check, we are in big trouble if this message pops up!
 733          */
 734         if (mp_irqs[idx].mpc_dstirq != pin)
 735                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 736
 737         switch (mp_bus_id_to_type[bus])
 738         {
 739                 case MP_BUS_ISA: /* ISA pin */
 740                 case MP_BUS_EISA:
 741                 case MP_BUS_MCA:
 742                 {
 743                         irq = mp_irqs[idx].mpc_srcbusirq;
 744                         break;
 745                 }
 746                 case MP_BUS_PCI: /* PCI pin */
 747                 {
 748                         /*
 749                          * PCI IRQs are mapped in order
 750                          */
 751                         i = irq = 0;
 752                         while (i < apic)
 753                                 irq += nr_ioapic_registers[i++];
 754                         irq += pin;
 755                         irq = gsi_irq_sharing(irq);
 756                         break;
 757                 }
 758                 default:
 759                 {
 760                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 761                         irq = 0;
 762                         break;
 763                 }
 764         }
 765         BUG_ON(irq >= NR_IRQS);
 766
 767         /*
 768          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 769          */
 770         if ((pin >= 16) && (pin <= 23)) {
 771                 if (pirq_entries[pin-16] != -1) {
 772                         if (!pirq_entries[pin-16]) {
 773                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 774                         } else {
 775                                 irq = pirq_entries[pin-16];
 776                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 777                                                 pin-16, irq);
 778                         }
 779                 }
 780         }
 781         BUG_ON(irq >= NR_IRQS);
 782         return irq;
 783 }
 784
 785 static inline int IO_APIC_irq_trigger(int irq)
 786 {
 787         int apic, idx, pin;
 788
 789         for (apic = 0; apic < nr_ioapics; apic++) {
 790                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 791                         idx = find_irq_entry(apic,pin,mp_INT);
 792                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 793                                 return irq_trigger(idx);
 794                 }
 795         }
 796         /*
 797          * nonexistent IRQs are edge default
 798          */
 799         return 0;
 800 }
 801
 802 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 803 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 804
 805 int assign_irq_vector(int irq)
 806 {
 807         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 808
 809         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 810         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
 811                 return IO_APIC_VECTOR(irq);
 812 next:
 813         current_vector += 8;
 814         if (current_vector == IA32_SYSCALL_VECTOR)
 815                 goto next;
 816
 817         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 818                 /* If we run out of vectors on large boxen, must share them. */
 819                 offset = (offset + 1) % 8;
 820                 current_vector = FIRST_DEVICE_VECTOR + offset;
 821         }
 822
 823         vector_irq[current_vector] = irq;
 824         if (irq != AUTO_ASSIGN)
 825                 IO_APIC_VECTOR(irq) = current_vector;
 826
 827         return current_vector;
 828 }
 829
 830 extern void (*interrupt[NR_IRQS])(void);
 831 static struct hw_interrupt_type ioapic_level_type;
 832 static struct hw_interrupt_type ioapic_edge_type;
 833
 834 #define IOAPIC_AUTO     -1
 835 #define IOAPIC_EDGE     0
 836 #define IOAPIC_LEVEL    1
 837
 838 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 839 {
 840         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 841                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 842                                 trigger == IOAPIC_LEVEL)
 843                         irq_desc[vector].handler = &ioapic_level_type;
 844                 else
 845                         irq_desc[vector].handler = &ioapic_edge_type;
 846                 set_intr_gate(vector, interrupt[vector]);
 847         } else  {
 848                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 849                                 trigger == IOAPIC_LEVEL)
 850                         irq_desc[irq].handler = &ioapic_level_type;
 851                 else
 852                         irq_desc[irq].handler = &ioapic_edge_type;
 853                 set_intr_gate(vector, interrupt[irq]);
 854         }
 855 }
 856
 857 static void __init setup_IO_APIC_irqs(void)
 858 {
 859         struct IO_APIC_route_entry entry;
 860         int apic, pin, idx, irq, first_notcon = 1, vector;
 861         unsigned long flags;
 862
 863         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 864
 865         for (apic = 0; apic < nr_ioapics; apic++) {
 866         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 867
 868                 /*
 869                  * add it to the IO-APIC irq-routing table:
 870                  */
 871                 memset(&entry,0,sizeof(entry));
 872
 873                 entry.delivery_mode = INT_DELIVERY_MODE;
 874                 entry.dest_mode = INT_DEST_MODE;
 875                 entry.mask = 0;                         /* enable IRQ */
 876                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 877
 878                 idx = find_irq_entry(apic,pin,mp_INT);
 879                 if (idx == -1) {
 880                         if (first_notcon) {
 881                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 882                                 first_notcon = 0;
 883                         } else
 884                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 885                         continue;
 886                 }
 887
 888                 entry.trigger = irq_trigger(idx);
 889                 entry.polarity = irq_polarity(idx);
 890
 891                 if (irq_trigger(idx)) {
 892                         entry.trigger = 1;
 893                         entry.mask = 1;
 894                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 895                 }
 896
 897                 irq = pin_2_irq(idx, apic, pin);
 898                 add_pin_to_irq(irq, apic, pin);
 899
 900                 if (!apic && !IO_APIC_IRQ(irq))
 901                         continue;
 902
 903                 if (IO_APIC_IRQ(irq)) {
 904                         vector = assign_irq_vector(irq);
 905                         entry.vector = vector;
 906
 907                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 908                         if (!apic && (irq < 16))
 909                                 disable_8259A_irq(irq);
 910                 }
 911                 spin_lock_irqsave(&ioapic_lock, flags);
 912                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 913                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 914                 set_native_irq_info(irq, TARGET_CPUS);
 915                 spin_unlock_irqrestore(&ioapic_lock, flags);
 916         }
 917         }
 918
 919         if (!first_notcon)
 920                 apic_printk(APIC_VERBOSE," not connected.\n");
 921 }
 922
 923 /*
 924  * Set up the 8259A-master output pin as broadcast to all
 925  * CPUs.
 926  */
 927 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 928 {
 929         struct IO_APIC_route_entry entry;
 930         unsigned long flags;
 931
 932         memset(&entry,0,sizeof(entry));
 933
 934         disable_8259A_irq(0);
 935
 936         /* mask LVT0 */
 937         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 938
 939         /*
 940          * We use logical delivery to get the timer IRQ
 941          * to the first CPU.
 942          */
 943         entry.dest_mode = INT_DEST_MODE;
 944         entry.mask = 0;                                 /* unmask IRQ now */
 945         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 946         entry.delivery_mode = INT_DELIVERY_MODE;
 947         entry.polarity = 0;
 948         entry.trigger = 0;
 949         entry.vector = vector;
 950
 951         /*
 952          * The timer IRQ doesn't have to know that behind the
 953          * scene we have a 8259A-master in AEOI mode ...
 954          */
 955         irq_desc[0].handler = &ioapic_edge_type;
 956
 957         /*
 958          * Add it to the IO-APIC irq-routing table:
 959          */
 960         spin_lock_irqsave(&ioapic_lock, flags);
 961         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 962         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 963         spin_unlock_irqrestore(&ioapic_lock, flags);
 964
 965         enable_8259A_irq(0);
 966 }
 967
 968 void __init UNEXPECTED_IO_APIC(void)
 969 {
 970 }
 971
 972 void __apicdebuginit print_IO_APIC(void)
 973 {
 974         int apic, i;
 975         union IO_APIC_reg_00 reg_00;
 976         union IO_APIC_reg_01 reg_01;
 977         union IO_APIC_reg_02 reg_02;
 978         unsigned long flags;
 979
 980         if (apic_verbosity == APIC_QUIET)
 981                 return;
 982
 983         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 984         for (i = 0; i < nr_ioapics; i++)
 985                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 986                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 987
 988         /*
 989          * We are a bit conservative about what we expect.  We have to
 990          * know about every hardware change ASAP.
 991          */
 992         printk(KERN_INFO "testing the IO APIC.......................\n");
 993
 994         for (apic = 0; apic < nr_ioapics; apic++) {
 995
 996         spin_lock_irqsave(&ioapic_lock, flags);
 997         reg_00.raw = io_apic_read(apic, 0);
 998         reg_01.raw = io_apic_read(apic, 1);
 999         if (reg_01.bits.version >= 0x10)
1000                 reg_02.raw = io_apic_read(apic, 2);
1001         spin_unlock_irqrestore(&ioapic_lock, flags);
1002
1003         printk("\n");
1004         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1005         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1006         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1007         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1008                 UNEXPECTED_IO_APIC();
1009
1010         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1011         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1012         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1013                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1014                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1015                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1016                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1017                 (reg_01.bits.entries != 0x2E) &&
1018                 (reg_01.bits.entries != 0x3F) &&
1019                 (reg_01.bits.entries != 0x03)
1020         )
1021                 UNEXPECTED_IO_APIC();
1022
1023         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1024         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1025         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1026                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1027                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1028                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1029                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1030                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1031         )
1032                 UNEXPECTED_IO_APIC();
1033         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1034                 UNEXPECTED_IO_APIC();
1035
1036         if (reg_01.bits.version >= 0x10) {
1037                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1038                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1039                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1040                         UNEXPECTED_IO_APIC();
1041         }
1042
1043         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1044
1045         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1046                           " Stat Dest Deli Vect:   \n");
1047
1048         for (i = 0; i <= reg_01.bits.entries; i++) {
1049                 struct IO_APIC_route_entry entry;
1050
1051                 spin_lock_irqsave(&ioapic_lock, flags);
1052                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1053                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1054                 spin_unlock_irqrestore(&ioapic_lock, flags);
1055
1056                 printk(KERN_DEBUG " %02x %03X %02X  ",
1057                         i,
1058                         entry.dest.logical.logical_dest,
1059                         entry.dest.physical.physical_dest
1060                 );
1061
1062                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1063                         entry.mask,
1064                         entry.trigger,
1065                         entry.irr,
1066                         entry.polarity,
1067                         entry.delivery_status,
1068                         entry.dest_mode,
1069                         entry.delivery_mode,
1070                         entry.vector
1071                 );
1072         }
1073         }
1074         if (use_pci_vector())
1075                 printk(KERN_INFO "Using vector-based indexing\n");
1076         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1077         for (i = 0; i < NR_IRQS; i++) {
1078                 struct irq_pin_list *entry = irq_2_pin + i;
1079                 if (entry->pin < 0)
1080                         continue;
1081                 if (use_pci_vector() && !platform_legacy_irq(i))
1082                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1083                 else
1084                         printk(KERN_DEBUG "IRQ%d ", i);
1085                 for (;;) {
1086                         printk("-> %d:%d", entry->apic, entry->pin);
1087                         if (!entry->next)
1088                                 break;
1089                         entry = irq_2_pin + entry->next;
1090                 }
1091                 printk("\n");
1092         }
1093
1094         printk(KERN_INFO ".................................... done.\n");
1095
1096         return;
1097 }
1098
1099 #if 0
1100
1101 static __apicdebuginit void print_APIC_bitfield (int base)
1102 {
1103         unsigned int v;
1104         int i, j;
1105
1106         if (apic_verbosity == APIC_QUIET)
1107                 return;
1108
1109         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1110         for (i = 0; i < 8; i++) {
1111                 v = apic_read(base + i*0x10);
1112                 for (j = 0; j < 32; j++) {
1113                         if (v & (1<<j))
1114                                 printk("1");
1115                         else
1116                                 printk("0");
1117                 }
1118                 printk("\n");
1119         }
1120 }
1121
1122 void __apicdebuginit print_local_APIC(void * dummy)
1123 {
1124         unsigned int v, ver, maxlvt;
1125
1126         if (apic_verbosity == APIC_QUIET)
1127                 return;
1128
1129         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1130                 smp_processor_id(), hard_smp_processor_id());
1131         v = apic_read(APIC_ID);
1132         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1133         v = apic_read(APIC_LVR);
1134         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1135         ver = GET_APIC_VERSION(v);
1136         maxlvt = get_maxlvt();
1137
1138         v = apic_read(APIC_TASKPRI);
1139         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1140
1141         v = apic_read(APIC_ARBPRI);
1142         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1143                 v & APIC_ARBPRI_MASK);
1144         v = apic_read(APIC_PROCPRI);
1145         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1146
1147         v = apic_read(APIC_EOI);
1148         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1149         v = apic_read(APIC_RRR);
1150         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1151         v = apic_read(APIC_LDR);
1152         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1153         v = apic_read(APIC_DFR);
1154         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1155         v = apic_read(APIC_SPIV);
1156         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1157
1158         printk(KERN_DEBUG "... APIC ISR field:\n");
1159         print_APIC_bitfield(APIC_ISR);
1160         printk(KERN_DEBUG "... APIC TMR field:\n");
1161         print_APIC_bitfield(APIC_TMR);
1162         printk(KERN_DEBUG "... APIC IRR field:\n");
1163         print_APIC_bitfield(APIC_IRR);
1164
1165         v = apic_read(APIC_ESR);
1166         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1167
1168         v = apic_read(APIC_ICR);
1169         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1170         v = apic_read(APIC_ICR2);
1171         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1172
1173         v = apic_read(APIC_LVTT);
1174         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1175
1176         if (maxlvt > 3) {                       /* PC is LVT#4. */
1177                 v = apic_read(APIC_LVTPC);
1178                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1179         }
1180         v = apic_read(APIC_LVT0);
1181         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1182         v = apic_read(APIC_LVT1);
1183         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1184
1185         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1186                 v = apic_read(APIC_LVTERR);
1187                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1188         }
1189
1190         v = apic_read(APIC_TMICT);
1191         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1192         v = apic_read(APIC_TMCCT);
1193         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1194         v = apic_read(APIC_TDCR);
1195         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1196         printk("\n");
1197 }
1198
1199 void print_all_local_APICs (void)
1200 {
1201         on_each_cpu(print_local_APIC, NULL, 1, 1);
1202 }
1203
1204 void __apicdebuginit print_PIC(void)
1205 {
1206         unsigned int v;
1207         unsigned long flags;
1208
1209         if (apic_verbosity == APIC_QUIET)
1210                 return;
1211
1212         printk(KERN_DEBUG "\nprinting PIC contents\n");
1213
1214         spin_lock_irqsave(&i8259A_lock, flags);
1215
1216         v = inb(0xa1) << 8 | inb(0x21);
1217         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1218
1219         v = inb(0xa0) << 8 | inb(0x20);
1220         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1221
1222         outb(0x0b,0xa0);
1223         outb(0x0b,0x20);
1224         v = inb(0xa0) << 8 | inb(0x20);
1225         outb(0x0a,0xa0);
1226         outb(0x0a,0x20);
1227
1228         spin_unlock_irqrestore(&i8259A_lock, flags);
1229
1230         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1231
1232         v = inb(0x4d1) << 8 | inb(0x4d0);
1233         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1234 }
1235
1236 #endif  /*  0  */
1237
1238 static void __init enable_IO_APIC(void)
1239 {
1240         union IO_APIC_reg_01 reg_01;
1241         int i8259_apic, i8259_pin;
1242         int i, apic;
1243         unsigned long flags;
1244
1245         for (i = 0; i < PIN_MAP_SIZE; i++) {
1246                 irq_2_pin[i].pin = -1;
1247                 irq_2_pin[i].next = 0;
1248         }
1249         if (!pirqs_enabled)
1250                 for (i = 0; i < MAX_PIRQS; i++)
1251                         pirq_entries[i] = -1;
1252
1253         /*
1254          * The number of IO-APIC IRQ registers (== #pins):
1255          */
1256         for (apic = 0; apic < nr_ioapics; apic++) {
1257                 spin_lock_irqsave(&ioapic_lock, flags);
1258                 reg_01.raw = io_apic_read(apic, 1);
1259                 spin_unlock_irqrestore(&ioapic_lock, flags);
1260                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1261         }
1262         for(apic = 0; apic < nr_ioapics; apic++) {
1263                 int pin;
1264                 /* See if any of the pins is in ExtINT mode */
1265                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1266                         struct IO_APIC_route_entry entry;
1267                         spin_lock_irqsave(&ioapic_lock, flags);
1268                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1269                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1270                         spin_unlock_irqrestore(&ioapic_lock, flags);
1271
1272
1273                         /* If the interrupt line is enabled and in ExtInt mode
1274                          * I have found the pin where the i8259 is connected.
1275                          */
1276                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1277                                 ioapic_i8259.apic = apic;
1278                                 ioapic_i8259.pin  = pin;
1279                                 goto found_i8259;
1280                         }
1281                 }
1282         }
1283  found_i8259:
1284         /* Look to see what if the MP table has reported the ExtINT */
1285         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1286         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1287         /* Trust the MP table if nothing is setup in the hardware */
1288         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1289                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1290                 ioapic_i8259.pin  = i8259_pin;
1291                 ioapic_i8259.apic = i8259_apic;
1292         }
1293         /* Complain if the MP table and the hardware disagree */
1294         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1295                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1296         {
1297                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1298         }
1299
1300         /*
1301          * Do not trust the IO-APIC being empty at bootup
1302          */
1303         clear_IO_APIC();
1304 }
1305
1306 /*
1307  * Not an __init, needed by the reboot code
1308  */
1309 void disable_IO_APIC(void)
1310 {
1311         /*
1312          * Clear the IO-APIC before rebooting:
1313          */
1314         clear_IO_APIC();
1315
1316         /*
1317          * If the i8259 is routed through an IOAPIC
1318          * Put that IOAPIC in virtual wire mode
1319          * so legacy interrupts can be delivered.
1320          */
1321         if (ioapic_i8259.pin != -1) {
1322                 struct IO_APIC_route_entry entry;
1323                 unsigned long flags;
1324
1325                 memset(&entry, 0, sizeof(entry));
1326                 entry.mask            = 0; /* Enabled */
1327                 entry.trigger         = 0; /* Edge */
1328                 entry.irr             = 0;
1329                 entry.polarity        = 0; /* High */
1330                 entry.delivery_status = 0;
1331                 entry.dest_mode       = 0; /* Physical */
1332                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1333                 entry.vector          = 0;
1334                 entry.dest.physical.physical_dest =
1335                                         GET_APIC_ID(apic_read(APIC_ID));
1336
1337                 /*
1338                  * Add it to the IO-APIC irq-routing table:
1339                  */
1340                 spin_lock_irqsave(&ioapic_lock, flags);
1341                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1342                         *(((int *)&entry)+1));
1343                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1344                         *(((int *)&entry)+0));
1345                 spin_unlock_irqrestore(&ioapic_lock, flags);
1346         }
1347
1348         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1349 }
1350
1351 /*
1352  * function to set the IO-APIC physical IDs based on the
1353  * values stored in the MPC table.
1354  *
1355  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1356  */
1357
1358 static void __init setup_ioapic_ids_from_mpc (void)
1359 {
1360         union IO_APIC_reg_00 reg_00;
1361         int apic;
1362         int i;
1363         unsigned char old_id;
1364         unsigned long flags;
1365
1366         /*
1367          * Set the IOAPIC ID to the value stored in the MPC table.
1368          */
1369         for (apic = 0; apic < nr_ioapics; apic++) {
1370
1371                 /* Read the register 0 value */
1372                 spin_lock_irqsave(&ioapic_lock, flags);
1373                 reg_00.raw = io_apic_read(apic, 0);
1374                 spin_unlock_irqrestore(&ioapic_lock, flags);
1375
1376                 old_id = mp_ioapics[apic].mpc_apicid;
1377
1378
1379                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1380
1381
1382                 /*
1383                  * We need to adjust the IRQ routing table
1384                  * if the ID changed.
1385                  */
1386                 if (old_id != mp_ioapics[apic].mpc_apicid)
1387                         for (i = 0; i < mp_irq_entries; i++)
1388                                 if (mp_irqs[i].mpc_dstapic == old_id)
1389                                         mp_irqs[i].mpc_dstapic
1390                                                 = mp_ioapics[apic].mpc_apicid;
1391
1392                 /*
1393                  * Read the right value from the MPC table and
1394                  * write it into the ID register.
1395                  */
1396                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1397                                 mp_ioapics[apic].mpc_apicid);
1398
1399                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1400                 spin_lock_irqsave(&ioapic_lock, flags);
1401                 io_apic_write(apic, 0, reg_00.raw);
1402                 spin_unlock_irqrestore(&ioapic_lock, flags);
1403
1404                 /*
1405                  * Sanity check
1406                  */
1407                 spin_lock_irqsave(&ioapic_lock, flags);
1408                 reg_00.raw = io_apic_read(apic, 0);
1409                 spin_unlock_irqrestore(&ioapic_lock, flags);
1410                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1411                         printk("could not set ID!\n");
1412                 else
1413                         apic_printk(APIC_VERBOSE," ok.\n");
1414         }
1415 }
1416
1417 /*
1418  * There is a nasty bug in some older SMP boards, their mptable lies
1419  * about the timer IRQ. We do the following to work around the situation:
1420  *
1421  *      - timer IRQ defaults to IO-APIC IRQ
1422  *      - if this function detects that timer IRQs are defunct, then we fall
1423  *        back to ISA timer IRQs
1424  */
1425 static int __init timer_irq_works(void)
1426 {
1427         unsigned long t1 = jiffies;
1428
1429         local_irq_enable();
1430         /* Let ten ticks pass... */
1431         mdelay((10 * 1000) / HZ);
1432
1433         /*
1434          * Expect a few ticks at least, to be sure some possible
1435          * glue logic does not lock up after one or two first
1436          * ticks in a non-ExtINT mode.  Also the local APIC
1437          * might have cached one ExtINT interrupt.  Finally, at
1438          * least one tick may be lost due to delays.
1439          */
1440
1441         /* jiffies wrap? */
1442         if (jiffies - t1 > 4)
1443                 return 1;
1444         return 0;
1445 }
1446
1447 /*
1448  * In the SMP+IOAPIC case it might happen that there are an unspecified
1449  * number of pending IRQ events unhandled. These cases are very rare,
1450  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1451  * better to do it this way as thus we do not have to be aware of
1452  * 'pending' interrupts in the IRQ path, except at this point.
1453  */
1454 /*
1455  * Edge triggered needs to resend any interrupt
1456  * that was delayed but this is now handled in the device
1457  * independent code.
1458  */
1459
1460 /*
1461  * Starting up a edge-triggered IO-APIC interrupt is
1462  * nasty - we need to make sure that we get the edge.
1463  * If it is already asserted for some reason, we need
1464  * return 1 to indicate that is was pending.
1465  *
1466  * This is not complete - we should be able to fake
1467  * an edge even if it isn't on the 8259A...
1468  */
1469
1470 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1471 {
1472         int was_pending = 0;
1473         unsigned long flags;
1474
1475         spin_lock_irqsave(&ioapic_lock, flags);
1476         if (irq < 16) {
1477                 disable_8259A_irq(irq);
1478                 if (i8259A_irq_pending(irq))
1479                         was_pending = 1;
1480         }
1481         __unmask_IO_APIC_irq(irq);
1482         spin_unlock_irqrestore(&ioapic_lock, flags);
1483
1484         return was_pending;
1485 }
1486
1487 /*
1488  * Once we have recorded IRQ_PENDING already, we can mask the
1489  * interrupt for real. This prevents IRQ storms from unhandled
1490  * devices.
1491  */
1492 static void ack_edge_ioapic_irq(unsigned int irq)
1493 {
1494         move_irq(irq);
1495         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1496                                         == (IRQ_PENDING | IRQ_DISABLED))
1497                 mask_IO_APIC_irq(irq);
1498         ack_APIC_irq();
1499 }
1500
1501 /*
1502  * Level triggered interrupts can just be masked,
1503  * and shutting down and starting up the interrupt
1504  * is the same as enabling and disabling them -- except
1505  * with a startup need to return a "was pending" value.
1506  *
1507  * Level triggered interrupts are special because we
1508  * do not touch any IO-APIC register while handling
1509  * them. We ack the APIC in the end-IRQ handler, not
1510  * in the start-IRQ-handler. Protection against reentrance
1511  * from the same interrupt is still provided, both by the
1512  * generic IRQ layer and by the fact that an unacked local
1513  * APIC does not accept IRQs.
1514  */
1515 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1516 {
1517         unmask_IO_APIC_irq(irq);
1518
1519         return 0; /* don't check for pending */
1520 }
1521
1522 static void end_level_ioapic_irq (unsigned int irq)
1523 {
1524         move_irq(irq);
1525         ack_APIC_irq();
1526 }
1527
1528 #ifdef CONFIG_PCI_MSI
1529 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1530 {
1531         int irq = vector_to_irq(vector);
1532
1533         return startup_edge_ioapic_irq(irq);
1534 }
1535
1536 static void ack_edge_ioapic_vector(unsigned int vector)
1537 {
1538         int irq = vector_to_irq(vector);
1539
1540         move_native_irq(vector);
1541         ack_edge_ioapic_irq(irq);
1542 }
1543
1544 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1545 {
1546         int irq = vector_to_irq(vector);
1547
1548         return startup_level_ioapic_irq (irq);
1549 }
1550
1551 static void end_level_ioapic_vector (unsigned int vector)
1552 {
1553         int irq = vector_to_irq(vector);
1554
1555         move_native_irq(vector);
1556         end_level_ioapic_irq(irq);
1557 }
1558
1559 static void mask_IO_APIC_vector (unsigned int vector)
1560 {
1561         int irq = vector_to_irq(vector);
1562
1563         mask_IO_APIC_irq(irq);
1564 }
1565
1566 static void unmask_IO_APIC_vector (unsigned int vector)
1567 {
1568         int irq = vector_to_irq(vector);
1569
1570         unmask_IO_APIC_irq(irq);
1571 }
1572
1573 #ifdef CONFIG_SMP
1574 static void set_ioapic_affinity_vector (unsigned int vector,
1575                                         cpumask_t cpu_mask)
1576 {
1577         int irq = vector_to_irq(vector);
1578
1579         set_native_irq_info(vector, cpu_mask);
1580         set_ioapic_affinity_irq(irq, cpu_mask);
1581 }
1582 #endif // CONFIG_SMP
1583 #endif // CONFIG_PCI_MSI
1584
1585 /*
1586  * Level and edge triggered IO-APIC interrupts need different handling,
1587  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1588  * handled with the level-triggered descriptor, but that one has slightly
1589  * more overhead. Level-triggered interrupts cannot be handled with the
1590  * edge-triggered handler, without risking IRQ storms and other ugly
1591  * races.
1592  */
1593
1594 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1595         .typename = "IO-APIC-edge",
1596         .startup        = startup_edge_ioapic,
1597         .shutdown       = shutdown_edge_ioapic,
1598         .enable         = enable_edge_ioapic,
1599         .disable        = disable_edge_ioapic,
1600         .ack            = ack_edge_ioapic,
1601         .end            = end_edge_ioapic,
1602 #ifdef CONFIG_SMP
1603         .set_affinity = set_ioapic_affinity,
1604 #endif
1605 };
1606
1607 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1608         .typename = "IO-APIC-level",
1609         .startup        = startup_level_ioapic,
1610         .shutdown       = shutdown_level_ioapic,
1611         .enable         = enable_level_ioapic,
1612         .disable        = disable_level_ioapic,
1613         .ack            = mask_and_ack_level_ioapic,
1614         .end            = end_level_ioapic,
1615 #ifdef CONFIG_SMP
1616         .set_affinity = set_ioapic_affinity,
1617 #endif
1618 };
1619
1620 static inline void init_IO_APIC_traps(void)
1621 {
1622         int irq;
1623
1624         /*
1625          * NOTE! The local APIC isn't very good at handling
1626          * multiple interrupts at the same interrupt level.
1627          * As the interrupt level is determined by taking the
1628          * vector number and shifting that right by 4, we
1629          * want to spread these out a bit so that they don't
1630          * all fall in the same interrupt level.
1631          *
1632          * Also, we've got to be careful not to trash gate
1633          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1634          */
1635         for (irq = 0; irq < NR_IRQS ; irq++) {
1636                 int tmp = irq;
1637                 if (use_pci_vector()) {
1638                         if (!platform_legacy_irq(tmp))
1639                                 if ((tmp = vector_to_irq(tmp)) == -1)
1640                                         continue;
1641                 }
1642                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1643                         /*
1644                          * Hmm.. We don't have an entry for this,
1645                          * so default to an old-fashioned 8259
1646                          * interrupt if we can..
1647                          */
1648                         if (irq < 16)
1649                                 make_8259A_irq(irq);
1650                         else
1651                                 /* Strange. Oh, well.. */
1652                                 irq_desc[irq].handler = &no_irq_type;
1653                 }
1654         }
1655 }
1656
1657 static void enable_lapic_irq (unsigned int irq)
1658 {
1659         unsigned long v;
1660
1661         v = apic_read(APIC_LVT0);
1662         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1663 }
1664
1665 static void disable_lapic_irq (unsigned int irq)
1666 {
1667         unsigned long v;
1668
1669         v = apic_read(APIC_LVT0);
1670         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1671 }
1672
1673 static void ack_lapic_irq (unsigned int irq)
1674 {
1675         ack_APIC_irq();
1676 }
1677
1678 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1679
1680 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1681         .typename = "local-APIC-edge",
1682         .startup = NULL, /* startup_irq() not used for IRQ0 */
1683         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1684         .enable = enable_lapic_irq,
1685         .disable = disable_lapic_irq,
1686         .ack = ack_lapic_irq,
1687         .end = end_lapic_irq,
1688 };
1689
1690 static void setup_nmi (void)
1691 {
1692         /*
1693          * Dirty trick to enable the NMI watchdog ...
1694          * We put the 8259A master into AEOI mode and
1695          * unmask on all local APICs LVT0 as NMI.
1696          *
1697          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1698          * is from Maciej W. Rozycki - so we do not have to EOI from
1699          * the NMI handler or the timer interrupt.
1700          */
1701         printk(KERN_INFO "activating NMI Watchdog ...");
1702
1703         enable_NMI_through_LVT0(NULL);
1704
1705         printk(" done.\n");
1706 }
1707
1708 /*
1709  * This looks a bit hackish but it's about the only one way of sending
1710  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1711  * not support the ExtINT mode, unfortunately.  We need to send these
1712  * cycles as some i82489DX-based boards have glue logic that keeps the
1713  * 8259A interrupt line asserted until INTA.  --macro
1714  */
1715 static inline void unlock_ExtINT_logic(void)
1716 {
1717         int apic, pin, i;
1718         struct IO_APIC_route_entry entry0, entry1;
1719         unsigned char save_control, save_freq_select;
1720         unsigned long flags;
1721
1722         pin  = find_isa_irq_pin(8, mp_INT);
1723         apic = find_isa_irq_apic(8, mp_INT);
1724         if (pin == -1)
1725                 return;
1726
1727         spin_lock_irqsave(&ioapic_lock, flags);
1728         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1729         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1730         spin_unlock_irqrestore(&ioapic_lock, flags);
1731         clear_IO_APIC_pin(apic, pin);
1732
1733         memset(&entry1, 0, sizeof(entry1));
1734
1735         entry1.dest_mode = 0;                   /* physical delivery */
1736         entry1.mask = 0;                        /* unmask IRQ now */
1737         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1738         entry1.delivery_mode = dest_ExtINT;
1739         entry1.polarity = entry0.polarity;
1740         entry1.trigger = 0;
1741         entry1.vector = 0;
1742
1743         spin_lock_irqsave(&ioapic_lock, flags);
1744         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1745         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1746         spin_unlock_irqrestore(&ioapic_lock, flags);
1747
1748         save_control = CMOS_READ(RTC_CONTROL);
1749         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1750         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1751                    RTC_FREQ_SELECT);
1752         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1753
1754         i = 100;
1755         while (i-- > 0) {
1756                 mdelay(10);
1757                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1758                         i -= 10;
1759         }
1760
1761         CMOS_WRITE(save_control, RTC_CONTROL);
1762         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1763         clear_IO_APIC_pin(apic, pin);
1764
1765         spin_lock_irqsave(&ioapic_lock, flags);
1766         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1767         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1768         spin_unlock_irqrestore(&ioapic_lock, flags);
1769 }
1770
1771 /*
1772  * This code may look a bit paranoid, but it's supposed to cooperate with
1773  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1774  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1775  * fanatically on his truly buggy board.
1776  */
1777 static inline void check_timer(void)
1778 {
1779         int apic1, pin1, apic2, pin2;
1780         int vector;
1781
1782         /*
1783          * get/set the timer IRQ vector:
1784          */
1785         disable_8259A_irq(0);
1786         vector = assign_irq_vector(0);
1787         set_intr_gate(vector, interrupt[0]);
1788
1789         /*
1790          * Subtle, code in do_timer_interrupt() expects an AEOI
1791          * mode for the 8259A whenever interrupts are routed
1792          * through I/O APICs.  Also IRQ0 has to be enabled in
1793          * the 8259A which implies the virtual wire has to be
1794          * disabled in the local APIC.
1795          */
1796         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1797         init_8259A(1);
1798         enable_8259A_irq(0);
1799
1800         pin1  = find_isa_irq_pin(0, mp_INT);
1801         apic1 = find_isa_irq_apic(0, mp_INT);
1802         pin2  = ioapic_i8259.pin;
1803         apic2 = ioapic_i8259.apic;
1804
1805         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1806                 vector, apic1, pin1, apic2, pin2);
1807
1808         if (pin1 != -1) {
1809                 /*
1810                  * Ok, does IRQ0 through the IOAPIC work?
1811                  */
1812                 unmask_IO_APIC_irq(0);
1813                 if (!no_timer_check && timer_irq_works()) {
1814                         nmi_watchdog_default();
1815                         if (nmi_watchdog == NMI_IO_APIC) {
1816                                 disable_8259A_irq(0);
1817                                 setup_nmi();
1818                                 enable_8259A_irq(0);
1819                         }
1820                         if (disable_timer_pin_1 > 0)
1821                                 clear_IO_APIC_pin(0, pin1);
1822                         return;
1823                 }
1824                 clear_IO_APIC_pin(apic1, pin1);
1825                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1826                                 "connected to IO-APIC\n");
1827         }
1828
1829         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1830                                 "through the 8259A ... ");
1831         if (pin2 != -1) {
1832                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1833                         apic2, pin2);
1834                 /*
1835                  * legacy devices should be connected to IO APIC #0
1836                  */
1837                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1838                 if (timer_irq_works()) {
1839                         printk("works.\n");
1840                         nmi_watchdog_default();
1841                         if (nmi_watchdog == NMI_IO_APIC) {
1842                                 setup_nmi();
1843                         }
1844                         return;
1845                 }
1846                 /*
1847                  * Cleanup, just in case ...
1848                  */
1849                 clear_IO_APIC_pin(apic2, pin2);
1850         }
1851         printk(" failed.\n");
1852
1853         if (nmi_watchdog) {
1854                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1855                 nmi_watchdog = 0;
1856         }
1857
1858         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1859
1860         disable_8259A_irq(0);
1861         irq_desc[0].handler = &lapic_irq_type;
1862         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1863         enable_8259A_irq(0);
1864
1865         if (timer_irq_works()) {
1866                 apic_printk(APIC_QUIET, " works.\n");
1867                 return;
1868         }
1869         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1870         apic_printk(APIC_VERBOSE," failed.\n");
1871
1872         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1873
1874         init_8259A(0);
1875         make_8259A_irq(0);
1876         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1877
1878         unlock_ExtINT_logic();
1879
1880         if (timer_irq_works()) {
1881                 apic_printk(APIC_VERBOSE," works.\n");
1882                 return;
1883         }
1884         apic_printk(APIC_VERBOSE," failed :(.\n");
1885         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1886 }
1887
1888 static int __init notimercheck(char *s)
1889 {
1890         no_timer_check = 1;
1891         return 1;
1892 }
1893 __setup("no_timer_check", notimercheck);
1894
1895 /*
1896  *
1897  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1898  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1899  *   Linux doesn't really care, as it's not actually used
1900  *   for any interrupt handling anyway.
1901  */
1902 #define PIC_IRQS        (1<<2)
1903
1904 void __init setup_IO_APIC(void)
1905 {
1906         enable_IO_APIC();
1907
1908         if (acpi_ioapic)
1909                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1910         else
1911                 io_apic_irqs = ~PIC_IRQS;
1912
1913         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1914
1915         /*
1916          * Set up the IO-APIC IRQ routing table.
1917          */
1918         if (!acpi_ioapic)
1919                 setup_ioapic_ids_from_mpc();
1920         sync_Arb_IDs();
1921         setup_IO_APIC_irqs();
1922         init_IO_APIC_traps();
1923         check_timer();
1924         if (!acpi_ioapic)
1925                 print_IO_APIC();
1926 }
1927
1928 struct sysfs_ioapic_data {
1929         struct sys_device dev;
1930         struct IO_APIC_route_entry entry[0];
1931 };
1932 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1933
1934 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1935 {
1936         struct IO_APIC_route_entry *entry;
1937         struct sysfs_ioapic_data *data;
1938         unsigned long flags;
1939         int i;
1940
1941         data = container_of(dev, struct sysfs_ioapic_data, dev);
1942         entry = data->entry;
1943         spin_lock_irqsave(&ioapic_lock, flags);
1944         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1945                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1946                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1947         }
1948         spin_unlock_irqrestore(&ioapic_lock, flags);
1949
1950         return 0;
1951 }
1952
1953 static int ioapic_resume(struct sys_device *dev)
1954 {
1955         struct IO_APIC_route_entry *entry;
1956         struct sysfs_ioapic_data *data;
1957         unsigned long flags;
1958         union IO_APIC_reg_00 reg_00;
1959         int i;
1960
1961         data = container_of(dev, struct sysfs_ioapic_data, dev);
1962         entry = data->entry;
1963
1964         spin_lock_irqsave(&ioapic_lock, flags);
1965         reg_00.raw = io_apic_read(dev->id, 0);
1966         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1967                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1968                 io_apic_write(dev->id, 0, reg_00.raw);
1969         }
1970         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1971                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1972                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1973         }
1974         spin_unlock_irqrestore(&ioapic_lock, flags);
1975
1976         return 0;
1977 }
1978
1979 static struct sysdev_class ioapic_sysdev_class = {
1980         set_kset_name("ioapic"),
1981         .suspend = ioapic_suspend,
1982         .resume = ioapic_resume,
1983 };
1984
1985 static int __init ioapic_init_sysfs(void)
1986 {
1987         struct sys_device * dev;
1988         int i, size, error = 0;
1989
1990         error = sysdev_class_register(&ioapic_sysdev_class);
1991         if (error)
1992                 return error;
1993
1994         for (i = 0; i < nr_ioapics; i++ ) {
1995                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1996                         * sizeof(struct IO_APIC_route_entry);
1997                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1998                 if (!mp_ioapic_data[i]) {
1999                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2000                         continue;
2001                 }
2002                 memset(mp_ioapic_data[i], 0, size);
2003                 dev = &mp_ioapic_data[i]->dev;
2004                 dev->id = i;
2005                 dev->cls = &ioapic_sysdev_class;
2006                 error = sysdev_register(dev);
2007                 if (error) {
2008                         kfree(mp_ioapic_data[i]);
2009                         mp_ioapic_data[i] = NULL;
2010                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2011                         continue;
2012                 }
2013         }
2014
2015         return 0;
2016 }
2017
2018 device_initcall(ioapic_init_sysfs);
2019
2020 /* --------------------------------------------------------------------------
2021                           ACPI-based IOAPIC Configuration
2022    -------------------------------------------------------------------------- */
2023
2024 #ifdef CONFIG_ACPI
2025
2026 #define IO_APIC_MAX_ID          0xFE
2027
2028 int __init io_apic_get_version (int ioapic)
2029 {
2030         union IO_APIC_reg_01    reg_01;
2031         unsigned long flags;
2032
2033         spin_lock_irqsave(&ioapic_lock, flags);
2034         reg_01.raw = io_apic_read(ioapic, 1);
2035         spin_unlock_irqrestore(&ioapic_lock, flags);
2036
2037         return reg_01.bits.version;
2038 }
2039
2040
2041 int __init io_apic_get_redir_entries (int ioapic)
2042 {
2043         union IO_APIC_reg_01    reg_01;
2044         unsigned long flags;
2045
2046         spin_lock_irqsave(&ioapic_lock, flags);
2047         reg_01.raw = io_apic_read(ioapic, 1);
2048         spin_unlock_irqrestore(&ioapic_lock, flags);
2049
2050         return reg_01.bits.entries;
2051 }
2052
2053
2054 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2055 {
2056         struct IO_APIC_route_entry entry;
2057         unsigned long flags;
2058
2059         if (!IO_APIC_IRQ(irq)) {
2060                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2061                         ioapic);
2062                 return -EINVAL;
2063         }
2064
2065         /*
2066          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2067          * Note that we mask (disable) IRQs now -- these get enabled when the
2068          * corresponding device driver registers for this IRQ.
2069          */
2070
2071         memset(&entry,0,sizeof(entry));
2072
2073         entry.delivery_mode = INT_DELIVERY_MODE;
2074         entry.dest_mode = INT_DEST_MODE;
2075         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2076         entry.trigger = triggering;
2077         entry.polarity = polarity;
2078         entry.mask = 1;                                  /* Disabled (masked) */
2079
2080         irq = gsi_irq_sharing(irq);
2081         /*
2082          * IRQs < 16 are already in the irq_2_pin[] map
2083          */
2084         if (irq >= 16)
2085                 add_pin_to_irq(irq, ioapic, pin);
2086
2087         entry.vector = assign_irq_vector(irq);
2088
2089         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2090                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2091                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2092                triggering, polarity);
2093
2094         ioapic_register_intr(irq, entry.vector, triggering);
2095
2096         if (!ioapic && (irq < 16))
2097                 disable_8259A_irq(irq);
2098
2099         spin_lock_irqsave(&ioapic_lock, flags);
2100         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2101         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2102         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2103         spin_unlock_irqrestore(&ioapic_lock, flags);
2104
2105         return 0;
2106 }
2107
2108 #endif /* CONFIG_ACPI */
2109
2110
2111 /*
2112  * This function currently is only a helper for the i386 smp boot process where
2113  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2114  * so mask in all cases should simply be TARGET_CPUS
2115  */
2116 #ifdef CONFIG_SMP
2117 void __init setup_ioapic_dest(void)
2118 {
2119         int pin, ioapic, irq, irq_entry;
2120
2121         if (skip_ioapic_setup == 1)
2122                 return;
2123
2124         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2125                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2126                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2127                         if (irq_entry == -1)
2128                                 continue;
2129                         irq = pin_2_irq(irq_entry, ioapic, pin);
2130                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2131                 }
2132
2133         }
2134 }
2135 #endif