Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[pandora-kernel.git] / arch / x86_64 / kernel / genapic_flat.c
1 /*
2  * Copyright 2004 James Cleverdon, IBM.
3  * Subject to the GNU Public License, v.2
4  *
5  * Flat APIC subarch code.
6  *
7  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
8  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
9  * James Cleverdon.
10  */
11 #include <linux/config.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <asm/smp.h>
19 #include <asm/ipi.h>
20
21 static cpumask_t flat_target_cpus(void)
22 {
23         return cpu_online_map;
24 }
25
26 /*
27  * Set up the logical destination ID.
28  *
29  * Intel recommends to set DFR, LDR and TPR before enabling
30  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
31  * document number 292116).  So here it goes...
32  */
33 static void flat_init_apic_ldr(void)
34 {
35         unsigned long val;
36         unsigned long num, id;
37
38         num = smp_processor_id();
39         id = 1UL << num;
40         x86_cpu_to_log_apicid[num] = id;
41         apic_write(APIC_DFR, APIC_DFR_FLAT);
42         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
43         val |= SET_APIC_LOGICAL_ID(id);
44         apic_write(APIC_LDR, val);
45 }
46
47 static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
48 {
49         unsigned long mask = cpus_addr(cpumask)[0];
50         unsigned long cfg;
51         unsigned long flags;
52
53         local_save_flags(flags);
54         local_irq_disable();
55
56         /*
57          * Wait for idle.
58          */
59         apic_wait_icr_idle();
60
61         /*
62          * prepare target chip field
63          */
64         cfg = __prepare_ICR2(mask);
65         apic_write(APIC_ICR2, cfg);
66
67         /*
68          * program the ICR
69          */
70         cfg = __prepare_ICR(0, vector, APIC_DEST_LOGICAL);
71
72         /*
73          * Send the IPI. The write to APIC_ICR fires this off.
74          */
75         apic_write(APIC_ICR, cfg);
76         local_irq_restore(flags);
77 }
78
79 static void flat_send_IPI_allbutself(int vector)
80 {
81 #ifdef  CONFIG_HOTPLUG_CPU
82         int hotplug = 1;
83 #else
84         int hotplug = 0;
85 #endif
86         if (hotplug || vector == NMI_VECTOR) {
87                 cpumask_t allbutme = cpu_online_map;
88
89                 cpu_clear(smp_processor_id(), allbutme);
90
91                 if (!cpus_empty(allbutme))
92                         flat_send_IPI_mask(allbutme, vector);
93         } else if (num_online_cpus() > 1) {
94                 __send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
95         }
96 }
97
98 static void flat_send_IPI_all(int vector)
99 {
100         if (vector == NMI_VECTOR)
101                 flat_send_IPI_mask(cpu_online_map, vector);
102         else
103                 __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
104 }
105
106 static int flat_apic_id_registered(void)
107 {
108         return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map);
109 }
110
111 static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
112 {
113         return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
114 }
115
116 static unsigned int phys_pkg_id(int index_msb)
117 {
118         return hard_smp_processor_id() >> index_msb;
119 }
120
121 struct genapic apic_flat =  {
122         .name = "flat",
123         .int_delivery_mode = dest_LowestPrio,
124         .int_dest_mode = (APIC_DEST_LOGICAL != 0),
125         .int_delivery_dest = APIC_DEST_LOGICAL | APIC_DM_LOWEST,
126         .target_cpus = flat_target_cpus,
127         .apic_id_registered = flat_apic_id_registered,
128         .init_apic_ldr = flat_init_apic_ldr,
129         .send_IPI_all = flat_send_IPI_all,
130         .send_IPI_allbutself = flat_send_IPI_allbutself,
131         .send_IPI_mask = flat_send_IPI_mask,
132         .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
133         .phys_pkg_id = phys_pkg_id,
134 };
135
136 /*
137  * Physflat mode is used when there are more than 8 CPUs on a AMD system.
138  * We cannot use logical delivery in this case because the mask
139  * overflows, so use physical mode.
140  */
141
142 static cpumask_t physflat_target_cpus(void)
143 {
144         return cpumask_of_cpu(0);
145 }
146
147 static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
148 {
149         send_IPI_mask_sequence(cpumask, vector);
150 }
151
152 static void physflat_send_IPI_allbutself(int vector)
153 {
154         cpumask_t allbutme = cpu_online_map;
155
156         cpu_clear(smp_processor_id(), allbutme);
157         physflat_send_IPI_mask(allbutme, vector);
158 }
159
160 static void physflat_send_IPI_all(int vector)
161 {
162         physflat_send_IPI_mask(cpu_online_map, vector);
163 }
164
165 static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
166 {
167         int cpu;
168
169         /*
170          * We're using fixed IRQ delivery, can only return one phys APIC ID.
171          * May as well be the first.
172          */
173         cpu = first_cpu(cpumask);
174         if ((unsigned)cpu < NR_CPUS)
175                 return x86_cpu_to_apicid[cpu];
176         else
177                 return BAD_APICID;
178 }
179
180 struct genapic apic_physflat =  {
181         .name = "physical flat",
182         .int_delivery_mode = dest_Fixed,
183         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
184         .int_delivery_dest = APIC_DEST_PHYSICAL | APIC_DM_FIXED,
185         .target_cpus = physflat_target_cpus,
186         .apic_id_registered = flat_apic_id_registered,
187         .init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
188         .send_IPI_all = physflat_send_IPI_all,
189         .send_IPI_allbutself = physflat_send_IPI_allbutself,
190         .send_IPI_mask = physflat_send_IPI_mask,
191         .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
192         .phys_pkg_id = phys_pkg_id,
193 };